1 /* ---------------------------------------------------------------------------- */ 2 /* Atmel Microcontroller Software Support */ 3 /* SAM Software Package License */ 4 /* ---------------------------------------------------------------------------- */ 5 /* Copyright (c) %copyright_year%, Atmel Corporation */ 6 /* */ 7 /* All rights reserved. */ 8 /* */ 9 /* Redistribution and use in source and binary forms, with or without */ 10 /* modification, are permitted provided that the following condition is met: */ 11 /* */ 12 /* - Redistributions of source code must retain the above copyright notice, */ 13 /* this list of conditions and the disclaimer below. */ 14 /* */ 15 /* Atmel's name may not be used to endorse or promote products derived from */ 16 /* this software without specific prior written permission. */ 17 /* */ 18 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ 19 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ 20 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ 21 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ 22 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ 23 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ 24 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ 25 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ 26 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ 27 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ 28 /* ---------------------------------------------------------------------------- */ 29 30 #ifndef _SAM3XA_DACC_INSTANCE_ 31 #define _SAM3XA_DACC_INSTANCE_ 32 33 /* ========== Register definition for DACC peripheral ========== */ 34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 35 #define REG_DACC_CR (0x400C8000U) /**< \brief (DACC) Control Register */ 36 #define REG_DACC_MR (0x400C8004U) /**< \brief (DACC) Mode Register */ 37 #define REG_DACC_CHER (0x400C8010U) /**< \brief (DACC) Channel Enable Register */ 38 #define REG_DACC_CHDR (0x400C8014U) /**< \brief (DACC) Channel Disable Register */ 39 #define REG_DACC_CHSR (0x400C8018U) /**< \brief (DACC) Channel Status Register */ 40 #define REG_DACC_CDR (0x400C8020U) /**< \brief (DACC) Conversion Data Register */ 41 #define REG_DACC_IER (0x400C8024U) /**< \brief (DACC) Interrupt Enable Register */ 42 #define REG_DACC_IDR (0x400C8028U) /**< \brief (DACC) Interrupt Disable Register */ 43 #define REG_DACC_IMR (0x400C802CU) /**< \brief (DACC) Interrupt Mask Register */ 44 #define REG_DACC_ISR (0x400C8030U) /**< \brief (DACC) Interrupt Status Register */ 45 #define REG_DACC_ACR (0x400C8094U) /**< \brief (DACC) Analog Current Register */ 46 #define REG_DACC_WPMR (0x400C80E4U) /**< \brief (DACC) Write Protect Mode register */ 47 #define REG_DACC_WPSR (0x400C80E8U) /**< \brief (DACC) Write Protect Status register */ 48 #define REG_DACC_TPR (0x400C8108U) /**< \brief (DACC) Transmit Pointer Register */ 49 #define REG_DACC_TCR (0x400C810CU) /**< \brief (DACC) Transmit Counter Register */ 50 #define REG_DACC_TNPR (0x400C8118U) /**< \brief (DACC) Transmit Next Pointer Register */ 51 #define REG_DACC_TNCR (0x400C811CU) /**< \brief (DACC) Transmit Next Counter Register */ 52 #define REG_DACC_PTCR (0x400C8120U) /**< \brief (DACC) Transfer Control Register */ 53 #define REG_DACC_PTSR (0x400C8124U) /**< \brief (DACC) Transfer Status Register */ 54 #else 55 #define REG_DACC_CR (*(__O uint32_t*)0x400C8000U) /**< \brief (DACC) Control Register */ 56 #define REG_DACC_MR (*(__IO uint32_t*)0x400C8004U) /**< \brief (DACC) Mode Register */ 57 #define REG_DACC_CHER (*(__O uint32_t*)0x400C8010U) /**< \brief (DACC) Channel Enable Register */ 58 #define REG_DACC_CHDR (*(__O uint32_t*)0x400C8014U) /**< \brief (DACC) Channel Disable Register */ 59 #define REG_DACC_CHSR (*(__I uint32_t*)0x400C8018U) /**< \brief (DACC) Channel Status Register */ 60 #define REG_DACC_CDR (*(__O uint32_t*)0x400C8020U) /**< \brief (DACC) Conversion Data Register */ 61 #define REG_DACC_IER (*(__O uint32_t*)0x400C8024U) /**< \brief (DACC) Interrupt Enable Register */ 62 #define REG_DACC_IDR (*(__O uint32_t*)0x400C8028U) /**< \brief (DACC) Interrupt Disable Register */ 63 #define REG_DACC_IMR (*(__I uint32_t*)0x400C802CU) /**< \brief (DACC) Interrupt Mask Register */ 64 #define REG_DACC_ISR (*(__I uint32_t*)0x400C8030U) /**< \brief (DACC) Interrupt Status Register */ 65 #define REG_DACC_ACR (*(__IO uint32_t*)0x400C8094U) /**< \brief (DACC) Analog Current Register */ 66 #define REG_DACC_WPMR (*(__IO uint32_t*)0x400C80E4U) /**< \brief (DACC) Write Protect Mode register */ 67 #define REG_DACC_WPSR (*(__I uint32_t*)0x400C80E8U) /**< \brief (DACC) Write Protect Status register */ 68 #define REG_DACC_TPR (*(__IO uint32_t*)0x400C8108U) /**< \brief (DACC) Transmit Pointer Register */ 69 #define REG_DACC_TCR (*(__IO uint32_t*)0x400C810CU) /**< \brief (DACC) Transmit Counter Register */ 70 #define REG_DACC_TNPR (*(__IO uint32_t*)0x400C8118U) /**< \brief (DACC) Transmit Next Pointer Register */ 71 #define REG_DACC_TNCR (*(__IO uint32_t*)0x400C811CU) /**< \brief (DACC) Transmit Next Counter Register */ 72 #define REG_DACC_PTCR (*(__O uint32_t*)0x400C8120U) /**< \brief (DACC) Transfer Control Register */ 73 #define REG_DACC_PTSR (*(__I uint32_t*)0x400C8124U) /**< \brief (DACC) Transfer Status Register */ 74 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 75 76 #endif /* _SAM3XA_DACC_INSTANCE_ */ 77
