1 /* ---------------------------------------------------------------------------- */ 2 /* Atmel Microcontroller Software Support */ 3 /* SAM Software Package License */ 4 /* ---------------------------------------------------------------------------- */ 5 /* Copyright (c) %copyright_year%, Atmel Corporation */ 6 /* */ 7 /* All rights reserved. */ 8 /* */ 9 /* Redistribution and use in source and binary forms, with or without */ 10 /* modification, are permitted provided that the following condition is met: */ 11 /* */ 12 /* - Redistributions of source code must retain the above copyright notice, */ 13 /* this list of conditions and the disclaimer below. */ 14 /* */ 15 /* Atmel's name may not be used to endorse or promote products derived from */ 16 /* this software without specific prior written permission. */ 17 /* */ 18 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ 19 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ 20 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ 21 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ 22 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ 23 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ 24 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ 25 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ 26 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ 27 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ 28 /* ---------------------------------------------------------------------------- */ 29 30 #ifndef _SAM3XA_CAN0_INSTANCE_ 31 #define _SAM3XA_CAN0_INSTANCE_ 32 33 /* ========== Register definition for CAN0 peripheral ========== */ 34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 35 #define REG_CAN0_MR (0x400B4000U) /**< \brief (CAN0) Mode Register */ 36 #define REG_CAN0_IER (0x400B4004U) /**< \brief (CAN0) Interrupt Enable Register */ 37 #define REG_CAN0_IDR (0x400B4008U) /**< \brief (CAN0) Interrupt Disable Register */ 38 #define REG_CAN0_IMR (0x400B400CU) /**< \brief (CAN0) Interrupt Mask Register */ 39 #define REG_CAN0_SR (0x400B4010U) /**< \brief (CAN0) Status Register */ 40 #define REG_CAN0_BR (0x400B4014U) /**< \brief (CAN0) Baudrate Register */ 41 #define REG_CAN0_TIM (0x400B4018U) /**< \brief (CAN0) Timer Register */ 42 #define REG_CAN0_TIMESTP (0x400B401CU) /**< \brief (CAN0) Timestamp Register */ 43 #define REG_CAN0_ECR (0x400B4020U) /**< \brief (CAN0) Error Counter Register */ 44 #define REG_CAN0_TCR (0x400B4024U) /**< \brief (CAN0) Transfer Command Register */ 45 #define REG_CAN0_ACR (0x400B4028U) /**< \brief (CAN0) Abort Command Register */ 46 #define REG_CAN0_WPMR (0x400B40E4U) /**< \brief (CAN0) Write Protect Mode Register */ 47 #define REG_CAN0_WPSR (0x400B40E8U) /**< \brief (CAN0) Write Protect Status Register */ 48 #define REG_CAN0_MMR0 (0x400B4200U) /**< \brief (CAN0) Mailbox Mode Register (MB = 0) */ 49 #define REG_CAN0_MAM0 (0x400B4204U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 0) */ 50 #define REG_CAN0_MID0 (0x400B4208U) /**< \brief (CAN0) Mailbox ID Register (MB = 0) */ 51 #define REG_CAN0_MFID0 (0x400B420CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 0) */ 52 #define REG_CAN0_MSR0 (0x400B4210U) /**< \brief (CAN0) Mailbox Status Register (MB = 0) */ 53 #define REG_CAN0_MDL0 (0x400B4214U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 0) */ 54 #define REG_CAN0_MDH0 (0x400B4218U) /**< \brief (CAN0) Mailbox Data High Register (MB = 0) */ 55 #define REG_CAN0_MCR0 (0x400B421CU) /**< \brief (CAN0) Mailbox Control Register (MB = 0) */ 56 #define REG_CAN0_MMR1 (0x400B4220U) /**< \brief (CAN0) Mailbox Mode Register (MB = 1) */ 57 #define REG_CAN0_MAM1 (0x400B4224U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 1) */ 58 #define REG_CAN0_MID1 (0x400B4228U) /**< \brief (CAN0) Mailbox ID Register (MB = 1) */ 59 #define REG_CAN0_MFID1 (0x400B422CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 1) */ 60 #define REG_CAN0_MSR1 (0x400B4230U) /**< \brief (CAN0) Mailbox Status Register (MB = 1) */ 61 #define REG_CAN0_MDL1 (0x400B4234U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 1) */ 62 #define REG_CAN0_MDH1 (0x400B4238U) /**< \brief (CAN0) Mailbox Data High Register (MB = 1) */ 63 #define REG_CAN0_MCR1 (0x400B423CU) /**< \brief (CAN0) Mailbox Control Register (MB = 1) */ 64 #define REG_CAN0_MMR2 (0x400B4240U) /**< \brief (CAN0) Mailbox Mode Register (MB = 2) */ 65 #define REG_CAN0_MAM2 (0x400B4244U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 2) */ 66 #define REG_CAN0_MID2 (0x400B4248U) /**< \brief (CAN0) Mailbox ID Register (MB = 2) */ 67 #define REG_CAN0_MFID2 (0x400B424CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 2) */ 68 #define REG_CAN0_MSR2 (0x400B4250U) /**< \brief (CAN0) Mailbox Status Register (MB = 2) */ 69 #define REG_CAN0_MDL2 (0x400B4254U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 2) */ 70 #define REG_CAN0_MDH2 (0x400B4258U) /**< \brief (CAN0) Mailbox Data High Register (MB = 2) */ 71 #define REG_CAN0_MCR2 (0x400B425CU) /**< \brief (CAN0) Mailbox Control Register (MB = 2) */ 72 #define REG_CAN0_MMR3 (0x400B4260U) /**< \brief (CAN0) Mailbox Mode Register (MB = 3) */ 73 #define REG_CAN0_MAM3 (0x400B4264U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 3) */ 74 #define REG_CAN0_MID3 (0x400B4268U) /**< \brief (CAN0) Mailbox ID Register (MB = 3) */ 75 #define REG_CAN0_MFID3 (0x400B426CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 3) */ 76 #define REG_CAN0_MSR3 (0x400B4270U) /**< \brief (CAN0) Mailbox Status Register (MB = 3) */ 77 #define REG_CAN0_MDL3 (0x400B4274U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 3) */ 78 #define REG_CAN0_MDH3 (0x400B4278U) /**< \brief (CAN0) Mailbox Data High Register (MB = 3) */ 79 #define REG_CAN0_MCR3 (0x400B427CU) /**< \brief (CAN0) Mailbox Control Register (MB = 3) */ 80 #define REG_CAN0_MMR4 (0x400B4280U) /**< \brief (CAN0) Mailbox Mode Register (MB = 4) */ 81 #define REG_CAN0_MAM4 (0x400B4284U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 4) */ 82 #define REG_CAN0_MID4 (0x400B4288U) /**< \brief (CAN0) Mailbox ID Register (MB = 4) */ 83 #define REG_CAN0_MFID4 (0x400B428CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 4) */ 84 #define REG_CAN0_MSR4 (0x400B4290U) /**< \brief (CAN0) Mailbox Status Register (MB = 4) */ 85 #define REG_CAN0_MDL4 (0x400B4294U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 4) */ 86 #define REG_CAN0_MDH4 (0x400B4298U) /**< \brief (CAN0) Mailbox Data High Register (MB = 4) */ 87 #define REG_CAN0_MCR4 (0x400B429CU) /**< \brief (CAN0) Mailbox Control Register (MB = 4) */ 88 #define REG_CAN0_MMR5 (0x400B42A0U) /**< \brief (CAN0) Mailbox Mode Register (MB = 5) */ 89 #define REG_CAN0_MAM5 (0x400B42A4U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 5) */ 90 #define REG_CAN0_MID5 (0x400B42A8U) /**< \brief (CAN0) Mailbox ID Register (MB = 5) */ 91 #define REG_CAN0_MFID5 (0x400B42ACU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 5) */ 92 #define REG_CAN0_MSR5 (0x400B42B0U) /**< \brief (CAN0) Mailbox Status Register (MB = 5) */ 93 #define REG_CAN0_MDL5 (0x400B42B4U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 5) */ 94 #define REG_CAN0_MDH5 (0x400B42B8U) /**< \brief (CAN0) Mailbox Data High Register (MB = 5) */ 95 #define REG_CAN0_MCR5 (0x400B42BCU) /**< \brief (CAN0) Mailbox Control Register (MB = 5) */ 96 #define REG_CAN0_MMR6 (0x400B42C0U) /**< \brief (CAN0) Mailbox Mode Register (MB = 6) */ 97 #define REG_CAN0_MAM6 (0x400B42C4U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 6) */ 98 #define REG_CAN0_MID6 (0x400B42C8U) /**< \brief (CAN0) Mailbox ID Register (MB = 6) */ 99 #define REG_CAN0_MFID6 (0x400B42CCU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 6) */ 100 #define REG_CAN0_MSR6 (0x400B42D0U) /**< \brief (CAN0) Mailbox Status Register (MB = 6) */ 101 #define REG_CAN0_MDL6 (0x400B42D4U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 6) */ 102 #define REG_CAN0_MDH6 (0x400B42D8U) /**< \brief (CAN0) Mailbox Data High Register (MB = 6) */ 103 #define REG_CAN0_MCR6 (0x400B42DCU) /**< \brief (CAN0) Mailbox Control Register (MB = 6) */ 104 #define REG_CAN0_MMR7 (0x400B42E0U) /**< \brief (CAN0) Mailbox Mode Register (MB = 7) */ 105 #define REG_CAN0_MAM7 (0x400B42E4U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 7) */ 106 #define REG_CAN0_MID7 (0x400B42E8U) /**< \brief (CAN0) Mailbox ID Register (MB = 7) */ 107 #define REG_CAN0_MFID7 (0x400B42ECU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 7) */ 108 #define REG_CAN0_MSR7 (0x400B42F0U) /**< \brief (CAN0) Mailbox Status Register (MB = 7) */ 109 #define REG_CAN0_MDL7 (0x400B42F4U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 7) */ 110 #define REG_CAN0_MDH7 (0x400B42F8U) /**< \brief (CAN0) Mailbox Data High Register (MB = 7) */ 111 #define REG_CAN0_MCR7 (0x400B42FCU) /**< \brief (CAN0) Mailbox Control Register (MB = 7) */ 112 #else 113 #define REG_CAN0_MR (*(__IO uint32_t*)0x400B4000U) /**< \brief (CAN0) Mode Register */ 114 #define REG_CAN0_IER (*(__O uint32_t*)0x400B4004U) /**< \brief (CAN0) Interrupt Enable Register */ 115 #define REG_CAN0_IDR (*(__O uint32_t*)0x400B4008U) /**< \brief (CAN0) Interrupt Disable Register */ 116 #define REG_CAN0_IMR (*(__I uint32_t*)0x400B400CU) /**< \brief (CAN0) Interrupt Mask Register */ 117 #define REG_CAN0_SR (*(__I uint32_t*)0x400B4010U) /**< \brief (CAN0) Status Register */ 118 #define REG_CAN0_BR (*(__IO uint32_t*)0x400B4014U) /**< \brief (CAN0) Baudrate Register */ 119 #define REG_CAN0_TIM (*(__I uint32_t*)0x400B4018U) /**< \brief (CAN0) Timer Register */ 120 #define REG_CAN0_TIMESTP (*(__I uint32_t*)0x400B401CU) /**< \brief (CAN0) Timestamp Register */ 121 #define REG_CAN0_ECR (*(__I uint32_t*)0x400B4020U) /**< \brief (CAN0) Error Counter Register */ 122 #define REG_CAN0_TCR (*(__O uint32_t*)0x400B4024U) /**< \brief (CAN0) Transfer Command Register */ 123 #define REG_CAN0_ACR (*(__O uint32_t*)0x400B4028U) /**< \brief (CAN0) Abort Command Register */ 124 #define REG_CAN0_WPMR (*(__IO uint32_t*)0x400B40E4U) /**< \brief (CAN0) Write Protect Mode Register */ 125 #define REG_CAN0_WPSR (*(__I uint32_t*)0x400B40E8U) /**< \brief (CAN0) Write Protect Status Register */ 126 #define REG_CAN0_MMR0 (*(__IO uint32_t*)0x400B4200U) /**< \brief (CAN0) Mailbox Mode Register (MB = 0) */ 127 #define REG_CAN0_MAM0 (*(__IO uint32_t*)0x400B4204U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 0) */ 128 #define REG_CAN0_MID0 (*(__IO uint32_t*)0x400B4208U) /**< \brief (CAN0) Mailbox ID Register (MB = 0) */ 129 #define REG_CAN0_MFID0 (*(__I uint32_t*)0x400B420CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 0) */ 130 #define REG_CAN0_MSR0 (*(__I uint32_t*)0x400B4210U) /**< \brief (CAN0) Mailbox Status Register (MB = 0) */ 131 #define REG_CAN0_MDL0 (*(__IO uint32_t*)0x400B4214U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 0) */ 132 #define REG_CAN0_MDH0 (*(__IO uint32_t*)0x400B4218U) /**< \brief (CAN0) Mailbox Data High Register (MB = 0) */ 133 #define REG_CAN0_MCR0 (*(__O uint32_t*)0x400B421CU) /**< \brief (CAN0) Mailbox Control Register (MB = 0) */ 134 #define REG_CAN0_MMR1 (*(__IO uint32_t*)0x400B4220U) /**< \brief (CAN0) Mailbox Mode Register (MB = 1) */ 135 #define REG_CAN0_MAM1 (*(__IO uint32_t*)0x400B4224U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 1) */ 136 #define REG_CAN0_MID1 (*(__IO uint32_t*)0x400B4228U) /**< \brief (CAN0) Mailbox ID Register (MB = 1) */ 137 #define REG_CAN0_MFID1 (*(__I uint32_t*)0x400B422CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 1) */ 138 #define REG_CAN0_MSR1 (*(__I uint32_t*)0x400B4230U) /**< \brief (CAN0) Mailbox Status Register (MB = 1) */ 139 #define REG_CAN0_MDL1 (*(__IO uint32_t*)0x400B4234U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 1) */ 140 #define REG_CAN0_MDH1 (*(__IO uint32_t*)0x400B4238U) /**< \brief (CAN0) Mailbox Data High Register (MB = 1) */ 141 #define REG_CAN0_MCR1 (*(__O uint32_t*)0x400B423CU) /**< \brief (CAN0) Mailbox Control Register (MB = 1) */ 142 #define REG_CAN0_MMR2 (*(__IO uint32_t*)0x400B4240U) /**< \brief (CAN0) Mailbox Mode Register (MB = 2) */ 143 #define REG_CAN0_MAM2 (*(__IO uint32_t*)0x400B4244U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 2) */ 144 #define REG_CAN0_MID2 (*(__IO uint32_t*)0x400B4248U) /**< \brief (CAN0) Mailbox ID Register (MB = 2) */ 145 #define REG_CAN0_MFID2 (*(__I uint32_t*)0x400B424CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 2) */ 146 #define REG_CAN0_MSR2 (*(__I uint32_t*)0x400B4250U) /**< \brief (CAN0) Mailbox Status Register (MB = 2) */ 147 #define REG_CAN0_MDL2 (*(__IO uint32_t*)0x400B4254U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 2) */ 148 #define REG_CAN0_MDH2 (*(__IO uint32_t*)0x400B4258U) /**< \brief (CAN0) Mailbox Data High Register (MB = 2) */ 149 #define REG_CAN0_MCR2 (*(__O uint32_t*)0x400B425CU) /**< \brief (CAN0) Mailbox Control Register (MB = 2) */ 150 #define REG_CAN0_MMR3 (*(__IO uint32_t*)0x400B4260U) /**< \brief (CAN0) Mailbox Mode Register (MB = 3) */ 151 #define REG_CAN0_MAM3 (*(__IO uint32_t*)0x400B4264U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 3) */ 152 #define REG_CAN0_MID3 (*(__IO uint32_t*)0x400B4268U) /**< \brief (CAN0) Mailbox ID Register (MB = 3) */ 153 #define REG_CAN0_MFID3 (*(__I uint32_t*)0x400B426CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 3) */ 154 #define REG_CAN0_MSR3 (*(__I uint32_t*)0x400B4270U) /**< \brief (CAN0) Mailbox Status Register (MB = 3) */ 155 #define REG_CAN0_MDL3 (*(__IO uint32_t*)0x400B4274U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 3) */ 156 #define REG_CAN0_MDH3 (*(__IO uint32_t*)0x400B4278U) /**< \brief (CAN0) Mailbox Data High Register (MB = 3) */ 157 #define REG_CAN0_MCR3 (*(__O uint32_t*)0x400B427CU) /**< \brief (CAN0) Mailbox Control Register (MB = 3) */ 158 #define REG_CAN0_MMR4 (*(__IO uint32_t*)0x400B4280U) /**< \brief (CAN0) Mailbox Mode Register (MB = 4) */ 159 #define REG_CAN0_MAM4 (*(__IO uint32_t*)0x400B4284U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 4) */ 160 #define REG_CAN0_MID4 (*(__IO uint32_t*)0x400B4288U) /**< \brief (CAN0) Mailbox ID Register (MB = 4) */ 161 #define REG_CAN0_MFID4 (*(__I uint32_t*)0x400B428CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 4) */ 162 #define REG_CAN0_MSR4 (*(__I uint32_t*)0x400B4290U) /**< \brief (CAN0) Mailbox Status Register (MB = 4) */ 163 #define REG_CAN0_MDL4 (*(__IO uint32_t*)0x400B4294U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 4) */ 164 #define REG_CAN0_MDH4 (*(__IO uint32_t*)0x400B4298U) /**< \brief (CAN0) Mailbox Data High Register (MB = 4) */ 165 #define REG_CAN0_MCR4 (*(__O uint32_t*)0x400B429CU) /**< \brief (CAN0) Mailbox Control Register (MB = 4) */ 166 #define REG_CAN0_MMR5 (*(__IO uint32_t*)0x400B42A0U) /**< \brief (CAN0) Mailbox Mode Register (MB = 5) */ 167 #define REG_CAN0_MAM5 (*(__IO uint32_t*)0x400B42A4U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 5) */ 168 #define REG_CAN0_MID5 (*(__IO uint32_t*)0x400B42A8U) /**< \brief (CAN0) Mailbox ID Register (MB = 5) */ 169 #define REG_CAN0_MFID5 (*(__I uint32_t*)0x400B42ACU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 5) */ 170 #define REG_CAN0_MSR5 (*(__I uint32_t*)0x400B42B0U) /**< \brief (CAN0) Mailbox Status Register (MB = 5) */ 171 #define REG_CAN0_MDL5 (*(__IO uint32_t*)0x400B42B4U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 5) */ 172 #define REG_CAN0_MDH5 (*(__IO uint32_t*)0x400B42B8U) /**< \brief (CAN0) Mailbox Data High Register (MB = 5) */ 173 #define REG_CAN0_MCR5 (*(__O uint32_t*)0x400B42BCU) /**< \brief (CAN0) Mailbox Control Register (MB = 5) */ 174 #define REG_CAN0_MMR6 (*(__IO uint32_t*)0x400B42C0U) /**< \brief (CAN0) Mailbox Mode Register (MB = 6) */ 175 #define REG_CAN0_MAM6 (*(__IO uint32_t*)0x400B42C4U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 6) */ 176 #define REG_CAN0_MID6 (*(__IO uint32_t*)0x400B42C8U) /**< \brief (CAN0) Mailbox ID Register (MB = 6) */ 177 #define REG_CAN0_MFID6 (*(__I uint32_t*)0x400B42CCU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 6) */ 178 #define REG_CAN0_MSR6 (*(__I uint32_t*)0x400B42D0U) /**< \brief (CAN0) Mailbox Status Register (MB = 6) */ 179 #define REG_CAN0_MDL6 (*(__IO uint32_t*)0x400B42D4U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 6) */ 180 #define REG_CAN0_MDH6 (*(__IO uint32_t*)0x400B42D8U) /**< \brief (CAN0) Mailbox Data High Register (MB = 6) */ 181 #define REG_CAN0_MCR6 (*(__O uint32_t*)0x400B42DCU) /**< \brief (CAN0) Mailbox Control Register (MB = 6) */ 182 #define REG_CAN0_MMR7 (*(__IO uint32_t*)0x400B42E0U) /**< \brief (CAN0) Mailbox Mode Register (MB = 7) */ 183 #define REG_CAN0_MAM7 (*(__IO uint32_t*)0x400B42E4U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 7) */ 184 #define REG_CAN0_MID7 (*(__IO uint32_t*)0x400B42E8U) /**< \brief (CAN0) Mailbox ID Register (MB = 7) */ 185 #define REG_CAN0_MFID7 (*(__I uint32_t*)0x400B42ECU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 7) */ 186 #define REG_CAN0_MSR7 (*(__I uint32_t*)0x400B42F0U) /**< \brief (CAN0) Mailbox Status Register (MB = 7) */ 187 #define REG_CAN0_MDL7 (*(__IO uint32_t*)0x400B42F4U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 7) */ 188 #define REG_CAN0_MDH7 (*(__IO uint32_t*)0x400B42F8U) /**< \brief (CAN0) Mailbox Data High Register (MB = 7) */ 189 #define REG_CAN0_MCR7 (*(__O uint32_t*)0x400B42FCU) /**< \brief (CAN0) Mailbox Control Register (MB = 7) */ 190 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 191 192 #endif /* _SAM3XA_CAN0_INSTANCE_ */ 193
