1 /* 2 * Autogenerated file 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #include <dt-bindings/pinctrl/atmel_sam_pinctrl.h> 8 9 /* pa6_gpio */ 10 #define PA6_GPIO \ 11 SAM_PINMUX(a, 6, gpio, gpio) 12 13 /* pa6a_eic_extint6 */ 14 #define PA6A_EIC_EXTINT6 \ 15 SAM_PINMUX(a, 6, a, periph) 16 17 /* pa6b_adc_ain6 */ 18 #define PA6B_ADC_AIN6 \ 19 SAM_PINMUX(a, 6, b, periph) 20 21 /* pa6b_ac_ain2 */ 22 #define PA6B_AC_AIN2 \ 23 SAM_PINMUX(a, 6, b, periph) 24 25 /* pa6b_ptc_y4 */ 26 #define PA6B_PTC_Y4 \ 27 SAM_PINMUX(a, 6, b, periph) 28 29 /* pa6d_sercom0_pad2 */ 30 #define PA6D_SERCOM0_PAD2 \ 31 SAM_PINMUX(a, 6, d, periph) 32 33 /* pa6e_tcc1_wo0 */ 34 #define PA6E_TCC1_WO0 \ 35 SAM_PINMUX(a, 6, e, periph) 36 37 /* pa7_gpio */ 38 #define PA7_GPIO \ 39 SAM_PINMUX(a, 7, gpio, gpio) 40 41 /* pa7a_eic_extint7 */ 42 #define PA7A_EIC_EXTINT7 \ 43 SAM_PINMUX(a, 7, a, periph) 44 45 /* pa7b_adc_ain7 */ 46 #define PA7B_ADC_AIN7 \ 47 SAM_PINMUX(a, 7, b, periph) 48 49 /* pa7b_ac_ain3 */ 50 #define PA7B_AC_AIN3 \ 51 SAM_PINMUX(a, 7, b, periph) 52 53 /* pa7b_ptc_y5 */ 54 #define PA7B_PTC_Y5 \ 55 SAM_PINMUX(a, 7, b, periph) 56 57 /* pa7d_sercom0_pad3 */ 58 #define PA7D_SERCOM0_PAD3 \ 59 SAM_PINMUX(a, 7, d, periph) 60 61 /* pa7e_tcc1_wo1 */ 62 #define PA7E_TCC1_WO1 \ 63 SAM_PINMUX(a, 7, e, periph) 64 65 /* pa8_gpio */ 66 #define PA8_GPIO \ 67 SAM_PINMUX(a, 8, gpio, gpio) 68 69 /* pa8a_eic_nmi */ 70 #define PA8A_EIC_NMI \ 71 SAM_PINMUX(a, 8, a, periph) 72 73 /* pa8b_adc_ain16 */ 74 #define PA8B_ADC_AIN16 \ 75 SAM_PINMUX(a, 8, b, periph) 76 77 /* pa8b_ptc_x0 */ 78 #define PA8B_PTC_X0 \ 79 SAM_PINMUX(a, 8, b, periph) 80 81 /* pa8c_sercom0_pad0 */ 82 #define PA8C_SERCOM0_PAD0 \ 83 SAM_PINMUX(a, 8, c, periph) 84 85 /* pa8d_sercom2_pad0 */ 86 #define PA8D_SERCOM2_PAD0 \ 87 SAM_PINMUX(a, 8, d, periph) 88 89 /* pa8e_tcc0_wo0 */ 90 #define PA8E_TCC0_WO0 \ 91 SAM_PINMUX(a, 8, e, periph) 92 93 /* pa8f_radio_fectrl0 */ 94 #define PA8F_RADIO_FECTRL0 \ 95 SAM_PINMUX(a, 8, f, periph) 96 97 /* pa9_gpio */ 98 #define PA9_GPIO \ 99 SAM_PINMUX(a, 9, gpio, gpio) 100 101 /* pa9a_eic_extint9 */ 102 #define PA9A_EIC_EXTINT9 \ 103 SAM_PINMUX(a, 9, a, periph) 104 105 /* pa9b_adc_ain17 */ 106 #define PA9B_ADC_AIN17 \ 107 SAM_PINMUX(a, 9, b, periph) 108 109 /* pa9b_ptc_x1 */ 110 #define PA9B_PTC_X1 \ 111 SAM_PINMUX(a, 9, b, periph) 112 113 /* pa9c_sercom0_pad1 */ 114 #define PA9C_SERCOM0_PAD1 \ 115 SAM_PINMUX(a, 9, c, periph) 116 117 /* pa9d_sercom2_pad1 */ 118 #define PA9D_SERCOM2_PAD1 \ 119 SAM_PINMUX(a, 9, d, periph) 120 121 /* pa9e_tcc0_wo1 */ 122 #define PA9E_TCC0_WO1 \ 123 SAM_PINMUX(a, 9, e, periph) 124 125 /* pa9f_radio_fectrl1 */ 126 #define PA9F_RADIO_FECTRL1 \ 127 SAM_PINMUX(a, 9, f, periph) 128 129 /* pa10_gpio */ 130 #define PA10_GPIO \ 131 SAM_PINMUX(a, 10, gpio, gpio) 132 133 /* pa10a_eic_extint10 */ 134 #define PA10A_EIC_EXTINT10 \ 135 SAM_PINMUX(a, 10, a, periph) 136 137 /* pa11_gpio */ 138 #define PA11_GPIO \ 139 SAM_PINMUX(a, 11, gpio, gpio) 140 141 /* pa11a_eic_extint11 */ 142 #define PA11A_EIC_EXTINT11 \ 143 SAM_PINMUX(a, 11, a, periph) 144 145 /* pa14_gpio */ 146 #define PA14_GPIO \ 147 SAM_PINMUX(a, 14, gpio, gpio) 148 149 /* pa14a_eic_extint14 */ 150 #define PA14A_EIC_EXTINT14 \ 151 SAM_PINMUX(a, 14, a, periph) 152 153 /* pa14c_sercom2_pad2 */ 154 #define PA14C_SERCOM2_PAD2 \ 155 SAM_PINMUX(a, 14, c, periph) 156 157 /* pa14e_tc3_wo0 */ 158 #define PA14E_TC3_WO0 \ 159 SAM_PINMUX(a, 14, e, periph) 160 161 /* pa14f_radio_fectrl4 */ 162 #define PA14F_RADIO_FECTRL4 \ 163 SAM_PINMUX(a, 14, f, periph) 164 165 /* pa14h_gclk_io0 */ 166 #define PA14H_GCLK_IO0 \ 167 SAM_PINMUX(a, 14, h, periph) 168 169 /* pa15_gpio */ 170 #define PA15_GPIO \ 171 SAM_PINMUX(a, 15, gpio, gpio) 172 173 /* pa15a_eic_extint15 */ 174 #define PA15A_EIC_EXTINT15 \ 175 SAM_PINMUX(a, 15, a, periph) 176 177 /* pa15c_sercom2_pad3 */ 178 #define PA15C_SERCOM2_PAD3 \ 179 SAM_PINMUX(a, 15, c, periph) 180 181 /* pa15e_tc3_wo1 */ 182 #define PA15E_TC3_WO1 \ 183 SAM_PINMUX(a, 15, e, periph) 184 185 /* pa15f_radio_fectrl5 */ 186 #define PA15F_RADIO_FECTRL5 \ 187 SAM_PINMUX(a, 15, f, periph) 188 189 /* pa15h_gclk_io1 */ 190 #define PA15H_GCLK_IO1 \ 191 SAM_PINMUX(a, 15, h, periph) 192 193 /* pa16_gpio */ 194 #define PA16_GPIO \ 195 SAM_PINMUX(a, 16, gpio, gpio) 196 197 /* pa16b_ptc_x4 */ 198 #define PA16B_PTC_X4 \ 199 SAM_PINMUX(a, 16, b, periph) 200 201 /* pa16c_sercom1_pad0 */ 202 #define PA16C_SERCOM1_PAD0 \ 203 SAM_PINMUX(a, 16, c, periph) 204 205 /* pa16d_sercom3_pad0 */ 206 #define PA16D_SERCOM3_PAD0 \ 207 SAM_PINMUX(a, 16, d, periph) 208 209 /* pa16e_tcc2_wo0 */ 210 #define PA16E_TCC2_WO0 \ 211 SAM_PINMUX(a, 16, e, periph) 212 213 /* pa16f_tcc0_wo6 */ 214 #define PA16F_TCC0_WO6 \ 215 SAM_PINMUX(a, 16, f, periph) 216 217 /* pa16h_gclk_io2 */ 218 #define PA16H_GCLK_IO2 \ 219 SAM_PINMUX(a, 16, h, periph) 220 221 /* pa17_gpio */ 222 #define PA17_GPIO \ 223 SAM_PINMUX(a, 17, gpio, gpio) 224 225 /* pa17a_eic_extint1 */ 226 #define PA17A_EIC_EXTINT1 \ 227 SAM_PINMUX(a, 17, a, periph) 228 229 /* pa17b_ptc_x5 */ 230 #define PA17B_PTC_X5 \ 231 SAM_PINMUX(a, 17, b, periph) 232 233 /* pa17c_sercom1_pad1 */ 234 #define PA17C_SERCOM1_PAD1 \ 235 SAM_PINMUX(a, 17, c, periph) 236 237 /* pa17d_sercom3_pad1 */ 238 #define PA17D_SERCOM3_PAD1 \ 239 SAM_PINMUX(a, 17, d, periph) 240 241 /* pa17e_tcc2_wo1 */ 242 #define PA17E_TCC2_WO1 \ 243 SAM_PINMUX(a, 17, e, periph) 244 245 /* pa17f_tcc0_wo7 */ 246 #define PA17F_TCC0_WO7 \ 247 SAM_PINMUX(a, 17, f, periph) 248 249 /* pa17h_gclk_io3 */ 250 #define PA17H_GCLK_IO3 \ 251 SAM_PINMUX(a, 17, h, periph) 252 253 /* pa18_gpio */ 254 #define PA18_GPIO \ 255 SAM_PINMUX(a, 18, gpio, gpio) 256 257 /* pa18a_eic_extint2 */ 258 #define PA18A_EIC_EXTINT2 \ 259 SAM_PINMUX(a, 18, a, periph) 260 261 /* pa18b_ptc_x6 */ 262 #define PA18B_PTC_X6 \ 263 SAM_PINMUX(a, 18, b, periph) 264 265 /* pa18c_sercom1_pad2 */ 266 #define PA18C_SERCOM1_PAD2 \ 267 SAM_PINMUX(a, 18, c, periph) 268 269 /* pa18d_sercom3_pad2 */ 270 #define PA18D_SERCOM3_PAD2 \ 271 SAM_PINMUX(a, 18, d, periph) 272 273 /* pa18e_tc3_wo0 */ 274 #define PA18E_TC3_WO0 \ 275 SAM_PINMUX(a, 18, e, periph) 276 277 /* pa18f_tcc0_wo2 */ 278 #define PA18F_TCC0_WO2 \ 279 SAM_PINMUX(a, 18, f, periph) 280 281 /* pa18h_ac_cmp0 */ 282 #define PA18H_AC_CMP0 \ 283 SAM_PINMUX(a, 18, h, periph) 284 285 /* pa19_gpio */ 286 #define PA19_GPIO \ 287 SAM_PINMUX(a, 19, gpio, gpio) 288 289 /* pa19a_eic_extint3 */ 290 #define PA19A_EIC_EXTINT3 \ 291 SAM_PINMUX(a, 19, a, periph) 292 293 /* pa19b_ptc_x7 */ 294 #define PA19B_PTC_X7 \ 295 SAM_PINMUX(a, 19, b, periph) 296 297 /* pa19c_sercom1_pad3 */ 298 #define PA19C_SERCOM1_PAD3 \ 299 SAM_PINMUX(a, 19, c, periph) 300 301 /* pa19d_sercom3_pad3 */ 302 #define PA19D_SERCOM3_PAD3 \ 303 SAM_PINMUX(a, 19, d, periph) 304 305 /* pa19e_tc3_wo1 */ 306 #define PA19E_TC3_WO1 \ 307 SAM_PINMUX(a, 19, e, periph) 308 309 /* pa19f_tcc0_wo3 */ 310 #define PA19F_TCC0_WO3 \ 311 SAM_PINMUX(a, 19, f, periph) 312 313 /* pa19h_ac_cmp1 */ 314 #define PA19H_AC_CMP1 \ 315 SAM_PINMUX(a, 19, h, periph) 316 317 /* pa20_gpio */ 318 #define PA20_GPIO \ 319 SAM_PINMUX(a, 20, gpio, gpio) 320 321 /* pa24_gpio */ 322 #define PA24_GPIO \ 323 SAM_PINMUX(a, 24, gpio, gpio) 324 325 /* pa24a_eic_extint12 */ 326 #define PA24A_EIC_EXTINT12 \ 327 SAM_PINMUX(a, 24, a, periph) 328 329 /* pa24c_sercom3_pad2 */ 330 #define PA24C_SERCOM3_PAD2 \ 331 SAM_PINMUX(a, 24, c, periph) 332 333 /* pa24d_sercom5_pad2 */ 334 #define PA24D_SERCOM5_PAD2 \ 335 SAM_PINMUX(a, 24, d, periph) 336 337 /* pa24e_tc5_wo0 */ 338 #define PA24E_TC5_WO0 \ 339 SAM_PINMUX(a, 24, e, periph) 340 341 /* pa24f_tcc1_wo2 */ 342 #define PA24F_TCC1_WO2 \ 343 SAM_PINMUX(a, 24, f, periph) 344 345 /* pa24g_usb_dm */ 346 #define PA24G_USB_DM \ 347 SAM_PINMUX(a, 24, g, periph) 348 349 /* pa25_gpio */ 350 #define PA25_GPIO \ 351 SAM_PINMUX(a, 25, gpio, gpio) 352 353 /* pa25a_eic_extint13 */ 354 #define PA25A_EIC_EXTINT13 \ 355 SAM_PINMUX(a, 25, a, periph) 356 357 /* pa25b_ptc_x11 */ 358 #define PA25B_PTC_X11 \ 359 SAM_PINMUX(a, 25, b, periph) 360 361 /* pa25c_sercom3_pad3 */ 362 #define PA25C_SERCOM3_PAD3 \ 363 SAM_PINMUX(a, 25, c, periph) 364 365 /* pa25d_sercom5_pad3 */ 366 #define PA25D_SERCOM5_PAD3 \ 367 SAM_PINMUX(a, 25, d, periph) 368 369 /* pa25e_tc5_wo1 */ 370 #define PA25E_TC5_WO1 \ 371 SAM_PINMUX(a, 25, e, periph) 372 373 /* pa25f_tcc1_wo3 */ 374 #define PA25F_TCC1_WO3 \ 375 SAM_PINMUX(a, 25, f, periph) 376 377 /* pa25g_usb_dp */ 378 #define PA25G_USB_DP \ 379 SAM_PINMUX(a, 25, g, periph) 380 381 /* pa27_gpio */ 382 #define PA27_GPIO \ 383 SAM_PINMUX(a, 27, gpio, gpio) 384 385 /* pa27a_eic_extint15 */ 386 #define PA27A_EIC_EXTINT15 \ 387 SAM_PINMUX(a, 27, a, periph) 388 389 /* pa27f_sercom3_pad0 */ 390 #define PA27F_SERCOM3_PAD0 \ 391 SAM_PINMUX(a, 27, f, periph) 392 393 /* pa27h_gclk_io0 */ 394 #define PA27H_GCLK_IO0 \ 395 SAM_PINMUX(a, 27, h, periph) 396 397 /* pa28_gpio */ 398 #define PA28_GPIO \ 399 SAM_PINMUX(a, 28, gpio, gpio) 400 401 /* pa28a_eic_extint8 */ 402 #define PA28A_EIC_EXTINT8 \ 403 SAM_PINMUX(a, 28, a, periph) 404 405 /* pa28f_sercom3_pad1 */ 406 #define PA28F_SERCOM3_PAD1 \ 407 SAM_PINMUX(a, 28, f, periph) 408 409 /* pa28h_gclk_io0 */ 410 #define PA28H_GCLK_IO0 \ 411 SAM_PINMUX(a, 28, h, periph) 412 413 /* pa30_gpio */ 414 #define PA30_GPIO \ 415 SAM_PINMUX(a, 30, gpio, gpio) 416 417 /* pa30a_eic_extint10 */ 418 #define PA30A_EIC_EXTINT10 \ 419 SAM_PINMUX(a, 30, a, periph) 420 421 /* pa30d_sercom1_pad2 */ 422 #define PA30D_SERCOM1_PAD2 \ 423 SAM_PINMUX(a, 30, d, periph) 424 425 /* pa30e_tcc1_wo0 */ 426 #define PA30E_TCC1_WO0 \ 427 SAM_PINMUX(a, 30, e, periph) 428 429 /* pa30g_swd_clk */ 430 #define PA30G_SWD_CLK \ 431 SAM_PINMUX(a, 30, g, periph) 432 433 /* pa30h_gclk_io0 */ 434 #define PA30H_GCLK_IO0 \ 435 SAM_PINMUX(a, 30, h, periph) 436 437 /* pa31_gpio */ 438 #define PA31_GPIO \ 439 SAM_PINMUX(a, 31, gpio, gpio) 440 441 /* pa31a_eic_extint11 */ 442 #define PA31A_EIC_EXTINT11 \ 443 SAM_PINMUX(a, 31, a, periph) 444 445 /* pa31d_sercom1_pad3 */ 446 #define PA31D_SERCOM1_PAD3 \ 447 SAM_PINMUX(a, 31, d, periph) 448 449 /* pa31e_tcc1_wo1 */ 450 #define PA31E_TCC1_WO1 \ 451 SAM_PINMUX(a, 31, e, periph) 452 453 /* pa31g_swd_io */ 454 #define PA31G_SWD_IO \ 455 SAM_PINMUX(a, 31, g, periph) 456 457 /* pb0_gpio */ 458 #define PB0_GPIO \ 459 SAM_PINMUX(b, 0, gpio, gpio) 460 461 /* pb0a_eic_extint0 */ 462 #define PB0A_EIC_EXTINT0 \ 463 SAM_PINMUX(b, 0, a, periph) 464 465 /* pb15_gpio */ 466 #define PB15_GPIO \ 467 SAM_PINMUX(b, 15, gpio, gpio) 468 469 /* pb16_gpio */ 470 #define PB16_GPIO \ 471 SAM_PINMUX(b, 16, gpio, gpio) 472 473 /* pb16a_eic_extint0 */ 474 #define PB16A_EIC_EXTINT0 \ 475 SAM_PINMUX(b, 16, a, periph) 476 477 /* pb17_gpio */ 478 #define PB17_GPIO \ 479 SAM_PINMUX(b, 17, gpio, gpio) 480 481 /* pb17a_eic_extint1 */ 482 #define PB17A_EIC_EXTINT1 \ 483 SAM_PINMUX(b, 17, a, periph) 484 485 /* pb30_gpio */ 486 #define PB30_GPIO \ 487 SAM_PINMUX(b, 30, gpio, gpio) 488 489 /* pb30f_sercom4_pad2 */ 490 #define PB30F_SERCOM4_PAD2 \ 491 SAM_PINMUX(b, 30, f, periph) 492 493 /* pb31_gpio */ 494 #define PB31_GPIO \ 495 SAM_PINMUX(b, 31, gpio, gpio) 496 497 /* pb31f_sercom4_pad1 */ 498 #define PB31F_SERCOM4_PAD1 \ 499 SAM_PINMUX(b, 31, f, periph) 500 501 /* pc16_gpio */ 502 #define PC16_GPIO \ 503 SAM_PINMUX(c, 16, gpio, gpio) 504 505 /* pc16f_glkc_io1 */ 506 #define PC16F_GLKC_IO1 \ 507 SAM_PINMUX(c, 16, f, periph) 508 509 /* pc18_gpio */ 510 #define PC18_GPIO \ 511 SAM_PINMUX(c, 18, gpio, gpio) 512 513 /* pc18f_sercom4_pad3 */ 514 #define PC18F_SERCOM4_PAD3 \ 515 SAM_PINMUX(c, 18, f, periph) 516 517 /* pc19_gpio */ 518 #define PC19_GPIO \ 519 SAM_PINMUX(c, 19, gpio, gpio) 520 521 /* pc19f_sercom4_pad0 */ 522 #define PC19F_SERCOM4_PAD0 \ 523 SAM_PINMUX(c, 19, f, periph) 524
