1 /* 2 * Autogenerated file 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #include <dt-bindings/pinctrl/atmel_sam_pinctrl.h> 8 9 /* pa0_gpio */ 10 #define PA0_GPIO \ 11 SAM_PINMUX(a, 0, gpio, gpio) 12 13 /* pa0a_eic_extint0 */ 14 #define PA0A_EIC_EXTINT0 \ 15 SAM_PINMUX(a, 0, a, periph) 16 17 /* pa0d_sercom1_pad0 */ 18 #define PA0D_SERCOM1_PAD0 \ 19 SAM_PINMUX(a, 0, d, periph) 20 21 /* pa0e_tc2_wo0 */ 22 #define PA0E_TC2_WO0 \ 23 SAM_PINMUX(a, 0, e, periph) 24 25 /* pa1_gpio */ 26 #define PA1_GPIO \ 27 SAM_PINMUX(a, 1, gpio, gpio) 28 29 /* pa1a_eic_extint1 */ 30 #define PA1A_EIC_EXTINT1 \ 31 SAM_PINMUX(a, 1, a, periph) 32 33 /* pa1d_sercom1_pad1 */ 34 #define PA1D_SERCOM1_PAD1 \ 35 SAM_PINMUX(a, 1, d, periph) 36 37 /* pa1e_tc2_wo1 */ 38 #define PA1E_TC2_WO1 \ 39 SAM_PINMUX(a, 1, e, periph) 40 41 /* pa2_gpio */ 42 #define PA2_GPIO \ 43 SAM_PINMUX(a, 2, gpio, gpio) 44 45 /* pa2a_eic_extint2 */ 46 #define PA2A_EIC_EXTINT2 \ 47 SAM_PINMUX(a, 2, a, periph) 48 49 /* pa2b_adc0_ain0 */ 50 #define PA2B_ADC0_AIN0 \ 51 SAM_PINMUX(a, 2, b, periph) 52 53 /* pa2b_dac_vout0 */ 54 #define PA2B_DAC_VOUT0 \ 55 SAM_PINMUX(a, 2, b, periph) 56 57 /* pa3_gpio */ 58 #define PA3_GPIO \ 59 SAM_PINMUX(a, 3, gpio, gpio) 60 61 /* pa3a_eic_extint3 */ 62 #define PA3A_EIC_EXTINT3 \ 63 SAM_PINMUX(a, 3, a, periph) 64 65 /* pa3b_anaref_vrefa */ 66 #define PA3B_ANAREF_VREFA \ 67 SAM_PINMUX(a, 3, b, periph) 68 69 /* pa3b_adc0_ain1 */ 70 #define PA3B_ADC0_AIN1 \ 71 SAM_PINMUX(a, 3, b, periph) 72 73 /* pa3b_ptc_xy0 */ 74 #define PA3B_PTC_XY0 \ 75 SAM_PINMUX(a, 3, b, periph) 76 77 /* pa4_gpio */ 78 #define PA4_GPIO \ 79 SAM_PINMUX(a, 4, gpio, gpio) 80 81 /* pa4a_eic_extint4 */ 82 #define PA4A_EIC_EXTINT4 \ 83 SAM_PINMUX(a, 4, a, periph) 84 85 /* pa4b_anaref_vrefb */ 86 #define PA4B_ANAREF_VREFB \ 87 SAM_PINMUX(a, 4, b, periph) 88 89 /* pa4b_adc0_ain4 */ 90 #define PA4B_ADC0_AIN4 \ 91 SAM_PINMUX(a, 4, b, periph) 92 93 /* pa4b_ac_ain0 */ 94 #define PA4B_AC_AIN0 \ 95 SAM_PINMUX(a, 4, b, periph) 96 97 /* pa4b_ptc_xy3 */ 98 #define PA4B_PTC_XY3 \ 99 SAM_PINMUX(a, 4, b, periph) 100 101 /* pa4d_sercom0_pad0 */ 102 #define PA4D_SERCOM0_PAD0 \ 103 SAM_PINMUX(a, 4, d, periph) 104 105 /* pa4e_tc0_wo0 */ 106 #define PA4E_TC0_WO0 \ 107 SAM_PINMUX(a, 4, e, periph) 108 109 /* pa4n_ccl_in0 */ 110 #define PA4N_CCL_IN0 \ 111 SAM_PINMUX(a, 4, n, periph) 112 113 /* pa5_gpio */ 114 #define PA5_GPIO \ 115 SAM_PINMUX(a, 5, gpio, gpio) 116 117 /* pa5a_eic_extint5 */ 118 #define PA5A_EIC_EXTINT5 \ 119 SAM_PINMUX(a, 5, a, periph) 120 121 /* pa5b_adc0_ain5 */ 122 #define PA5B_ADC0_AIN5 \ 123 SAM_PINMUX(a, 5, b, periph) 124 125 /* pa5b_ac_ain1 */ 126 #define PA5B_AC_AIN1 \ 127 SAM_PINMUX(a, 5, b, periph) 128 129 /* pa5b_dac_vout1 */ 130 #define PA5B_DAC_VOUT1 \ 131 SAM_PINMUX(a, 5, b, periph) 132 133 /* pa5d_sercom0_pad1 */ 134 #define PA5D_SERCOM0_PAD1 \ 135 SAM_PINMUX(a, 5, d, periph) 136 137 /* pa5e_tc0_wo1 */ 138 #define PA5E_TC0_WO1 \ 139 SAM_PINMUX(a, 5, e, periph) 140 141 /* pa5n_ccl_in1 */ 142 #define PA5N_CCL_IN1 \ 143 SAM_PINMUX(a, 5, n, periph) 144 145 /* pa6_gpio */ 146 #define PA6_GPIO \ 147 SAM_PINMUX(a, 6, gpio, gpio) 148 149 /* pa6a_eic_extint6 */ 150 #define PA6A_EIC_EXTINT6 \ 151 SAM_PINMUX(a, 6, a, periph) 152 153 /* pa6b_anaref_vrefc */ 154 #define PA6B_ANAREF_VREFC \ 155 SAM_PINMUX(a, 6, b, periph) 156 157 /* pa6b_adc0_ain6 */ 158 #define PA6B_ADC0_AIN6 \ 159 SAM_PINMUX(a, 6, b, periph) 160 161 /* pa6b_ac_ain2 */ 162 #define PA6B_AC_AIN2 \ 163 SAM_PINMUX(a, 6, b, periph) 164 165 /* pa6b_ptc_xy4 */ 166 #define PA6B_PTC_XY4 \ 167 SAM_PINMUX(a, 6, b, periph) 168 169 /* pa6d_sercom0_pad2 */ 170 #define PA6D_SERCOM0_PAD2 \ 171 SAM_PINMUX(a, 6, d, periph) 172 173 /* pa6e_tc1_wo0 */ 174 #define PA6E_TC1_WO0 \ 175 SAM_PINMUX(a, 6, e, periph) 176 177 /* pa6i_sdhc0_cd */ 178 #define PA6I_SDHC0_CD \ 179 SAM_PINMUX(a, 6, i, periph) 180 181 /* pa6n_ccl_in2 */ 182 #define PA6N_CCL_IN2 \ 183 SAM_PINMUX(a, 6, n, periph) 184 185 /* pa7_gpio */ 186 #define PA7_GPIO \ 187 SAM_PINMUX(a, 7, gpio, gpio) 188 189 /* pa7a_eic_extint7 */ 190 #define PA7A_EIC_EXTINT7 \ 191 SAM_PINMUX(a, 7, a, periph) 192 193 /* pa7b_adc0_ain7 */ 194 #define PA7B_ADC0_AIN7 \ 195 SAM_PINMUX(a, 7, b, periph) 196 197 /* pa7b_ac_ain3 */ 198 #define PA7B_AC_AIN3 \ 199 SAM_PINMUX(a, 7, b, periph) 200 201 /* pa7b_ptc_xy5 */ 202 #define PA7B_PTC_XY5 \ 203 SAM_PINMUX(a, 7, b, periph) 204 205 /* pa7d_sercom0_pad3 */ 206 #define PA7D_SERCOM0_PAD3 \ 207 SAM_PINMUX(a, 7, d, periph) 208 209 /* pa7e_tc1_wo1 */ 210 #define PA7E_TC1_WO1 \ 211 SAM_PINMUX(a, 7, e, periph) 212 213 /* pa7i_sdhc0_wp */ 214 #define PA7I_SDHC0_WP \ 215 SAM_PINMUX(a, 7, i, periph) 216 217 /* pa7n_ccl_out0 */ 218 #define PA7N_CCL_OUT0 \ 219 SAM_PINMUX(a, 7, n, periph) 220 221 /* pa8_gpio */ 222 #define PA8_GPIO \ 223 SAM_PINMUX(a, 8, gpio, gpio) 224 225 /* pa8a_eic_nmi */ 226 #define PA8A_EIC_NMI \ 227 SAM_PINMUX(a, 8, a, periph) 228 229 /* pa8b_adc0_ain8 */ 230 #define PA8B_ADC0_AIN8 \ 231 SAM_PINMUX(a, 8, b, periph) 232 233 /* pa8b_adc1_ain2 */ 234 #define PA8B_ADC1_AIN2 \ 235 SAM_PINMUX(a, 8, b, periph) 236 237 /* pa8b_ptc_xy6 */ 238 #define PA8B_PTC_XY6 \ 239 SAM_PINMUX(a, 8, b, periph) 240 241 /* pa8c_sercom0_pad0 */ 242 #define PA8C_SERCOM0_PAD0 \ 243 SAM_PINMUX(a, 8, c, periph) 244 245 /* pa8d_sercom2_pad1 */ 246 #define PA8D_SERCOM2_PAD1 \ 247 SAM_PINMUX(a, 8, d, periph) 248 249 /* pa8e_tc0_wo0 */ 250 #define PA8E_TC0_WO0 \ 251 SAM_PINMUX(a, 8, e, periph) 252 253 /* pa8f_tcc0_wo0 */ 254 #define PA8F_TCC0_WO0 \ 255 SAM_PINMUX(a, 8, f, periph) 256 257 /* pa8g_tcc1_wo4 */ 258 #define PA8G_TCC1_WO4 \ 259 SAM_PINMUX(a, 8, g, periph) 260 261 /* pa8h_qspi_data0 */ 262 #define PA8H_QSPI_DATA0 \ 263 SAM_PINMUX(a, 8, h, periph) 264 265 /* pa8i_sdhc0_cmd */ 266 #define PA8I_SDHC0_CMD \ 267 SAM_PINMUX(a, 8, i, periph) 268 269 /* pa8j_iis_mck0 */ 270 #define PA8J_IIS_MCK0 \ 271 SAM_PINMUX(a, 8, j, periph) 272 273 /* pa8n_ccl_in3 */ 274 #define PA8N_CCL_IN3 \ 275 SAM_PINMUX(a, 8, n, periph) 276 277 /* pa9_gpio */ 278 #define PA9_GPIO \ 279 SAM_PINMUX(a, 9, gpio, gpio) 280 281 /* pa9a_eic_extint9 */ 282 #define PA9A_EIC_EXTINT9 \ 283 SAM_PINMUX(a, 9, a, periph) 284 285 /* pa9b_adc0_ain9 */ 286 #define PA9B_ADC0_AIN9 \ 287 SAM_PINMUX(a, 9, b, periph) 288 289 /* pa9b_adc1_ain3 */ 290 #define PA9B_ADC1_AIN3 \ 291 SAM_PINMUX(a, 9, b, periph) 292 293 /* pa9b_ptc_xy7 */ 294 #define PA9B_PTC_XY7 \ 295 SAM_PINMUX(a, 9, b, periph) 296 297 /* pa9c_sercom0_pad1 */ 298 #define PA9C_SERCOM0_PAD1 \ 299 SAM_PINMUX(a, 9, c, periph) 300 301 /* pa9d_sercom2_pad0 */ 302 #define PA9D_SERCOM2_PAD0 \ 303 SAM_PINMUX(a, 9, d, periph) 304 305 /* pa9e_tc0_wo1 */ 306 #define PA9E_TC0_WO1 \ 307 SAM_PINMUX(a, 9, e, periph) 308 309 /* pa9f_tcc0_wo1 */ 310 #define PA9F_TCC0_WO1 \ 311 SAM_PINMUX(a, 9, f, periph) 312 313 /* pa9g_tcc1_wo5 */ 314 #define PA9G_TCC1_WO5 \ 315 SAM_PINMUX(a, 9, g, periph) 316 317 /* pa9h_qspi_data1 */ 318 #define PA9H_QSPI_DATA1 \ 319 SAM_PINMUX(a, 9, h, periph) 320 321 /* pa9i_sdhc0_dat0 */ 322 #define PA9I_SDHC0_DAT0 \ 323 SAM_PINMUX(a, 9, i, periph) 324 325 /* pa9j_iis_fs0 */ 326 #define PA9J_IIS_FS0 \ 327 SAM_PINMUX(a, 9, j, periph) 328 329 /* pa9n_ccl_in4 */ 330 #define PA9N_CCL_IN4 \ 331 SAM_PINMUX(a, 9, n, periph) 332 333 /* pa10_gpio */ 334 #define PA10_GPIO \ 335 SAM_PINMUX(a, 10, gpio, gpio) 336 337 /* pa10a_eic_extint10 */ 338 #define PA10A_EIC_EXTINT10 \ 339 SAM_PINMUX(a, 10, a, periph) 340 341 /* pa10b_adc0_ain10 */ 342 #define PA10B_ADC0_AIN10 \ 343 SAM_PINMUX(a, 10, b, periph) 344 345 /* pa10b_ptc_xy8 */ 346 #define PA10B_PTC_XY8 \ 347 SAM_PINMUX(a, 10, b, periph) 348 349 /* pa10c_sercom0_pad2 */ 350 #define PA10C_SERCOM0_PAD2 \ 351 SAM_PINMUX(a, 10, c, periph) 352 353 /* pa10d_sercom2_pad2 */ 354 #define PA10D_SERCOM2_PAD2 \ 355 SAM_PINMUX(a, 10, d, periph) 356 357 /* pa10e_tc1_wo0 */ 358 #define PA10E_TC1_WO0 \ 359 SAM_PINMUX(a, 10, e, periph) 360 361 /* pa10f_tcc0_wo2 */ 362 #define PA10F_TCC0_WO2 \ 363 SAM_PINMUX(a, 10, f, periph) 364 365 /* pa10g_tcc1_wo6 */ 366 #define PA10G_TCC1_WO6 \ 367 SAM_PINMUX(a, 10, g, periph) 368 369 /* pa10h_qspi_data2 */ 370 #define PA10H_QSPI_DATA2 \ 371 SAM_PINMUX(a, 10, h, periph) 372 373 /* pa10i_sdhc0_dat1 */ 374 #define PA10I_SDHC0_DAT1 \ 375 SAM_PINMUX(a, 10, i, periph) 376 377 /* pa10j_iis_sck0 */ 378 #define PA10J_IIS_SCK0 \ 379 SAM_PINMUX(a, 10, j, periph) 380 381 /* pa10m_gclk_io4 */ 382 #define PA10M_GCLK_IO4 \ 383 SAM_PINMUX(a, 10, m, periph) 384 385 /* pa10n_ccl_in5 */ 386 #define PA10N_CCL_IN5 \ 387 SAM_PINMUX(a, 10, n, periph) 388 389 /* pa11_gpio */ 390 #define PA11_GPIO \ 391 SAM_PINMUX(a, 11, gpio, gpio) 392 393 /* pa11a_eic_extint11 */ 394 #define PA11A_EIC_EXTINT11 \ 395 SAM_PINMUX(a, 11, a, periph) 396 397 /* pa11b_adc0_ain11 */ 398 #define PA11B_ADC0_AIN11 \ 399 SAM_PINMUX(a, 11, b, periph) 400 401 /* pa11b_ptc_xy9 */ 402 #define PA11B_PTC_XY9 \ 403 SAM_PINMUX(a, 11, b, periph) 404 405 /* pa11c_sercom0_pad3 */ 406 #define PA11C_SERCOM0_PAD3 \ 407 SAM_PINMUX(a, 11, c, periph) 408 409 /* pa11d_sercom2_pad3 */ 410 #define PA11D_SERCOM2_PAD3 \ 411 SAM_PINMUX(a, 11, d, periph) 412 413 /* pa11e_tc1_wo1 */ 414 #define PA11E_TC1_WO1 \ 415 SAM_PINMUX(a, 11, e, periph) 416 417 /* pa11f_tcc0_wo3 */ 418 #define PA11F_TCC0_WO3 \ 419 SAM_PINMUX(a, 11, f, periph) 420 421 /* pa11g_tcc1_wo7 */ 422 #define PA11G_TCC1_WO7 \ 423 SAM_PINMUX(a, 11, g, periph) 424 425 /* pa11h_qspi_data3 */ 426 #define PA11H_QSPI_DATA3 \ 427 SAM_PINMUX(a, 11, h, periph) 428 429 /* pa11i_sdhc0_dat2 */ 430 #define PA11I_SDHC0_DAT2 \ 431 SAM_PINMUX(a, 11, i, periph) 432 433 /* pa11j_iis_sdo */ 434 #define PA11J_IIS_SDO \ 435 SAM_PINMUX(a, 11, j, periph) 436 437 /* pa11m_gclk_io5 */ 438 #define PA11M_GCLK_IO5 \ 439 SAM_PINMUX(a, 11, m, periph) 440 441 /* pa11n_ccl_out1 */ 442 #define PA11N_CCL_OUT1 \ 443 SAM_PINMUX(a, 11, n, periph) 444 445 /* pa12_gpio */ 446 #define PA12_GPIO \ 447 SAM_PINMUX(a, 12, gpio, gpio) 448 449 /* pa12a_eic_extint12 */ 450 #define PA12A_EIC_EXTINT12 \ 451 SAM_PINMUX(a, 12, a, periph) 452 453 /* pa12c_sercom2_pad0 */ 454 #define PA12C_SERCOM2_PAD0 \ 455 SAM_PINMUX(a, 12, c, periph) 456 457 /* pa12d_sercom4_pad1 */ 458 #define PA12D_SERCOM4_PAD1 \ 459 SAM_PINMUX(a, 12, d, periph) 460 461 /* pa12e_tc2_wo0 */ 462 #define PA12E_TC2_WO0 \ 463 SAM_PINMUX(a, 12, e, periph) 464 465 /* pa12f_tcc0_wo6 */ 466 #define PA12F_TCC0_WO6 \ 467 SAM_PINMUX(a, 12, f, periph) 468 469 /* pa12g_tcc1_wo2 */ 470 #define PA12G_TCC1_WO2 \ 471 SAM_PINMUX(a, 12, g, periph) 472 473 /* pa12i_sdhc0_cd */ 474 #define PA12I_SDHC0_CD \ 475 SAM_PINMUX(a, 12, i, periph) 476 477 /* pa12k_pcc_den1 */ 478 #define PA12K_PCC_DEN1 \ 479 SAM_PINMUX(a, 12, k, periph) 480 481 /* pa12l_gmac_grx1 */ 482 #define PA12L_GMAC_GRX1 \ 483 SAM_PINMUX(a, 12, l, periph) 484 485 /* pa12m_ac_cmp0 */ 486 #define PA12M_AC_CMP0 \ 487 SAM_PINMUX(a, 12, m, periph) 488 489 /* pa13_gpio */ 490 #define PA13_GPIO \ 491 SAM_PINMUX(a, 13, gpio, gpio) 492 493 /* pa13a_eic_extint13 */ 494 #define PA13A_EIC_EXTINT13 \ 495 SAM_PINMUX(a, 13, a, periph) 496 497 /* pa13c_sercom2_pad1 */ 498 #define PA13C_SERCOM2_PAD1 \ 499 SAM_PINMUX(a, 13, c, periph) 500 501 /* pa13d_sercom4_pad0 */ 502 #define PA13D_SERCOM4_PAD0 \ 503 SAM_PINMUX(a, 13, d, periph) 504 505 /* pa13e_tc2_wo1 */ 506 #define PA13E_TC2_WO1 \ 507 SAM_PINMUX(a, 13, e, periph) 508 509 /* pa13f_tcc0_wo7 */ 510 #define PA13F_TCC0_WO7 \ 511 SAM_PINMUX(a, 13, f, periph) 512 513 /* pa13g_tcc1_wo3 */ 514 #define PA13G_TCC1_WO3 \ 515 SAM_PINMUX(a, 13, g, periph) 516 517 /* pa13i_sdhc0_wp */ 518 #define PA13I_SDHC0_WP \ 519 SAM_PINMUX(a, 13, i, periph) 520 521 /* pa13k_pcc_den2 */ 522 #define PA13K_PCC_DEN2 \ 523 SAM_PINMUX(a, 13, k, periph) 524 525 /* pa13l_gmac_grx0 */ 526 #define PA13L_GMAC_GRX0 \ 527 SAM_PINMUX(a, 13, l, periph) 528 529 /* pa13m_ac_cmp1 */ 530 #define PA13M_AC_CMP1 \ 531 SAM_PINMUX(a, 13, m, periph) 532 533 /* pa14_gpio */ 534 #define PA14_GPIO \ 535 SAM_PINMUX(a, 14, gpio, gpio) 536 537 /* pa14a_eic_extint14 */ 538 #define PA14A_EIC_EXTINT14 \ 539 SAM_PINMUX(a, 14, a, periph) 540 541 /* pa14c_sercom2_pad2 */ 542 #define PA14C_SERCOM2_PAD2 \ 543 SAM_PINMUX(a, 14, c, periph) 544 545 /* pa14d_sercom4_pad2 */ 546 #define PA14D_SERCOM4_PAD2 \ 547 SAM_PINMUX(a, 14, d, periph) 548 549 /* pa14e_tc3_wo0 */ 550 #define PA14E_TC3_WO0 \ 551 SAM_PINMUX(a, 14, e, periph) 552 553 /* pa14f_tcc2_wo0 */ 554 #define PA14F_TCC2_WO0 \ 555 SAM_PINMUX(a, 14, f, periph) 556 557 /* pa14g_tcc1_wo2 */ 558 #define PA14G_TCC1_WO2 \ 559 SAM_PINMUX(a, 14, g, periph) 560 561 /* pa14k_pcc_clk */ 562 #define PA14K_PCC_CLK \ 563 SAM_PINMUX(a, 14, k, periph) 564 565 /* pa14l_gmac_gtxck */ 566 #define PA14L_GMAC_GTXCK \ 567 SAM_PINMUX(a, 14, l, periph) 568 569 /* pa14m_glkc_io0 */ 570 #define PA14M_GLKC_IO0 \ 571 SAM_PINMUX(a, 14, m, periph) 572 573 /* pa15_gpio */ 574 #define PA15_GPIO \ 575 SAM_PINMUX(a, 15, gpio, gpio) 576 577 /* pa15a_eic_extint15 */ 578 #define PA15A_EIC_EXTINT15 \ 579 SAM_PINMUX(a, 15, a, periph) 580 581 /* pa15c_sercom2_pad3 */ 582 #define PA15C_SERCOM2_PAD3 \ 583 SAM_PINMUX(a, 15, c, periph) 584 585 /* pa15d_sercom4_pad3 */ 586 #define PA15D_SERCOM4_PAD3 \ 587 SAM_PINMUX(a, 15, d, periph) 588 589 /* pa15e_tc3_wo1 */ 590 #define PA15E_TC3_WO1 \ 591 SAM_PINMUX(a, 15, e, periph) 592 593 /* pa15f_tcc2_wo1 */ 594 #define PA15F_TCC2_WO1 \ 595 SAM_PINMUX(a, 15, f, periph) 596 597 /* pa15g_tcc1_wo3 */ 598 #define PA15G_TCC1_WO3 \ 599 SAM_PINMUX(a, 15, g, periph) 600 601 /* pa15l_gmac_grxer */ 602 #define PA15L_GMAC_GRXER \ 603 SAM_PINMUX(a, 15, l, periph) 604 605 /* pa15m_glkc_io1 */ 606 #define PA15M_GLKC_IO1 \ 607 SAM_PINMUX(a, 15, m, periph) 608 609 /* pa16_gpio */ 610 #define PA16_GPIO \ 611 SAM_PINMUX(a, 16, gpio, gpio) 612 613 /* pa16a_eic_extint0 */ 614 #define PA16A_EIC_EXTINT0 \ 615 SAM_PINMUX(a, 16, a, periph) 616 617 /* pa16b_ptc_xy10 */ 618 #define PA16B_PTC_XY10 \ 619 SAM_PINMUX(a, 16, b, periph) 620 621 /* pa16c_sercom1_pad0 */ 622 #define PA16C_SERCOM1_PAD0 \ 623 SAM_PINMUX(a, 16, c, periph) 624 625 /* pa16d_sercom3_pad1 */ 626 #define PA16D_SERCOM3_PAD1 \ 627 SAM_PINMUX(a, 16, d, periph) 628 629 /* pa16e_tc2_wo0 */ 630 #define PA16E_TC2_WO0 \ 631 SAM_PINMUX(a, 16, e, periph) 632 633 /* pa16f_tcc1_wo0 */ 634 #define PA16F_TCC1_WO0 \ 635 SAM_PINMUX(a, 16, f, periph) 636 637 /* pa16g_tcc0_wo4 */ 638 #define PA16G_TCC0_WO4 \ 639 SAM_PINMUX(a, 16, g, periph) 640 641 /* pa16k_pcc_data0 */ 642 #define PA16K_PCC_DATA0 \ 643 SAM_PINMUX(a, 16, k, periph) 644 645 /* pa16l_gmac_gcrs_grxdv */ 646 #define PA16L_GMAC_GCRS_GRXDV \ 647 SAM_PINMUX(a, 16, l, periph) 648 649 /* pa16m_gclk_io2 */ 650 #define PA16M_GCLK_IO2 \ 651 SAM_PINMUX(a, 16, m, periph) 652 653 /* pa16n_ccl_in0 */ 654 #define PA16N_CCL_IN0 \ 655 SAM_PINMUX(a, 16, n, periph) 656 657 /* pa17_gpio */ 658 #define PA17_GPIO \ 659 SAM_PINMUX(a, 17, gpio, gpio) 660 661 /* pa17a_eic_extint1 */ 662 #define PA17A_EIC_EXTINT1 \ 663 SAM_PINMUX(a, 17, a, periph) 664 665 /* pa17b_ptc_xy11 */ 666 #define PA17B_PTC_XY11 \ 667 SAM_PINMUX(a, 17, b, periph) 668 669 /* pa17c_sercom1_pad1 */ 670 #define PA17C_SERCOM1_PAD1 \ 671 SAM_PINMUX(a, 17, c, periph) 672 673 /* pa17d_sercom3_pad0 */ 674 #define PA17D_SERCOM3_PAD0 \ 675 SAM_PINMUX(a, 17, d, periph) 676 677 /* pa17e_tc2_wo1 */ 678 #define PA17E_TC2_WO1 \ 679 SAM_PINMUX(a, 17, e, periph) 680 681 /* pa17f_tcc1_wo1 */ 682 #define PA17F_TCC1_WO1 \ 683 SAM_PINMUX(a, 17, f, periph) 684 685 /* pa17g_tcc0_wo5 */ 686 #define PA17G_TCC0_WO5 \ 687 SAM_PINMUX(a, 17, g, periph) 688 689 /* pa17k_pcc_data1 */ 690 #define PA17K_PCC_DATA1 \ 691 SAM_PINMUX(a, 17, k, periph) 692 693 /* pa17l_gmac_gtxen */ 694 #define PA17L_GMAC_GTXEN \ 695 SAM_PINMUX(a, 17, l, periph) 696 697 /* pa17m_gclk_io3 */ 698 #define PA17M_GCLK_IO3 \ 699 SAM_PINMUX(a, 17, m, periph) 700 701 /* pa17n_ccl_in1 */ 702 #define PA17N_CCL_IN1 \ 703 SAM_PINMUX(a, 17, n, periph) 704 705 /* pa18_gpio */ 706 #define PA18_GPIO \ 707 SAM_PINMUX(a, 18, gpio, gpio) 708 709 /* pa18a_eic_extint2 */ 710 #define PA18A_EIC_EXTINT2 \ 711 SAM_PINMUX(a, 18, a, periph) 712 713 /* pa18b_ptc_xy12 */ 714 #define PA18B_PTC_XY12 \ 715 SAM_PINMUX(a, 18, b, periph) 716 717 /* pa18c_sercom1_pad2 */ 718 #define PA18C_SERCOM1_PAD2 \ 719 SAM_PINMUX(a, 18, c, periph) 720 721 /* pa18d_sercom3_pad2 */ 722 #define PA18D_SERCOM3_PAD2 \ 723 SAM_PINMUX(a, 18, d, periph) 724 725 /* pa18e_tc3_wo0 */ 726 #define PA18E_TC3_WO0 \ 727 SAM_PINMUX(a, 18, e, periph) 728 729 /* pa18f_tcc1_wo2 */ 730 #define PA18F_TCC1_WO2 \ 731 SAM_PINMUX(a, 18, f, periph) 732 733 /* pa18g_tcc0_wo6 */ 734 #define PA18G_TCC0_WO6 \ 735 SAM_PINMUX(a, 18, g, periph) 736 737 /* pa18k_pcc_data2 */ 738 #define PA18K_PCC_DATA2 \ 739 SAM_PINMUX(a, 18, k, periph) 740 741 /* pa18l_gmac_gtx0 */ 742 #define PA18L_GMAC_GTX0 \ 743 SAM_PINMUX(a, 18, l, periph) 744 745 /* pa18m_ac_cmp0 */ 746 #define PA18M_AC_CMP0 \ 747 SAM_PINMUX(a, 18, m, periph) 748 749 /* pa18n_ccl_in2 */ 750 #define PA18N_CCL_IN2 \ 751 SAM_PINMUX(a, 18, n, periph) 752 753 /* pa19_gpio */ 754 #define PA19_GPIO \ 755 SAM_PINMUX(a, 19, gpio, gpio) 756 757 /* pa19a_eic_extint3 */ 758 #define PA19A_EIC_EXTINT3 \ 759 SAM_PINMUX(a, 19, a, periph) 760 761 /* pa19b_ptc_xy13 */ 762 #define PA19B_PTC_XY13 \ 763 SAM_PINMUX(a, 19, b, periph) 764 765 /* pa19c_sercom1_pad3 */ 766 #define PA19C_SERCOM1_PAD3 \ 767 SAM_PINMUX(a, 19, c, periph) 768 769 /* pa19d_sercom3_pad3 */ 770 #define PA19D_SERCOM3_PAD3 \ 771 SAM_PINMUX(a, 19, d, periph) 772 773 /* pa19e_tc3_wo1 */ 774 #define PA19E_TC3_WO1 \ 775 SAM_PINMUX(a, 19, e, periph) 776 777 /* pa19f_tcc1_wo3 */ 778 #define PA19F_TCC1_WO3 \ 779 SAM_PINMUX(a, 19, f, periph) 780 781 /* pa19g_tcc0_wo7 */ 782 #define PA19G_TCC0_WO7 \ 783 SAM_PINMUX(a, 19, g, periph) 784 785 /* pa19k_pcc_data3 */ 786 #define PA19K_PCC_DATA3 \ 787 SAM_PINMUX(a, 19, k, periph) 788 789 /* pa19l_gmac_gtx1 */ 790 #define PA19L_GMAC_GTX1 \ 791 SAM_PINMUX(a, 19, l, periph) 792 793 /* pa19m_ac_cmp1 */ 794 #define PA19M_AC_CMP1 \ 795 SAM_PINMUX(a, 19, m, periph) 796 797 /* pa19n_ccl_out0 */ 798 #define PA19N_CCL_OUT0 \ 799 SAM_PINMUX(a, 19, n, periph) 800 801 /* pa20_gpio */ 802 #define PA20_GPIO \ 803 SAM_PINMUX(a, 20, gpio, gpio) 804 805 /* pa20a_eic_extint4 */ 806 #define PA20A_EIC_EXTINT4 \ 807 SAM_PINMUX(a, 20, a, periph) 808 809 /* pa20b_ptc_xy14 */ 810 #define PA20B_PTC_XY14 \ 811 SAM_PINMUX(a, 20, b, periph) 812 813 /* pa20c_sercom5_pad2 */ 814 #define PA20C_SERCOM5_PAD2 \ 815 SAM_PINMUX(a, 20, c, periph) 816 817 /* pa20d_sercom3_pad2 */ 818 #define PA20D_SERCOM3_PAD2 \ 819 SAM_PINMUX(a, 20, d, periph) 820 821 /* pa20e_tc7_wo0 */ 822 #define PA20E_TC7_WO0 \ 823 SAM_PINMUX(a, 20, e, periph) 824 825 /* pa20f_tcc1_wo4 */ 826 #define PA20F_TCC1_WO4 \ 827 SAM_PINMUX(a, 20, f, periph) 828 829 /* pa20g_tcc0_wo0 */ 830 #define PA20G_TCC0_WO0 \ 831 SAM_PINMUX(a, 20, g, periph) 832 833 /* pa20i_sdhc1_cmd */ 834 #define PA20I_SDHC1_CMD \ 835 SAM_PINMUX(a, 20, i, periph) 836 837 /* pa20j_iis_fs0 */ 838 #define PA20J_IIS_FS0 \ 839 SAM_PINMUX(a, 20, j, periph) 840 841 /* pa20k_pcc_data4 */ 842 #define PA20K_PCC_DATA4 \ 843 SAM_PINMUX(a, 20, k, periph) 844 845 /* pa20l_gmac_gmdc */ 846 #define PA20L_GMAC_GMDC \ 847 SAM_PINMUX(a, 20, l, periph) 848 849 /* pa21_gpio */ 850 #define PA21_GPIO \ 851 SAM_PINMUX(a, 21, gpio, gpio) 852 853 /* pa21a_eic_extint5 */ 854 #define PA21A_EIC_EXTINT5 \ 855 SAM_PINMUX(a, 21, a, periph) 856 857 /* pa21b_ptc_xy15 */ 858 #define PA21B_PTC_XY15 \ 859 SAM_PINMUX(a, 21, b, periph) 860 861 /* pa21c_sercom5_pad3 */ 862 #define PA21C_SERCOM5_PAD3 \ 863 SAM_PINMUX(a, 21, c, periph) 864 865 /* pa21d_sercom3_pad3 */ 866 #define PA21D_SERCOM3_PAD3 \ 867 SAM_PINMUX(a, 21, d, periph) 868 869 /* pa21e_tc7_wo1 */ 870 #define PA21E_TC7_WO1 \ 871 SAM_PINMUX(a, 21, e, periph) 872 873 /* pa21f_tcc1_wo5 */ 874 #define PA21F_TCC1_WO5 \ 875 SAM_PINMUX(a, 21, f, periph) 876 877 /* pa21g_tcc0_wo1 */ 878 #define PA21G_TCC0_WO1 \ 879 SAM_PINMUX(a, 21, g, periph) 880 881 /* pa21i_sdhc1_ck */ 882 #define PA21I_SDHC1_CK \ 883 SAM_PINMUX(a, 21, i, periph) 884 885 /* pa21j_iis_sdo */ 886 #define PA21J_IIS_SDO \ 887 SAM_PINMUX(a, 21, j, periph) 888 889 /* pa21k_pcc_data5 */ 890 #define PA21K_PCC_DATA5 \ 891 SAM_PINMUX(a, 21, k, periph) 892 893 /* pa21l_gmac_gmdio */ 894 #define PA21L_GMAC_GMDIO \ 895 SAM_PINMUX(a, 21, l, periph) 896 897 /* pa22_gpio */ 898 #define PA22_GPIO \ 899 SAM_PINMUX(a, 22, gpio, gpio) 900 901 /* pa22a_eic_extint6 */ 902 #define PA22A_EIC_EXTINT6 \ 903 SAM_PINMUX(a, 22, a, periph) 904 905 /* pa22b_ptc_xy16 */ 906 #define PA22B_PTC_XY16 \ 907 SAM_PINMUX(a, 22, b, periph) 908 909 /* pa22c_sercom3_pad0 */ 910 #define PA22C_SERCOM3_PAD0 \ 911 SAM_PINMUX(a, 22, c, periph) 912 913 /* pa22d_sercom5_pad1 */ 914 #define PA22D_SERCOM5_PAD1 \ 915 SAM_PINMUX(a, 22, d, periph) 916 917 /* pa22e_tc4_wo0 */ 918 #define PA22E_TC4_WO0 \ 919 SAM_PINMUX(a, 22, e, periph) 920 921 /* pa22f_tcc1_wo6 */ 922 #define PA22F_TCC1_WO6 \ 923 SAM_PINMUX(a, 22, f, periph) 924 925 /* pa22g_tcc0_wo2 */ 926 #define PA22G_TCC0_WO2 \ 927 SAM_PINMUX(a, 22, g, periph) 928 929 /* pa22j_iis_sdi */ 930 #define PA22J_IIS_SDI \ 931 SAM_PINMUX(a, 22, j, periph) 932 933 /* pa22k_pcc_data6 */ 934 #define PA22K_PCC_DATA6 \ 935 SAM_PINMUX(a, 22, k, periph) 936 937 /* pa22n_ccl_in6 */ 938 #define PA22N_CCL_IN6 \ 939 SAM_PINMUX(a, 22, n, periph) 940 941 /* pa23_gpio */ 942 #define PA23_GPIO \ 943 SAM_PINMUX(a, 23, gpio, gpio) 944 945 /* pa23a_eic_extint7 */ 946 #define PA23A_EIC_EXTINT7 \ 947 SAM_PINMUX(a, 23, a, periph) 948 949 /* pa23b_ptc_xy17 */ 950 #define PA23B_PTC_XY17 \ 951 SAM_PINMUX(a, 23, b, periph) 952 953 /* pa23c_sercom3_pad1 */ 954 #define PA23C_SERCOM3_PAD1 \ 955 SAM_PINMUX(a, 23, c, periph) 956 957 /* pa23d_sercom5_pad0 */ 958 #define PA23D_SERCOM5_PAD0 \ 959 SAM_PINMUX(a, 23, d, periph) 960 961 /* pa23e_tc4_wo1 */ 962 #define PA23E_TC4_WO1 \ 963 SAM_PINMUX(a, 23, e, periph) 964 965 /* pa23f_tcc1_wo7 */ 966 #define PA23F_TCC1_WO7 \ 967 SAM_PINMUX(a, 23, f, periph) 968 969 /* pa23g_tcc0_wo3 */ 970 #define PA23G_TCC0_WO3 \ 971 SAM_PINMUX(a, 23, g, periph) 972 973 /* pa23h_usb_sof */ 974 #define PA23H_USB_SOF \ 975 SAM_PINMUX(a, 23, h, periph) 976 977 /* pa23j_iis_fs1 */ 978 #define PA23J_IIS_FS1 \ 979 SAM_PINMUX(a, 23, j, periph) 980 981 /* pa23k_pcc_data7 */ 982 #define PA23K_PCC_DATA7 \ 983 SAM_PINMUX(a, 23, k, periph) 984 985 /* pa23n_ccl_in7 */ 986 #define PA23N_CCL_IN7 \ 987 SAM_PINMUX(a, 23, n, periph) 988 989 /* pa24_gpio */ 990 #define PA24_GPIO \ 991 SAM_PINMUX(a, 24, gpio, gpio) 992 993 /* pa24a_eic_extint8 */ 994 #define PA24A_EIC_EXTINT8 \ 995 SAM_PINMUX(a, 24, a, periph) 996 997 /* pa24c_sercom3_pad2 */ 998 #define PA24C_SERCOM3_PAD2 \ 999 SAM_PINMUX(a, 24, c, periph) 1000 1001 /* pa24d_sercom5_pad2 */ 1002 #define PA24D_SERCOM5_PAD2 \ 1003 SAM_PINMUX(a, 24, d, periph) 1004 1005 /* pa24e_tc5_wo0 */ 1006 #define PA24E_TC5_WO0 \ 1007 SAM_PINMUX(a, 24, e, periph) 1008 1009 /* pa24f_tcc2_wo2 */ 1010 #define PA24F_TCC2_WO2 \ 1011 SAM_PINMUX(a, 24, f, periph) 1012 1013 /* pa24g_pdec_qdi0 */ 1014 #define PA24G_PDEC_QDI0 \ 1015 SAM_PINMUX(a, 24, g, periph) 1016 1017 /* pa24h_usb_dm */ 1018 #define PA24H_USB_DM \ 1019 SAM_PINMUX(a, 24, h, periph) 1020 1021 /* pa24n_ccl_in8 */ 1022 #define PA24N_CCL_IN8 \ 1023 SAM_PINMUX(a, 24, n, periph) 1024 1025 /* pa25_gpio */ 1026 #define PA25_GPIO \ 1027 SAM_PINMUX(a, 25, gpio, gpio) 1028 1029 /* pa25a_eic_extint9 */ 1030 #define PA25A_EIC_EXTINT9 \ 1031 SAM_PINMUX(a, 25, a, periph) 1032 1033 /* pa25c_sercom3_pad3 */ 1034 #define PA25C_SERCOM3_PAD3 \ 1035 SAM_PINMUX(a, 25, c, periph) 1036 1037 /* pa25d_sercom5_pad3 */ 1038 #define PA25D_SERCOM5_PAD3 \ 1039 SAM_PINMUX(a, 25, d, periph) 1040 1041 /* pa25e_tc5_wo1 */ 1042 #define PA25E_TC5_WO1 \ 1043 SAM_PINMUX(a, 25, e, periph) 1044 1045 /* pa25g_pdec_qdi1 */ 1046 #define PA25G_PDEC_QDI1 \ 1047 SAM_PINMUX(a, 25, g, periph) 1048 1049 /* pa25h_usb_dp */ 1050 #define PA25H_USB_DP \ 1051 SAM_PINMUX(a, 25, h, periph) 1052 1053 /* pa25n_ccl_out2 */ 1054 #define PA25N_CCL_OUT2 \ 1055 SAM_PINMUX(a, 25, n, periph) 1056 1057 /* pa27_gpio */ 1058 #define PA27_GPIO \ 1059 SAM_PINMUX(a, 27, gpio, gpio) 1060 1061 /* pa27a_eic_extint11 */ 1062 #define PA27A_EIC_EXTINT11 \ 1063 SAM_PINMUX(a, 27, a, periph) 1064 1065 /* pa27b_ptc_xy18 */ 1066 #define PA27B_PTC_XY18 \ 1067 SAM_PINMUX(a, 27, b, periph) 1068 1069 /* pa27m_gclk_io1 */ 1070 #define PA27M_GCLK_IO1 \ 1071 SAM_PINMUX(a, 27, m, periph) 1072 1073 /* pa30_gpio */ 1074 #define PA30_GPIO \ 1075 SAM_PINMUX(a, 30, gpio, gpio) 1076 1077 /* pa30a_eic_extint14 */ 1078 #define PA30A_EIC_EXTINT14 \ 1079 SAM_PINMUX(a, 30, a, periph) 1080 1081 /* pa30b_ptc_xy19 */ 1082 #define PA30B_PTC_XY19 \ 1083 SAM_PINMUX(a, 30, b, periph) 1084 1085 /* pa30d_sercom1_pad2 */ 1086 #define PA30D_SERCOM1_PAD2 \ 1087 SAM_PINMUX(a, 30, d, periph) 1088 1089 /* pa30e_tc6_wo0 */ 1090 #define PA30E_TC6_WO0 \ 1091 SAM_PINMUX(a, 30, e, periph) 1092 1093 /* pa30f_tcc2_wo0 */ 1094 #define PA30F_TCC2_WO0 \ 1095 SAM_PINMUX(a, 30, f, periph) 1096 1097 /* pa30h_swd_clk */ 1098 #define PA30H_SWD_CLK \ 1099 SAM_PINMUX(a, 30, h, periph) 1100 1101 /* pa30m_gclk_io0 */ 1102 #define PA30M_GCLK_IO0 \ 1103 SAM_PINMUX(a, 30, m, periph) 1104 1105 /* pa30n_ccl_in3 */ 1106 #define PA30N_CCL_IN3 \ 1107 SAM_PINMUX(a, 30, n, periph) 1108 1109 /* pa31_gpio */ 1110 #define PA31_GPIO \ 1111 SAM_PINMUX(a, 31, gpio, gpio) 1112 1113 /* pa31a_eic_extint15 */ 1114 #define PA31A_EIC_EXTINT15 \ 1115 SAM_PINMUX(a, 31, a, periph) 1116 1117 /* pa31d_sercom1_pad3 */ 1118 #define PA31D_SERCOM1_PAD3 \ 1119 SAM_PINMUX(a, 31, d, periph) 1120 1121 /* pa31e_tc6_wo1 */ 1122 #define PA31E_TC6_WO1 \ 1123 SAM_PINMUX(a, 31, e, periph) 1124 1125 /* pa31f_tcc2_wo1 */ 1126 #define PA31F_TCC2_WO1 \ 1127 SAM_PINMUX(a, 31, f, periph) 1128 1129 /* pa31h_swd_io */ 1130 #define PA31H_SWD_IO \ 1131 SAM_PINMUX(a, 31, h, periph) 1132 1133 /* pa31n_ccl_out1 */ 1134 #define PA31N_CCL_OUT1 \ 1135 SAM_PINMUX(a, 31, n, periph) 1136 1137 /* pb0_gpio */ 1138 #define PB0_GPIO \ 1139 SAM_PINMUX(b, 0, gpio, gpio) 1140 1141 /* pb0a_eic_extint0 */ 1142 #define PB0A_EIC_EXTINT0 \ 1143 SAM_PINMUX(b, 0, a, periph) 1144 1145 /* pb0b_adc0_ain12 */ 1146 #define PB0B_ADC0_AIN12 \ 1147 SAM_PINMUX(b, 0, b, periph) 1148 1149 /* pb0b_ptc_xy30 */ 1150 #define PB0B_PTC_XY30 \ 1151 SAM_PINMUX(b, 0, b, periph) 1152 1153 /* pb0d_sercom5_pad2 */ 1154 #define PB0D_SERCOM5_PAD2 \ 1155 SAM_PINMUX(b, 0, d, periph) 1156 1157 /* pb0e_tc7_wo0 */ 1158 #define PB0E_TC7_WO0 \ 1159 SAM_PINMUX(b, 0, e, periph) 1160 1161 /* pb0n_ccl_in1 */ 1162 #define PB0N_CCL_IN1 \ 1163 SAM_PINMUX(b, 0, n, periph) 1164 1165 /* pb1_gpio */ 1166 #define PB1_GPIO \ 1167 SAM_PINMUX(b, 1, gpio, gpio) 1168 1169 /* pb1a_eic_extint1 */ 1170 #define PB1A_EIC_EXTINT1 \ 1171 SAM_PINMUX(b, 1, a, periph) 1172 1173 /* pb1b_adc0_ain13 */ 1174 #define PB1B_ADC0_AIN13 \ 1175 SAM_PINMUX(b, 1, b, periph) 1176 1177 /* pb1b_ptc_xy31 */ 1178 #define PB1B_PTC_XY31 \ 1179 SAM_PINMUX(b, 1, b, periph) 1180 1181 /* pb1d_sercom5_pad3 */ 1182 #define PB1D_SERCOM5_PAD3 \ 1183 SAM_PINMUX(b, 1, d, periph) 1184 1185 /* pb1e_tc7_wo1 */ 1186 #define PB1E_TC7_WO1 \ 1187 SAM_PINMUX(b, 1, e, periph) 1188 1189 /* pb1n_ccl_in2 */ 1190 #define PB1N_CCL_IN2 \ 1191 SAM_PINMUX(b, 1, n, periph) 1192 1193 /* pb2_gpio */ 1194 #define PB2_GPIO \ 1195 SAM_PINMUX(b, 2, gpio, gpio) 1196 1197 /* pb2a_eic_extint2 */ 1198 #define PB2A_EIC_EXTINT2 \ 1199 SAM_PINMUX(b, 2, a, periph) 1200 1201 /* pb2b_adc0_ain14 */ 1202 #define PB2B_ADC0_AIN14 \ 1203 SAM_PINMUX(b, 2, b, periph) 1204 1205 /* pb2b_ptc_xy20 */ 1206 #define PB2B_PTC_XY20 \ 1207 SAM_PINMUX(b, 2, b, periph) 1208 1209 /* pb2d_sercom5_pad0 */ 1210 #define PB2D_SERCOM5_PAD0 \ 1211 SAM_PINMUX(b, 2, d, periph) 1212 1213 /* pb2e_tc6_wo0 */ 1214 #define PB2E_TC6_WO0 \ 1215 SAM_PINMUX(b, 2, e, periph) 1216 1217 /* pb2f_tcc2_wo2 */ 1218 #define PB2F_TCC2_WO2 \ 1219 SAM_PINMUX(b, 2, f, periph) 1220 1221 /* pb2n_ccl_out0 */ 1222 #define PB2N_CCL_OUT0 \ 1223 SAM_PINMUX(b, 2, n, periph) 1224 1225 /* pb3_gpio */ 1226 #define PB3_GPIO \ 1227 SAM_PINMUX(b, 3, gpio, gpio) 1228 1229 /* pb3a_eic_extint3 */ 1230 #define PB3A_EIC_EXTINT3 \ 1231 SAM_PINMUX(b, 3, a, periph) 1232 1233 /* pb3b_adc0_ain15 */ 1234 #define PB3B_ADC0_AIN15 \ 1235 SAM_PINMUX(b, 3, b, periph) 1236 1237 /* pb3b_ptc_xy21 */ 1238 #define PB3B_PTC_XY21 \ 1239 SAM_PINMUX(b, 3, b, periph) 1240 1241 /* pb3d_sercom5_pad1 */ 1242 #define PB3D_SERCOM5_PAD1 \ 1243 SAM_PINMUX(b, 3, d, periph) 1244 1245 /* pb3e_tc6_wo1 */ 1246 #define PB3E_TC6_WO1 \ 1247 SAM_PINMUX(b, 3, e, periph) 1248 1249 /* pb4_gpio */ 1250 #define PB4_GPIO \ 1251 SAM_PINMUX(b, 4, gpio, gpio) 1252 1253 /* pb4a_eic_extint4 */ 1254 #define PB4A_EIC_EXTINT4 \ 1255 SAM_PINMUX(b, 4, a, periph) 1256 1257 /* pb4b_adc1_ain6 */ 1258 #define PB4B_ADC1_AIN6 \ 1259 SAM_PINMUX(b, 4, b, periph) 1260 1261 /* pb4b_ptc_xy22 */ 1262 #define PB4B_PTC_XY22 \ 1263 SAM_PINMUX(b, 4, b, periph) 1264 1265 /* pb5_gpio */ 1266 #define PB5_GPIO \ 1267 SAM_PINMUX(b, 5, gpio, gpio) 1268 1269 /* pb5a_eic_extint5 */ 1270 #define PB5A_EIC_EXTINT5 \ 1271 SAM_PINMUX(b, 5, a, periph) 1272 1273 /* pb5b_adc1_ain7 */ 1274 #define PB5B_ADC1_AIN7 \ 1275 SAM_PINMUX(b, 5, b, periph) 1276 1277 /* pb5b_ptc_xy23 */ 1278 #define PB5B_PTC_XY23 \ 1279 SAM_PINMUX(b, 5, b, periph) 1280 1281 /* pb6_gpio */ 1282 #define PB6_GPIO \ 1283 SAM_PINMUX(b, 6, gpio, gpio) 1284 1285 /* pb6a_eic_extint6 */ 1286 #define PB6A_EIC_EXTINT6 \ 1287 SAM_PINMUX(b, 6, a, periph) 1288 1289 /* pb6b_adc1_ain8 */ 1290 #define PB6B_ADC1_AIN8 \ 1291 SAM_PINMUX(b, 6, b, periph) 1292 1293 /* pb6b_ptc_xy24 */ 1294 #define PB6B_PTC_XY24 \ 1295 SAM_PINMUX(b, 6, b, periph) 1296 1297 /* pb6n_ccl_in6 */ 1298 #define PB6N_CCL_IN6 \ 1299 SAM_PINMUX(b, 6, n, periph) 1300 1301 /* pb7_gpio */ 1302 #define PB7_GPIO \ 1303 SAM_PINMUX(b, 7, gpio, gpio) 1304 1305 /* pb7a_eic_extint7 */ 1306 #define PB7A_EIC_EXTINT7 \ 1307 SAM_PINMUX(b, 7, a, periph) 1308 1309 /* pb7b_adc1_ain9 */ 1310 #define PB7B_ADC1_AIN9 \ 1311 SAM_PINMUX(b, 7, b, periph) 1312 1313 /* pb7b_ptc_xy25 */ 1314 #define PB7B_PTC_XY25 \ 1315 SAM_PINMUX(b, 7, b, periph) 1316 1317 /* pb7n_ccl_in7 */ 1318 #define PB7N_CCL_IN7 \ 1319 SAM_PINMUX(b, 7, n, periph) 1320 1321 /* pb8_gpio */ 1322 #define PB8_GPIO \ 1323 SAM_PINMUX(b, 8, gpio, gpio) 1324 1325 /* pb8a_eic_extint8 */ 1326 #define PB8A_EIC_EXTINT8 \ 1327 SAM_PINMUX(b, 8, a, periph) 1328 1329 /* pb8b_adc0_ain2 */ 1330 #define PB8B_ADC0_AIN2 \ 1331 SAM_PINMUX(b, 8, b, periph) 1332 1333 /* pb8b_adc1_ain0 */ 1334 #define PB8B_ADC1_AIN0 \ 1335 SAM_PINMUX(b, 8, b, periph) 1336 1337 /* pb8b_ptc_xy1 */ 1338 #define PB8B_PTC_XY1 \ 1339 SAM_PINMUX(b, 8, b, periph) 1340 1341 /* pb8d_sercom4_pad0 */ 1342 #define PB8D_SERCOM4_PAD0 \ 1343 SAM_PINMUX(b, 8, d, periph) 1344 1345 /* pb8e_tc4_wo0 */ 1346 #define PB8E_TC4_WO0 \ 1347 SAM_PINMUX(b, 8, e, periph) 1348 1349 /* pb8n_ccl_in8 */ 1350 #define PB8N_CCL_IN8 \ 1351 SAM_PINMUX(b, 8, n, periph) 1352 1353 /* pb9_gpio */ 1354 #define PB9_GPIO \ 1355 SAM_PINMUX(b, 9, gpio, gpio) 1356 1357 /* pb9a_eic_extint9 */ 1358 #define PB9A_EIC_EXTINT9 \ 1359 SAM_PINMUX(b, 9, a, periph) 1360 1361 /* pb9b_adc0_ain3 */ 1362 #define PB9B_ADC0_AIN3 \ 1363 SAM_PINMUX(b, 9, b, periph) 1364 1365 /* pb9b_adc1_ain1 */ 1366 #define PB9B_ADC1_AIN1 \ 1367 SAM_PINMUX(b, 9, b, periph) 1368 1369 /* pb9b_ptc_xy2 */ 1370 #define PB9B_PTC_XY2 \ 1371 SAM_PINMUX(b, 9, b, periph) 1372 1373 /* pb9d_sercom4_pad1 */ 1374 #define PB9D_SERCOM4_PAD1 \ 1375 SAM_PINMUX(b, 9, d, periph) 1376 1377 /* pb9e_tc4_wo1 */ 1378 #define PB9E_TC4_WO1 \ 1379 SAM_PINMUX(b, 9, e, periph) 1380 1381 /* pb9n_ccl_out2 */ 1382 #define PB9N_CCL_OUT2 \ 1383 SAM_PINMUX(b, 9, n, periph) 1384 1385 /* pb10_gpio */ 1386 #define PB10_GPIO \ 1387 SAM_PINMUX(b, 10, gpio, gpio) 1388 1389 /* pb10a_eic_extint10 */ 1390 #define PB10A_EIC_EXTINT10 \ 1391 SAM_PINMUX(b, 10, a, periph) 1392 1393 /* pb10d_sercom4_pad2 */ 1394 #define PB10D_SERCOM4_PAD2 \ 1395 SAM_PINMUX(b, 10, d, periph) 1396 1397 /* pb10e_tc5_wo0 */ 1398 #define PB10E_TC5_WO0 \ 1399 SAM_PINMUX(b, 10, e, periph) 1400 1401 /* pb10f_tcc0_wo4 */ 1402 #define PB10F_TCC0_WO4 \ 1403 SAM_PINMUX(b, 10, f, periph) 1404 1405 /* pb10g_tcc1_wo0 */ 1406 #define PB10G_TCC1_WO0 \ 1407 SAM_PINMUX(b, 10, g, periph) 1408 1409 /* pb10h_qspi_sck */ 1410 #define PB10H_QSPI_SCK \ 1411 SAM_PINMUX(b, 10, h, periph) 1412 1413 /* pb10i_sdhc0_dat3 */ 1414 #define PB10I_SDHC0_DAT3 \ 1415 SAM_PINMUX(b, 10, i, periph) 1416 1417 /* pb10j_iis_sdi */ 1418 #define PB10J_IIS_SDI \ 1419 SAM_PINMUX(b, 10, j, periph) 1420 1421 /* pb10m_gclk_io4 */ 1422 #define PB10M_GCLK_IO4 \ 1423 SAM_PINMUX(b, 10, m, periph) 1424 1425 /* pb10n_ccl_in11 */ 1426 #define PB10N_CCL_IN11 \ 1427 SAM_PINMUX(b, 10, n, periph) 1428 1429 /* pb11_gpio */ 1430 #define PB11_GPIO \ 1431 SAM_PINMUX(b, 11, gpio, gpio) 1432 1433 /* pb11a_eic_extint11 */ 1434 #define PB11A_EIC_EXTINT11 \ 1435 SAM_PINMUX(b, 11, a, periph) 1436 1437 /* pb11d_sercom4_pad3 */ 1438 #define PB11D_SERCOM4_PAD3 \ 1439 SAM_PINMUX(b, 11, d, periph) 1440 1441 /* pb11e_tc5_wo1 */ 1442 #define PB11E_TC5_WO1 \ 1443 SAM_PINMUX(b, 11, e, periph) 1444 1445 /* pb11f_tcc0_wo5 */ 1446 #define PB11F_TCC0_WO5 \ 1447 SAM_PINMUX(b, 11, f, periph) 1448 1449 /* pb11g_tcc1_wo1 */ 1450 #define PB11G_TCC1_WO1 \ 1451 SAM_PINMUX(b, 11, g, periph) 1452 1453 /* pb11h_qspi_cs */ 1454 #define PB11H_QSPI_CS \ 1455 SAM_PINMUX(b, 11, h, periph) 1456 1457 /* pb11i_sdhc0_ck */ 1458 #define PB11I_SDHC0_CK \ 1459 SAM_PINMUX(b, 11, i, periph) 1460 1461 /* pb11j_iis_fs1 */ 1462 #define PB11J_IIS_FS1 \ 1463 SAM_PINMUX(b, 11, j, periph) 1464 1465 /* pb11m_gclk_io5 */ 1466 #define PB11M_GCLK_IO5 \ 1467 SAM_PINMUX(b, 11, m, periph) 1468 1469 /* pb11n_ccl_out1 */ 1470 #define PB11N_CCL_OUT1 \ 1471 SAM_PINMUX(b, 11, n, periph) 1472 1473 /* pb12_gpio */ 1474 #define PB12_GPIO \ 1475 SAM_PINMUX(b, 12, gpio, gpio) 1476 1477 /* pb12a_eic_extint12 */ 1478 #define PB12A_EIC_EXTINT12 \ 1479 SAM_PINMUX(b, 12, a, periph) 1480 1481 /* pb12b_ptc_xy26 */ 1482 #define PB12B_PTC_XY26 \ 1483 SAM_PINMUX(b, 12, b, periph) 1484 1485 /* pb12c_sercom4_pad0 */ 1486 #define PB12C_SERCOM4_PAD0 \ 1487 SAM_PINMUX(b, 12, c, periph) 1488 1489 /* pb12e_tc4_wo0 */ 1490 #define PB12E_TC4_WO0 \ 1491 SAM_PINMUX(b, 12, e, periph) 1492 1493 /* pb12f_tcc3_wo0 */ 1494 #define PB12F_TCC3_WO0 \ 1495 SAM_PINMUX(b, 12, f, periph) 1496 1497 /* pb12g_tcc0_wo0 */ 1498 #define PB12G_TCC0_WO0 \ 1499 SAM_PINMUX(b, 12, g, periph) 1500 1501 /* pb12i_sdhc0_cd */ 1502 #define PB12I_SDHC0_CD \ 1503 SAM_PINMUX(b, 12, i, periph) 1504 1505 /* pb12j_iis_sck1 */ 1506 #define PB12J_IIS_SCK1 \ 1507 SAM_PINMUX(b, 12, j, periph) 1508 1509 /* pb12m_gclk_io6 */ 1510 #define PB12M_GCLK_IO6 \ 1511 SAM_PINMUX(b, 12, m, periph) 1512 1513 /* pb13_gpio */ 1514 #define PB13_GPIO \ 1515 SAM_PINMUX(b, 13, gpio, gpio) 1516 1517 /* pb13a_eic_extint13 */ 1518 #define PB13A_EIC_EXTINT13 \ 1519 SAM_PINMUX(b, 13, a, periph) 1520 1521 /* pb13b_ptc_xy27 */ 1522 #define PB13B_PTC_XY27 \ 1523 SAM_PINMUX(b, 13, b, periph) 1524 1525 /* pb13c_sercom4_pad1 */ 1526 #define PB13C_SERCOM4_PAD1 \ 1527 SAM_PINMUX(b, 13, c, periph) 1528 1529 /* pb13e_tc4_wo1 */ 1530 #define PB13E_TC4_WO1 \ 1531 SAM_PINMUX(b, 13, e, periph) 1532 1533 /* pb13f_tcc3_wo1 */ 1534 #define PB13F_TCC3_WO1 \ 1535 SAM_PINMUX(b, 13, f, periph) 1536 1537 /* pb13g_tcc0_wo1 */ 1538 #define PB13G_TCC0_WO1 \ 1539 SAM_PINMUX(b, 13, g, periph) 1540 1541 /* pb13i_sdhc0_wp */ 1542 #define PB13I_SDHC0_WP \ 1543 SAM_PINMUX(b, 13, i, periph) 1544 1545 /* pb13j_iis_mck1 */ 1546 #define PB13J_IIS_MCK1 \ 1547 SAM_PINMUX(b, 13, j, periph) 1548 1549 /* pb13m_gclk_io7 */ 1550 #define PB13M_GCLK_IO7 \ 1551 SAM_PINMUX(b, 13, m, periph) 1552 1553 /* pb14_gpio */ 1554 #define PB14_GPIO \ 1555 SAM_PINMUX(b, 14, gpio, gpio) 1556 1557 /* pb14a_eic_extint14 */ 1558 #define PB14A_EIC_EXTINT14 \ 1559 SAM_PINMUX(b, 14, a, periph) 1560 1561 /* pb14b_ptc_xy28 */ 1562 #define PB14B_PTC_XY28 \ 1563 SAM_PINMUX(b, 14, b, periph) 1564 1565 /* pb14c_sercom4_pad2 */ 1566 #define PB14C_SERCOM4_PAD2 \ 1567 SAM_PINMUX(b, 14, c, periph) 1568 1569 /* pb14e_tc5_wo0 */ 1570 #define PB14E_TC5_WO0 \ 1571 SAM_PINMUX(b, 14, e, periph) 1572 1573 /* pb14f_tcc4_wo0 */ 1574 #define PB14F_TCC4_WO0 \ 1575 SAM_PINMUX(b, 14, f, periph) 1576 1577 /* pb14g_tcc0_wo2 */ 1578 #define PB14G_TCC0_WO2 \ 1579 SAM_PINMUX(b, 14, g, periph) 1580 1581 /* pb14k_pcc_data8 */ 1582 #define PB14K_PCC_DATA8 \ 1583 SAM_PINMUX(b, 14, k, periph) 1584 1585 /* pb14l_gmac_gmdc */ 1586 #define PB14L_GMAC_GMDC \ 1587 SAM_PINMUX(b, 14, l, periph) 1588 1589 /* pb14m_gclk_io0 */ 1590 #define PB14M_GCLK_IO0 \ 1591 SAM_PINMUX(b, 14, m, periph) 1592 1593 /* pb14n_ccl_in9 */ 1594 #define PB14N_CCL_IN9 \ 1595 SAM_PINMUX(b, 14, n, periph) 1596 1597 /* pb15_gpio */ 1598 #define PB15_GPIO \ 1599 SAM_PINMUX(b, 15, gpio, gpio) 1600 1601 /* pb15a_eic_extint15 */ 1602 #define PB15A_EIC_EXTINT15 \ 1603 SAM_PINMUX(b, 15, a, periph) 1604 1605 /* pb15b_ptc_xy29 */ 1606 #define PB15B_PTC_XY29 \ 1607 SAM_PINMUX(b, 15, b, periph) 1608 1609 /* pb15c_sercom4_pad3 */ 1610 #define PB15C_SERCOM4_PAD3 \ 1611 SAM_PINMUX(b, 15, c, periph) 1612 1613 /* pb15e_tc5_wo1 */ 1614 #define PB15E_TC5_WO1 \ 1615 SAM_PINMUX(b, 15, e, periph) 1616 1617 /* pb15f_tcc4_wo1 */ 1618 #define PB15F_TCC4_WO1 \ 1619 SAM_PINMUX(b, 15, f, periph) 1620 1621 /* pb15g_tcc0_wo3 */ 1622 #define PB15G_TCC0_WO3 \ 1623 SAM_PINMUX(b, 15, g, periph) 1624 1625 /* pb15k_pcc_data9 */ 1626 #define PB15K_PCC_DATA9 \ 1627 SAM_PINMUX(b, 15, k, periph) 1628 1629 /* pb15l_gmac_gmdio */ 1630 #define PB15L_GMAC_GMDIO \ 1631 SAM_PINMUX(b, 15, l, periph) 1632 1633 /* pb15m_gclk_io1 */ 1634 #define PB15M_GCLK_IO1 \ 1635 SAM_PINMUX(b, 15, m, periph) 1636 1637 /* pb15n_ccl_in10 */ 1638 #define PB15N_CCL_IN10 \ 1639 SAM_PINMUX(b, 15, n, periph) 1640 1641 /* pb16_gpio */ 1642 #define PB16_GPIO \ 1643 SAM_PINMUX(b, 16, gpio, gpio) 1644 1645 /* pb16a_eic_extint0 */ 1646 #define PB16A_EIC_EXTINT0 \ 1647 SAM_PINMUX(b, 16, a, periph) 1648 1649 /* pb16c_sercom5_pad0 */ 1650 #define PB16C_SERCOM5_PAD0 \ 1651 SAM_PINMUX(b, 16, c, periph) 1652 1653 /* pb16e_tc6_wo0 */ 1654 #define PB16E_TC6_WO0 \ 1655 SAM_PINMUX(b, 16, e, periph) 1656 1657 /* pb16f_tcc3_wo0 */ 1658 #define PB16F_TCC3_WO0 \ 1659 SAM_PINMUX(b, 16, f, periph) 1660 1661 /* pb16g_tcc0_wo4 */ 1662 #define PB16G_TCC0_WO4 \ 1663 SAM_PINMUX(b, 16, g, periph) 1664 1665 /* pb16i_sdhc1_cd */ 1666 #define PB16I_SDHC1_CD \ 1667 SAM_PINMUX(b, 16, i, periph) 1668 1669 /* pb16j_iis_sck0 */ 1670 #define PB16J_IIS_SCK0 \ 1671 SAM_PINMUX(b, 16, j, periph) 1672 1673 /* pb16m_gclk_io2 */ 1674 #define PB16M_GCLK_IO2 \ 1675 SAM_PINMUX(b, 16, m, periph) 1676 1677 /* pb16n_ccl_in11 */ 1678 #define PB16N_CCL_IN11 \ 1679 SAM_PINMUX(b, 16, n, periph) 1680 1681 /* pb17_gpio */ 1682 #define PB17_GPIO \ 1683 SAM_PINMUX(b, 17, gpio, gpio) 1684 1685 /* pb17a_eic_extint1 */ 1686 #define PB17A_EIC_EXTINT1 \ 1687 SAM_PINMUX(b, 17, a, periph) 1688 1689 /* pb17c_sercom5_pad1 */ 1690 #define PB17C_SERCOM5_PAD1 \ 1691 SAM_PINMUX(b, 17, c, periph) 1692 1693 /* pb17e_tc6_wo1 */ 1694 #define PB17E_TC6_WO1 \ 1695 SAM_PINMUX(b, 17, e, periph) 1696 1697 /* pb17f_tcc3_wo1 */ 1698 #define PB17F_TCC3_WO1 \ 1699 SAM_PINMUX(b, 17, f, periph) 1700 1701 /* pb17g_tcc0_wo5 */ 1702 #define PB17G_TCC0_WO5 \ 1703 SAM_PINMUX(b, 17, g, periph) 1704 1705 /* pb17i_sdhc1_wp */ 1706 #define PB17I_SDHC1_WP \ 1707 SAM_PINMUX(b, 17, i, periph) 1708 1709 /* pb17j_iis_mck0 */ 1710 #define PB17J_IIS_MCK0 \ 1711 SAM_PINMUX(b, 17, j, periph) 1712 1713 /* pb17m_gclk_io3 */ 1714 #define PB17M_GCLK_IO3 \ 1715 SAM_PINMUX(b, 17, m, periph) 1716 1717 /* pb17n_ccl_out3 */ 1718 #define PB17N_CCL_OUT3 \ 1719 SAM_PINMUX(b, 17, n, periph) 1720 1721 /* pb18_gpio */ 1722 #define PB18_GPIO \ 1723 SAM_PINMUX(b, 18, gpio, gpio) 1724 1725 /* pb18a_eic_extint2 */ 1726 #define PB18A_EIC_EXTINT2 \ 1727 SAM_PINMUX(b, 18, a, periph) 1728 1729 /* pb18c_sercom5_pad2 */ 1730 #define PB18C_SERCOM5_PAD2 \ 1731 SAM_PINMUX(b, 18, c, periph) 1732 1733 /* pb18d_sercom7_pad2 */ 1734 #define PB18D_SERCOM7_PAD2 \ 1735 SAM_PINMUX(b, 18, d, periph) 1736 1737 /* pb18f_tcc1_wo0 */ 1738 #define PB18F_TCC1_WO0 \ 1739 SAM_PINMUX(b, 18, f, periph) 1740 1741 /* pb18g_pdec_qdi0 */ 1742 #define PB18G_PDEC_QDI0 \ 1743 SAM_PINMUX(b, 18, g, periph) 1744 1745 /* pb18i_sdhc1_dat0 */ 1746 #define PB18I_SDHC1_DAT0 \ 1747 SAM_PINMUX(b, 18, i, periph) 1748 1749 /* pb18m_gclk_io4 */ 1750 #define PB18M_GCLK_IO4 \ 1751 SAM_PINMUX(b, 18, m, periph) 1752 1753 /* pb19_gpio */ 1754 #define PB19_GPIO \ 1755 SAM_PINMUX(b, 19, gpio, gpio) 1756 1757 /* pb19a_eic_extint3 */ 1758 #define PB19A_EIC_EXTINT3 \ 1759 SAM_PINMUX(b, 19, a, periph) 1760 1761 /* pb19c_sercom5_pad3 */ 1762 #define PB19C_SERCOM5_PAD3 \ 1763 SAM_PINMUX(b, 19, c, periph) 1764 1765 /* pb19d_sercom7_pad3 */ 1766 #define PB19D_SERCOM7_PAD3 \ 1767 SAM_PINMUX(b, 19, d, periph) 1768 1769 /* pb19f_tcc1_wo1 */ 1770 #define PB19F_TCC1_WO1 \ 1771 SAM_PINMUX(b, 19, f, periph) 1772 1773 /* pb19g_pdec_qdi1 */ 1774 #define PB19G_PDEC_QDI1 \ 1775 SAM_PINMUX(b, 19, g, periph) 1776 1777 /* pb19i_sdhc1_dat1 */ 1778 #define PB19I_SDHC1_DAT1 \ 1779 SAM_PINMUX(b, 19, i, periph) 1780 1781 /* pb19m_gclk_io5 */ 1782 #define PB19M_GCLK_IO5 \ 1783 SAM_PINMUX(b, 19, m, periph) 1784 1785 /* pb20_gpio */ 1786 #define PB20_GPIO \ 1787 SAM_PINMUX(b, 20, gpio, gpio) 1788 1789 /* pb20a_eic_extint4 */ 1790 #define PB20A_EIC_EXTINT4 \ 1791 SAM_PINMUX(b, 20, a, periph) 1792 1793 /* pb20c_sercom3_pad0 */ 1794 #define PB20C_SERCOM3_PAD0 \ 1795 SAM_PINMUX(b, 20, c, periph) 1796 1797 /* pb20d_sercom7_pad1 */ 1798 #define PB20D_SERCOM7_PAD1 \ 1799 SAM_PINMUX(b, 20, d, periph) 1800 1801 /* pb20f_tcc1_wo2 */ 1802 #define PB20F_TCC1_WO2 \ 1803 SAM_PINMUX(b, 20, f, periph) 1804 1805 /* pb20g_pdec_qdi2 */ 1806 #define PB20G_PDEC_QDI2 \ 1807 SAM_PINMUX(b, 20, g, periph) 1808 1809 /* pb20i_sdhc1_dat2 */ 1810 #define PB20I_SDHC1_DAT2 \ 1811 SAM_PINMUX(b, 20, i, periph) 1812 1813 /* pb20m_gclk_io6 */ 1814 #define PB20M_GCLK_IO6 \ 1815 SAM_PINMUX(b, 20, m, periph) 1816 1817 /* pb21_gpio */ 1818 #define PB21_GPIO \ 1819 SAM_PINMUX(b, 21, gpio, gpio) 1820 1821 /* pb21a_eic_extint5 */ 1822 #define PB21A_EIC_EXTINT5 \ 1823 SAM_PINMUX(b, 21, a, periph) 1824 1825 /* pb21c_sercom3_pad1 */ 1826 #define PB21C_SERCOM3_PAD1 \ 1827 SAM_PINMUX(b, 21, c, periph) 1828 1829 /* pb21d_sercom7_pad0 */ 1830 #define PB21D_SERCOM7_PAD0 \ 1831 SAM_PINMUX(b, 21, d, periph) 1832 1833 /* pb21f_tcc1_wo3 */ 1834 #define PB21F_TCC1_WO3 \ 1835 SAM_PINMUX(b, 21, f, periph) 1836 1837 /* pb21i_sdhc1_dat3 */ 1838 #define PB21I_SDHC1_DAT3 \ 1839 SAM_PINMUX(b, 21, i, periph) 1840 1841 /* pb21m_gclk_io7 */ 1842 #define PB21M_GCLK_IO7 \ 1843 SAM_PINMUX(b, 21, m, periph) 1844 1845 /* pb22_gpio */ 1846 #define PB22_GPIO \ 1847 SAM_PINMUX(b, 22, gpio, gpio) 1848 1849 /* pb22a_eic_extint6 */ 1850 #define PB22A_EIC_EXTINT6 \ 1851 SAM_PINMUX(b, 22, a, periph) 1852 1853 /* pb22c_sercom1_pad2 */ 1854 #define PB22C_SERCOM1_PAD2 \ 1855 SAM_PINMUX(b, 22, c, periph) 1856 1857 /* pb22d_sercom5_pad2 */ 1858 #define PB22D_SERCOM5_PAD2 \ 1859 SAM_PINMUX(b, 22, d, periph) 1860 1861 /* pb22e_tc7_wo0 */ 1862 #define PB22E_TC7_WO0 \ 1863 SAM_PINMUX(b, 22, e, periph) 1864 1865 /* pb22g_pdec_qdi2 */ 1866 #define PB22G_PDEC_QDI2 \ 1867 SAM_PINMUX(b, 22, g, periph) 1868 1869 /* pb22h_usb_sof */ 1870 #define PB22H_USB_SOF \ 1871 SAM_PINMUX(b, 22, h, periph) 1872 1873 /* pb22m_gclk_io0 */ 1874 #define PB22M_GCLK_IO0 \ 1875 SAM_PINMUX(b, 22, m, periph) 1876 1877 /* pb22n_ccl_in0 */ 1878 #define PB22N_CCL_IN0 \ 1879 SAM_PINMUX(b, 22, n, periph) 1880 1881 /* pb23_gpio */ 1882 #define PB23_GPIO \ 1883 SAM_PINMUX(b, 23, gpio, gpio) 1884 1885 /* pb23a_eic_extint7 */ 1886 #define PB23A_EIC_EXTINT7 \ 1887 SAM_PINMUX(b, 23, a, periph) 1888 1889 /* pb23c_sercom1_pad3 */ 1890 #define PB23C_SERCOM1_PAD3 \ 1891 SAM_PINMUX(b, 23, c, periph) 1892 1893 /* pb23d_sercom5_pad3 */ 1894 #define PB23D_SERCOM5_PAD3 \ 1895 SAM_PINMUX(b, 23, d, periph) 1896 1897 /* pb23e_tc7_wo1 */ 1898 #define PB23E_TC7_WO1 \ 1899 SAM_PINMUX(b, 23, e, periph) 1900 1901 /* pb23g_pdec_qdi0 */ 1902 #define PB23G_PDEC_QDI0 \ 1903 SAM_PINMUX(b, 23, g, periph) 1904 1905 /* pb23m_gclk_io1 */ 1906 #define PB23M_GCLK_IO1 \ 1907 SAM_PINMUX(b, 23, m, periph) 1908 1909 /* pb23n_ccl_out0 */ 1910 #define PB23N_CCL_OUT0 \ 1911 SAM_PINMUX(b, 23, n, periph) 1912 1913 /* pb24_gpio */ 1914 #define PB24_GPIO \ 1915 SAM_PINMUX(b, 24, gpio, gpio) 1916 1917 /* pb24a_eic_extint8 */ 1918 #define PB24A_EIC_EXTINT8 \ 1919 SAM_PINMUX(b, 24, a, periph) 1920 1921 /* pb24c_sercom0_pad0 */ 1922 #define PB24C_SERCOM0_PAD0 \ 1923 SAM_PINMUX(b, 24, c, periph) 1924 1925 /* pb24d_sercom2_pad1 */ 1926 #define PB24D_SERCOM2_PAD1 \ 1927 SAM_PINMUX(b, 24, d, periph) 1928 1929 /* pb24g_pdec_qdi1 */ 1930 #define PB24G_PDEC_QDI1 \ 1931 SAM_PINMUX(b, 24, g, periph) 1932 1933 /* pb24m_ac_cmp0 */ 1934 #define PB24M_AC_CMP0 \ 1935 SAM_PINMUX(b, 24, m, periph) 1936 1937 /* pb25_gpio */ 1938 #define PB25_GPIO \ 1939 SAM_PINMUX(b, 25, gpio, gpio) 1940 1941 /* pb25a_eic_extint9 */ 1942 #define PB25A_EIC_EXTINT9 \ 1943 SAM_PINMUX(b, 25, a, periph) 1944 1945 /* pb25c_sercom0_pad1 */ 1946 #define PB25C_SERCOM0_PAD1 \ 1947 SAM_PINMUX(b, 25, c, periph) 1948 1949 /* pb25d_sercom2_pad0 */ 1950 #define PB25D_SERCOM2_PAD0 \ 1951 SAM_PINMUX(b, 25, d, periph) 1952 1953 /* pb25g_pdec_qdi2 */ 1954 #define PB25G_PDEC_QDI2 \ 1955 SAM_PINMUX(b, 25, g, periph) 1956 1957 /* pb25m_ac_cmp1 */ 1958 #define PB25M_AC_CMP1 \ 1959 SAM_PINMUX(b, 25, m, periph) 1960 1961 /* pb30_gpio */ 1962 #define PB30_GPIO \ 1963 SAM_PINMUX(b, 30, gpio, gpio) 1964 1965 /* pb30a_eic_extint14 */ 1966 #define PB30A_EIC_EXTINT14 \ 1967 SAM_PINMUX(b, 30, a, periph) 1968 1969 /* pb30d_sercom5_pad1 */ 1970 #define PB30D_SERCOM5_PAD1 \ 1971 SAM_PINMUX(b, 30, d, periph) 1972 1973 /* pb30e_tc0_wo0 */ 1974 #define PB30E_TC0_WO0 \ 1975 SAM_PINMUX(b, 30, e, periph) 1976 1977 /* pb30f_tcc4_wo0 */ 1978 #define PB30F_TCC4_WO0 \ 1979 SAM_PINMUX(b, 30, f, periph) 1980 1981 /* pb30g_tcc0_wo6 */ 1982 #define PB30G_TCC0_WO6 \ 1983 SAM_PINMUX(b, 30, g, periph) 1984 1985 /* pb30h_swd_swo */ 1986 #define PB30H_SWD_SWO \ 1987 SAM_PINMUX(b, 30, h, periph) 1988 1989 /* pb31_gpio */ 1990 #define PB31_GPIO \ 1991 SAM_PINMUX(b, 31, gpio, gpio) 1992 1993 /* pb31a_eic_extint15 */ 1994 #define PB31A_EIC_EXTINT15 \ 1995 SAM_PINMUX(b, 31, a, periph) 1996 1997 /* pb31d_sercom5_pad0 */ 1998 #define PB31D_SERCOM5_PAD0 \ 1999 SAM_PINMUX(b, 31, d, periph) 2000 2001 /* pb31e_tc0_wo1 */ 2002 #define PB31E_TC0_WO1 \ 2003 SAM_PINMUX(b, 31, e, periph) 2004 2005 /* pb31f_tcc4_wo1 */ 2006 #define PB31F_TCC4_WO1 \ 2007 SAM_PINMUX(b, 31, f, periph) 2008 2009 /* pb31g_tcc0_wo7 */ 2010 #define PB31G_TCC0_WO7 \ 2011 SAM_PINMUX(b, 31, g, periph) 2012 2013 /* pc0_gpio */ 2014 #define PC0_GPIO \ 2015 SAM_PINMUX(c, 0, gpio, gpio) 2016 2017 /* pc0a_eic_extint0 */ 2018 #define PC0A_EIC_EXTINT0 \ 2019 SAM_PINMUX(c, 0, a, periph) 2020 2021 /* pc0b_adc1_ain10 */ 2022 #define PC0B_ADC1_AIN10 \ 2023 SAM_PINMUX(c, 0, b, periph) 2024 2025 /* pc1_gpio */ 2026 #define PC1_GPIO \ 2027 SAM_PINMUX(c, 1, gpio, gpio) 2028 2029 /* pc1a_eic_extint1 */ 2030 #define PC1A_EIC_EXTINT1 \ 2031 SAM_PINMUX(c, 1, a, periph) 2032 2033 /* pc1b_adc1_ain11 */ 2034 #define PC1B_ADC1_AIN11 \ 2035 SAM_PINMUX(c, 1, b, periph) 2036 2037 /* pc2_gpio */ 2038 #define PC2_GPIO \ 2039 SAM_PINMUX(c, 2, gpio, gpio) 2040 2041 /* pc2a_eic_extint2 */ 2042 #define PC2A_EIC_EXTINT2 \ 2043 SAM_PINMUX(c, 2, a, periph) 2044 2045 /* pc2b_adc1_ain4 */ 2046 #define PC2B_ADC1_AIN4 \ 2047 SAM_PINMUX(c, 2, b, periph) 2048 2049 /* pc3_gpio */ 2050 #define PC3_GPIO \ 2051 SAM_PINMUX(c, 3, gpio, gpio) 2052 2053 /* pc3a_eic_extint3 */ 2054 #define PC3A_EIC_EXTINT3 \ 2055 SAM_PINMUX(c, 3, a, periph) 2056 2057 /* pc3b_adc1_ain5 */ 2058 #define PC3B_ADC1_AIN5 \ 2059 SAM_PINMUX(c, 3, b, periph) 2060 2061 /* pc5_gpio */ 2062 #define PC5_GPIO \ 2063 SAM_PINMUX(c, 5, gpio, gpio) 2064 2065 /* pc5a_eic_extint5 */ 2066 #define PC5A_EIC_EXTINT5 \ 2067 SAM_PINMUX(c, 5, a, periph) 2068 2069 /* pc5c_sercom6_pad1 */ 2070 #define PC5C_SERCOM6_PAD1 \ 2071 SAM_PINMUX(c, 5, c, periph) 2072 2073 /* pc6_gpio */ 2074 #define PC6_GPIO \ 2075 SAM_PINMUX(c, 6, gpio, gpio) 2076 2077 /* pc6a_eic_extint6 */ 2078 #define PC6A_EIC_EXTINT6 \ 2079 SAM_PINMUX(c, 6, a, periph) 2080 2081 /* pc6c_sercom6_pad2 */ 2082 #define PC6C_SERCOM6_PAD2 \ 2083 SAM_PINMUX(c, 6, c, periph) 2084 2085 /* pc6i_sdhc0_cd */ 2086 #define PC6I_SDHC0_CD \ 2087 SAM_PINMUX(c, 6, i, periph) 2088 2089 /* pc7_gpio */ 2090 #define PC7_GPIO \ 2091 SAM_PINMUX(c, 7, gpio, gpio) 2092 2093 /* pc7a_eic_extint7 */ 2094 #define PC7A_EIC_EXTINT7 \ 2095 SAM_PINMUX(c, 7, a, periph) 2096 2097 /* pc7c_sercom6_pad3 */ 2098 #define PC7C_SERCOM6_PAD3 \ 2099 SAM_PINMUX(c, 7, c, periph) 2100 2101 /* pc7i_sdhc0_wp */ 2102 #define PC7I_SDHC0_WP \ 2103 SAM_PINMUX(c, 7, i, periph) 2104 2105 /* pc10_gpio */ 2106 #define PC10_GPIO \ 2107 SAM_PINMUX(c, 10, gpio, gpio) 2108 2109 /* pc10a_eic_extint10 */ 2110 #define PC10A_EIC_EXTINT10 \ 2111 SAM_PINMUX(c, 10, a, periph) 2112 2113 /* pc10c_sercom6_pad2 */ 2114 #define PC10C_SERCOM6_PAD2 \ 2115 SAM_PINMUX(c, 10, c, periph) 2116 2117 /* pc10d_sercom7_pad2 */ 2118 #define PC10D_SERCOM7_PAD2 \ 2119 SAM_PINMUX(c, 10, d, periph) 2120 2121 /* pc10f_tcc0_wo0 */ 2122 #define PC10F_TCC0_WO0 \ 2123 SAM_PINMUX(c, 10, f, periph) 2124 2125 /* pc10g_tcc1_wo4 */ 2126 #define PC10G_TCC1_WO4 \ 2127 SAM_PINMUX(c, 10, g, periph) 2128 2129 /* pc11_gpio */ 2130 #define PC11_GPIO \ 2131 SAM_PINMUX(c, 11, gpio, gpio) 2132 2133 /* pc11a_eic_extint11 */ 2134 #define PC11A_EIC_EXTINT11 \ 2135 SAM_PINMUX(c, 11, a, periph) 2136 2137 /* pc11c_sercom6_pad3 */ 2138 #define PC11C_SERCOM6_PAD3 \ 2139 SAM_PINMUX(c, 11, c, periph) 2140 2141 /* pc11d_sercom7_pad3 */ 2142 #define PC11D_SERCOM7_PAD3 \ 2143 SAM_PINMUX(c, 11, d, periph) 2144 2145 /* pc11f_tcc0_wo1 */ 2146 #define PC11F_TCC0_WO1 \ 2147 SAM_PINMUX(c, 11, f, periph) 2148 2149 /* pc11g_tcc1_wo5 */ 2150 #define PC11G_TCC1_WO5 \ 2151 SAM_PINMUX(c, 11, g, periph) 2152 2153 /* pc11l_gmac_gmdc */ 2154 #define PC11L_GMAC_GMDC \ 2155 SAM_PINMUX(c, 11, l, periph) 2156 2157 /* pc12_gpio */ 2158 #define PC12_GPIO \ 2159 SAM_PINMUX(c, 12, gpio, gpio) 2160 2161 /* pc12a_eic_extint12 */ 2162 #define PC12A_EIC_EXTINT12 \ 2163 SAM_PINMUX(c, 12, a, periph) 2164 2165 /* pc12c_sercom7_pad0 */ 2166 #define PC12C_SERCOM7_PAD0 \ 2167 SAM_PINMUX(c, 12, c, periph) 2168 2169 /* pc12d_sercom6_pad1 */ 2170 #define PC12D_SERCOM6_PAD1 \ 2171 SAM_PINMUX(c, 12, d, periph) 2172 2173 /* pc12f_tcc0_wo2 */ 2174 #define PC12F_TCC0_WO2 \ 2175 SAM_PINMUX(c, 12, f, periph) 2176 2177 /* pc12g_tcc1_wo6 */ 2178 #define PC12G_TCC1_WO6 \ 2179 SAM_PINMUX(c, 12, g, periph) 2180 2181 /* pc12k_pcc_data10 */ 2182 #define PC12K_PCC_DATA10 \ 2183 SAM_PINMUX(c, 12, k, periph) 2184 2185 /* pc12l_gmac_gmdio */ 2186 #define PC12L_GMAC_GMDIO \ 2187 SAM_PINMUX(c, 12, l, periph) 2188 2189 /* pc13_gpio */ 2190 #define PC13_GPIO \ 2191 SAM_PINMUX(c, 13, gpio, gpio) 2192 2193 /* pc13a_eic_extint13 */ 2194 #define PC13A_EIC_EXTINT13 \ 2195 SAM_PINMUX(c, 13, a, periph) 2196 2197 /* pc13c_sercom7_pad1 */ 2198 #define PC13C_SERCOM7_PAD1 \ 2199 SAM_PINMUX(c, 13, c, periph) 2200 2201 /* pc13d_sercom6_pad0 */ 2202 #define PC13D_SERCOM6_PAD0 \ 2203 SAM_PINMUX(c, 13, d, periph) 2204 2205 /* pc13f_tcc0_wo3 */ 2206 #define PC13F_TCC0_WO3 \ 2207 SAM_PINMUX(c, 13, f, periph) 2208 2209 /* pc13g_tcc1_wo7 */ 2210 #define PC13G_TCC1_WO7 \ 2211 SAM_PINMUX(c, 13, g, periph) 2212 2213 /* pc13k_pcc_data11 */ 2214 #define PC13K_PCC_DATA11 \ 2215 SAM_PINMUX(c, 13, k, periph) 2216 2217 /* pc14_gpio */ 2218 #define PC14_GPIO \ 2219 SAM_PINMUX(c, 14, gpio, gpio) 2220 2221 /* pc14a_eic_extint14 */ 2222 #define PC14A_EIC_EXTINT14 \ 2223 SAM_PINMUX(c, 14, a, periph) 2224 2225 /* pc14c_sercom7_pad2 */ 2226 #define PC14C_SERCOM7_PAD2 \ 2227 SAM_PINMUX(c, 14, c, periph) 2228 2229 /* pc14d_sercom6_pad2 */ 2230 #define PC14D_SERCOM6_PAD2 \ 2231 SAM_PINMUX(c, 14, d, periph) 2232 2233 /* pc14f_tcc0_wo4 */ 2234 #define PC14F_TCC0_WO4 \ 2235 SAM_PINMUX(c, 14, f, periph) 2236 2237 /* pc14g_tcc1_wo0 */ 2238 #define PC14G_TCC1_WO0 \ 2239 SAM_PINMUX(c, 14, g, periph) 2240 2241 /* pc14k_pcc_data12 */ 2242 #define PC14K_PCC_DATA12 \ 2243 SAM_PINMUX(c, 14, k, periph) 2244 2245 /* pc14l_gmac_grx3 */ 2246 #define PC14L_GMAC_GRX3 \ 2247 SAM_PINMUX(c, 14, l, periph) 2248 2249 /* pc15_gpio */ 2250 #define PC15_GPIO \ 2251 SAM_PINMUX(c, 15, gpio, gpio) 2252 2253 /* pc15a_eic_extint15 */ 2254 #define PC15A_EIC_EXTINT15 \ 2255 SAM_PINMUX(c, 15, a, periph) 2256 2257 /* pc15c_sercom7_pad3 */ 2258 #define PC15C_SERCOM7_PAD3 \ 2259 SAM_PINMUX(c, 15, c, periph) 2260 2261 /* pc15d_sercom6_pad3 */ 2262 #define PC15D_SERCOM6_PAD3 \ 2263 SAM_PINMUX(c, 15, d, periph) 2264 2265 /* pc15f_tcc0_wo5 */ 2266 #define PC15F_TCC0_WO5 \ 2267 SAM_PINMUX(c, 15, f, periph) 2268 2269 /* pc15g_tcc1_wo1 */ 2270 #define PC15G_TCC1_WO1 \ 2271 SAM_PINMUX(c, 15, g, periph) 2272 2273 /* pc15k_pcc_data13 */ 2274 #define PC15K_PCC_DATA13 \ 2275 SAM_PINMUX(c, 15, k, periph) 2276 2277 /* pc15l_gmac_grx2 */ 2278 #define PC15L_GMAC_GRX2 \ 2279 SAM_PINMUX(c, 15, l, periph) 2280 2281 /* pc16_gpio */ 2282 #define PC16_GPIO \ 2283 SAM_PINMUX(c, 16, gpio, gpio) 2284 2285 /* pc16a_eic_extint0 */ 2286 #define PC16A_EIC_EXTINT0 \ 2287 SAM_PINMUX(c, 16, a, periph) 2288 2289 /* pc16c_sercom6_pad0 */ 2290 #define PC16C_SERCOM6_PAD0 \ 2291 SAM_PINMUX(c, 16, c, periph) 2292 2293 /* pc16d_sercom0_pad1 */ 2294 #define PC16D_SERCOM0_PAD1 \ 2295 SAM_PINMUX(c, 16, d, periph) 2296 2297 /* pc16f_tcc0_wo0 */ 2298 #define PC16F_TCC0_WO0 \ 2299 SAM_PINMUX(c, 16, f, periph) 2300 2301 /* pc16g_pdec_qdi0 */ 2302 #define PC16G_PDEC_QDI0 \ 2303 SAM_PINMUX(c, 16, g, periph) 2304 2305 /* pc16l_gmac_gtx2 */ 2306 #define PC16L_GMAC_GTX2 \ 2307 SAM_PINMUX(c, 16, l, periph) 2308 2309 /* pc17_gpio */ 2310 #define PC17_GPIO \ 2311 SAM_PINMUX(c, 17, gpio, gpio) 2312 2313 /* pc17a_eic_extint1 */ 2314 #define PC17A_EIC_EXTINT1 \ 2315 SAM_PINMUX(c, 17, a, periph) 2316 2317 /* pc17c_sercom6_pad1 */ 2318 #define PC17C_SERCOM6_PAD1 \ 2319 SAM_PINMUX(c, 17, c, periph) 2320 2321 /* pc17d_sercom0_pad0 */ 2322 #define PC17D_SERCOM0_PAD0 \ 2323 SAM_PINMUX(c, 17, d, periph) 2324 2325 /* pc17f_tcc0_wo1 */ 2326 #define PC17F_TCC0_WO1 \ 2327 SAM_PINMUX(c, 17, f, periph) 2328 2329 /* pc17g_pdec_qdi1 */ 2330 #define PC17G_PDEC_QDI1 \ 2331 SAM_PINMUX(c, 17, g, periph) 2332 2333 /* pc17l_gmac_gtx3 */ 2334 #define PC17L_GMAC_GTX3 \ 2335 SAM_PINMUX(c, 17, l, periph) 2336 2337 /* pc18_gpio */ 2338 #define PC18_GPIO \ 2339 SAM_PINMUX(c, 18, gpio, gpio) 2340 2341 /* pc18a_eic_extint2 */ 2342 #define PC18A_EIC_EXTINT2 \ 2343 SAM_PINMUX(c, 18, a, periph) 2344 2345 /* pc18c_sercom6_pad2 */ 2346 #define PC18C_SERCOM6_PAD2 \ 2347 SAM_PINMUX(c, 18, c, periph) 2348 2349 /* pc18d_sercom0_pad2 */ 2350 #define PC18D_SERCOM0_PAD2 \ 2351 SAM_PINMUX(c, 18, d, periph) 2352 2353 /* pc18f_tcc0_wo2 */ 2354 #define PC18F_TCC0_WO2 \ 2355 SAM_PINMUX(c, 18, f, periph) 2356 2357 /* pc18g_pdec_qdi2 */ 2358 #define PC18G_PDEC_QDI2 \ 2359 SAM_PINMUX(c, 18, g, periph) 2360 2361 /* pc18l_gmac_grxck */ 2362 #define PC18L_GMAC_GRXCK \ 2363 SAM_PINMUX(c, 18, l, periph) 2364 2365 /* pc19_gpio */ 2366 #define PC19_GPIO \ 2367 SAM_PINMUX(c, 19, gpio, gpio) 2368 2369 /* pc19a_eic_extint3 */ 2370 #define PC19A_EIC_EXTINT3 \ 2371 SAM_PINMUX(c, 19, a, periph) 2372 2373 /* pc19c_sercom6_pad3 */ 2374 #define PC19C_SERCOM6_PAD3 \ 2375 SAM_PINMUX(c, 19, c, periph) 2376 2377 /* pc19d_sercom0_pad3 */ 2378 #define PC19D_SERCOM0_PAD3 \ 2379 SAM_PINMUX(c, 19, d, periph) 2380 2381 /* pc19f_tcc0_wo3 */ 2382 #define PC19F_TCC0_WO3 \ 2383 SAM_PINMUX(c, 19, f, periph) 2384 2385 /* pc19l_gmac_gtxer */ 2386 #define PC19L_GMAC_GTXER \ 2387 SAM_PINMUX(c, 19, l, periph) 2388 2389 /* pc20_gpio */ 2390 #define PC20_GPIO \ 2391 SAM_PINMUX(c, 20, gpio, gpio) 2392 2393 /* pc20a_eic_extint4 */ 2394 #define PC20A_EIC_EXTINT4 \ 2395 SAM_PINMUX(c, 20, a, periph) 2396 2397 /* pc20f_tcc0_wo4 */ 2398 #define PC20F_TCC0_WO4 \ 2399 SAM_PINMUX(c, 20, f, periph) 2400 2401 /* pc20i_sdhc1_cd */ 2402 #define PC20I_SDHC1_CD \ 2403 SAM_PINMUX(c, 20, i, periph) 2404 2405 /* pc20l_gmac_grxdv */ 2406 #define PC20L_GMAC_GRXDV \ 2407 SAM_PINMUX(c, 20, l, periph) 2408 2409 /* pc20n_ccl_in9 */ 2410 #define PC20N_CCL_IN9 \ 2411 SAM_PINMUX(c, 20, n, periph) 2412 2413 /* pc21_gpio */ 2414 #define PC21_GPIO \ 2415 SAM_PINMUX(c, 21, gpio, gpio) 2416 2417 /* pc21a_eic_extint5 */ 2418 #define PC21A_EIC_EXTINT5 \ 2419 SAM_PINMUX(c, 21, a, periph) 2420 2421 /* pc21f_tcc0_wo5 */ 2422 #define PC21F_TCC0_WO5 \ 2423 SAM_PINMUX(c, 21, f, periph) 2424 2425 /* pc21i_sdhc1_wp */ 2426 #define PC21I_SDHC1_WP \ 2427 SAM_PINMUX(c, 21, i, periph) 2428 2429 /* pc21l_gmac_gcol */ 2430 #define PC21L_GMAC_GCOL \ 2431 SAM_PINMUX(c, 21, l, periph) 2432 2433 /* pc21n_ccl_in10 */ 2434 #define PC21N_CCL_IN10 \ 2435 SAM_PINMUX(c, 21, n, periph) 2436 2437 /* pc24_gpio */ 2438 #define PC24_GPIO \ 2439 SAM_PINMUX(c, 24, gpio, gpio) 2440 2441 /* pc24a_eic_extint8 */ 2442 #define PC24A_EIC_EXTINT8 \ 2443 SAM_PINMUX(c, 24, a, periph) 2444 2445 /* pc24c_sercom0_pad2 */ 2446 #define PC24C_SERCOM0_PAD2 \ 2447 SAM_PINMUX(c, 24, c, periph) 2448 2449 /* pc24d_sercom2_pad2 */ 2450 #define PC24D_SERCOM2_PAD2 \ 2451 SAM_PINMUX(c, 24, d, periph) 2452 2453 /* pc24h_trace_data3 */ 2454 #define PC24H_TRACE_DATA3 \ 2455 SAM_PINMUX(c, 24, h, periph) 2456 2457 /* pc25_gpio */ 2458 #define PC25_GPIO \ 2459 SAM_PINMUX(c, 25, gpio, gpio) 2460 2461 /* pc25a_eic_extint9 */ 2462 #define PC25A_EIC_EXTINT9 \ 2463 SAM_PINMUX(c, 25, a, periph) 2464 2465 /* pc25c_sercom0_pad3 */ 2466 #define PC25C_SERCOM0_PAD3 \ 2467 SAM_PINMUX(c, 25, c, periph) 2468 2469 /* pc25d_sercom2_pad3 */ 2470 #define PC25D_SERCOM2_PAD3 \ 2471 SAM_PINMUX(c, 25, d, periph) 2472 2473 /* pc25h_trace_data2 */ 2474 #define PC25H_TRACE_DATA2 \ 2475 SAM_PINMUX(c, 25, h, periph) 2476 2477 /* pc26_gpio */ 2478 #define PC26_GPIO \ 2479 SAM_PINMUX(c, 26, gpio, gpio) 2480 2481 /* pc26a_eic_extint10 */ 2482 #define PC26A_EIC_EXTINT10 \ 2483 SAM_PINMUX(c, 26, a, periph) 2484 2485 /* pc26h_trace_data1 */ 2486 #define PC26H_TRACE_DATA1 \ 2487 SAM_PINMUX(c, 26, h, periph) 2488 2489 /* pc27_gpio */ 2490 #define PC27_GPIO \ 2491 SAM_PINMUX(c, 27, gpio, gpio) 2492 2493 /* pc27a_eic_extint11 */ 2494 #define PC27A_EIC_EXTINT11 \ 2495 SAM_PINMUX(c, 27, a, periph) 2496 2497 /* pc27c_sercom1_pad0 */ 2498 #define PC27C_SERCOM1_PAD0 \ 2499 SAM_PINMUX(c, 27, c, periph) 2500 2501 /* pc27h_trace_clk */ 2502 #define PC27H_TRACE_CLK \ 2503 SAM_PINMUX(c, 27, h, periph) 2504 2505 /* pc27m_swd_swo */ 2506 #define PC27M_SWD_SWO \ 2507 SAM_PINMUX(c, 27, m, periph) 2508 2509 /* pc27n_ccl_in4 */ 2510 #define PC27N_CCL_IN4 \ 2511 SAM_PINMUX(c, 27, n, periph) 2512 2513 /* pc28_gpio */ 2514 #define PC28_GPIO \ 2515 SAM_PINMUX(c, 28, gpio, gpio) 2516 2517 /* pc28a_eic_extint12 */ 2518 #define PC28A_EIC_EXTINT12 \ 2519 SAM_PINMUX(c, 28, a, periph) 2520 2521 /* pc28c_sercom1_pad1 */ 2522 #define PC28C_SERCOM1_PAD1 \ 2523 SAM_PINMUX(c, 28, c, periph) 2524 2525 /* pc28h_trace_data0 */ 2526 #define PC28H_TRACE_DATA0 \ 2527 SAM_PINMUX(c, 28, h, periph) 2528 2529 /* pc28n_ccl_in5 */ 2530 #define PC28N_CCL_IN5 \ 2531 SAM_PINMUX(c, 28, n, periph) 2532
