1 /* 2 * Autogenerated file 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #include <dt-bindings/pinctrl/atmel_sam_pinctrl.h> 8 9 /* 10 * WARNING: this variant has package exception. 11 * 12 * Read datasheet topics related to I/O Multiplexing and Considerations or 13 * Peripheral Signal Multiplexing on I/O Lines for more information. 14 */ 15 16 /* pa0_gpio */ 17 #define PA0_GPIO \ 18 SAM_PINMUX(a, 0, gpio, gpio) 19 20 /* pa0a_eic_extint0 */ 21 #define PA0A_EIC_EXTINT0 \ 22 SAM_PINMUX(a, 0, a, periph) 23 24 /* pa0d_sercom1_pad0 */ 25 #define PA0D_SERCOM1_PAD0 \ 26 SAM_PINMUX(a, 0, d, periph) 27 28 /* pa0e_tc2_wo0 */ 29 #define PA0E_TC2_WO0 \ 30 SAM_PINMUX(a, 0, e, periph) 31 32 /* pa1_gpio */ 33 #define PA1_GPIO \ 34 SAM_PINMUX(a, 1, gpio, gpio) 35 36 /* pa1a_eic_extint1 */ 37 #define PA1A_EIC_EXTINT1 \ 38 SAM_PINMUX(a, 1, a, periph) 39 40 /* pa1d_sercom1_pad1 */ 41 #define PA1D_SERCOM1_PAD1 \ 42 SAM_PINMUX(a, 1, d, periph) 43 44 /* pa1e_tc2_wo1 */ 45 #define PA1E_TC2_WO1 \ 46 SAM_PINMUX(a, 1, e, periph) 47 48 /* pa2_gpio */ 49 #define PA2_GPIO \ 50 SAM_PINMUX(a, 2, gpio, gpio) 51 52 /* pa2a_eic_extint2 */ 53 #define PA2A_EIC_EXTINT2 \ 54 SAM_PINMUX(a, 2, a, periph) 55 56 /* pa2b_adc0_ain0 */ 57 #define PA2B_ADC0_AIN0 \ 58 SAM_PINMUX(a, 2, b, periph) 59 60 /* pa2b_dac_vout0 */ 61 #define PA2B_DAC_VOUT0 \ 62 SAM_PINMUX(a, 2, b, periph) 63 64 /* pa3_gpio */ 65 #define PA3_GPIO \ 66 SAM_PINMUX(a, 3, gpio, gpio) 67 68 /* pa3a_eic_extint3 */ 69 #define PA3A_EIC_EXTINT3 \ 70 SAM_PINMUX(a, 3, a, periph) 71 72 /* pa3b_anaref_vrefa */ 73 #define PA3B_ANAREF_VREFA \ 74 SAM_PINMUX(a, 3, b, periph) 75 76 /* pa3b_adc0_ain1 */ 77 #define PA3B_ADC0_AIN1 \ 78 SAM_PINMUX(a, 3, b, periph) 79 80 /* pa3b_ptc_xy0 */ 81 #define PA3B_PTC_XY0 \ 82 SAM_PINMUX(a, 3, b, periph) 83 84 /* pa4_gpio */ 85 #define PA4_GPIO \ 86 SAM_PINMUX(a, 4, gpio, gpio) 87 88 /* pa4a_eic_extint4 */ 89 #define PA4A_EIC_EXTINT4 \ 90 SAM_PINMUX(a, 4, a, periph) 91 92 /* pa4b_anaref_vrefb */ 93 #define PA4B_ANAREF_VREFB \ 94 SAM_PINMUX(a, 4, b, periph) 95 96 /* pa4b_adc0_ain4 */ 97 #define PA4B_ADC0_AIN4 \ 98 SAM_PINMUX(a, 4, b, periph) 99 100 /* pa4b_ac_ain0 */ 101 #define PA4B_AC_AIN0 \ 102 SAM_PINMUX(a, 4, b, periph) 103 104 /* pa4b_ptc_xy3 */ 105 #define PA4B_PTC_XY3 \ 106 SAM_PINMUX(a, 4, b, periph) 107 108 /* pa4d_sercom0_pad0 */ 109 #define PA4D_SERCOM0_PAD0 \ 110 SAM_PINMUX(a, 4, d, periph) 111 112 /* pa4e_tc0_wo0 */ 113 #define PA4E_TC0_WO0 \ 114 SAM_PINMUX(a, 4, e, periph) 115 116 /* pa4n_ccl_in0 */ 117 #define PA4N_CCL_IN0 \ 118 SAM_PINMUX(a, 4, n, periph) 119 120 /* pa5_gpio */ 121 #define PA5_GPIO \ 122 SAM_PINMUX(a, 5, gpio, gpio) 123 124 /* pa5a_eic_extint5 */ 125 #define PA5A_EIC_EXTINT5 \ 126 SAM_PINMUX(a, 5, a, periph) 127 128 /* pa5b_adc0_ain5 */ 129 #define PA5B_ADC0_AIN5 \ 130 SAM_PINMUX(a, 5, b, periph) 131 132 /* pa5b_ac_ain1 */ 133 #define PA5B_AC_AIN1 \ 134 SAM_PINMUX(a, 5, b, periph) 135 136 /* pa5b_dac_vout1 */ 137 #define PA5B_DAC_VOUT1 \ 138 SAM_PINMUX(a, 5, b, periph) 139 140 /* pa5d_sercom0_pad1 */ 141 #define PA5D_SERCOM0_PAD1 \ 142 SAM_PINMUX(a, 5, d, periph) 143 144 /* pa5e_tc0_wo1 */ 145 #define PA5E_TC0_WO1 \ 146 SAM_PINMUX(a, 5, e, periph) 147 148 /* pa5n_ccl_in1 */ 149 #define PA5N_CCL_IN1 \ 150 SAM_PINMUX(a, 5, n, periph) 151 152 /* pa6_gpio */ 153 #define PA6_GPIO \ 154 SAM_PINMUX(a, 6, gpio, gpio) 155 156 /* pa6a_eic_extint6 */ 157 #define PA6A_EIC_EXTINT6 \ 158 SAM_PINMUX(a, 6, a, periph) 159 160 /* pa6b_anaref_vrefc */ 161 #define PA6B_ANAREF_VREFC \ 162 SAM_PINMUX(a, 6, b, periph) 163 164 /* pa6b_adc0_ain6 */ 165 #define PA6B_ADC0_AIN6 \ 166 SAM_PINMUX(a, 6, b, periph) 167 168 /* pa6b_ac_ain2 */ 169 #define PA6B_AC_AIN2 \ 170 SAM_PINMUX(a, 6, b, periph) 171 172 /* pa6b_ptc_xy4 */ 173 #define PA6B_PTC_XY4 \ 174 SAM_PINMUX(a, 6, b, periph) 175 176 /* pa6d_sercom0_pad2 */ 177 #define PA6D_SERCOM0_PAD2 \ 178 SAM_PINMUX(a, 6, d, periph) 179 180 /* pa6e_tc1_wo0 */ 181 #define PA6E_TC1_WO0 \ 182 SAM_PINMUX(a, 6, e, periph) 183 184 /* pa6i_sdhc0_cd */ 185 #define PA6I_SDHC0_CD \ 186 SAM_PINMUX(a, 6, i, periph) 187 188 /* pa6n_ccl_in2 */ 189 #define PA6N_CCL_IN2 \ 190 SAM_PINMUX(a, 6, n, periph) 191 192 /* pa7_gpio */ 193 #define PA7_GPIO \ 194 SAM_PINMUX(a, 7, gpio, gpio) 195 196 /* pa7a_eic_extint7 */ 197 #define PA7A_EIC_EXTINT7 \ 198 SAM_PINMUX(a, 7, a, periph) 199 200 /* pa7b_adc0_ain7 */ 201 #define PA7B_ADC0_AIN7 \ 202 SAM_PINMUX(a, 7, b, periph) 203 204 /* pa7b_ac_ain3 */ 205 #define PA7B_AC_AIN3 \ 206 SAM_PINMUX(a, 7, b, periph) 207 208 /* pa7b_ptc_xy5 */ 209 #define PA7B_PTC_XY5 \ 210 SAM_PINMUX(a, 7, b, periph) 211 212 /* pa7d_sercom0_pad3 */ 213 #define PA7D_SERCOM0_PAD3 \ 214 SAM_PINMUX(a, 7, d, periph) 215 216 /* pa7e_tc1_wo1 */ 217 #define PA7E_TC1_WO1 \ 218 SAM_PINMUX(a, 7, e, periph) 219 220 /* pa7i_sdhc0_wp */ 221 #define PA7I_SDHC0_WP \ 222 SAM_PINMUX(a, 7, i, periph) 223 224 /* pa7n_ccl_out0 */ 225 #define PA7N_CCL_OUT0 \ 226 SAM_PINMUX(a, 7, n, periph) 227 228 /* pa8_gpio */ 229 #define PA8_GPIO \ 230 SAM_PINMUX(a, 8, gpio, gpio) 231 232 /* pa8a_eic_nmi */ 233 #define PA8A_EIC_NMI \ 234 SAM_PINMUX(a, 8, a, periph) 235 236 /* pa8b_adc0_ain8 */ 237 #define PA8B_ADC0_AIN8 \ 238 SAM_PINMUX(a, 8, b, periph) 239 240 /* pa8b_adc1_ain2 */ 241 #define PA8B_ADC1_AIN2 \ 242 SAM_PINMUX(a, 8, b, periph) 243 244 /* pa8b_ptc_xy6 */ 245 #define PA8B_PTC_XY6 \ 246 SAM_PINMUX(a, 8, b, periph) 247 248 /* pa8c_sercom0_pad0 */ 249 #define PA8C_SERCOM0_PAD0 \ 250 SAM_PINMUX(a, 8, c, periph) 251 252 /* pa8d_sercom2_pad1 */ 253 #define PA8D_SERCOM2_PAD1 \ 254 SAM_PINMUX(a, 8, d, periph) 255 256 /* pa8e_tc0_wo0 */ 257 #define PA8E_TC0_WO0 \ 258 SAM_PINMUX(a, 8, e, periph) 259 260 /* pa8f_tcc0_wo0 */ 261 #define PA8F_TCC0_WO0 \ 262 SAM_PINMUX(a, 8, f, periph) 263 264 /* pa8g_tcc1_wo4 */ 265 #define PA8G_TCC1_WO4 \ 266 SAM_PINMUX(a, 8, g, periph) 267 268 /* pa8h_qspi_data0 */ 269 #define PA8H_QSPI_DATA0 \ 270 SAM_PINMUX(a, 8, h, periph) 271 272 /* pa8i_sdhc0_cmd */ 273 #define PA8I_SDHC0_CMD \ 274 SAM_PINMUX(a, 8, i, periph) 275 276 /* pa8j_iis_mck0 */ 277 #define PA8J_IIS_MCK0 \ 278 SAM_PINMUX(a, 8, j, periph) 279 280 /* pa8n_ccl_in3 */ 281 #define PA8N_CCL_IN3 \ 282 SAM_PINMUX(a, 8, n, periph) 283 284 /* pa9_gpio */ 285 #define PA9_GPIO \ 286 SAM_PINMUX(a, 9, gpio, gpio) 287 288 /* pa9a_eic_extint9 */ 289 #define PA9A_EIC_EXTINT9 \ 290 SAM_PINMUX(a, 9, a, periph) 291 292 /* pa9b_adc0_ain9 */ 293 #define PA9B_ADC0_AIN9 \ 294 SAM_PINMUX(a, 9, b, periph) 295 296 /* pa9b_adc1_ain3 */ 297 #define PA9B_ADC1_AIN3 \ 298 SAM_PINMUX(a, 9, b, periph) 299 300 /* pa9b_ptc_xy7 */ 301 #define PA9B_PTC_XY7 \ 302 SAM_PINMUX(a, 9, b, periph) 303 304 /* pa9c_sercom0_pad1 */ 305 #define PA9C_SERCOM0_PAD1 \ 306 SAM_PINMUX(a, 9, c, periph) 307 308 /* pa9d_sercom2_pad0 */ 309 #define PA9D_SERCOM2_PAD0 \ 310 SAM_PINMUX(a, 9, d, periph) 311 312 /* pa9e_tc0_wo1 */ 313 #define PA9E_TC0_WO1 \ 314 SAM_PINMUX(a, 9, e, periph) 315 316 /* pa9f_tcc0_wo1 */ 317 #define PA9F_TCC0_WO1 \ 318 SAM_PINMUX(a, 9, f, periph) 319 320 /* pa9g_tcc1_wo5 */ 321 #define PA9G_TCC1_WO5 \ 322 SAM_PINMUX(a, 9, g, periph) 323 324 /* pa9h_qspi_data1 */ 325 #define PA9H_QSPI_DATA1 \ 326 SAM_PINMUX(a, 9, h, periph) 327 328 /* pa9i_sdhc0_dat0 */ 329 #define PA9I_SDHC0_DAT0 \ 330 SAM_PINMUX(a, 9, i, periph) 331 332 /* pa9j_iis_fs0 */ 333 #define PA9J_IIS_FS0 \ 334 SAM_PINMUX(a, 9, j, periph) 335 336 /* pa9n_ccl_in4 */ 337 #define PA9N_CCL_IN4 \ 338 SAM_PINMUX(a, 9, n, periph) 339 340 /* pa10_gpio */ 341 #define PA10_GPIO \ 342 SAM_PINMUX(a, 10, gpio, gpio) 343 344 /* pa10a_eic_extint10 */ 345 #define PA10A_EIC_EXTINT10 \ 346 SAM_PINMUX(a, 10, a, periph) 347 348 /* pa10b_adc0_ain10 */ 349 #define PA10B_ADC0_AIN10 \ 350 SAM_PINMUX(a, 10, b, periph) 351 352 /* pa10b_ptc_xy8 */ 353 #define PA10B_PTC_XY8 \ 354 SAM_PINMUX(a, 10, b, periph) 355 356 /* pa10c_sercom0_pad2 */ 357 #define PA10C_SERCOM0_PAD2 \ 358 SAM_PINMUX(a, 10, c, periph) 359 360 /* pa10d_sercom2_pad2 */ 361 #define PA10D_SERCOM2_PAD2 \ 362 SAM_PINMUX(a, 10, d, periph) 363 364 /* pa10e_tc1_wo0 */ 365 #define PA10E_TC1_WO0 \ 366 SAM_PINMUX(a, 10, e, periph) 367 368 /* pa10f_tcc0_wo2 */ 369 #define PA10F_TCC0_WO2 \ 370 SAM_PINMUX(a, 10, f, periph) 371 372 /* pa10g_tcc1_wo6 */ 373 #define PA10G_TCC1_WO6 \ 374 SAM_PINMUX(a, 10, g, periph) 375 376 /* pa10h_qspi_data2 */ 377 #define PA10H_QSPI_DATA2 \ 378 SAM_PINMUX(a, 10, h, periph) 379 380 /* pa10i_sdhc0_dat1 */ 381 #define PA10I_SDHC0_DAT1 \ 382 SAM_PINMUX(a, 10, i, periph) 383 384 /* pa10j_iis_sck0 */ 385 #define PA10J_IIS_SCK0 \ 386 SAM_PINMUX(a, 10, j, periph) 387 388 /* pa10m_gclk_io4 */ 389 #define PA10M_GCLK_IO4 \ 390 SAM_PINMUX(a, 10, m, periph) 391 392 /* pa10n_ccl_in5 */ 393 #define PA10N_CCL_IN5 \ 394 SAM_PINMUX(a, 10, n, periph) 395 396 /* pa11_gpio */ 397 #define PA11_GPIO \ 398 SAM_PINMUX(a, 11, gpio, gpio) 399 400 /* pa11a_eic_extint11 */ 401 #define PA11A_EIC_EXTINT11 \ 402 SAM_PINMUX(a, 11, a, periph) 403 404 /* pa11b_adc0_ain11 */ 405 #define PA11B_ADC0_AIN11 \ 406 SAM_PINMUX(a, 11, b, periph) 407 408 /* pa11b_ptc_xy9 */ 409 #define PA11B_PTC_XY9 \ 410 SAM_PINMUX(a, 11, b, periph) 411 412 /* pa11c_sercom0_pad3 */ 413 #define PA11C_SERCOM0_PAD3 \ 414 SAM_PINMUX(a, 11, c, periph) 415 416 /* pa11d_sercom2_pad3 */ 417 #define PA11D_SERCOM2_PAD3 \ 418 SAM_PINMUX(a, 11, d, periph) 419 420 /* pa11e_tc1_wo1 */ 421 #define PA11E_TC1_WO1 \ 422 SAM_PINMUX(a, 11, e, periph) 423 424 /* pa11f_tcc0_wo3 */ 425 #define PA11F_TCC0_WO3 \ 426 SAM_PINMUX(a, 11, f, periph) 427 428 /* pa11g_tcc1_wo7 */ 429 #define PA11G_TCC1_WO7 \ 430 SAM_PINMUX(a, 11, g, periph) 431 432 /* pa11h_qspi_data3 */ 433 #define PA11H_QSPI_DATA3 \ 434 SAM_PINMUX(a, 11, h, periph) 435 436 /* pa11i_sdhc0_dat2 */ 437 #define PA11I_SDHC0_DAT2 \ 438 SAM_PINMUX(a, 11, i, periph) 439 440 /* pa11j_iis_sdo */ 441 #define PA11J_IIS_SDO \ 442 SAM_PINMUX(a, 11, j, periph) 443 444 /* pa11m_gclk_io5 */ 445 #define PA11M_GCLK_IO5 \ 446 SAM_PINMUX(a, 11, m, periph) 447 448 /* pa11n_ccl_out1 */ 449 #define PA11N_CCL_OUT1 \ 450 SAM_PINMUX(a, 11, n, periph) 451 452 /* pa12_gpio */ 453 #define PA12_GPIO \ 454 SAM_PINMUX(a, 12, gpio, gpio) 455 456 /* pa12a_eic_extint12 */ 457 #define PA12A_EIC_EXTINT12 \ 458 SAM_PINMUX(a, 12, a, periph) 459 460 /* pa12c_sercom2_pad0 */ 461 #define PA12C_SERCOM2_PAD0 \ 462 SAM_PINMUX(a, 12, c, periph) 463 464 /* pa12d_sercom4_pad1 */ 465 #define PA12D_SERCOM4_PAD1 \ 466 SAM_PINMUX(a, 12, d, periph) 467 468 /* pa12e_tc2_wo0 */ 469 #define PA12E_TC2_WO0 \ 470 SAM_PINMUX(a, 12, e, periph) 471 472 /* pa12f_tcc0_wo6 */ 473 #define PA12F_TCC0_WO6 \ 474 SAM_PINMUX(a, 12, f, periph) 475 476 /* pa12g_tcc1_wo2 */ 477 #define PA12G_TCC1_WO2 \ 478 SAM_PINMUX(a, 12, g, periph) 479 480 /* pa12i_sdhc0_cd */ 481 #define PA12I_SDHC0_CD \ 482 SAM_PINMUX(a, 12, i, periph) 483 484 /* pa12k_pcc_den1 */ 485 #define PA12K_PCC_DEN1 \ 486 SAM_PINMUX(a, 12, k, periph) 487 488 /* pa12m_ac_cmp0 */ 489 #define PA12M_AC_CMP0 \ 490 SAM_PINMUX(a, 12, m, periph) 491 492 /* pa13_gpio */ 493 #define PA13_GPIO \ 494 SAM_PINMUX(a, 13, gpio, gpio) 495 496 /* pa13a_eic_extint13 */ 497 #define PA13A_EIC_EXTINT13 \ 498 SAM_PINMUX(a, 13, a, periph) 499 500 /* pa13c_sercom2_pad1 */ 501 #define PA13C_SERCOM2_PAD1 \ 502 SAM_PINMUX(a, 13, c, periph) 503 504 /* pa13d_sercom4_pad0 */ 505 #define PA13D_SERCOM4_PAD0 \ 506 SAM_PINMUX(a, 13, d, periph) 507 508 /* pa13e_tc2_wo1 */ 509 #define PA13E_TC2_WO1 \ 510 SAM_PINMUX(a, 13, e, periph) 511 512 /* pa13f_tcc0_wo7 */ 513 #define PA13F_TCC0_WO7 \ 514 SAM_PINMUX(a, 13, f, periph) 515 516 /* pa13g_tcc1_wo3 */ 517 #define PA13G_TCC1_WO3 \ 518 SAM_PINMUX(a, 13, g, periph) 519 520 /* pa13i_sdhc0_wp */ 521 #define PA13I_SDHC0_WP \ 522 SAM_PINMUX(a, 13, i, periph) 523 524 /* pa13k_pcc_den2 */ 525 #define PA13K_PCC_DEN2 \ 526 SAM_PINMUX(a, 13, k, periph) 527 528 /* pa13m_ac_cmp1 */ 529 #define PA13M_AC_CMP1 \ 530 SAM_PINMUX(a, 13, m, periph) 531 532 /* pa14_gpio */ 533 #define PA14_GPIO \ 534 SAM_PINMUX(a, 14, gpio, gpio) 535 536 /* pa14a_eic_extint14 */ 537 #define PA14A_EIC_EXTINT14 \ 538 SAM_PINMUX(a, 14, a, periph) 539 540 /* pa14c_sercom2_pad2 */ 541 #define PA14C_SERCOM2_PAD2 \ 542 SAM_PINMUX(a, 14, c, periph) 543 544 /* pa14d_sercom4_pad2 */ 545 #define PA14D_SERCOM4_PAD2 \ 546 SAM_PINMUX(a, 14, d, periph) 547 548 /* pa14e_tc3_wo0 */ 549 #define PA14E_TC3_WO0 \ 550 SAM_PINMUX(a, 14, e, periph) 551 552 /* pa14f_tcc2_wo0 */ 553 #define PA14F_TCC2_WO0 \ 554 SAM_PINMUX(a, 14, f, periph) 555 556 /* pa14g_tcc1_wo2 */ 557 #define PA14G_TCC1_WO2 \ 558 SAM_PINMUX(a, 14, g, periph) 559 560 /* pa14k_pcc_clk */ 561 #define PA14K_PCC_CLK \ 562 SAM_PINMUX(a, 14, k, periph) 563 564 /* pa14m_glkc_io0 */ 565 #define PA14M_GLKC_IO0 \ 566 SAM_PINMUX(a, 14, m, periph) 567 568 /* pa15_gpio */ 569 #define PA15_GPIO \ 570 SAM_PINMUX(a, 15, gpio, gpio) 571 572 /* pa15a_eic_extint15 */ 573 #define PA15A_EIC_EXTINT15 \ 574 SAM_PINMUX(a, 15, a, periph) 575 576 /* pa15c_sercom2_pad3 */ 577 #define PA15C_SERCOM2_PAD3 \ 578 SAM_PINMUX(a, 15, c, periph) 579 580 /* pa15d_sercom4_pad3 */ 581 #define PA15D_SERCOM4_PAD3 \ 582 SAM_PINMUX(a, 15, d, periph) 583 584 /* pa15e_tc3_wo1 */ 585 #define PA15E_TC3_WO1 \ 586 SAM_PINMUX(a, 15, e, periph) 587 588 /* pa15f_tcc2_wo1 */ 589 #define PA15F_TCC2_WO1 \ 590 SAM_PINMUX(a, 15, f, periph) 591 592 /* pa15g_tcc1_wo3 */ 593 #define PA15G_TCC1_WO3 \ 594 SAM_PINMUX(a, 15, g, periph) 595 596 /* pa15m_glkc_io1 */ 597 #define PA15M_GLKC_IO1 \ 598 SAM_PINMUX(a, 15, m, periph) 599 600 /* pa16_gpio */ 601 #define PA16_GPIO \ 602 SAM_PINMUX(a, 16, gpio, gpio) 603 604 /* pa16a_eic_extint0 */ 605 #define PA16A_EIC_EXTINT0 \ 606 SAM_PINMUX(a, 16, a, periph) 607 608 /* pa16b_ptc_xy10 */ 609 #define PA16B_PTC_XY10 \ 610 SAM_PINMUX(a, 16, b, periph) 611 612 /* pa16c_sercom1_pad0 */ 613 #define PA16C_SERCOM1_PAD0 \ 614 SAM_PINMUX(a, 16, c, periph) 615 616 /* pa16d_sercom3_pad1 */ 617 #define PA16D_SERCOM3_PAD1 \ 618 SAM_PINMUX(a, 16, d, periph) 619 620 /* pa16e_tc2_wo0 */ 621 #define PA16E_TC2_WO0 \ 622 SAM_PINMUX(a, 16, e, periph) 623 624 /* pa16f_tcc1_wo0 */ 625 #define PA16F_TCC1_WO0 \ 626 SAM_PINMUX(a, 16, f, periph) 627 628 /* pa16g_tcc0_wo4 */ 629 #define PA16G_TCC0_WO4 \ 630 SAM_PINMUX(a, 16, g, periph) 631 632 /* pa16k_pcc_data0 */ 633 #define PA16K_PCC_DATA0 \ 634 SAM_PINMUX(a, 16, k, periph) 635 636 /* pa16m_gclk_io2 */ 637 #define PA16M_GCLK_IO2 \ 638 SAM_PINMUX(a, 16, m, periph) 639 640 /* pa16n_ccl_in0 */ 641 #define PA16N_CCL_IN0 \ 642 SAM_PINMUX(a, 16, n, periph) 643 644 /* pa17_gpio */ 645 #define PA17_GPIO \ 646 SAM_PINMUX(a, 17, gpio, gpio) 647 648 /* pa17a_eic_extint1 */ 649 #define PA17A_EIC_EXTINT1 \ 650 SAM_PINMUX(a, 17, a, periph) 651 652 /* pa17b_ptc_xy11 */ 653 #define PA17B_PTC_XY11 \ 654 SAM_PINMUX(a, 17, b, periph) 655 656 /* pa17c_sercom1_pad1 */ 657 #define PA17C_SERCOM1_PAD1 \ 658 SAM_PINMUX(a, 17, c, periph) 659 660 /* pa17d_sercom3_pad0 */ 661 #define PA17D_SERCOM3_PAD0 \ 662 SAM_PINMUX(a, 17, d, periph) 663 664 /* pa17e_tc2_wo1 */ 665 #define PA17E_TC2_WO1 \ 666 SAM_PINMUX(a, 17, e, periph) 667 668 /* pa17f_tcc1_wo1 */ 669 #define PA17F_TCC1_WO1 \ 670 SAM_PINMUX(a, 17, f, periph) 671 672 /* pa17g_tcc0_wo5 */ 673 #define PA17G_TCC0_WO5 \ 674 SAM_PINMUX(a, 17, g, periph) 675 676 /* pa17k_pcc_data1 */ 677 #define PA17K_PCC_DATA1 \ 678 SAM_PINMUX(a, 17, k, periph) 679 680 /* pa17m_gclk_io3 */ 681 #define PA17M_GCLK_IO3 \ 682 SAM_PINMUX(a, 17, m, periph) 683 684 /* pa17n_ccl_in1 */ 685 #define PA17N_CCL_IN1 \ 686 SAM_PINMUX(a, 17, n, periph) 687 688 /* pa18_gpio */ 689 #define PA18_GPIO \ 690 SAM_PINMUX(a, 18, gpio, gpio) 691 692 /* pa18a_eic_extint2 */ 693 #define PA18A_EIC_EXTINT2 \ 694 SAM_PINMUX(a, 18, a, periph) 695 696 /* pa18b_ptc_xy12 */ 697 #define PA18B_PTC_XY12 \ 698 SAM_PINMUX(a, 18, b, periph) 699 700 /* pa18c_sercom1_pad2 */ 701 #define PA18C_SERCOM1_PAD2 \ 702 SAM_PINMUX(a, 18, c, periph) 703 704 /* pa18d_sercom3_pad2 */ 705 #define PA18D_SERCOM3_PAD2 \ 706 SAM_PINMUX(a, 18, d, periph) 707 708 /* pa18e_tc3_wo0 */ 709 #define PA18E_TC3_WO0 \ 710 SAM_PINMUX(a, 18, e, periph) 711 712 /* pa18f_tcc1_wo2 */ 713 #define PA18F_TCC1_WO2 \ 714 SAM_PINMUX(a, 18, f, periph) 715 716 /* pa18g_tcc0_wo6 */ 717 #define PA18G_TCC0_WO6 \ 718 SAM_PINMUX(a, 18, g, periph) 719 720 /* pa18k_pcc_data2 */ 721 #define PA18K_PCC_DATA2 \ 722 SAM_PINMUX(a, 18, k, periph) 723 724 /* pa18m_ac_cmp0 */ 725 #define PA18M_AC_CMP0 \ 726 SAM_PINMUX(a, 18, m, periph) 727 728 /* pa18n_ccl_in2 */ 729 #define PA18N_CCL_IN2 \ 730 SAM_PINMUX(a, 18, n, periph) 731 732 /* pa19_gpio */ 733 #define PA19_GPIO \ 734 SAM_PINMUX(a, 19, gpio, gpio) 735 736 /* pa19a_eic_extint3 */ 737 #define PA19A_EIC_EXTINT3 \ 738 SAM_PINMUX(a, 19, a, periph) 739 740 /* pa19b_ptc_xy13 */ 741 #define PA19B_PTC_XY13 \ 742 SAM_PINMUX(a, 19, b, periph) 743 744 /* pa19c_sercom1_pad3 */ 745 #define PA19C_SERCOM1_PAD3 \ 746 SAM_PINMUX(a, 19, c, periph) 747 748 /* pa19d_sercom3_pad3 */ 749 #define PA19D_SERCOM3_PAD3 \ 750 SAM_PINMUX(a, 19, d, periph) 751 752 /* pa19e_tc3_wo1 */ 753 #define PA19E_TC3_WO1 \ 754 SAM_PINMUX(a, 19, e, periph) 755 756 /* pa19f_tcc1_wo3 */ 757 #define PA19F_TCC1_WO3 \ 758 SAM_PINMUX(a, 19, f, periph) 759 760 /* pa19g_tcc0_wo7 */ 761 #define PA19G_TCC0_WO7 \ 762 SAM_PINMUX(a, 19, g, periph) 763 764 /* pa19k_pcc_data3 */ 765 #define PA19K_PCC_DATA3 \ 766 SAM_PINMUX(a, 19, k, periph) 767 768 /* pa19m_ac_cmp1 */ 769 #define PA19M_AC_CMP1 \ 770 SAM_PINMUX(a, 19, m, periph) 771 772 /* pa19n_ccl_out0 */ 773 #define PA19N_CCL_OUT0 \ 774 SAM_PINMUX(a, 19, n, periph) 775 776 /* pa20_gpio */ 777 #define PA20_GPIO \ 778 SAM_PINMUX(a, 20, gpio, gpio) 779 780 /* pa20a_eic_extint4 */ 781 #define PA20A_EIC_EXTINT4 \ 782 SAM_PINMUX(a, 20, a, periph) 783 784 /* pa20b_ptc_xy14 */ 785 #define PA20B_PTC_XY14 \ 786 SAM_PINMUX(a, 20, b, periph) 787 788 /* pa20c_sercom5_pad2 */ 789 #define PA20C_SERCOM5_PAD2 \ 790 SAM_PINMUX(a, 20, c, periph) 791 792 /* pa20d_sercom3_pad2 */ 793 #define PA20D_SERCOM3_PAD2 \ 794 SAM_PINMUX(a, 20, d, periph) 795 796 /* pa20e_tc7_wo0 */ 797 #define PA20E_TC7_WO0 \ 798 SAM_PINMUX(a, 20, e, periph) 799 800 /* pa20f_tcc1_wo4 */ 801 #define PA20F_TCC1_WO4 \ 802 SAM_PINMUX(a, 20, f, periph) 803 804 /* pa20g_tcc0_wo0 */ 805 #define PA20G_TCC0_WO0 \ 806 SAM_PINMUX(a, 20, g, periph) 807 808 /* pa20i_sdhc1_cmd */ 809 #define PA20I_SDHC1_CMD \ 810 SAM_PINMUX(a, 20, i, periph) 811 812 /* pa20j_iis_fs0 */ 813 #define PA20J_IIS_FS0 \ 814 SAM_PINMUX(a, 20, j, periph) 815 816 /* pa20k_pcc_data4 */ 817 #define PA20K_PCC_DATA4 \ 818 SAM_PINMUX(a, 20, k, periph) 819 820 /* pa21_gpio */ 821 #define PA21_GPIO \ 822 SAM_PINMUX(a, 21, gpio, gpio) 823 824 /* pa21a_eic_extint5 */ 825 #define PA21A_EIC_EXTINT5 \ 826 SAM_PINMUX(a, 21, a, periph) 827 828 /* pa21b_ptc_xy15 */ 829 #define PA21B_PTC_XY15 \ 830 SAM_PINMUX(a, 21, b, periph) 831 832 /* pa21c_sercom5_pad3 */ 833 #define PA21C_SERCOM5_PAD3 \ 834 SAM_PINMUX(a, 21, c, periph) 835 836 /* pa21d_sercom3_pad3 */ 837 #define PA21D_SERCOM3_PAD3 \ 838 SAM_PINMUX(a, 21, d, periph) 839 840 /* pa21e_tc7_wo1 */ 841 #define PA21E_TC7_WO1 \ 842 SAM_PINMUX(a, 21, e, periph) 843 844 /* pa21f_tcc1_wo5 */ 845 #define PA21F_TCC1_WO5 \ 846 SAM_PINMUX(a, 21, f, periph) 847 848 /* pa21g_tcc0_wo1 */ 849 #define PA21G_TCC0_WO1 \ 850 SAM_PINMUX(a, 21, g, periph) 851 852 /* pa21i_sdhc1_ck */ 853 #define PA21I_SDHC1_CK \ 854 SAM_PINMUX(a, 21, i, periph) 855 856 /* pa21j_iis_sdo */ 857 #define PA21J_IIS_SDO \ 858 SAM_PINMUX(a, 21, j, periph) 859 860 /* pa21k_pcc_data5 */ 861 #define PA21K_PCC_DATA5 \ 862 SAM_PINMUX(a, 21, k, periph) 863 864 /* pa22_gpio */ 865 #define PA22_GPIO \ 866 SAM_PINMUX(a, 22, gpio, gpio) 867 868 /* pa22a_eic_extint6 */ 869 #define PA22A_EIC_EXTINT6 \ 870 SAM_PINMUX(a, 22, a, periph) 871 872 /* pa22b_ptc_xy16 */ 873 #define PA22B_PTC_XY16 \ 874 SAM_PINMUX(a, 22, b, periph) 875 876 /* pa22c_sercom3_pad0 */ 877 #define PA22C_SERCOM3_PAD0 \ 878 SAM_PINMUX(a, 22, c, periph) 879 880 /* pa22d_sercom5_pad1 */ 881 #define PA22D_SERCOM5_PAD1 \ 882 SAM_PINMUX(a, 22, d, periph) 883 884 /* pa22e_tc4_wo0 */ 885 #define PA22E_TC4_WO0 \ 886 SAM_PINMUX(a, 22, e, periph) 887 888 /* pa22f_tcc1_wo6 */ 889 #define PA22F_TCC1_WO6 \ 890 SAM_PINMUX(a, 22, f, periph) 891 892 /* pa22g_tcc0_wo2 */ 893 #define PA22G_TCC0_WO2 \ 894 SAM_PINMUX(a, 22, g, periph) 895 896 /* pa22j_iis_sdi */ 897 #define PA22J_IIS_SDI \ 898 SAM_PINMUX(a, 22, j, periph) 899 900 /* pa22k_pcc_data6 */ 901 #define PA22K_PCC_DATA6 \ 902 SAM_PINMUX(a, 22, k, periph) 903 904 /* pa22n_ccl_in6 */ 905 #define PA22N_CCL_IN6 \ 906 SAM_PINMUX(a, 22, n, periph) 907 908 /* pa23_gpio */ 909 #define PA23_GPIO \ 910 SAM_PINMUX(a, 23, gpio, gpio) 911 912 /* pa23a_eic_extint7 */ 913 #define PA23A_EIC_EXTINT7 \ 914 SAM_PINMUX(a, 23, a, periph) 915 916 /* pa23b_ptc_xy17 */ 917 #define PA23B_PTC_XY17 \ 918 SAM_PINMUX(a, 23, b, periph) 919 920 /* pa23c_sercom3_pad1 */ 921 #define PA23C_SERCOM3_PAD1 \ 922 SAM_PINMUX(a, 23, c, periph) 923 924 /* pa23d_sercom5_pad0 */ 925 #define PA23D_SERCOM5_PAD0 \ 926 SAM_PINMUX(a, 23, d, periph) 927 928 /* pa23e_tc4_wo1 */ 929 #define PA23E_TC4_WO1 \ 930 SAM_PINMUX(a, 23, e, periph) 931 932 /* pa23f_tcc1_wo7 */ 933 #define PA23F_TCC1_WO7 \ 934 SAM_PINMUX(a, 23, f, periph) 935 936 /* pa23g_tcc0_wo3 */ 937 #define PA23G_TCC0_WO3 \ 938 SAM_PINMUX(a, 23, g, periph) 939 940 /* pa23h_usb_sof */ 941 #define PA23H_USB_SOF \ 942 SAM_PINMUX(a, 23, h, periph) 943 944 /* pa23j_iis_fs1 */ 945 #define PA23J_IIS_FS1 \ 946 SAM_PINMUX(a, 23, j, periph) 947 948 /* pa23k_pcc_data7 */ 949 #define PA23K_PCC_DATA7 \ 950 SAM_PINMUX(a, 23, k, periph) 951 952 /* pa23n_ccl_in7 */ 953 #define PA23N_CCL_IN7 \ 954 SAM_PINMUX(a, 23, n, periph) 955 956 /* pa24_gpio */ 957 #define PA24_GPIO \ 958 SAM_PINMUX(a, 24, gpio, gpio) 959 960 /* pa24a_eic_extint8 */ 961 #define PA24A_EIC_EXTINT8 \ 962 SAM_PINMUX(a, 24, a, periph) 963 964 /* pa24c_sercom3_pad2 */ 965 #define PA24C_SERCOM3_PAD2 \ 966 SAM_PINMUX(a, 24, c, periph) 967 968 /* pa24d_sercom5_pad2 */ 969 #define PA24D_SERCOM5_PAD2 \ 970 SAM_PINMUX(a, 24, d, periph) 971 972 /* pa24e_tc5_wo0 */ 973 #define PA24E_TC5_WO0 \ 974 SAM_PINMUX(a, 24, e, periph) 975 976 /* pa24f_tcc2_wo2 */ 977 #define PA24F_TCC2_WO2 \ 978 SAM_PINMUX(a, 24, f, periph) 979 980 /* pa24g_pdec_qdi0 */ 981 #define PA24G_PDEC_QDI0 \ 982 SAM_PINMUX(a, 24, g, periph) 983 984 /* pa24h_usb_dm */ 985 #define PA24H_USB_DM \ 986 SAM_PINMUX(a, 24, h, periph) 987 988 /* pa24n_ccl_in8 */ 989 #define PA24N_CCL_IN8 \ 990 SAM_PINMUX(a, 24, n, periph) 991 992 /* pa25_gpio */ 993 #define PA25_GPIO \ 994 SAM_PINMUX(a, 25, gpio, gpio) 995 996 /* pa25a_eic_extint9 */ 997 #define PA25A_EIC_EXTINT9 \ 998 SAM_PINMUX(a, 25, a, periph) 999 1000 /* pa25c_sercom3_pad3 */ 1001 #define PA25C_SERCOM3_PAD3 \ 1002 SAM_PINMUX(a, 25, c, periph) 1003 1004 /* pa25d_sercom5_pad3 */ 1005 #define PA25D_SERCOM5_PAD3 \ 1006 SAM_PINMUX(a, 25, d, periph) 1007 1008 /* pa25e_tc5_wo1 */ 1009 #define PA25E_TC5_WO1 \ 1010 SAM_PINMUX(a, 25, e, periph) 1011 1012 /* pa25g_pdec_qdi1 */ 1013 #define PA25G_PDEC_QDI1 \ 1014 SAM_PINMUX(a, 25, g, periph) 1015 1016 /* pa25h_usb_dp */ 1017 #define PA25H_USB_DP \ 1018 SAM_PINMUX(a, 25, h, periph) 1019 1020 /* pa25n_ccl_out2 */ 1021 #define PA25N_CCL_OUT2 \ 1022 SAM_PINMUX(a, 25, n, periph) 1023 1024 /* pa27_gpio */ 1025 #define PA27_GPIO \ 1026 SAM_PINMUX(a, 27, gpio, gpio) 1027 1028 /* pa27a_eic_extint11 */ 1029 #define PA27A_EIC_EXTINT11 \ 1030 SAM_PINMUX(a, 27, a, periph) 1031 1032 /* pa27b_ptc_xy18 */ 1033 #define PA27B_PTC_XY18 \ 1034 SAM_PINMUX(a, 27, b, periph) 1035 1036 /* pa27m_gclk_io1 */ 1037 #define PA27M_GCLK_IO1 \ 1038 SAM_PINMUX(a, 27, m, periph) 1039 1040 /* pa30_gpio */ 1041 #define PA30_GPIO \ 1042 SAM_PINMUX(a, 30, gpio, gpio) 1043 1044 /* pa30a_eic_extint14 */ 1045 #define PA30A_EIC_EXTINT14 \ 1046 SAM_PINMUX(a, 30, a, periph) 1047 1048 /* pa30b_ptc_xy19 */ 1049 #define PA30B_PTC_XY19 \ 1050 SAM_PINMUX(a, 30, b, periph) 1051 1052 /* pa30d_sercom1_pad2 */ 1053 #define PA30D_SERCOM1_PAD2 \ 1054 SAM_PINMUX(a, 30, d, periph) 1055 1056 /* pa30e_tc6_wo0 */ 1057 #define PA30E_TC6_WO0 \ 1058 SAM_PINMUX(a, 30, e, periph) 1059 1060 /* pa30f_tcc2_wo0 */ 1061 #define PA30F_TCC2_WO0 \ 1062 SAM_PINMUX(a, 30, f, periph) 1063 1064 /* pa30h_swd_clk */ 1065 #define PA30H_SWD_CLK \ 1066 SAM_PINMUX(a, 30, h, periph) 1067 1068 /* pa30m_gclk_io0 */ 1069 #define PA30M_GCLK_IO0 \ 1070 SAM_PINMUX(a, 30, m, periph) 1071 1072 /* pa30n_ccl_in3 */ 1073 #define PA30N_CCL_IN3 \ 1074 SAM_PINMUX(a, 30, n, periph) 1075 1076 /* pa31_gpio */ 1077 #define PA31_GPIO \ 1078 SAM_PINMUX(a, 31, gpio, gpio) 1079 1080 /* pa31a_eic_extint15 */ 1081 #define PA31A_EIC_EXTINT15 \ 1082 SAM_PINMUX(a, 31, a, periph) 1083 1084 /* pa31d_sercom1_pad3 */ 1085 #define PA31D_SERCOM1_PAD3 \ 1086 SAM_PINMUX(a, 31, d, periph) 1087 1088 /* pa31e_tc6_wo1 */ 1089 #define PA31E_TC6_WO1 \ 1090 SAM_PINMUX(a, 31, e, periph) 1091 1092 /* pa31f_tcc2_wo1 */ 1093 #define PA31F_TCC2_WO1 \ 1094 SAM_PINMUX(a, 31, f, periph) 1095 1096 /* pa31h_swd_io */ 1097 #define PA31H_SWD_IO \ 1098 SAM_PINMUX(a, 31, h, periph) 1099 1100 /* pa31n_ccl_out1 */ 1101 #define PA31N_CCL_OUT1 \ 1102 SAM_PINMUX(a, 31, n, periph) 1103 1104 /* pb0_gpio */ 1105 #define PB0_GPIO \ 1106 SAM_PINMUX(b, 0, gpio, gpio) 1107 1108 /* pb0a_eic_extint0 */ 1109 #define PB0A_EIC_EXTINT0 \ 1110 SAM_PINMUX(b, 0, a, periph) 1111 1112 /* pb0b_adc0_ain12 */ 1113 #define PB0B_ADC0_AIN12 \ 1114 SAM_PINMUX(b, 0, b, periph) 1115 1116 /* pb0b_ptc_xy30 */ 1117 #define PB0B_PTC_XY30 \ 1118 SAM_PINMUX(b, 0, b, periph) 1119 1120 /* pb0d_sercom5_pad2 */ 1121 #define PB0D_SERCOM5_PAD2 \ 1122 SAM_PINMUX(b, 0, d, periph) 1123 1124 /* pb0e_tc7_wo0 */ 1125 #define PB0E_TC7_WO0 \ 1126 SAM_PINMUX(b, 0, e, periph) 1127 1128 /* pb0n_ccl_in1 */ 1129 #define PB0N_CCL_IN1 \ 1130 SAM_PINMUX(b, 0, n, periph) 1131 1132 /* pb1_gpio */ 1133 #define PB1_GPIO \ 1134 SAM_PINMUX(b, 1, gpio, gpio) 1135 1136 /* pb1a_eic_extint1 */ 1137 #define PB1A_EIC_EXTINT1 \ 1138 SAM_PINMUX(b, 1, a, periph) 1139 1140 /* pb1b_adc0_ain13 */ 1141 #define PB1B_ADC0_AIN13 \ 1142 SAM_PINMUX(b, 1, b, periph) 1143 1144 /* pb1b_ptc_xy31 */ 1145 #define PB1B_PTC_XY31 \ 1146 SAM_PINMUX(b, 1, b, periph) 1147 1148 /* pb1d_sercom5_pad3 */ 1149 #define PB1D_SERCOM5_PAD3 \ 1150 SAM_PINMUX(b, 1, d, periph) 1151 1152 /* pb1e_tc7_wo1 */ 1153 #define PB1E_TC7_WO1 \ 1154 SAM_PINMUX(b, 1, e, periph) 1155 1156 /* pb1n_ccl_in2 */ 1157 #define PB1N_CCL_IN2 \ 1158 SAM_PINMUX(b, 1, n, periph) 1159 1160 /* pb2_gpio */ 1161 #define PB2_GPIO \ 1162 SAM_PINMUX(b, 2, gpio, gpio) 1163 1164 /* pb2a_eic_extint2 */ 1165 #define PB2A_EIC_EXTINT2 \ 1166 SAM_PINMUX(b, 2, a, periph) 1167 1168 /* pb2b_adc0_ain14 */ 1169 #define PB2B_ADC0_AIN14 \ 1170 SAM_PINMUX(b, 2, b, periph) 1171 1172 /* pb2b_ptc_xy20 */ 1173 #define PB2B_PTC_XY20 \ 1174 SAM_PINMUX(b, 2, b, periph) 1175 1176 /* pb2d_sercom5_pad0 */ 1177 #define PB2D_SERCOM5_PAD0 \ 1178 SAM_PINMUX(b, 2, d, periph) 1179 1180 /* pb2e_tc6_wo0 */ 1181 #define PB2E_TC6_WO0 \ 1182 SAM_PINMUX(b, 2, e, periph) 1183 1184 /* pb2f_tcc2_wo2 */ 1185 #define PB2F_TCC2_WO2 \ 1186 SAM_PINMUX(b, 2, f, periph) 1187 1188 /* pb2n_ccl_out0 */ 1189 #define PB2N_CCL_OUT0 \ 1190 SAM_PINMUX(b, 2, n, periph) 1191 1192 /* pb3_gpio */ 1193 #define PB3_GPIO \ 1194 SAM_PINMUX(b, 3, gpio, gpio) 1195 1196 /* pb3a_eic_extint3 */ 1197 #define PB3A_EIC_EXTINT3 \ 1198 SAM_PINMUX(b, 3, a, periph) 1199 1200 /* pb3b_adc0_ain15 */ 1201 #define PB3B_ADC0_AIN15 \ 1202 SAM_PINMUX(b, 3, b, periph) 1203 1204 /* pb3b_ptc_xy21 */ 1205 #define PB3B_PTC_XY21 \ 1206 SAM_PINMUX(b, 3, b, periph) 1207 1208 /* pb3d_sercom5_pad1 */ 1209 #define PB3D_SERCOM5_PAD1 \ 1210 SAM_PINMUX(b, 3, d, periph) 1211 1212 /* pb3e_tc6_wo1 */ 1213 #define PB3E_TC6_WO1 \ 1214 SAM_PINMUX(b, 3, e, periph) 1215 1216 /* pb4_gpio */ 1217 #define PB4_GPIO \ 1218 SAM_PINMUX(b, 4, gpio, gpio) 1219 1220 /* pb4a_eic_extint4 */ 1221 #define PB4A_EIC_EXTINT4 \ 1222 SAM_PINMUX(b, 4, a, periph) 1223 1224 /* pb4b_adc1_ain6 */ 1225 #define PB4B_ADC1_AIN6 \ 1226 SAM_PINMUX(b, 4, b, periph) 1227 1228 /* pb4b_ptc_xy22 */ 1229 #define PB4B_PTC_XY22 \ 1230 SAM_PINMUX(b, 4, b, periph) 1231 1232 /* pb5_gpio */ 1233 #define PB5_GPIO \ 1234 SAM_PINMUX(b, 5, gpio, gpio) 1235 1236 /* pb5a_eic_extint5 */ 1237 #define PB5A_EIC_EXTINT5 \ 1238 SAM_PINMUX(b, 5, a, periph) 1239 1240 /* pb5b_adc1_ain7 */ 1241 #define PB5B_ADC1_AIN7 \ 1242 SAM_PINMUX(b, 5, b, periph) 1243 1244 /* pb5b_ptc_xy23 */ 1245 #define PB5B_PTC_XY23 \ 1246 SAM_PINMUX(b, 5, b, periph) 1247 1248 /* pb6_gpio */ 1249 #define PB6_GPIO \ 1250 SAM_PINMUX(b, 6, gpio, gpio) 1251 1252 /* pb6a_eic_extint6 */ 1253 #define PB6A_EIC_EXTINT6 \ 1254 SAM_PINMUX(b, 6, a, periph) 1255 1256 /* pb6b_adc1_ain8 */ 1257 #define PB6B_ADC1_AIN8 \ 1258 SAM_PINMUX(b, 6, b, periph) 1259 1260 /* pb6b_ptc_xy24 */ 1261 #define PB6B_PTC_XY24 \ 1262 SAM_PINMUX(b, 6, b, periph) 1263 1264 /* pb6n_ccl_in6 */ 1265 #define PB6N_CCL_IN6 \ 1266 SAM_PINMUX(b, 6, n, periph) 1267 1268 /* pb7_gpio */ 1269 #define PB7_GPIO \ 1270 SAM_PINMUX(b, 7, gpio, gpio) 1271 1272 /* pb7a_eic_extint7 */ 1273 #define PB7A_EIC_EXTINT7 \ 1274 SAM_PINMUX(b, 7, a, periph) 1275 1276 /* pb7b_adc1_ain9 */ 1277 #define PB7B_ADC1_AIN9 \ 1278 SAM_PINMUX(b, 7, b, periph) 1279 1280 /* pb7b_ptc_xy25 */ 1281 #define PB7B_PTC_XY25 \ 1282 SAM_PINMUX(b, 7, b, periph) 1283 1284 /* pb7n_ccl_in7 */ 1285 #define PB7N_CCL_IN7 \ 1286 SAM_PINMUX(b, 7, n, periph) 1287 1288 /* pb8_gpio */ 1289 #define PB8_GPIO \ 1290 SAM_PINMUX(b, 8, gpio, gpio) 1291 1292 /* pb8a_eic_extint8 */ 1293 #define PB8A_EIC_EXTINT8 \ 1294 SAM_PINMUX(b, 8, a, periph) 1295 1296 /* pb8b_adc0_ain2 */ 1297 #define PB8B_ADC0_AIN2 \ 1298 SAM_PINMUX(b, 8, b, periph) 1299 1300 /* pb8b_adc1_ain0 */ 1301 #define PB8B_ADC1_AIN0 \ 1302 SAM_PINMUX(b, 8, b, periph) 1303 1304 /* pb8b_ptc_xy1 */ 1305 #define PB8B_PTC_XY1 \ 1306 SAM_PINMUX(b, 8, b, periph) 1307 1308 /* pb8d_sercom4_pad0 */ 1309 #define PB8D_SERCOM4_PAD0 \ 1310 SAM_PINMUX(b, 8, d, periph) 1311 1312 /* pb8e_tc4_wo0 */ 1313 #define PB8E_TC4_WO0 \ 1314 SAM_PINMUX(b, 8, e, periph) 1315 1316 /* pb8n_ccl_in8 */ 1317 #define PB8N_CCL_IN8 \ 1318 SAM_PINMUX(b, 8, n, periph) 1319 1320 /* pb9_gpio */ 1321 #define PB9_GPIO \ 1322 SAM_PINMUX(b, 9, gpio, gpio) 1323 1324 /* pb9a_eic_extint9 */ 1325 #define PB9A_EIC_EXTINT9 \ 1326 SAM_PINMUX(b, 9, a, periph) 1327 1328 /* pb9b_adc0_ain3 */ 1329 #define PB9B_ADC0_AIN3 \ 1330 SAM_PINMUX(b, 9, b, periph) 1331 1332 /* pb9b_adc1_ain1 */ 1333 #define PB9B_ADC1_AIN1 \ 1334 SAM_PINMUX(b, 9, b, periph) 1335 1336 /* pb9b_ptc_xy2 */ 1337 #define PB9B_PTC_XY2 \ 1338 SAM_PINMUX(b, 9, b, periph) 1339 1340 /* pb9d_sercom4_pad1 */ 1341 #define PB9D_SERCOM4_PAD1 \ 1342 SAM_PINMUX(b, 9, d, periph) 1343 1344 /* pb9e_tc4_wo1 */ 1345 #define PB9E_TC4_WO1 \ 1346 SAM_PINMUX(b, 9, e, periph) 1347 1348 /* pb9n_ccl_out2 */ 1349 #define PB9N_CCL_OUT2 \ 1350 SAM_PINMUX(b, 9, n, periph) 1351 1352 /* pb10_gpio */ 1353 #define PB10_GPIO \ 1354 SAM_PINMUX(b, 10, gpio, gpio) 1355 1356 /* pb10a_eic_extint10 */ 1357 #define PB10A_EIC_EXTINT10 \ 1358 SAM_PINMUX(b, 10, a, periph) 1359 1360 /* pb10d_sercom4_pad2 */ 1361 #define PB10D_SERCOM4_PAD2 \ 1362 SAM_PINMUX(b, 10, d, periph) 1363 1364 /* pb10e_tc5_wo0 */ 1365 #define PB10E_TC5_WO0 \ 1366 SAM_PINMUX(b, 10, e, periph) 1367 1368 /* pb10f_tcc0_wo4 */ 1369 #define PB10F_TCC0_WO4 \ 1370 SAM_PINMUX(b, 10, f, periph) 1371 1372 /* pb10g_tcc1_wo0 */ 1373 #define PB10G_TCC1_WO0 \ 1374 SAM_PINMUX(b, 10, g, periph) 1375 1376 /* pb10h_qspi_sck */ 1377 #define PB10H_QSPI_SCK \ 1378 SAM_PINMUX(b, 10, h, periph) 1379 1380 /* pb10i_sdhc0_dat3 */ 1381 #define PB10I_SDHC0_DAT3 \ 1382 SAM_PINMUX(b, 10, i, periph) 1383 1384 /* pb10j_iis_sdi */ 1385 #define PB10J_IIS_SDI \ 1386 SAM_PINMUX(b, 10, j, periph) 1387 1388 /* pb10m_gclk_io4 */ 1389 #define PB10M_GCLK_IO4 \ 1390 SAM_PINMUX(b, 10, m, periph) 1391 1392 /* pb10n_ccl_in11 */ 1393 #define PB10N_CCL_IN11 \ 1394 SAM_PINMUX(b, 10, n, periph) 1395 1396 /* pb11_gpio */ 1397 #define PB11_GPIO \ 1398 SAM_PINMUX(b, 11, gpio, gpio) 1399 1400 /* pb11a_eic_extint11 */ 1401 #define PB11A_EIC_EXTINT11 \ 1402 SAM_PINMUX(b, 11, a, periph) 1403 1404 /* pb11d_sercom4_pad3 */ 1405 #define PB11D_SERCOM4_PAD3 \ 1406 SAM_PINMUX(b, 11, d, periph) 1407 1408 /* pb11e_tc5_wo1 */ 1409 #define PB11E_TC5_WO1 \ 1410 SAM_PINMUX(b, 11, e, periph) 1411 1412 /* pb11f_tcc0_wo5 */ 1413 #define PB11F_TCC0_WO5 \ 1414 SAM_PINMUX(b, 11, f, periph) 1415 1416 /* pb11g_tcc1_wo1 */ 1417 #define PB11G_TCC1_WO1 \ 1418 SAM_PINMUX(b, 11, g, periph) 1419 1420 /* pb11h_qspi_cs */ 1421 #define PB11H_QSPI_CS \ 1422 SAM_PINMUX(b, 11, h, periph) 1423 1424 /* pb11i_sdhc0_ck */ 1425 #define PB11I_SDHC0_CK \ 1426 SAM_PINMUX(b, 11, i, periph) 1427 1428 /* pb11j_iis_fs1 */ 1429 #define PB11J_IIS_FS1 \ 1430 SAM_PINMUX(b, 11, j, periph) 1431 1432 /* pb11m_gclk_io5 */ 1433 #define PB11M_GCLK_IO5 \ 1434 SAM_PINMUX(b, 11, m, periph) 1435 1436 /* pb11n_ccl_out1 */ 1437 #define PB11N_CCL_OUT1 \ 1438 SAM_PINMUX(b, 11, n, periph) 1439 1440 /* pb12_gpio */ 1441 #define PB12_GPIO \ 1442 SAM_PINMUX(b, 12, gpio, gpio) 1443 1444 /* pb12a_eic_extint12 */ 1445 #define PB12A_EIC_EXTINT12 \ 1446 SAM_PINMUX(b, 12, a, periph) 1447 1448 /* pb12b_ptc_xy26 */ 1449 #define PB12B_PTC_XY26 \ 1450 SAM_PINMUX(b, 12, b, periph) 1451 1452 /* pb12c_sercom4_pad0 */ 1453 #define PB12C_SERCOM4_PAD0 \ 1454 SAM_PINMUX(b, 12, c, periph) 1455 1456 /* pb12e_tc4_wo0 */ 1457 #define PB12E_TC4_WO0 \ 1458 SAM_PINMUX(b, 12, e, periph) 1459 1460 /* pb12f_tcc3_wo0 */ 1461 #define PB12F_TCC3_WO0 \ 1462 SAM_PINMUX(b, 12, f, periph) 1463 1464 /* pb12g_tcc0_wo0 */ 1465 #define PB12G_TCC0_WO0 \ 1466 SAM_PINMUX(b, 12, g, periph) 1467 1468 /* pb12i_sdhc0_cd */ 1469 #define PB12I_SDHC0_CD \ 1470 SAM_PINMUX(b, 12, i, periph) 1471 1472 /* pb12j_iis_sck1 */ 1473 #define PB12J_IIS_SCK1 \ 1474 SAM_PINMUX(b, 12, j, periph) 1475 1476 /* pb12m_gclk_io6 */ 1477 #define PB12M_GCLK_IO6 \ 1478 SAM_PINMUX(b, 12, m, periph) 1479 1480 /* pb13_gpio */ 1481 #define PB13_GPIO \ 1482 SAM_PINMUX(b, 13, gpio, gpio) 1483 1484 /* pb13a_eic_extint13 */ 1485 #define PB13A_EIC_EXTINT13 \ 1486 SAM_PINMUX(b, 13, a, periph) 1487 1488 /* pb13b_ptc_xy27 */ 1489 #define PB13B_PTC_XY27 \ 1490 SAM_PINMUX(b, 13, b, periph) 1491 1492 /* pb13c_sercom4_pad1 */ 1493 #define PB13C_SERCOM4_PAD1 \ 1494 SAM_PINMUX(b, 13, c, periph) 1495 1496 /* pb13e_tc4_wo1 */ 1497 #define PB13E_TC4_WO1 \ 1498 SAM_PINMUX(b, 13, e, periph) 1499 1500 /* pb13f_tcc3_wo1 */ 1501 #define PB13F_TCC3_WO1 \ 1502 SAM_PINMUX(b, 13, f, periph) 1503 1504 /* pb13g_tcc0_wo1 */ 1505 #define PB13G_TCC0_WO1 \ 1506 SAM_PINMUX(b, 13, g, periph) 1507 1508 /* pb13i_sdhc0_wp */ 1509 #define PB13I_SDHC0_WP \ 1510 SAM_PINMUX(b, 13, i, periph) 1511 1512 /* pb13j_iis_mck1 */ 1513 #define PB13J_IIS_MCK1 \ 1514 SAM_PINMUX(b, 13, j, periph) 1515 1516 /* pb13m_gclk_io7 */ 1517 #define PB13M_GCLK_IO7 \ 1518 SAM_PINMUX(b, 13, m, periph) 1519 1520 /* pb14_gpio */ 1521 #define PB14_GPIO \ 1522 SAM_PINMUX(b, 14, gpio, gpio) 1523 1524 /* pb14a_eic_extint14 */ 1525 #define PB14A_EIC_EXTINT14 \ 1526 SAM_PINMUX(b, 14, a, periph) 1527 1528 /* pb14b_ptc_xy28 */ 1529 #define PB14B_PTC_XY28 \ 1530 SAM_PINMUX(b, 14, b, periph) 1531 1532 /* pb14c_sercom4_pad2 */ 1533 #define PB14C_SERCOM4_PAD2 \ 1534 SAM_PINMUX(b, 14, c, periph) 1535 1536 /* pb14e_tc5_wo0 */ 1537 #define PB14E_TC5_WO0 \ 1538 SAM_PINMUX(b, 14, e, periph) 1539 1540 /* pb14f_tcc4_wo0 */ 1541 #define PB14F_TCC4_WO0 \ 1542 SAM_PINMUX(b, 14, f, periph) 1543 1544 /* pb14g_tcc0_wo2 */ 1545 #define PB14G_TCC0_WO2 \ 1546 SAM_PINMUX(b, 14, g, periph) 1547 1548 /* pb14k_pcc_data8 */ 1549 #define PB14K_PCC_DATA8 \ 1550 SAM_PINMUX(b, 14, k, periph) 1551 1552 /* pb14m_gclk_io0 */ 1553 #define PB14M_GCLK_IO0 \ 1554 SAM_PINMUX(b, 14, m, periph) 1555 1556 /* pb14n_ccl_in9 */ 1557 #define PB14N_CCL_IN9 \ 1558 SAM_PINMUX(b, 14, n, periph) 1559 1560 /* pb15_gpio */ 1561 #define PB15_GPIO \ 1562 SAM_PINMUX(b, 15, gpio, gpio) 1563 1564 /* pb15a_eic_extint15 */ 1565 #define PB15A_EIC_EXTINT15 \ 1566 SAM_PINMUX(b, 15, a, periph) 1567 1568 /* pb15b_ptc_xy29 */ 1569 #define PB15B_PTC_XY29 \ 1570 SAM_PINMUX(b, 15, b, periph) 1571 1572 /* pb15c_sercom4_pad3 */ 1573 #define PB15C_SERCOM4_PAD3 \ 1574 SAM_PINMUX(b, 15, c, periph) 1575 1576 /* pb15e_tc5_wo1 */ 1577 #define PB15E_TC5_WO1 \ 1578 SAM_PINMUX(b, 15, e, periph) 1579 1580 /* pb15f_tcc4_wo1 */ 1581 #define PB15F_TCC4_WO1 \ 1582 SAM_PINMUX(b, 15, f, periph) 1583 1584 /* pb15g_tcc0_wo3 */ 1585 #define PB15G_TCC0_WO3 \ 1586 SAM_PINMUX(b, 15, g, periph) 1587 1588 /* pb15k_pcc_data9 */ 1589 #define PB15K_PCC_DATA9 \ 1590 SAM_PINMUX(b, 15, k, periph) 1591 1592 /* pb15m_gclk_io1 */ 1593 #define PB15M_GCLK_IO1 \ 1594 SAM_PINMUX(b, 15, m, periph) 1595 1596 /* pb15n_ccl_in10 */ 1597 #define PB15N_CCL_IN10 \ 1598 SAM_PINMUX(b, 15, n, periph) 1599 1600 /* pb16_gpio */ 1601 #define PB16_GPIO \ 1602 SAM_PINMUX(b, 16, gpio, gpio) 1603 1604 /* pb16a_eic_extint0 */ 1605 #define PB16A_EIC_EXTINT0 \ 1606 SAM_PINMUX(b, 16, a, periph) 1607 1608 /* pb16c_sercom5_pad0 */ 1609 #define PB16C_SERCOM5_PAD0 \ 1610 SAM_PINMUX(b, 16, c, periph) 1611 1612 /* pb16e_tc6_wo0 */ 1613 #define PB16E_TC6_WO0 \ 1614 SAM_PINMUX(b, 16, e, periph) 1615 1616 /* pb16f_tcc3_wo0 */ 1617 #define PB16F_TCC3_WO0 \ 1618 SAM_PINMUX(b, 16, f, periph) 1619 1620 /* pb16g_tcc0_wo4 */ 1621 #define PB16G_TCC0_WO4 \ 1622 SAM_PINMUX(b, 16, g, periph) 1623 1624 /* pb16i_sdhc1_cd */ 1625 #define PB16I_SDHC1_CD \ 1626 SAM_PINMUX(b, 16, i, periph) 1627 1628 /* pb16j_iis_sck0 */ 1629 #define PB16J_IIS_SCK0 \ 1630 SAM_PINMUX(b, 16, j, periph) 1631 1632 /* pb16m_gclk_io2 */ 1633 #define PB16M_GCLK_IO2 \ 1634 SAM_PINMUX(b, 16, m, periph) 1635 1636 /* pb16n_ccl_in11 */ 1637 #define PB16N_CCL_IN11 \ 1638 SAM_PINMUX(b, 16, n, periph) 1639 1640 /* pb17_gpio */ 1641 #define PB17_GPIO \ 1642 SAM_PINMUX(b, 17, gpio, gpio) 1643 1644 /* pb17a_eic_extint1 */ 1645 #define PB17A_EIC_EXTINT1 \ 1646 SAM_PINMUX(b, 17, a, periph) 1647 1648 /* pb17c_sercom5_pad1 */ 1649 #define PB17C_SERCOM5_PAD1 \ 1650 SAM_PINMUX(b, 17, c, periph) 1651 1652 /* pb17e_tc6_wo1 */ 1653 #define PB17E_TC6_WO1 \ 1654 SAM_PINMUX(b, 17, e, periph) 1655 1656 /* pb17f_tcc3_wo1 */ 1657 #define PB17F_TCC3_WO1 \ 1658 SAM_PINMUX(b, 17, f, periph) 1659 1660 /* pb17g_tcc0_wo5 */ 1661 #define PB17G_TCC0_WO5 \ 1662 SAM_PINMUX(b, 17, g, periph) 1663 1664 /* pb17i_sdhc1_wp */ 1665 #define PB17I_SDHC1_WP \ 1666 SAM_PINMUX(b, 17, i, periph) 1667 1668 /* pb17j_iis_mck0 */ 1669 #define PB17J_IIS_MCK0 \ 1670 SAM_PINMUX(b, 17, j, periph) 1671 1672 /* pb17m_gclk_io3 */ 1673 #define PB17M_GCLK_IO3 \ 1674 SAM_PINMUX(b, 17, m, periph) 1675 1676 /* pb17n_ccl_out3 */ 1677 #define PB17N_CCL_OUT3 \ 1678 SAM_PINMUX(b, 17, n, periph) 1679 1680 /* pb18_gpio */ 1681 #define PB18_GPIO \ 1682 SAM_PINMUX(b, 18, gpio, gpio) 1683 1684 /* pb18a_eic_extint2 */ 1685 #define PB18A_EIC_EXTINT2 \ 1686 SAM_PINMUX(b, 18, a, periph) 1687 1688 /* pb18c_sercom5_pad2 */ 1689 #define PB18C_SERCOM5_PAD2 \ 1690 SAM_PINMUX(b, 18, c, periph) 1691 1692 /* pb18d_sercom7_pad2 */ 1693 #define PB18D_SERCOM7_PAD2 \ 1694 SAM_PINMUX(b, 18, d, periph) 1695 1696 /* pb18f_tcc1_wo0 */ 1697 #define PB18F_TCC1_WO0 \ 1698 SAM_PINMUX(b, 18, f, periph) 1699 1700 /* pb18g_pdec_qdi0 */ 1701 #define PB18G_PDEC_QDI0 \ 1702 SAM_PINMUX(b, 18, g, periph) 1703 1704 /* pb18i_sdhc1_dat0 */ 1705 #define PB18I_SDHC1_DAT0 \ 1706 SAM_PINMUX(b, 18, i, periph) 1707 1708 /* pb18m_gclk_io4 */ 1709 #define PB18M_GCLK_IO4 \ 1710 SAM_PINMUX(b, 18, m, periph) 1711 1712 /* pb19_gpio */ 1713 #define PB19_GPIO \ 1714 SAM_PINMUX(b, 19, gpio, gpio) 1715 1716 /* pb19a_eic_extint3 */ 1717 #define PB19A_EIC_EXTINT3 \ 1718 SAM_PINMUX(b, 19, a, periph) 1719 1720 /* pb19c_sercom5_pad3 */ 1721 #define PB19C_SERCOM5_PAD3 \ 1722 SAM_PINMUX(b, 19, c, periph) 1723 1724 /* pb19d_sercom7_pad3 */ 1725 #define PB19D_SERCOM7_PAD3 \ 1726 SAM_PINMUX(b, 19, d, periph) 1727 1728 /* pb19f_tcc1_wo1 */ 1729 #define PB19F_TCC1_WO1 \ 1730 SAM_PINMUX(b, 19, f, periph) 1731 1732 /* pb19g_pdec_qdi1 */ 1733 #define PB19G_PDEC_QDI1 \ 1734 SAM_PINMUX(b, 19, g, periph) 1735 1736 /* pb19i_sdhc1_dat1 */ 1737 #define PB19I_SDHC1_DAT1 \ 1738 SAM_PINMUX(b, 19, i, periph) 1739 1740 /* pb19m_gclk_io5 */ 1741 #define PB19M_GCLK_IO5 \ 1742 SAM_PINMUX(b, 19, m, periph) 1743 1744 /* pb20_gpio */ 1745 #define PB20_GPIO \ 1746 SAM_PINMUX(b, 20, gpio, gpio) 1747 1748 /* pb20a_eic_extint4 */ 1749 #define PB20A_EIC_EXTINT4 \ 1750 SAM_PINMUX(b, 20, a, periph) 1751 1752 /* pb20c_sercom3_pad0 */ 1753 #define PB20C_SERCOM3_PAD0 \ 1754 SAM_PINMUX(b, 20, c, periph) 1755 1756 /* pb20d_sercom7_pad1 */ 1757 #define PB20D_SERCOM7_PAD1 \ 1758 SAM_PINMUX(b, 20, d, periph) 1759 1760 /* pb20f_tcc1_wo2 */ 1761 #define PB20F_TCC1_WO2 \ 1762 SAM_PINMUX(b, 20, f, periph) 1763 1764 /* pb20g_pdec_qdi2 */ 1765 #define PB20G_PDEC_QDI2 \ 1766 SAM_PINMUX(b, 20, g, periph) 1767 1768 /* pb20i_sdhc1_dat2 */ 1769 #define PB20I_SDHC1_DAT2 \ 1770 SAM_PINMUX(b, 20, i, periph) 1771 1772 /* pb20m_gclk_io6 */ 1773 #define PB20M_GCLK_IO6 \ 1774 SAM_PINMUX(b, 20, m, periph) 1775 1776 /* pb21_gpio */ 1777 #define PB21_GPIO \ 1778 SAM_PINMUX(b, 21, gpio, gpio) 1779 1780 /* pb21a_eic_extint5 */ 1781 #define PB21A_EIC_EXTINT5 \ 1782 SAM_PINMUX(b, 21, a, periph) 1783 1784 /* pb21c_sercom3_pad1 */ 1785 #define PB21C_SERCOM3_PAD1 \ 1786 SAM_PINMUX(b, 21, c, periph) 1787 1788 /* pb21d_sercom7_pad0 */ 1789 #define PB21D_SERCOM7_PAD0 \ 1790 SAM_PINMUX(b, 21, d, periph) 1791 1792 /* pb21f_tcc1_wo3 */ 1793 #define PB21F_TCC1_WO3 \ 1794 SAM_PINMUX(b, 21, f, periph) 1795 1796 /* pb21i_sdhc1_dat3 */ 1797 #define PB21I_SDHC1_DAT3 \ 1798 SAM_PINMUX(b, 21, i, periph) 1799 1800 /* pb21m_gclk_io7 */ 1801 #define PB21M_GCLK_IO7 \ 1802 SAM_PINMUX(b, 21, m, periph) 1803 1804 /* pb22_gpio */ 1805 #define PB22_GPIO \ 1806 SAM_PINMUX(b, 22, gpio, gpio) 1807 1808 /* pb22a_eic_extint6 */ 1809 #define PB22A_EIC_EXTINT6 \ 1810 SAM_PINMUX(b, 22, a, periph) 1811 1812 /* pb22c_sercom1_pad2 */ 1813 #define PB22C_SERCOM1_PAD2 \ 1814 SAM_PINMUX(b, 22, c, periph) 1815 1816 /* pb22d_sercom5_pad2 */ 1817 #define PB22D_SERCOM5_PAD2 \ 1818 SAM_PINMUX(b, 22, d, periph) 1819 1820 /* pb22e_tc7_wo0 */ 1821 #define PB22E_TC7_WO0 \ 1822 SAM_PINMUX(b, 22, e, periph) 1823 1824 /* pb22g_pdec_qdi2 */ 1825 #define PB22G_PDEC_QDI2 \ 1826 SAM_PINMUX(b, 22, g, periph) 1827 1828 /* pb22h_usb_sof */ 1829 #define PB22H_USB_SOF \ 1830 SAM_PINMUX(b, 22, h, periph) 1831 1832 /* pb22m_gclk_io0 */ 1833 #define PB22M_GCLK_IO0 \ 1834 SAM_PINMUX(b, 22, m, periph) 1835 1836 /* pb22n_ccl_in0 */ 1837 #define PB22N_CCL_IN0 \ 1838 SAM_PINMUX(b, 22, n, periph) 1839 1840 /* pb23_gpio */ 1841 #define PB23_GPIO \ 1842 SAM_PINMUX(b, 23, gpio, gpio) 1843 1844 /* pb23a_eic_extint7 */ 1845 #define PB23A_EIC_EXTINT7 \ 1846 SAM_PINMUX(b, 23, a, periph) 1847 1848 /* pb23c_sercom1_pad3 */ 1849 #define PB23C_SERCOM1_PAD3 \ 1850 SAM_PINMUX(b, 23, c, periph) 1851 1852 /* pb23d_sercom5_pad3 */ 1853 #define PB23D_SERCOM5_PAD3 \ 1854 SAM_PINMUX(b, 23, d, periph) 1855 1856 /* pb23e_tc7_wo1 */ 1857 #define PB23E_TC7_WO1 \ 1858 SAM_PINMUX(b, 23, e, periph) 1859 1860 /* pb23g_pdec_qdi0 */ 1861 #define PB23G_PDEC_QDI0 \ 1862 SAM_PINMUX(b, 23, g, periph) 1863 1864 /* pb23m_gclk_io1 */ 1865 #define PB23M_GCLK_IO1 \ 1866 SAM_PINMUX(b, 23, m, periph) 1867 1868 /* pb23n_ccl_out0 */ 1869 #define PB23N_CCL_OUT0 \ 1870 SAM_PINMUX(b, 23, n, periph) 1871 1872 /* pb24_gpio */ 1873 #define PB24_GPIO \ 1874 SAM_PINMUX(b, 24, gpio, gpio) 1875 1876 /* pb24a_eic_extint8 */ 1877 #define PB24A_EIC_EXTINT8 \ 1878 SAM_PINMUX(b, 24, a, periph) 1879 1880 /* pb24c_sercom0_pad0 */ 1881 #define PB24C_SERCOM0_PAD0 \ 1882 SAM_PINMUX(b, 24, c, periph) 1883 1884 /* pb24d_sercom2_pad1 */ 1885 #define PB24D_SERCOM2_PAD1 \ 1886 SAM_PINMUX(b, 24, d, periph) 1887 1888 /* pb24g_pdec_qdi1 */ 1889 #define PB24G_PDEC_QDI1 \ 1890 SAM_PINMUX(b, 24, g, periph) 1891 1892 /* pb24m_ac_cmp0 */ 1893 #define PB24M_AC_CMP0 \ 1894 SAM_PINMUX(b, 24, m, periph) 1895 1896 /* pb25_gpio */ 1897 #define PB25_GPIO \ 1898 SAM_PINMUX(b, 25, gpio, gpio) 1899 1900 /* pb25a_eic_extint9 */ 1901 #define PB25A_EIC_EXTINT9 \ 1902 SAM_PINMUX(b, 25, a, periph) 1903 1904 /* pb25c_sercom0_pad1 */ 1905 #define PB25C_SERCOM0_PAD1 \ 1906 SAM_PINMUX(b, 25, c, periph) 1907 1908 /* pb25d_sercom2_pad0 */ 1909 #define PB25D_SERCOM2_PAD0 \ 1910 SAM_PINMUX(b, 25, d, periph) 1911 1912 /* pb25g_pdec_qdi2 */ 1913 #define PB25G_PDEC_QDI2 \ 1914 SAM_PINMUX(b, 25, g, periph) 1915 1916 /* pb25m_ac_cmp1 */ 1917 #define PB25M_AC_CMP1 \ 1918 SAM_PINMUX(b, 25, m, periph) 1919 1920 /* pb26_gpio */ 1921 #define PB26_GPIO \ 1922 SAM_PINMUX(b, 26, gpio, gpio) 1923 1924 /* pb26a_eic_extint12 */ 1925 #define PB26A_EIC_EXTINT12 \ 1926 SAM_PINMUX(b, 26, a, periph) 1927 1928 /* pb26c_sercom2_pad0 */ 1929 #define PB26C_SERCOM2_PAD0 \ 1930 SAM_PINMUX(b, 26, c, periph) 1931 1932 /* pb26d_sercom4_pad1 */ 1933 #define PB26D_SERCOM4_PAD1 \ 1934 SAM_PINMUX(b, 26, d, periph) 1935 1936 /* pb26f_tcc1_wo2 */ 1937 #define PB26F_TCC1_WO2 \ 1938 SAM_PINMUX(b, 26, f, periph) 1939 1940 /* pb27_gpio */ 1941 #define PB27_GPIO \ 1942 SAM_PINMUX(b, 27, gpio, gpio) 1943 1944 /* pb27a_eic_extint13 */ 1945 #define PB27A_EIC_EXTINT13 \ 1946 SAM_PINMUX(b, 27, a, periph) 1947 1948 /* pb27c_sercom2_pad1 */ 1949 #define PB27C_SERCOM2_PAD1 \ 1950 SAM_PINMUX(b, 27, c, periph) 1951 1952 /* pb27d_sercom4_pad0 */ 1953 #define PB27D_SERCOM4_PAD0 \ 1954 SAM_PINMUX(b, 27, d, periph) 1955 1956 /* pb27f_tcc1_wo3 */ 1957 #define PB27F_TCC1_WO3 \ 1958 SAM_PINMUX(b, 27, f, periph) 1959 1960 /* pb28_gpio */ 1961 #define PB28_GPIO \ 1962 SAM_PINMUX(b, 28, gpio, gpio) 1963 1964 /* pb28a_eic_extint14 */ 1965 #define PB28A_EIC_EXTINT14 \ 1966 SAM_PINMUX(b, 28, a, periph) 1967 1968 /* pb28c_sercom2_pad2 */ 1969 #define PB28C_SERCOM2_PAD2 \ 1970 SAM_PINMUX(b, 28, c, periph) 1971 1972 /* pb28d_sercom4_pad2 */ 1973 #define PB28D_SERCOM4_PAD2 \ 1974 SAM_PINMUX(b, 28, d, periph) 1975 1976 /* pb28f_tcc1_wo4 */ 1977 #define PB28F_TCC1_WO4 \ 1978 SAM_PINMUX(b, 28, f, periph) 1979 1980 /* pb28j_iis_sck1 */ 1981 #define PB28J_IIS_SCK1 \ 1982 SAM_PINMUX(b, 28, j, periph) 1983 1984 /* pb29_gpio */ 1985 #define PB29_GPIO \ 1986 SAM_PINMUX(b, 29, gpio, gpio) 1987 1988 /* pb29a_eic_extint15 */ 1989 #define PB29A_EIC_EXTINT15 \ 1990 SAM_PINMUX(b, 29, a, periph) 1991 1992 /* pb29c_sercom2_pad3 */ 1993 #define PB29C_SERCOM2_PAD3 \ 1994 SAM_PINMUX(b, 29, c, periph) 1995 1996 /* pb29d_sercom4_pad3 */ 1997 #define PB29D_SERCOM4_PAD3 \ 1998 SAM_PINMUX(b, 29, d, periph) 1999 2000 /* pb29f_tcc1_wo5 */ 2001 #define PB29F_TCC1_WO5 \ 2002 SAM_PINMUX(b, 29, f, periph) 2003 2004 /* pb29j_iis_mck1 */ 2005 #define PB29J_IIS_MCK1 \ 2006 SAM_PINMUX(b, 29, j, periph) 2007 2008 /* pb30_gpio */ 2009 #define PB30_GPIO \ 2010 SAM_PINMUX(b, 30, gpio, gpio) 2011 2012 /* pb30a_eic_extint14 */ 2013 #define PB30A_EIC_EXTINT14 \ 2014 SAM_PINMUX(b, 30, a, periph) 2015 2016 /* pb30d_sercom5_pad1 */ 2017 #define PB30D_SERCOM5_PAD1 \ 2018 SAM_PINMUX(b, 30, d, periph) 2019 2020 /* pb30e_tc0_wo0 */ 2021 #define PB30E_TC0_WO0 \ 2022 SAM_PINMUX(b, 30, e, periph) 2023 2024 /* pb30f_tcc4_wo0 */ 2025 #define PB30F_TCC4_WO0 \ 2026 SAM_PINMUX(b, 30, f, periph) 2027 2028 /* pb30g_tcc0_wo6 */ 2029 #define PB30G_TCC0_WO6 \ 2030 SAM_PINMUX(b, 30, g, periph) 2031 2032 /* pb30h_swd_swo */ 2033 #define PB30H_SWD_SWO \ 2034 SAM_PINMUX(b, 30, h, periph) 2035 2036 /* pb31_gpio */ 2037 #define PB31_GPIO \ 2038 SAM_PINMUX(b, 31, gpio, gpio) 2039 2040 /* pb31a_eic_extint15 */ 2041 #define PB31A_EIC_EXTINT15 \ 2042 SAM_PINMUX(b, 31, a, periph) 2043 2044 /* pb31d_sercom5_pad0 */ 2045 #define PB31D_SERCOM5_PAD0 \ 2046 SAM_PINMUX(b, 31, d, periph) 2047 2048 /* pb31e_tc0_wo1 */ 2049 #define PB31E_TC0_WO1 \ 2050 SAM_PINMUX(b, 31, e, periph) 2051 2052 /* pb31f_tcc4_wo1 */ 2053 #define PB31F_TCC4_WO1 \ 2054 SAM_PINMUX(b, 31, f, periph) 2055 2056 /* pb31g_tcc0_wo7 */ 2057 #define PB31G_TCC0_WO7 \ 2058 SAM_PINMUX(b, 31, g, periph) 2059 2060 /* pc0_gpio */ 2061 #define PC0_GPIO \ 2062 SAM_PINMUX(c, 0, gpio, gpio) 2063 2064 /* pc0a_eic_extint0 */ 2065 #define PC0A_EIC_EXTINT0 \ 2066 SAM_PINMUX(c, 0, a, periph) 2067 2068 /* pc0b_adc1_ain10 */ 2069 #define PC0B_ADC1_AIN10 \ 2070 SAM_PINMUX(c, 0, b, periph) 2071 2072 /* pc1_gpio */ 2073 #define PC1_GPIO \ 2074 SAM_PINMUX(c, 1, gpio, gpio) 2075 2076 /* pc1a_eic_extint1 */ 2077 #define PC1A_EIC_EXTINT1 \ 2078 SAM_PINMUX(c, 1, a, periph) 2079 2080 /* pc1b_adc1_ain11 */ 2081 #define PC1B_ADC1_AIN11 \ 2082 SAM_PINMUX(c, 1, b, periph) 2083 2084 /* pc2_gpio */ 2085 #define PC2_GPIO \ 2086 SAM_PINMUX(c, 2, gpio, gpio) 2087 2088 /* pc2a_eic_extint2 */ 2089 #define PC2A_EIC_EXTINT2 \ 2090 SAM_PINMUX(c, 2, a, periph) 2091 2092 /* pc2b_adc1_ain4 */ 2093 #define PC2B_ADC1_AIN4 \ 2094 SAM_PINMUX(c, 2, b, periph) 2095 2096 /* pc3_gpio */ 2097 #define PC3_GPIO \ 2098 SAM_PINMUX(c, 3, gpio, gpio) 2099 2100 /* pc3a_eic_extint3 */ 2101 #define PC3A_EIC_EXTINT3 \ 2102 SAM_PINMUX(c, 3, a, periph) 2103 2104 /* pc3b_adc1_ain5 */ 2105 #define PC3B_ADC1_AIN5 \ 2106 SAM_PINMUX(c, 3, b, periph) 2107 2108 /* pc4_gpio */ 2109 #define PC4_GPIO \ 2110 SAM_PINMUX(c, 4, gpio, gpio) 2111 2112 /* pc4a_eic_extint4 */ 2113 #define PC4A_EIC_EXTINT4 \ 2114 SAM_PINMUX(c, 4, a, periph) 2115 2116 /* pc4c_sercom6_pad0 */ 2117 #define PC4C_SERCOM6_PAD0 \ 2118 SAM_PINMUX(c, 4, c, periph) 2119 2120 /* pc4f_tcc0_wo0 */ 2121 #define PC4F_TCC0_WO0 \ 2122 SAM_PINMUX(c, 4, f, periph) 2123 2124 /* pc5_gpio */ 2125 #define PC5_GPIO \ 2126 SAM_PINMUX(c, 5, gpio, gpio) 2127 2128 /* pc5a_eic_extint5 */ 2129 #define PC5A_EIC_EXTINT5 \ 2130 SAM_PINMUX(c, 5, a, periph) 2131 2132 /* pc5c_sercom6_pad1 */ 2133 #define PC5C_SERCOM6_PAD1 \ 2134 SAM_PINMUX(c, 5, c, periph) 2135 2136 /* pc6_gpio */ 2137 #define PC6_GPIO \ 2138 SAM_PINMUX(c, 6, gpio, gpio) 2139 2140 /* pc6a_eic_extint6 */ 2141 #define PC6A_EIC_EXTINT6 \ 2142 SAM_PINMUX(c, 6, a, periph) 2143 2144 /* pc6c_sercom6_pad2 */ 2145 #define PC6C_SERCOM6_PAD2 \ 2146 SAM_PINMUX(c, 6, c, periph) 2147 2148 /* pc6i_sdhc0_cd */ 2149 #define PC6I_SDHC0_CD \ 2150 SAM_PINMUX(c, 6, i, periph) 2151 2152 /* pc7_gpio */ 2153 #define PC7_GPIO \ 2154 SAM_PINMUX(c, 7, gpio, gpio) 2155 2156 /* pc7a_eic_extint7 */ 2157 #define PC7A_EIC_EXTINT7 \ 2158 SAM_PINMUX(c, 7, a, periph) 2159 2160 /* pc7c_sercom6_pad3 */ 2161 #define PC7C_SERCOM6_PAD3 \ 2162 SAM_PINMUX(c, 7, c, periph) 2163 2164 /* pc7i_sdhc0_wp */ 2165 #define PC7I_SDHC0_WP \ 2166 SAM_PINMUX(c, 7, i, periph) 2167 2168 /* pc10_gpio */ 2169 #define PC10_GPIO \ 2170 SAM_PINMUX(c, 10, gpio, gpio) 2171 2172 /* pc10a_eic_extint10 */ 2173 #define PC10A_EIC_EXTINT10 \ 2174 SAM_PINMUX(c, 10, a, periph) 2175 2176 /* pc10c_sercom6_pad2 */ 2177 #define PC10C_SERCOM6_PAD2 \ 2178 SAM_PINMUX(c, 10, c, periph) 2179 2180 /* pc10d_sercom7_pad2 */ 2181 #define PC10D_SERCOM7_PAD2 \ 2182 SAM_PINMUX(c, 10, d, periph) 2183 2184 /* pc10f_tcc0_wo0 */ 2185 #define PC10F_TCC0_WO0 \ 2186 SAM_PINMUX(c, 10, f, periph) 2187 2188 /* pc10g_tcc1_wo4 */ 2189 #define PC10G_TCC1_WO4 \ 2190 SAM_PINMUX(c, 10, g, periph) 2191 2192 /* pc11_gpio */ 2193 #define PC11_GPIO \ 2194 SAM_PINMUX(c, 11, gpio, gpio) 2195 2196 /* pc11a_eic_extint11 */ 2197 #define PC11A_EIC_EXTINT11 \ 2198 SAM_PINMUX(c, 11, a, periph) 2199 2200 /* pc11c_sercom6_pad3 */ 2201 #define PC11C_SERCOM6_PAD3 \ 2202 SAM_PINMUX(c, 11, c, periph) 2203 2204 /* pc11d_sercom7_pad3 */ 2205 #define PC11D_SERCOM7_PAD3 \ 2206 SAM_PINMUX(c, 11, d, periph) 2207 2208 /* pc11f_tcc0_wo1 */ 2209 #define PC11F_TCC0_WO1 \ 2210 SAM_PINMUX(c, 11, f, periph) 2211 2212 /* pc11g_tcc1_wo5 */ 2213 #define PC11G_TCC1_WO5 \ 2214 SAM_PINMUX(c, 11, g, periph) 2215 2216 /* pc12_gpio */ 2217 #define PC12_GPIO \ 2218 SAM_PINMUX(c, 12, gpio, gpio) 2219 2220 /* pc12a_eic_extint12 */ 2221 #define PC12A_EIC_EXTINT12 \ 2222 SAM_PINMUX(c, 12, a, periph) 2223 2224 /* pc12c_sercom7_pad0 */ 2225 #define PC12C_SERCOM7_PAD0 \ 2226 SAM_PINMUX(c, 12, c, periph) 2227 2228 /* pc12d_sercom6_pad1 */ 2229 #define PC12D_SERCOM6_PAD1 \ 2230 SAM_PINMUX(c, 12, d, periph) 2231 2232 /* pc12f_tcc0_wo2 */ 2233 #define PC12F_TCC0_WO2 \ 2234 SAM_PINMUX(c, 12, f, periph) 2235 2236 /* pc12g_tcc1_wo6 */ 2237 #define PC12G_TCC1_WO6 \ 2238 SAM_PINMUX(c, 12, g, periph) 2239 2240 /* pc12k_pcc_data10 */ 2241 #define PC12K_PCC_DATA10 \ 2242 SAM_PINMUX(c, 12, k, periph) 2243 2244 /* pc13_gpio */ 2245 #define PC13_GPIO \ 2246 SAM_PINMUX(c, 13, gpio, gpio) 2247 2248 /* pc13a_eic_extint13 */ 2249 #define PC13A_EIC_EXTINT13 \ 2250 SAM_PINMUX(c, 13, a, periph) 2251 2252 /* pc13c_sercom7_pad1 */ 2253 #define PC13C_SERCOM7_PAD1 \ 2254 SAM_PINMUX(c, 13, c, periph) 2255 2256 /* pc13d_sercom6_pad0 */ 2257 #define PC13D_SERCOM6_PAD0 \ 2258 SAM_PINMUX(c, 13, d, periph) 2259 2260 /* pc13f_tcc0_wo3 */ 2261 #define PC13F_TCC0_WO3 \ 2262 SAM_PINMUX(c, 13, f, periph) 2263 2264 /* pc13g_tcc1_wo7 */ 2265 #define PC13G_TCC1_WO7 \ 2266 SAM_PINMUX(c, 13, g, periph) 2267 2268 /* pc13k_pcc_data11 */ 2269 #define PC13K_PCC_DATA11 \ 2270 SAM_PINMUX(c, 13, k, periph) 2271 2272 /* pc14_gpio */ 2273 #define PC14_GPIO \ 2274 SAM_PINMUX(c, 14, gpio, gpio) 2275 2276 /* pc14a_eic_extint14 */ 2277 #define PC14A_EIC_EXTINT14 \ 2278 SAM_PINMUX(c, 14, a, periph) 2279 2280 /* pc14c_sercom7_pad2 */ 2281 #define PC14C_SERCOM7_PAD2 \ 2282 SAM_PINMUX(c, 14, c, periph) 2283 2284 /* pc14d_sercom6_pad2 */ 2285 #define PC14D_SERCOM6_PAD2 \ 2286 SAM_PINMUX(c, 14, d, periph) 2287 2288 /* pc14f_tcc0_wo4 */ 2289 #define PC14F_TCC0_WO4 \ 2290 SAM_PINMUX(c, 14, f, periph) 2291 2292 /* pc14g_tcc1_wo0 */ 2293 #define PC14G_TCC1_WO0 \ 2294 SAM_PINMUX(c, 14, g, periph) 2295 2296 /* pc14k_pcc_data12 */ 2297 #define PC14K_PCC_DATA12 \ 2298 SAM_PINMUX(c, 14, k, periph) 2299 2300 /* pc15_gpio */ 2301 #define PC15_GPIO \ 2302 SAM_PINMUX(c, 15, gpio, gpio) 2303 2304 /* pc15a_eic_extint15 */ 2305 #define PC15A_EIC_EXTINT15 \ 2306 SAM_PINMUX(c, 15, a, periph) 2307 2308 /* pc15c_sercom7_pad3 */ 2309 #define PC15C_SERCOM7_PAD3 \ 2310 SAM_PINMUX(c, 15, c, periph) 2311 2312 /* pc15d_sercom6_pad3 */ 2313 #define PC15D_SERCOM6_PAD3 \ 2314 SAM_PINMUX(c, 15, d, periph) 2315 2316 /* pc15f_tcc0_wo5 */ 2317 #define PC15F_TCC0_WO5 \ 2318 SAM_PINMUX(c, 15, f, periph) 2319 2320 /* pc15g_tcc1_wo1 */ 2321 #define PC15G_TCC1_WO1 \ 2322 SAM_PINMUX(c, 15, g, periph) 2323 2324 /* pc15k_pcc_data13 */ 2325 #define PC15K_PCC_DATA13 \ 2326 SAM_PINMUX(c, 15, k, periph) 2327 2328 /* pc16_gpio */ 2329 #define PC16_GPIO \ 2330 SAM_PINMUX(c, 16, gpio, gpio) 2331 2332 /* pc16a_eic_extint0 */ 2333 #define PC16A_EIC_EXTINT0 \ 2334 SAM_PINMUX(c, 16, a, periph) 2335 2336 /* pc16c_sercom6_pad0 */ 2337 #define PC16C_SERCOM6_PAD0 \ 2338 SAM_PINMUX(c, 16, c, periph) 2339 2340 /* pc16d_sercom0_pad1 */ 2341 #define PC16D_SERCOM0_PAD1 \ 2342 SAM_PINMUX(c, 16, d, periph) 2343 2344 /* pc16f_tcc0_wo0 */ 2345 #define PC16F_TCC0_WO0 \ 2346 SAM_PINMUX(c, 16, f, periph) 2347 2348 /* pc16g_pdec_qdi0 */ 2349 #define PC16G_PDEC_QDI0 \ 2350 SAM_PINMUX(c, 16, g, periph) 2351 2352 /* pc17_gpio */ 2353 #define PC17_GPIO \ 2354 SAM_PINMUX(c, 17, gpio, gpio) 2355 2356 /* pc17a_eic_extint1 */ 2357 #define PC17A_EIC_EXTINT1 \ 2358 SAM_PINMUX(c, 17, a, periph) 2359 2360 /* pc17c_sercom6_pad1 */ 2361 #define PC17C_SERCOM6_PAD1 \ 2362 SAM_PINMUX(c, 17, c, periph) 2363 2364 /* pc17d_sercom0_pad0 */ 2365 #define PC17D_SERCOM0_PAD0 \ 2366 SAM_PINMUX(c, 17, d, periph) 2367 2368 /* pc17f_tcc0_wo1 */ 2369 #define PC17F_TCC0_WO1 \ 2370 SAM_PINMUX(c, 17, f, periph) 2371 2372 /* pc17g_pdec_qdi1 */ 2373 #define PC17G_PDEC_QDI1 \ 2374 SAM_PINMUX(c, 17, g, periph) 2375 2376 /* pc18_gpio */ 2377 #define PC18_GPIO \ 2378 SAM_PINMUX(c, 18, gpio, gpio) 2379 2380 /* pc18a_eic_extint2 */ 2381 #define PC18A_EIC_EXTINT2 \ 2382 SAM_PINMUX(c, 18, a, periph) 2383 2384 /* pc18c_sercom6_pad2 */ 2385 #define PC18C_SERCOM6_PAD2 \ 2386 SAM_PINMUX(c, 18, c, periph) 2387 2388 /* pc18d_sercom0_pad2 */ 2389 #define PC18D_SERCOM0_PAD2 \ 2390 SAM_PINMUX(c, 18, d, periph) 2391 2392 /* pc18f_tcc0_wo2 */ 2393 #define PC18F_TCC0_WO2 \ 2394 SAM_PINMUX(c, 18, f, periph) 2395 2396 /* pc18g_pdec_qdi2 */ 2397 #define PC18G_PDEC_QDI2 \ 2398 SAM_PINMUX(c, 18, g, periph) 2399 2400 /* pc19_gpio */ 2401 #define PC19_GPIO \ 2402 SAM_PINMUX(c, 19, gpio, gpio) 2403 2404 /* pc19a_eic_extint3 */ 2405 #define PC19A_EIC_EXTINT3 \ 2406 SAM_PINMUX(c, 19, a, periph) 2407 2408 /* pc19c_sercom6_pad3 */ 2409 #define PC19C_SERCOM6_PAD3 \ 2410 SAM_PINMUX(c, 19, c, periph) 2411 2412 /* pc19d_sercom0_pad3 */ 2413 #define PC19D_SERCOM0_PAD3 \ 2414 SAM_PINMUX(c, 19, d, periph) 2415 2416 /* pc19f_tcc0_wo3 */ 2417 #define PC19F_TCC0_WO3 \ 2418 SAM_PINMUX(c, 19, f, periph) 2419 2420 /* pc20_gpio */ 2421 #define PC20_GPIO \ 2422 SAM_PINMUX(c, 20, gpio, gpio) 2423 2424 /* pc20a_eic_extint4 */ 2425 #define PC20A_EIC_EXTINT4 \ 2426 SAM_PINMUX(c, 20, a, periph) 2427 2428 /* pc20f_tcc0_wo4 */ 2429 #define PC20F_TCC0_WO4 \ 2430 SAM_PINMUX(c, 20, f, periph) 2431 2432 /* pc20i_sdhc1_cd */ 2433 #define PC20I_SDHC1_CD \ 2434 SAM_PINMUX(c, 20, i, periph) 2435 2436 /* pc20n_ccl_in9 */ 2437 #define PC20N_CCL_IN9 \ 2438 SAM_PINMUX(c, 20, n, periph) 2439 2440 /* pc21_gpio */ 2441 #define PC21_GPIO \ 2442 SAM_PINMUX(c, 21, gpio, gpio) 2443 2444 /* pc21a_eic_extint5 */ 2445 #define PC21A_EIC_EXTINT5 \ 2446 SAM_PINMUX(c, 21, a, periph) 2447 2448 /* pc21f_tcc0_wo5 */ 2449 #define PC21F_TCC0_WO5 \ 2450 SAM_PINMUX(c, 21, f, periph) 2451 2452 /* pc21i_sdhc1_wp */ 2453 #define PC21I_SDHC1_WP \ 2454 SAM_PINMUX(c, 21, i, periph) 2455 2456 /* pc21n_ccl_in10 */ 2457 #define PC21N_CCL_IN10 \ 2458 SAM_PINMUX(c, 21, n, periph) 2459 2460 /* pc22_gpio */ 2461 #define PC22_GPIO \ 2462 SAM_PINMUX(c, 22, gpio, gpio) 2463 2464 /* pc22a_eic_extint6 */ 2465 #define PC22A_EIC_EXTINT6 \ 2466 SAM_PINMUX(c, 22, a, periph) 2467 2468 /* pc22c_sercom1_pad0 */ 2469 #define PC22C_SERCOM1_PAD0 \ 2470 SAM_PINMUX(c, 22, c, periph) 2471 2472 /* pc22d_sercom3_pad1 */ 2473 #define PC22D_SERCOM3_PAD1 \ 2474 SAM_PINMUX(c, 22, d, periph) 2475 2476 /* pc22f_tcc0_wo6 */ 2477 #define PC22F_TCC0_WO6 \ 2478 SAM_PINMUX(c, 22, f, periph) 2479 2480 /* pc23_gpio */ 2481 #define PC23_GPIO \ 2482 SAM_PINMUX(c, 23, gpio, gpio) 2483 2484 /* pc23a_eic_extint7 */ 2485 #define PC23A_EIC_EXTINT7 \ 2486 SAM_PINMUX(c, 23, a, periph) 2487 2488 /* pc23c_sercom1_pad1 */ 2489 #define PC23C_SERCOM1_PAD1 \ 2490 SAM_PINMUX(c, 23, c, periph) 2491 2492 /* pc23d_sercom3_pad0 */ 2493 #define PC23D_SERCOM3_PAD0 \ 2494 SAM_PINMUX(c, 23, d, periph) 2495 2496 /* pc23f_tcc0_wo7 */ 2497 #define PC23F_TCC0_WO7 \ 2498 SAM_PINMUX(c, 23, f, periph) 2499 2500 /* pc24_gpio */ 2501 #define PC24_GPIO \ 2502 SAM_PINMUX(c, 24, gpio, gpio) 2503 2504 /* pc24a_eic_extint8 */ 2505 #define PC24A_EIC_EXTINT8 \ 2506 SAM_PINMUX(c, 24, a, periph) 2507 2508 /* pc24c_sercom0_pad2 */ 2509 #define PC24C_SERCOM0_PAD2 \ 2510 SAM_PINMUX(c, 24, c, periph) 2511 2512 /* pc24d_sercom2_pad2 */ 2513 #define PC24D_SERCOM2_PAD2 \ 2514 SAM_PINMUX(c, 24, d, periph) 2515 2516 /* pc24h_trace_data3 */ 2517 #define PC24H_TRACE_DATA3 \ 2518 SAM_PINMUX(c, 24, h, periph) 2519 2520 /* pc25_gpio */ 2521 #define PC25_GPIO \ 2522 SAM_PINMUX(c, 25, gpio, gpio) 2523 2524 /* pc25a_eic_extint9 */ 2525 #define PC25A_EIC_EXTINT9 \ 2526 SAM_PINMUX(c, 25, a, periph) 2527 2528 /* pc25c_sercom0_pad3 */ 2529 #define PC25C_SERCOM0_PAD3 \ 2530 SAM_PINMUX(c, 25, c, periph) 2531 2532 /* pc25d_sercom2_pad3 */ 2533 #define PC25D_SERCOM2_PAD3 \ 2534 SAM_PINMUX(c, 25, d, periph) 2535 2536 /* pc25h_trace_data2 */ 2537 #define PC25H_TRACE_DATA2 \ 2538 SAM_PINMUX(c, 25, h, periph) 2539 2540 /* pc26_gpio */ 2541 #define PC26_GPIO \ 2542 SAM_PINMUX(c, 26, gpio, gpio) 2543 2544 /* pc26a_eic_extint10 */ 2545 #define PC26A_EIC_EXTINT10 \ 2546 SAM_PINMUX(c, 26, a, periph) 2547 2548 /* pc26h_trace_data1 */ 2549 #define PC26H_TRACE_DATA1 \ 2550 SAM_PINMUX(c, 26, h, periph) 2551 2552 /* pc27_gpio */ 2553 #define PC27_GPIO \ 2554 SAM_PINMUX(c, 27, gpio, gpio) 2555 2556 /* pc27a_eic_extint11 */ 2557 #define PC27A_EIC_EXTINT11 \ 2558 SAM_PINMUX(c, 27, a, periph) 2559 2560 /* pc27c_sercom1_pad0 */ 2561 #define PC27C_SERCOM1_PAD0 \ 2562 SAM_PINMUX(c, 27, c, periph) 2563 2564 /* pc27h_trace_clk */ 2565 #define PC27H_TRACE_CLK \ 2566 SAM_PINMUX(c, 27, h, periph) 2567 2568 /* pc27m_swd_swo */ 2569 #define PC27M_SWD_SWO \ 2570 SAM_PINMUX(c, 27, m, periph) 2571 2572 /* pc27n_ccl_in4 */ 2573 #define PC27N_CCL_IN4 \ 2574 SAM_PINMUX(c, 27, n, periph) 2575 2576 /* pc28_gpio */ 2577 #define PC28_GPIO \ 2578 SAM_PINMUX(c, 28, gpio, gpio) 2579 2580 /* pc28a_eic_extint12 */ 2581 #define PC28A_EIC_EXTINT12 \ 2582 SAM_PINMUX(c, 28, a, periph) 2583 2584 /* pc28c_sercom1_pad1 */ 2585 #define PC28C_SERCOM1_PAD1 \ 2586 SAM_PINMUX(c, 28, c, periph) 2587 2588 /* pc28h_trace_data0 */ 2589 #define PC28H_TRACE_DATA0 \ 2590 SAM_PINMUX(c, 28, h, periph) 2591 2592 /* pc28n_ccl_in5 */ 2593 #define PC28N_CCL_IN5 \ 2594 SAM_PINMUX(c, 28, n, periph) 2595 2596 /* pc30_gpio */ 2597 #define PC30_GPIO \ 2598 SAM_PINMUX(c, 30, gpio, gpio) 2599 2600 /* pc30a_eic_extint14 */ 2601 #define PC30A_EIC_EXTINT14 \ 2602 SAM_PINMUX(c, 30, a, periph) 2603 2604 /* pc30b_adc1_ain12 */ 2605 #define PC30B_ADC1_AIN12 \ 2606 SAM_PINMUX(c, 30, b, periph) 2607 2608 /* pc31_gpio */ 2609 #define PC31_GPIO \ 2610 SAM_PINMUX(c, 31, gpio, gpio) 2611 2612 /* pc31a_eic_extint15 */ 2613 #define PC31A_EIC_EXTINT15 \ 2614 SAM_PINMUX(c, 31, a, periph) 2615 2616 /* pc31b_adc1_ain13 */ 2617 #define PC31B_ADC1_AIN13 \ 2618 SAM_PINMUX(c, 31, b, periph) 2619 2620 /* pd0_gpio */ 2621 #define PD0_GPIO \ 2622 SAM_PINMUX(d, 0, gpio, gpio) 2623 2624 /* pd0a_eic_extint0 */ 2625 #define PD0A_EIC_EXTINT0 \ 2626 SAM_PINMUX(d, 0, a, periph) 2627 2628 /* pd0b_adc1_ain14 */ 2629 #define PD0B_ADC1_AIN14 \ 2630 SAM_PINMUX(d, 0, b, periph) 2631 2632 /* pd1_gpio */ 2633 #define PD1_GPIO \ 2634 SAM_PINMUX(d, 1, gpio, gpio) 2635 2636 /* pd1a_eic_extint1 */ 2637 #define PD1A_EIC_EXTINT1 \ 2638 SAM_PINMUX(d, 1, a, periph) 2639 2640 /* pd1b_adc1_ain15 */ 2641 #define PD1B_ADC1_AIN15 \ 2642 SAM_PINMUX(d, 1, b, periph) 2643 2644 /* pd8_gpio */ 2645 #define PD8_GPIO \ 2646 SAM_PINMUX(d, 8, gpio, gpio) 2647 2648 /* pd8a_eic_extint3 */ 2649 #define PD8A_EIC_EXTINT3 \ 2650 SAM_PINMUX(d, 8, a, periph) 2651 2652 /* pd8c_sercom7_pad0 */ 2653 #define PD8C_SERCOM7_PAD0 \ 2654 SAM_PINMUX(d, 8, c, periph) 2655 2656 /* pd8d_sercom6_pad1 */ 2657 #define PD8D_SERCOM6_PAD1 \ 2658 SAM_PINMUX(d, 8, d, periph) 2659 2660 /* pd8f_tcc0_wo1 */ 2661 #define PD8F_TCC0_WO1 \ 2662 SAM_PINMUX(d, 8, f, periph) 2663 2664 /* pd9_gpio */ 2665 #define PD9_GPIO \ 2666 SAM_PINMUX(d, 9, gpio, gpio) 2667 2668 /* pd9a_eic_extint4 */ 2669 #define PD9A_EIC_EXTINT4 \ 2670 SAM_PINMUX(d, 9, a, periph) 2671 2672 /* pd9c_sercom7_pad1 */ 2673 #define PD9C_SERCOM7_PAD1 \ 2674 SAM_PINMUX(d, 9, c, periph) 2675 2676 /* pd9d_sercom6_pad0 */ 2677 #define PD9D_SERCOM6_PAD0 \ 2678 SAM_PINMUX(d, 9, d, periph) 2679 2680 /* pd9f_tcc0_wo2 */ 2681 #define PD9F_TCC0_WO2 \ 2682 SAM_PINMUX(d, 9, f, periph) 2683 2684 /* pd10_gpio */ 2685 #define PD10_GPIO \ 2686 SAM_PINMUX(d, 10, gpio, gpio) 2687 2688 /* pd10a_eic_extint5 */ 2689 #define PD10A_EIC_EXTINT5 \ 2690 SAM_PINMUX(d, 10, a, periph) 2691 2692 /* pd10c_sercom7_pad2 */ 2693 #define PD10C_SERCOM7_PAD2 \ 2694 SAM_PINMUX(d, 10, c, periph) 2695 2696 /* pd10d_sercom6_pad2 */ 2697 #define PD10D_SERCOM6_PAD2 \ 2698 SAM_PINMUX(d, 10, d, periph) 2699 2700 /* pd10f_tcc0_wo3 */ 2701 #define PD10F_TCC0_WO3 \ 2702 SAM_PINMUX(d, 10, f, periph) 2703 2704 /* pd11_gpio */ 2705 #define PD11_GPIO \ 2706 SAM_PINMUX(d, 11, gpio, gpio) 2707 2708 /* pd11a_eic_extint6 */ 2709 #define PD11A_EIC_EXTINT6 \ 2710 SAM_PINMUX(d, 11, a, periph) 2711 2712 /* pd11c_sercom7_pad3 */ 2713 #define PD11C_SERCOM7_PAD3 \ 2714 SAM_PINMUX(d, 11, c, periph) 2715 2716 /* pd11d_sercom6_pad3 */ 2717 #define PD11D_SERCOM6_PAD3 \ 2718 SAM_PINMUX(d, 11, d, periph) 2719 2720 /* pd11f_tcc0_wo4 */ 2721 #define PD11F_TCC0_WO4 \ 2722 SAM_PINMUX(d, 11, f, periph) 2723 2724 /* pd12_gpio */ 2725 #define PD12_GPIO \ 2726 SAM_PINMUX(d, 12, gpio, gpio) 2727 2728 /* pd12a_eic_extint7 */ 2729 #define PD12A_EIC_EXTINT7 \ 2730 SAM_PINMUX(d, 12, a, periph) 2731 2732 /* pd12f_tcc0_wo5 */ 2733 #define PD12F_TCC0_WO5 \ 2734 SAM_PINMUX(d, 12, f, periph) 2735 2736 /* pd20_gpio */ 2737 #define PD20_GPIO \ 2738 SAM_PINMUX(d, 20, gpio, gpio) 2739 2740 /* pd20a_eic_extint10 */ 2741 #define PD20A_EIC_EXTINT10 \ 2742 SAM_PINMUX(d, 20, a, periph) 2743 2744 /* pd20c_sercom1_pad2 */ 2745 #define PD20C_SERCOM1_PAD2 \ 2746 SAM_PINMUX(d, 20, c, periph) 2747 2748 /* pd20d_sercom3_pad2 */ 2749 #define PD20D_SERCOM3_PAD2 \ 2750 SAM_PINMUX(d, 20, d, periph) 2751 2752 /* pd20f_tcc1_wo0 */ 2753 #define PD20F_TCC1_WO0 \ 2754 SAM_PINMUX(d, 20, f, periph) 2755 2756 /* pd20i_sdhc1_cd */ 2757 #define PD20I_SDHC1_CD \ 2758 SAM_PINMUX(d, 20, i, periph) 2759 2760 /* pd21_gpio */ 2761 #define PD21_GPIO \ 2762 SAM_PINMUX(d, 21, gpio, gpio) 2763 2764 /* pd21a_eic_extint11 */ 2765 #define PD21A_EIC_EXTINT11 \ 2766 SAM_PINMUX(d, 21, a, periph) 2767 2768 /* pd21c_sercom1_pad3 */ 2769 #define PD21C_SERCOM1_PAD3 \ 2770 SAM_PINMUX(d, 21, c, periph) 2771 2772 /* pd21d_sercom3_pad3 */ 2773 #define PD21D_SERCOM3_PAD3 \ 2774 SAM_PINMUX(d, 21, d, periph) 2775 2776 /* pd21f_tcc1_wo1 */ 2777 #define PD21F_TCC1_WO1 \ 2778 SAM_PINMUX(d, 21, f, periph) 2779 2780 /* pd21i_sdhc1_wp */ 2781 #define PD21I_SDHC1_WP \ 2782 SAM_PINMUX(d, 21, i, periph) 2783
