1 /** 2 * \file 3 * 4 * \brief Instance description for SERCOM3 5 * 6 * Copyright (c) 2018 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAMR34_SERCOM3_INSTANCE_ 31 #define _SAMR34_SERCOM3_INSTANCE_ 32 33 /* ========== Register definition for SERCOM3 peripheral ========== */ 34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 35 #define REG_SERCOM3_I2CM_CTRLA (0x42000C00) /**< \brief (SERCOM3) I2CM Control A */ 36 #define REG_SERCOM3_I2CM_CTRLB (0x42000C04) /**< \brief (SERCOM3) I2CM Control B */ 37 #define REG_SERCOM3_I2CM_BAUD (0x42000C0C) /**< \brief (SERCOM3) I2CM Baud Rate */ 38 #define REG_SERCOM3_I2CM_INTENCLR (0x42000C14) /**< \brief (SERCOM3) I2CM Interrupt Enable Clear */ 39 #define REG_SERCOM3_I2CM_INTENSET (0x42000C16) /**< \brief (SERCOM3) I2CM Interrupt Enable Set */ 40 #define REG_SERCOM3_I2CM_INTFLAG (0x42000C18) /**< \brief (SERCOM3) I2CM Interrupt Flag Status and Clear */ 41 #define REG_SERCOM3_I2CM_STATUS (0x42000C1A) /**< \brief (SERCOM3) I2CM Status */ 42 #define REG_SERCOM3_I2CM_SYNCBUSY (0x42000C1C) /**< \brief (SERCOM3) I2CM Synchronization Busy */ 43 #define REG_SERCOM3_I2CM_ADDR (0x42000C24) /**< \brief (SERCOM3) I2CM Address */ 44 #define REG_SERCOM3_I2CM_DATA (0x42000C28) /**< \brief (SERCOM3) I2CM Data */ 45 #define REG_SERCOM3_I2CM_DBGCTRL (0x42000C30) /**< \brief (SERCOM3) I2CM Debug Control */ 46 #define REG_SERCOM3_I2CS_CTRLA (0x42000C00) /**< \brief (SERCOM3) I2CS Control A */ 47 #define REG_SERCOM3_I2CS_CTRLB (0x42000C04) /**< \brief (SERCOM3) I2CS Control B */ 48 #define REG_SERCOM3_I2CS_INTENCLR (0x42000C14) /**< \brief (SERCOM3) I2CS Interrupt Enable Clear */ 49 #define REG_SERCOM3_I2CS_INTENSET (0x42000C16) /**< \brief (SERCOM3) I2CS Interrupt Enable Set */ 50 #define REG_SERCOM3_I2CS_INTFLAG (0x42000C18) /**< \brief (SERCOM3) I2CS Interrupt Flag Status and Clear */ 51 #define REG_SERCOM3_I2CS_STATUS (0x42000C1A) /**< \brief (SERCOM3) I2CS Status */ 52 #define REG_SERCOM3_I2CS_SYNCBUSY (0x42000C1C) /**< \brief (SERCOM3) I2CS Synchronization Busy */ 53 #define REG_SERCOM3_I2CS_ADDR (0x42000C24) /**< \brief (SERCOM3) I2CS Address */ 54 #define REG_SERCOM3_I2CS_DATA (0x42000C28) /**< \brief (SERCOM3) I2CS Data */ 55 #define REG_SERCOM3_SPI_CTRLA (0x42000C00) /**< \brief (SERCOM3) SPI Control A */ 56 #define REG_SERCOM3_SPI_CTRLB (0x42000C04) /**< \brief (SERCOM3) SPI Control B */ 57 #define REG_SERCOM3_SPI_BAUD (0x42000C0C) /**< \brief (SERCOM3) SPI Baud Rate */ 58 #define REG_SERCOM3_SPI_INTENCLR (0x42000C14) /**< \brief (SERCOM3) SPI Interrupt Enable Clear */ 59 #define REG_SERCOM3_SPI_INTENSET (0x42000C16) /**< \brief (SERCOM3) SPI Interrupt Enable Set */ 60 #define REG_SERCOM3_SPI_INTFLAG (0x42000C18) /**< \brief (SERCOM3) SPI Interrupt Flag Status and Clear */ 61 #define REG_SERCOM3_SPI_STATUS (0x42000C1A) /**< \brief (SERCOM3) SPI Status */ 62 #define REG_SERCOM3_SPI_SYNCBUSY (0x42000C1C) /**< \brief (SERCOM3) SPI Synchronization Busy */ 63 #define REG_SERCOM3_SPI_ADDR (0x42000C24) /**< \brief (SERCOM3) SPI Address */ 64 #define REG_SERCOM3_SPI_DATA (0x42000C28) /**< \brief (SERCOM3) SPI Data */ 65 #define REG_SERCOM3_SPI_DBGCTRL (0x42000C30) /**< \brief (SERCOM3) SPI Debug Control */ 66 #define REG_SERCOM3_USART_CTRLA (0x42000C00) /**< \brief (SERCOM3) USART Control A */ 67 #define REG_SERCOM3_USART_CTRLB (0x42000C04) /**< \brief (SERCOM3) USART Control B */ 68 #define REG_SERCOM3_USART_BAUD (0x42000C0C) /**< \brief (SERCOM3) USART Baud Rate */ 69 #define REG_SERCOM3_USART_RXPL (0x42000C0E) /**< \brief (SERCOM3) USART Receive Pulse Length */ 70 #define REG_SERCOM3_USART_INTENCLR (0x42000C14) /**< \brief (SERCOM3) USART Interrupt Enable Clear */ 71 #define REG_SERCOM3_USART_INTENSET (0x42000C16) /**< \brief (SERCOM3) USART Interrupt Enable Set */ 72 #define REG_SERCOM3_USART_INTFLAG (0x42000C18) /**< \brief (SERCOM3) USART Interrupt Flag Status and Clear */ 73 #define REG_SERCOM3_USART_STATUS (0x42000C1A) /**< \brief (SERCOM3) USART Status */ 74 #define REG_SERCOM3_USART_SYNCBUSY (0x42000C1C) /**< \brief (SERCOM3) USART Synchronization Busy */ 75 #define REG_SERCOM3_USART_DATA (0x42000C28) /**< \brief (SERCOM3) USART Data */ 76 #define REG_SERCOM3_USART_DBGCTRL (0x42000C30) /**< \brief (SERCOM3) USART Debug Control */ 77 #else 78 #define REG_SERCOM3_I2CM_CTRLA (*(RwReg *)0x42000C00UL) /**< \brief (SERCOM3) I2CM Control A */ 79 #define REG_SERCOM3_I2CM_CTRLB (*(RwReg *)0x42000C04UL) /**< \brief (SERCOM3) I2CM Control B */ 80 #define REG_SERCOM3_I2CM_BAUD (*(RwReg *)0x42000C0CUL) /**< \brief (SERCOM3) I2CM Baud Rate */ 81 #define REG_SERCOM3_I2CM_INTENCLR (*(RwReg8 *)0x42000C14UL) /**< \brief (SERCOM3) I2CM Interrupt Enable Clear */ 82 #define REG_SERCOM3_I2CM_INTENSET (*(RwReg8 *)0x42000C16UL) /**< \brief (SERCOM3) I2CM Interrupt Enable Set */ 83 #define REG_SERCOM3_I2CM_INTFLAG (*(RwReg8 *)0x42000C18UL) /**< \brief (SERCOM3) I2CM Interrupt Flag Status and Clear */ 84 #define REG_SERCOM3_I2CM_STATUS (*(RwReg16*)0x42000C1AUL) /**< \brief (SERCOM3) I2CM Status */ 85 #define REG_SERCOM3_I2CM_SYNCBUSY (*(RoReg *)0x42000C1CUL) /**< \brief (SERCOM3) I2CM Synchronization Busy */ 86 #define REG_SERCOM3_I2CM_ADDR (*(RwReg *)0x42000C24UL) /**< \brief (SERCOM3) I2CM Address */ 87 #define REG_SERCOM3_I2CM_DATA (*(RwReg8 *)0x42000C28UL) /**< \brief (SERCOM3) I2CM Data */ 88 #define REG_SERCOM3_I2CM_DBGCTRL (*(RwReg8 *)0x42000C30UL) /**< \brief (SERCOM3) I2CM Debug Control */ 89 #define REG_SERCOM3_I2CS_CTRLA (*(RwReg *)0x42000C00UL) /**< \brief (SERCOM3) I2CS Control A */ 90 #define REG_SERCOM3_I2CS_CTRLB (*(RwReg *)0x42000C04UL) /**< \brief (SERCOM3) I2CS Control B */ 91 #define REG_SERCOM3_I2CS_INTENCLR (*(RwReg8 *)0x42000C14UL) /**< \brief (SERCOM3) I2CS Interrupt Enable Clear */ 92 #define REG_SERCOM3_I2CS_INTENSET (*(RwReg8 *)0x42000C16UL) /**< \brief (SERCOM3) I2CS Interrupt Enable Set */ 93 #define REG_SERCOM3_I2CS_INTFLAG (*(RwReg8 *)0x42000C18UL) /**< \brief (SERCOM3) I2CS Interrupt Flag Status and Clear */ 94 #define REG_SERCOM3_I2CS_STATUS (*(RwReg16*)0x42000C1AUL) /**< \brief (SERCOM3) I2CS Status */ 95 #define REG_SERCOM3_I2CS_SYNCBUSY (*(RoReg *)0x42000C1CUL) /**< \brief (SERCOM3) I2CS Synchronization Busy */ 96 #define REG_SERCOM3_I2CS_ADDR (*(RwReg *)0x42000C24UL) /**< \brief (SERCOM3) I2CS Address */ 97 #define REG_SERCOM3_I2CS_DATA (*(RwReg8 *)0x42000C28UL) /**< \brief (SERCOM3) I2CS Data */ 98 #define REG_SERCOM3_SPI_CTRLA (*(RwReg *)0x42000C00UL) /**< \brief (SERCOM3) SPI Control A */ 99 #define REG_SERCOM3_SPI_CTRLB (*(RwReg *)0x42000C04UL) /**< \brief (SERCOM3) SPI Control B */ 100 #define REG_SERCOM3_SPI_BAUD (*(RwReg8 *)0x42000C0CUL) /**< \brief (SERCOM3) SPI Baud Rate */ 101 #define REG_SERCOM3_SPI_INTENCLR (*(RwReg8 *)0x42000C14UL) /**< \brief (SERCOM3) SPI Interrupt Enable Clear */ 102 #define REG_SERCOM3_SPI_INTENSET (*(RwReg8 *)0x42000C16UL) /**< \brief (SERCOM3) SPI Interrupt Enable Set */ 103 #define REG_SERCOM3_SPI_INTFLAG (*(RwReg8 *)0x42000C18UL) /**< \brief (SERCOM3) SPI Interrupt Flag Status and Clear */ 104 #define REG_SERCOM3_SPI_STATUS (*(RwReg16*)0x42000C1AUL) /**< \brief (SERCOM3) SPI Status */ 105 #define REG_SERCOM3_SPI_SYNCBUSY (*(RoReg *)0x42000C1CUL) /**< \brief (SERCOM3) SPI Synchronization Busy */ 106 #define REG_SERCOM3_SPI_ADDR (*(RwReg *)0x42000C24UL) /**< \brief (SERCOM3) SPI Address */ 107 #define REG_SERCOM3_SPI_DATA (*(RwReg *)0x42000C28UL) /**< \brief (SERCOM3) SPI Data */ 108 #define REG_SERCOM3_SPI_DBGCTRL (*(RwReg8 *)0x42000C30UL) /**< \brief (SERCOM3) SPI Debug Control */ 109 #define REG_SERCOM3_USART_CTRLA (*(RwReg *)0x42000C00UL) /**< \brief (SERCOM3) USART Control A */ 110 #define REG_SERCOM3_USART_CTRLB (*(RwReg *)0x42000C04UL) /**< \brief (SERCOM3) USART Control B */ 111 #define REG_SERCOM3_USART_BAUD (*(RwReg16*)0x42000C0CUL) /**< \brief (SERCOM3) USART Baud Rate */ 112 #define REG_SERCOM3_USART_RXPL (*(RwReg8 *)0x42000C0EUL) /**< \brief (SERCOM3) USART Receive Pulse Length */ 113 #define REG_SERCOM3_USART_INTENCLR (*(RwReg8 *)0x42000C14UL) /**< \brief (SERCOM3) USART Interrupt Enable Clear */ 114 #define REG_SERCOM3_USART_INTENSET (*(RwReg8 *)0x42000C16UL) /**< \brief (SERCOM3) USART Interrupt Enable Set */ 115 #define REG_SERCOM3_USART_INTFLAG (*(RwReg8 *)0x42000C18UL) /**< \brief (SERCOM3) USART Interrupt Flag Status and Clear */ 116 #define REG_SERCOM3_USART_STATUS (*(RwReg16*)0x42000C1AUL) /**< \brief (SERCOM3) USART Status */ 117 #define REG_SERCOM3_USART_SYNCBUSY (*(RoReg *)0x42000C1CUL) /**< \brief (SERCOM3) USART Synchronization Busy */ 118 #define REG_SERCOM3_USART_DATA (*(RwReg16*)0x42000C28UL) /**< \brief (SERCOM3) USART Data */ 119 #define REG_SERCOM3_USART_DBGCTRL (*(RwReg8 *)0x42000C30UL) /**< \brief (SERCOM3) USART Debug Control */ 120 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 121 122 /* ========== Instance parameters for SERCOM3 peripheral ========== */ 123 #define SERCOM3_DMAC_ID_RX 7 // Index of DMA RX trigger 124 #define SERCOM3_DMAC_ID_TX 8 // Index of DMA TX trigger 125 #define SERCOM3_GCLK_ID_CORE 21 126 #define SERCOM3_GCLK_ID_SLOW 17 127 #define SERCOM3_INT_MSB 6 128 #define SERCOM3_PMSB 3 129 130 #endif /* _SAMR34_SERCOM3_INSTANCE_ */ 131
