1 /** 2 * \file 3 * 4 * \brief Peripheral I/O description for SAMR21G17A 5 * 6 * Copyright (c) 2017 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAMR21G17A_PIO_ 30 #define _SAMR21G17A_PIO_ 31 32 #define PIN_PA00 0 /**< \brief Pin Number for PA00 */ 33 #define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */ 34 #define PIN_PA01 1 /**< \brief Pin Number for PA01 */ 35 #define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */ 36 #define PIN_PA04 4 /**< \brief Pin Number for PA04 */ 37 #define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */ 38 #define PIN_PA05 5 /**< \brief Pin Number for PA05 */ 39 #define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */ 40 #define PIN_PA06 6 /**< \brief Pin Number for PA06 */ 41 #define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */ 42 #define PIN_PA07 7 /**< \brief Pin Number for PA07 */ 43 #define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */ 44 #define PIN_PA08 8 /**< \brief Pin Number for PA08 */ 45 #define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */ 46 #define PIN_PA09 9 /**< \brief Pin Number for PA09 */ 47 #define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */ 48 #define PIN_PA10 10 /**< \brief Pin Number for PA10 */ 49 #define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */ 50 #define PIN_PA11 11 /**< \brief Pin Number for PA11 */ 51 #define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */ 52 #define PIN_PA12 12 /**< \brief Pin Number for PA12 */ 53 #define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */ 54 #define PIN_PA13 13 /**< \brief Pin Number for PA13 */ 55 #define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */ 56 #define PIN_PA14 14 /**< \brief Pin Number for PA14 */ 57 #define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */ 58 #define PIN_PA15 15 /**< \brief Pin Number for PA15 */ 59 #define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */ 60 #define PIN_PA16 16 /**< \brief Pin Number for PA16 */ 61 #define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */ 62 #define PIN_PA17 17 /**< \brief Pin Number for PA17 */ 63 #define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */ 64 #define PIN_PA18 18 /**< \brief Pin Number for PA18 */ 65 #define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */ 66 #define PIN_PA19 19 /**< \brief Pin Number for PA19 */ 67 #define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */ 68 #define PIN_PA20 20 /**< \brief Pin Number for PA20 */ 69 #define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */ 70 #define PIN_PA22 22 /**< \brief Pin Number for PA22 */ 71 #define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */ 72 #define PIN_PA23 23 /**< \brief Pin Number for PA23 */ 73 #define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */ 74 #define PIN_PA24 24 /**< \brief Pin Number for PA24 */ 75 #define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */ 76 #define PIN_PA25 25 /**< \brief Pin Number for PA25 */ 77 #define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */ 78 #define PIN_PA27 27 /**< \brief Pin Number for PA27 */ 79 #define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */ 80 #define PIN_PA28 28 /**< \brief Pin Number for PA28 */ 81 #define PORT_PA28 (_UL_(1) << 28) /**< \brief PORT Mask for PA28 */ 82 #define PIN_PA30 30 /**< \brief Pin Number for PA30 */ 83 #define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */ 84 #define PIN_PA31 31 /**< \brief Pin Number for PA31 */ 85 #define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */ 86 #define PIN_PB00 32 /**< \brief Pin Number for PB00 */ 87 #define PORT_PB00 (_UL_(1) << 0) /**< \brief PORT Mask for PB00 */ 88 #define PIN_PB02 34 /**< \brief Pin Number for PB02 */ 89 #define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */ 90 #define PIN_PB03 35 /**< \brief Pin Number for PB03 */ 91 #define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */ 92 #define PIN_PB08 40 /**< \brief Pin Number for PB08 */ 93 #define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */ 94 #define PIN_PB09 41 /**< \brief Pin Number for PB09 */ 95 #define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */ 96 #define PIN_PB14 46 /**< \brief Pin Number for PB14 */ 97 #define PORT_PB14 (_UL_(1) << 14) /**< \brief PORT Mask for PB14 */ 98 #define PIN_PB15 47 /**< \brief Pin Number for PB15 */ 99 #define PORT_PB15 (_UL_(1) << 15) /**< \brief PORT Mask for PB15 */ 100 #define PIN_PB16 48 /**< \brief Pin Number for PB16 */ 101 #define PORT_PB16 (_UL_(1) << 16) /**< \brief PORT Mask for PB16 */ 102 #define PIN_PB17 49 /**< \brief Pin Number for PB17 */ 103 #define PORT_PB17 (_UL_(1) << 17) /**< \brief PORT Mask for PB17 */ 104 #define PIN_PB22 54 /**< \brief Pin Number for PB22 */ 105 #define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */ 106 #define PIN_PB23 55 /**< \brief Pin Number for PB23 */ 107 #define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */ 108 #define PIN_PB30 62 /**< \brief Pin Number for PB30 */ 109 #define PORT_PB30 (_UL_(1) << 30) /**< \brief PORT Mask for PB30 */ 110 #define PIN_PB31 63 /**< \brief Pin Number for PB31 */ 111 #define PORT_PB31 (_UL_(1) << 31) /**< \brief PORT Mask for PB31 */ 112 #define PIN_PC16 80 /**< \brief Pin Number for PC16 */ 113 #define PORT_PC16 (_UL_(1) << 16) /**< \brief PORT Mask for PC16 */ 114 #define PIN_PC18 82 /**< \brief Pin Number for PC18 */ 115 #define PORT_PC18 (_UL_(1) << 18) /**< \brief PORT Mask for PC18 */ 116 #define PIN_PC19 83 /**< \brief Pin Number for PC19 */ 117 #define PORT_PC19 (_UL_(1) << 19) /**< \brief PORT Mask for PC19 */ 118 /* ========== PORT definition for GCLK peripheral ========== */ 119 #define PIN_PB14H_GCLK_IO0 _L_(46) /**< \brief GCLK signal: IO0 on PB14 mux H */ 120 #define MUX_PB14H_GCLK_IO0 _L_(7) 121 #define PINMUX_PB14H_GCLK_IO0 ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0) 122 #define PORT_PB14H_GCLK_IO0 (_UL_(1) << 14) 123 #define PIN_PB22H_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux H */ 124 #define MUX_PB22H_GCLK_IO0 _L_(7) 125 #define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0) 126 #define PORT_PB22H_GCLK_IO0 (_UL_(1) << 22) 127 #define PIN_PA14H_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux H */ 128 #define MUX_PA14H_GCLK_IO0 _L_(7) 129 #define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) 130 #define PORT_PA14H_GCLK_IO0 (_UL_(1) << 14) 131 #define PIN_PA27H_GCLK_IO0 _L_(27) /**< \brief GCLK signal: IO0 on PA27 mux H */ 132 #define MUX_PA27H_GCLK_IO0 _L_(7) 133 #define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) 134 #define PORT_PA27H_GCLK_IO0 (_UL_(1) << 27) 135 #define PIN_PA28H_GCLK_IO0 _L_(28) /**< \brief GCLK signal: IO0 on PA28 mux H */ 136 #define MUX_PA28H_GCLK_IO0 _L_(7) 137 #define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0) 138 #define PORT_PA28H_GCLK_IO0 (_UL_(1) << 28) 139 #define PIN_PA30H_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux H */ 140 #define MUX_PA30H_GCLK_IO0 _L_(7) 141 #define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) 142 #define PORT_PA30H_GCLK_IO0 (_UL_(1) << 30) 143 #define PIN_PB15H_GCLK_IO1 _L_(47) /**< \brief GCLK signal: IO1 on PB15 mux H */ 144 #define MUX_PB15H_GCLK_IO1 _L_(7) 145 #define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1) 146 #define PORT_PB15H_GCLK_IO1 (_UL_(1) << 15) 147 #define PIN_PB23H_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux H */ 148 #define MUX_PB23H_GCLK_IO1 _L_(7) 149 #define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1) 150 #define PORT_PB23H_GCLK_IO1 (_UL_(1) << 23) 151 #define PIN_PA15H_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux H */ 152 #define MUX_PA15H_GCLK_IO1 _L_(7) 153 #define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) 154 #define PORT_PA15H_GCLK_IO1 (_UL_(1) << 15) 155 #define PIN_PC16F_GCLK_IO1 _L_(80) /**< \brief GCLK signal: IO1 on PC16 mux F */ 156 #define MUX_PC16F_GCLK_IO1 _L_(5) 157 #define PINMUX_PC16F_GCLK_IO1 ((PIN_PC16F_GCLK_IO1 << 16) | MUX_PC16F_GCLK_IO1) 158 #define PORT_PC16F_GCLK_IO1 (_UL_(1) << 16) 159 #define PIN_PB16H_GCLK_IO2 _L_(48) /**< \brief GCLK signal: IO2 on PB16 mux H */ 160 #define MUX_PB16H_GCLK_IO2 _L_(7) 161 #define PINMUX_PB16H_GCLK_IO2 ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2) 162 #define PORT_PB16H_GCLK_IO2 (_UL_(1) << 16) 163 #define PIN_PA16H_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux H */ 164 #define MUX_PA16H_GCLK_IO2 _L_(7) 165 #define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) 166 #define PORT_PA16H_GCLK_IO2 (_UL_(1) << 16) 167 #define PIN_PA17H_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux H */ 168 #define MUX_PA17H_GCLK_IO3 _L_(7) 169 #define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) 170 #define PORT_PA17H_GCLK_IO3 (_UL_(1) << 17) 171 #define PIN_PB17H_GCLK_IO3 _L_(49) /**< \brief GCLK signal: IO3 on PB17 mux H */ 172 #define MUX_PB17H_GCLK_IO3 _L_(7) 173 #define PINMUX_PB17H_GCLK_IO3 ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3) 174 #define PORT_PB17H_GCLK_IO3 (_UL_(1) << 17) 175 #define PIN_PA10H_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux H */ 176 #define MUX_PA10H_GCLK_IO4 _L_(7) 177 #define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) 178 #define PORT_PA10H_GCLK_IO4 (_UL_(1) << 10) 179 #define PIN_PA20H_GCLK_IO4 _L_(20) /**< \brief GCLK signal: IO4 on PA20 mux H */ 180 #define MUX_PA20H_GCLK_IO4 _L_(7) 181 #define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4) 182 #define PORT_PA20H_GCLK_IO4 (_UL_(1) << 20) 183 #define PIN_PA11H_GCLK_IO5 _L_(11) /**< \brief GCLK signal: IO5 on PA11 mux H */ 184 #define MUX_PA11H_GCLK_IO5 _L_(7) 185 #define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) 186 #define PORT_PA11H_GCLK_IO5 (_UL_(1) << 11) 187 #define PIN_PA22H_GCLK_IO6 _L_(22) /**< \brief GCLK signal: IO6 on PA22 mux H */ 188 #define MUX_PA22H_GCLK_IO6 _L_(7) 189 #define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6) 190 #define PORT_PA22H_GCLK_IO6 (_UL_(1) << 22) 191 #define PIN_PA23H_GCLK_IO7 _L_(23) /**< \brief GCLK signal: IO7 on PA23 mux H */ 192 #define MUX_PA23H_GCLK_IO7 _L_(7) 193 #define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7) 194 #define PORT_PA23H_GCLK_IO7 (_UL_(1) << 23) 195 /* ========== PORT definition for EIC peripheral ========== */ 196 #define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */ 197 #define MUX_PA16A_EIC_EXTINT0 _L_(0) 198 #define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) 199 #define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16) 200 #define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ 201 #define PIN_PB00A_EIC_EXTINT0 _L_(32) /**< \brief EIC signal: EXTINT0 on PB00 mux A */ 202 #define MUX_PB00A_EIC_EXTINT0 _L_(0) 203 #define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) 204 #define PORT_PB00A_EIC_EXTINT0 (_UL_(1) << 0) 205 #define PIN_PB00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB00 External Interrupt Line */ 206 #define PIN_PB16A_EIC_EXTINT0 _L_(48) /**< \brief EIC signal: EXTINT0 on PB16 mux A */ 207 #define MUX_PB16A_EIC_EXTINT0 _L_(0) 208 #define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) 209 #define PORT_PB16A_EIC_EXTINT0 (_UL_(1) << 16) 210 #define PIN_PB16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB16 External Interrupt Line */ 211 #define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */ 212 #define MUX_PA00A_EIC_EXTINT0 _L_(0) 213 #define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) 214 #define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0) 215 #define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */ 216 #define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */ 217 #define MUX_PA17A_EIC_EXTINT1 _L_(0) 218 #define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) 219 #define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17) 220 #define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ 221 #define PIN_PB17A_EIC_EXTINT1 _L_(49) /**< \brief EIC signal: EXTINT1 on PB17 mux A */ 222 #define MUX_PB17A_EIC_EXTINT1 _L_(0) 223 #define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) 224 #define PORT_PB17A_EIC_EXTINT1 (_UL_(1) << 17) 225 #define PIN_PB17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB17 External Interrupt Line */ 226 #define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */ 227 #define MUX_PA01A_EIC_EXTINT1 _L_(0) 228 #define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) 229 #define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1) 230 #define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */ 231 #define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */ 232 #define MUX_PA18A_EIC_EXTINT2 _L_(0) 233 #define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) 234 #define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18) 235 #define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ 236 #define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */ 237 #define MUX_PB02A_EIC_EXTINT2 _L_(0) 238 #define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) 239 #define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2) 240 #define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */ 241 #define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */ 242 #define MUX_PA19A_EIC_EXTINT3 _L_(0) 243 #define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) 244 #define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19) 245 #define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ 246 #define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */ 247 #define MUX_PB03A_EIC_EXTINT3 _L_(0) 248 #define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) 249 #define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3) 250 #define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */ 251 #define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */ 252 #define MUX_PA04A_EIC_EXTINT4 _L_(0) 253 #define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) 254 #define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4) 255 #define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */ 256 #define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */ 257 #define MUX_PA20A_EIC_EXTINT4 _L_(0) 258 #define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) 259 #define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20) 260 #define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */ 261 #define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */ 262 #define MUX_PA05A_EIC_EXTINT5 _L_(0) 263 #define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) 264 #define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5) 265 #define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */ 266 #define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */ 267 #define MUX_PA06A_EIC_EXTINT6 _L_(0) 268 #define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) 269 #define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6) 270 #define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ 271 #define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */ 272 #define MUX_PA22A_EIC_EXTINT6 _L_(0) 273 #define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) 274 #define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22) 275 #define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */ 276 #define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */ 277 #define MUX_PB22A_EIC_EXTINT6 _L_(0) 278 #define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) 279 #define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22) 280 #define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */ 281 #define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */ 282 #define MUX_PA07A_EIC_EXTINT7 _L_(0) 283 #define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) 284 #define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7) 285 #define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ 286 #define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */ 287 #define MUX_PA23A_EIC_EXTINT7 _L_(0) 288 #define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) 289 #define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23) 290 #define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */ 291 #define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */ 292 #define MUX_PB23A_EIC_EXTINT7 _L_(0) 293 #define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) 294 #define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23) 295 #define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */ 296 #define PIN_PA28A_EIC_EXTINT8 _L_(28) /**< \brief EIC signal: EXTINT8 on PA28 mux A */ 297 #define MUX_PA28A_EIC_EXTINT8 _L_(0) 298 #define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8) 299 #define PORT_PA28A_EIC_EXTINT8 (_UL_(1) << 28) 300 #define PIN_PA28A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PA28 External Interrupt Line */ 301 #define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */ 302 #define MUX_PB08A_EIC_EXTINT8 _L_(0) 303 #define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) 304 #define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8) 305 #define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */ 306 #define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */ 307 #define MUX_PA09A_EIC_EXTINT9 _L_(0) 308 #define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) 309 #define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9) 310 #define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */ 311 #define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */ 312 #define MUX_PB09A_EIC_EXTINT9 _L_(0) 313 #define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) 314 #define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9) 315 #define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */ 316 #define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */ 317 #define MUX_PA10A_EIC_EXTINT10 _L_(0) 318 #define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) 319 #define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10) 320 #define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */ 321 #define PIN_PA30A_EIC_EXTINT10 _L_(30) /**< \brief EIC signal: EXTINT10 on PA30 mux A */ 322 #define MUX_PA30A_EIC_EXTINT10 _L_(0) 323 #define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) 324 #define PORT_PA30A_EIC_EXTINT10 (_UL_(1) << 30) 325 #define PIN_PA30A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */ 326 #define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */ 327 #define MUX_PA11A_EIC_EXTINT11 _L_(0) 328 #define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) 329 #define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11) 330 #define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */ 331 #define PIN_PA31A_EIC_EXTINT11 _L_(31) /**< \brief EIC signal: EXTINT11 on PA31 mux A */ 332 #define MUX_PA31A_EIC_EXTINT11 _L_(0) 333 #define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) 334 #define PORT_PA31A_EIC_EXTINT11 (_UL_(1) << 31) 335 #define PIN_PA31A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */ 336 #define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */ 337 #define MUX_PA12A_EIC_EXTINT12 _L_(0) 338 #define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) 339 #define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12) 340 #define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */ 341 #define PIN_PA24A_EIC_EXTINT12 _L_(24) /**< \brief EIC signal: EXTINT12 on PA24 mux A */ 342 #define MUX_PA24A_EIC_EXTINT12 _L_(0) 343 #define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) 344 #define PORT_PA24A_EIC_EXTINT12 (_UL_(1) << 24) 345 #define PIN_PA24A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */ 346 #define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */ 347 #define MUX_PA13A_EIC_EXTINT13 _L_(0) 348 #define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) 349 #define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13) 350 #define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */ 351 #define PIN_PA25A_EIC_EXTINT13 _L_(25) /**< \brief EIC signal: EXTINT13 on PA25 mux A */ 352 #define MUX_PA25A_EIC_EXTINT13 _L_(0) 353 #define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) 354 #define PORT_PA25A_EIC_EXTINT13 (_UL_(1) << 25) 355 #define PIN_PA25A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */ 356 #define PIN_PB14A_EIC_EXTINT14 _L_(46) /**< \brief EIC signal: EXTINT14 on PB14 mux A */ 357 #define MUX_PB14A_EIC_EXTINT14 _L_(0) 358 #define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) 359 #define PORT_PB14A_EIC_EXTINT14 (_UL_(1) << 14) 360 #define PIN_PB14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB14 External Interrupt Line */ 361 #define PIN_PB30A_EIC_EXTINT14 _L_(62) /**< \brief EIC signal: EXTINT14 on PB30 mux A */ 362 #define MUX_PB30A_EIC_EXTINT14 _L_(0) 363 #define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) 364 #define PORT_PB30A_EIC_EXTINT14 (_UL_(1) << 30) 365 #define PIN_PB30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB30 External Interrupt Line */ 366 #define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */ 367 #define MUX_PA14A_EIC_EXTINT14 _L_(0) 368 #define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) 369 #define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14) 370 #define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */ 371 #define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */ 372 #define MUX_PA15A_EIC_EXTINT15 _L_(0) 373 #define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) 374 #define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15) 375 #define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */ 376 #define PIN_PA27A_EIC_EXTINT15 _L_(27) /**< \brief EIC signal: EXTINT15 on PA27 mux A */ 377 #define MUX_PA27A_EIC_EXTINT15 _L_(0) 378 #define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) 379 #define PORT_PA27A_EIC_EXTINT15 (_UL_(1) << 27) 380 #define PIN_PA27A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */ 381 #define PIN_PB15A_EIC_EXTINT15 _L_(47) /**< \brief EIC signal: EXTINT15 on PB15 mux A */ 382 #define MUX_PB15A_EIC_EXTINT15 _L_(0) 383 #define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) 384 #define PORT_PB15A_EIC_EXTINT15 (_UL_(1) << 15) 385 #define PIN_PB15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB15 External Interrupt Line */ 386 #define PIN_PB31A_EIC_EXTINT15 _L_(63) /**< \brief EIC signal: EXTINT15 on PB31 mux A */ 387 #define MUX_PB31A_EIC_EXTINT15 _L_(0) 388 #define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) 389 #define PORT_PB31A_EIC_EXTINT15 (_UL_(1) << 31) 390 #define PIN_PB31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB31 External Interrupt Line */ 391 #define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */ 392 #define MUX_PA08A_EIC_NMI _L_(0) 393 #define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) 394 #define PORT_PA08A_EIC_NMI (_UL_(1) << 8) 395 /* ========== PORT definition for USB peripheral ========== */ 396 #define PIN_PA24G_USB_DM _L_(24) /**< \brief USB signal: DM on PA24 mux G */ 397 #define MUX_PA24G_USB_DM _L_(6) 398 #define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) 399 #define PORT_PA24G_USB_DM (_UL_(1) << 24) 400 #define PIN_PA25G_USB_DP _L_(25) /**< \brief USB signal: DP on PA25 mux G */ 401 #define MUX_PA25G_USB_DP _L_(6) 402 #define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) 403 #define PORT_PA25G_USB_DP (_UL_(1) << 25) 404 #define PIN_PA23G_USB_SOF_1KHZ _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ 405 #define MUX_PA23G_USB_SOF_1KHZ _L_(6) 406 #define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) 407 #define PORT_PA23G_USB_SOF_1KHZ (_UL_(1) << 23) 408 /* ========== PORT definition for SERCOM0 peripheral ========== */ 409 #define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ 410 #define MUX_PA04D_SERCOM0_PAD0 _L_(3) 411 #define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) 412 #define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4) 413 #define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ 414 #define MUX_PA08C_SERCOM0_PAD0 _L_(2) 415 #define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) 416 #define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8) 417 #define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ 418 #define MUX_PA05D_SERCOM0_PAD1 _L_(3) 419 #define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) 420 #define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5) 421 #define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ 422 #define MUX_PA09C_SERCOM0_PAD1 _L_(2) 423 #define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) 424 #define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9) 425 #define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ 426 #define MUX_PA06D_SERCOM0_PAD2 _L_(3) 427 #define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) 428 #define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6) 429 #define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ 430 #define MUX_PA10C_SERCOM0_PAD2 _L_(2) 431 #define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) 432 #define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10) 433 #define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ 434 #define MUX_PA07D_SERCOM0_PAD3 _L_(3) 435 #define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) 436 #define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7) 437 #define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ 438 #define MUX_PA11C_SERCOM0_PAD3 _L_(2) 439 #define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) 440 #define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11) 441 /* ========== PORT definition for SERCOM1 peripheral ========== */ 442 #define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ 443 #define MUX_PA16C_SERCOM1_PAD0 _L_(2) 444 #define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) 445 #define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16) 446 #define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ 447 #define MUX_PA00D_SERCOM1_PAD0 _L_(3) 448 #define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) 449 #define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0) 450 #define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ 451 #define MUX_PA17C_SERCOM1_PAD1 _L_(2) 452 #define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) 453 #define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17) 454 #define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ 455 #define MUX_PA01D_SERCOM1_PAD1 _L_(3) 456 #define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) 457 #define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1) 458 #define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ 459 #define MUX_PA30D_SERCOM1_PAD2 _L_(3) 460 #define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) 461 #define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30) 462 #define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ 463 #define MUX_PA18C_SERCOM1_PAD2 _L_(2) 464 #define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) 465 #define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18) 466 #define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ 467 #define MUX_PA31D_SERCOM1_PAD3 _L_(3) 468 #define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) 469 #define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31) 470 #define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ 471 #define MUX_PA19C_SERCOM1_PAD3 _L_(2) 472 #define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) 473 #define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19) 474 /* ========== PORT definition for SERCOM2 peripheral ========== */ 475 #define PIN_PA08D_SERCOM2_PAD0 _L_(8) /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ 476 #define MUX_PA08D_SERCOM2_PAD0 _L_(3) 477 #define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) 478 #define PORT_PA08D_SERCOM2_PAD0 (_UL_(1) << 8) 479 #define PIN_PA12C_SERCOM2_PAD0 _L_(12) /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ 480 #define MUX_PA12C_SERCOM2_PAD0 _L_(2) 481 #define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) 482 #define PORT_PA12C_SERCOM2_PAD0 (_UL_(1) << 12) 483 #define PIN_PA09D_SERCOM2_PAD1 _L_(9) /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ 484 #define MUX_PA09D_SERCOM2_PAD1 _L_(3) 485 #define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) 486 #define PORT_PA09D_SERCOM2_PAD1 (_UL_(1) << 9) 487 #define PIN_PA13C_SERCOM2_PAD1 _L_(13) /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ 488 #define MUX_PA13C_SERCOM2_PAD1 _L_(2) 489 #define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) 490 #define PORT_PA13C_SERCOM2_PAD1 (_UL_(1) << 13) 491 #define PIN_PA10D_SERCOM2_PAD2 _L_(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ 492 #define MUX_PA10D_SERCOM2_PAD2 _L_(3) 493 #define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) 494 #define PORT_PA10D_SERCOM2_PAD2 (_UL_(1) << 10) 495 #define PIN_PA14C_SERCOM2_PAD2 _L_(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ 496 #define MUX_PA14C_SERCOM2_PAD2 _L_(2) 497 #define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) 498 #define PORT_PA14C_SERCOM2_PAD2 (_UL_(1) << 14) 499 #define PIN_PA11D_SERCOM2_PAD3 _L_(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ 500 #define MUX_PA11D_SERCOM2_PAD3 _L_(3) 501 #define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) 502 #define PORT_PA11D_SERCOM2_PAD3 (_UL_(1) << 11) 503 #define PIN_PA15C_SERCOM2_PAD3 _L_(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ 504 #define MUX_PA15C_SERCOM2_PAD3 _L_(2) 505 #define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) 506 #define PORT_PA15C_SERCOM2_PAD3 (_UL_(1) << 15) 507 /* ========== PORT definition for SERCOM3 peripheral ========== */ 508 #define PIN_PA16D_SERCOM3_PAD0 _L_(16) /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ 509 #define MUX_PA16D_SERCOM3_PAD0 _L_(3) 510 #define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) 511 #define PORT_PA16D_SERCOM3_PAD0 (_UL_(1) << 16) 512 #define PIN_PA22C_SERCOM3_PAD0 _L_(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ 513 #define MUX_PA22C_SERCOM3_PAD0 _L_(2) 514 #define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) 515 #define PORT_PA22C_SERCOM3_PAD0 (_UL_(1) << 22) 516 #define PIN_PA27F_SERCOM3_PAD0 _L_(27) /**< \brief SERCOM3 signal: PAD0 on PA27 mux F */ 517 #define MUX_PA27F_SERCOM3_PAD0 _L_(5) 518 #define PINMUX_PA27F_SERCOM3_PAD0 ((PIN_PA27F_SERCOM3_PAD0 << 16) | MUX_PA27F_SERCOM3_PAD0) 519 #define PORT_PA27F_SERCOM3_PAD0 (_UL_(1) << 27) 520 #define PIN_PA17D_SERCOM3_PAD1 _L_(17) /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ 521 #define MUX_PA17D_SERCOM3_PAD1 _L_(3) 522 #define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) 523 #define PORT_PA17D_SERCOM3_PAD1 (_UL_(1) << 17) 524 #define PIN_PA23C_SERCOM3_PAD1 _L_(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ 525 #define MUX_PA23C_SERCOM3_PAD1 _L_(2) 526 #define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) 527 #define PORT_PA23C_SERCOM3_PAD1 (_UL_(1) << 23) 528 #define PIN_PA28F_SERCOM3_PAD1 _L_(28) /**< \brief SERCOM3 signal: PAD1 on PA28 mux F */ 529 #define MUX_PA28F_SERCOM3_PAD1 _L_(5) 530 #define PINMUX_PA28F_SERCOM3_PAD1 ((PIN_PA28F_SERCOM3_PAD1 << 16) | MUX_PA28F_SERCOM3_PAD1) 531 #define PORT_PA28F_SERCOM3_PAD1 (_UL_(1) << 28) 532 #define PIN_PA18D_SERCOM3_PAD2 _L_(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ 533 #define MUX_PA18D_SERCOM3_PAD2 _L_(3) 534 #define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) 535 #define PORT_PA18D_SERCOM3_PAD2 (_UL_(1) << 18) 536 #define PIN_PA20D_SERCOM3_PAD2 _L_(20) /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ 537 #define MUX_PA20D_SERCOM3_PAD2 _L_(3) 538 #define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) 539 #define PORT_PA20D_SERCOM3_PAD2 (_UL_(1) << 20) 540 #define PIN_PA24C_SERCOM3_PAD2 _L_(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ 541 #define MUX_PA24C_SERCOM3_PAD2 _L_(2) 542 #define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) 543 #define PORT_PA24C_SERCOM3_PAD2 (_UL_(1) << 24) 544 #define PIN_PA19D_SERCOM3_PAD3 _L_(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ 545 #define MUX_PA19D_SERCOM3_PAD3 _L_(3) 546 #define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) 547 #define PORT_PA19D_SERCOM3_PAD3 (_UL_(1) << 19) 548 #define PIN_PA25C_SERCOM3_PAD3 _L_(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ 549 #define MUX_PA25C_SERCOM3_PAD3 _L_(2) 550 #define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) 551 #define PORT_PA25C_SERCOM3_PAD3 (_UL_(1) << 25) 552 /* ========== PORT definition for SERCOM4 peripheral ========== */ 553 #define PIN_PA12D_SERCOM4_PAD0 _L_(12) /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */ 554 #define MUX_PA12D_SERCOM4_PAD0 _L_(3) 555 #define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0) 556 #define PORT_PA12D_SERCOM4_PAD0 (_UL_(1) << 12) 557 #define PIN_PB08D_SERCOM4_PAD0 _L_(40) /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ 558 #define MUX_PB08D_SERCOM4_PAD0 _L_(3) 559 #define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) 560 #define PORT_PB08D_SERCOM4_PAD0 (_UL_(1) << 8) 561 #define PIN_PC19F_SERCOM4_PAD0 _L_(83) /**< \brief SERCOM4 signal: PAD0 on PC19 mux F */ 562 #define MUX_PC19F_SERCOM4_PAD0 _L_(5) 563 #define PINMUX_PC19F_SERCOM4_PAD0 ((PIN_PC19F_SERCOM4_PAD0 << 16) | MUX_PC19F_SERCOM4_PAD0) 564 #define PORT_PC19F_SERCOM4_PAD0 (_UL_(1) << 19) 565 #define PIN_PA13D_SERCOM4_PAD1 _L_(13) /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */ 566 #define MUX_PA13D_SERCOM4_PAD1 _L_(3) 567 #define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1) 568 #define PORT_PA13D_SERCOM4_PAD1 (_UL_(1) << 13) 569 #define PIN_PB09D_SERCOM4_PAD1 _L_(41) /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ 570 #define MUX_PB09D_SERCOM4_PAD1 _L_(3) 571 #define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) 572 #define PORT_PB09D_SERCOM4_PAD1 (_UL_(1) << 9) 573 #define PIN_PB31F_SERCOM4_PAD1 _L_(63) /**< \brief SERCOM4 signal: PAD1 on PB31 mux F */ 574 #define MUX_PB31F_SERCOM4_PAD1 _L_(5) 575 #define PINMUX_PB31F_SERCOM4_PAD1 ((PIN_PB31F_SERCOM4_PAD1 << 16) | MUX_PB31F_SERCOM4_PAD1) 576 #define PORT_PB31F_SERCOM4_PAD1 (_UL_(1) << 31) 577 #define PIN_PA14D_SERCOM4_PAD2 _L_(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ 578 #define MUX_PA14D_SERCOM4_PAD2 _L_(3) 579 #define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) 580 #define PORT_PA14D_SERCOM4_PAD2 (_UL_(1) << 14) 581 #define PIN_PB14C_SERCOM4_PAD2 _L_(46) /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */ 582 #define MUX_PB14C_SERCOM4_PAD2 _L_(2) 583 #define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) 584 #define PORT_PB14C_SERCOM4_PAD2 (_UL_(1) << 14) 585 #define PIN_PB30F_SERCOM4_PAD2 _L_(62) /**< \brief SERCOM4 signal: PAD2 on PB30 mux F */ 586 #define MUX_PB30F_SERCOM4_PAD2 _L_(5) 587 #define PINMUX_PB30F_SERCOM4_PAD2 ((PIN_PB30F_SERCOM4_PAD2 << 16) | MUX_PB30F_SERCOM4_PAD2) 588 #define PORT_PB30F_SERCOM4_PAD2 (_UL_(1) << 30) 589 #define PIN_PA15D_SERCOM4_PAD3 _L_(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ 590 #define MUX_PA15D_SERCOM4_PAD3 _L_(3) 591 #define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) 592 #define PORT_PA15D_SERCOM4_PAD3 (_UL_(1) << 15) 593 #define PIN_PB15C_SERCOM4_PAD3 _L_(47) /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */ 594 #define MUX_PB15C_SERCOM4_PAD3 _L_(2) 595 #define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) 596 #define PORT_PB15C_SERCOM4_PAD3 (_UL_(1) << 15) 597 #define PIN_PC18F_SERCOM4_PAD3 _L_(82) /**< \brief SERCOM4 signal: PAD3 on PC18 mux F */ 598 #define MUX_PC18F_SERCOM4_PAD3 _L_(5) 599 #define PINMUX_PC18F_SERCOM4_PAD3 ((PIN_PC18F_SERCOM4_PAD3 << 16) | MUX_PC18F_SERCOM4_PAD3) 600 #define PORT_PC18F_SERCOM4_PAD3 (_UL_(1) << 18) 601 /* ========== PORT definition for SERCOM5 peripheral ========== */ 602 #define PIN_PB16C_SERCOM5_PAD0 _L_(48) /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ 603 #define MUX_PB16C_SERCOM5_PAD0 _L_(2) 604 #define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) 605 #define PORT_PB16C_SERCOM5_PAD0 (_UL_(1) << 16) 606 #define PIN_PA22D_SERCOM5_PAD0 _L_(22) /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */ 607 #define MUX_PA22D_SERCOM5_PAD0 _L_(3) 608 #define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0) 609 #define PORT_PA22D_SERCOM5_PAD0 (_UL_(1) << 22) 610 #define PIN_PB02D_SERCOM5_PAD0 _L_(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ 611 #define MUX_PB02D_SERCOM5_PAD0 _L_(3) 612 #define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) 613 #define PORT_PB02D_SERCOM5_PAD0 (_UL_(1) << 2) 614 #define PIN_PB30D_SERCOM5_PAD0 _L_(62) /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */ 615 #define MUX_PB30D_SERCOM5_PAD0 _L_(3) 616 #define PINMUX_PB30D_SERCOM5_PAD0 ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0) 617 #define PORT_PB30D_SERCOM5_PAD0 (_UL_(1) << 30) 618 #define PIN_PB17C_SERCOM5_PAD1 _L_(49) /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ 619 #define MUX_PB17C_SERCOM5_PAD1 _L_(2) 620 #define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) 621 #define PORT_PB17C_SERCOM5_PAD1 (_UL_(1) << 17) 622 #define PIN_PA23D_SERCOM5_PAD1 _L_(23) /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */ 623 #define MUX_PA23D_SERCOM5_PAD1 _L_(3) 624 #define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1) 625 #define PORT_PA23D_SERCOM5_PAD1 (_UL_(1) << 23) 626 #define PIN_PB03D_SERCOM5_PAD1 _L_(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ 627 #define MUX_PB03D_SERCOM5_PAD1 _L_(3) 628 #define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) 629 #define PORT_PB03D_SERCOM5_PAD1 (_UL_(1) << 3) 630 #define PIN_PB31D_SERCOM5_PAD1 _L_(63) /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */ 631 #define MUX_PB31D_SERCOM5_PAD1 _L_(3) 632 #define PINMUX_PB31D_SERCOM5_PAD1 ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1) 633 #define PORT_PB31D_SERCOM5_PAD1 (_UL_(1) << 31) 634 #define PIN_PA24D_SERCOM5_PAD2 _L_(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ 635 #define MUX_PA24D_SERCOM5_PAD2 _L_(3) 636 #define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) 637 #define PORT_PA24D_SERCOM5_PAD2 (_UL_(1) << 24) 638 #define PIN_PB00D_SERCOM5_PAD2 _L_(32) /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ 639 #define MUX_PB00D_SERCOM5_PAD2 _L_(3) 640 #define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) 641 #define PORT_PB00D_SERCOM5_PAD2 (_UL_(1) << 0) 642 #define PIN_PB22D_SERCOM5_PAD2 _L_(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ 643 #define MUX_PB22D_SERCOM5_PAD2 _L_(3) 644 #define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) 645 #define PORT_PB22D_SERCOM5_PAD2 (_UL_(1) << 22) 646 #define PIN_PA20C_SERCOM5_PAD2 _L_(20) /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ 647 #define MUX_PA20C_SERCOM5_PAD2 _L_(2) 648 #define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) 649 #define PORT_PA20C_SERCOM5_PAD2 (_UL_(1) << 20) 650 #define PIN_PA25D_SERCOM5_PAD3 _L_(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ 651 #define MUX_PA25D_SERCOM5_PAD3 _L_(3) 652 #define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) 653 #define PORT_PA25D_SERCOM5_PAD3 (_UL_(1) << 25) 654 #define PIN_PB23D_SERCOM5_PAD3 _L_(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ 655 #define MUX_PB23D_SERCOM5_PAD3 _L_(3) 656 #define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) 657 #define PORT_PB23D_SERCOM5_PAD3 (_UL_(1) << 23) 658 /* ========== PORT definition for TCC0 peripheral ========== */ 659 #define PIN_PA04E_TCC0_WO0 _L_(4) /**< \brief TCC0 signal: WO0 on PA04 mux E */ 660 #define MUX_PA04E_TCC0_WO0 _L_(4) 661 #define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) 662 #define PORT_PA04E_TCC0_WO0 (_UL_(1) << 4) 663 #define PIN_PA08E_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux E */ 664 #define MUX_PA08E_TCC0_WO0 _L_(4) 665 #define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) 666 #define PORT_PA08E_TCC0_WO0 (_UL_(1) << 8) 667 #define PIN_PB30E_TCC0_WO0 _L_(62) /**< \brief TCC0 signal: WO0 on PB30 mux E */ 668 #define MUX_PB30E_TCC0_WO0 _L_(4) 669 #define PINMUX_PB30E_TCC0_WO0 ((PIN_PB30E_TCC0_WO0 << 16) | MUX_PB30E_TCC0_WO0) 670 #define PORT_PB30E_TCC0_WO0 (_UL_(1) << 30) 671 #define PIN_PA16F_TCC0_WO0 _L_(16) /**< \brief TCC0 signal: WO0 on PA16 mux F */ 672 #define MUX_PA16F_TCC0_WO0 _L_(5) 673 #define PINMUX_PA16F_TCC0_WO0 ((PIN_PA16F_TCC0_WO0 << 16) | MUX_PA16F_TCC0_WO0) 674 #define PORT_PA16F_TCC0_WO0 (_UL_(1) << 16) 675 #define PIN_PA05E_TCC0_WO1 _L_(5) /**< \brief TCC0 signal: WO1 on PA05 mux E */ 676 #define MUX_PA05E_TCC0_WO1 _L_(4) 677 #define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) 678 #define PORT_PA05E_TCC0_WO1 (_UL_(1) << 5) 679 #define PIN_PA09E_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux E */ 680 #define MUX_PA09E_TCC0_WO1 _L_(4) 681 #define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) 682 #define PORT_PA09E_TCC0_WO1 (_UL_(1) << 9) 683 #define PIN_PB31E_TCC0_WO1 _L_(63) /**< \brief TCC0 signal: WO1 on PB31 mux E */ 684 #define MUX_PB31E_TCC0_WO1 _L_(4) 685 #define PINMUX_PB31E_TCC0_WO1 ((PIN_PB31E_TCC0_WO1 << 16) | MUX_PB31E_TCC0_WO1) 686 #define PORT_PB31E_TCC0_WO1 (_UL_(1) << 31) 687 #define PIN_PA17F_TCC0_WO1 _L_(17) /**< \brief TCC0 signal: WO1 on PA17 mux F */ 688 #define MUX_PA17F_TCC0_WO1 _L_(5) 689 #define PINMUX_PA17F_TCC0_WO1 ((PIN_PA17F_TCC0_WO1 << 16) | MUX_PA17F_TCC0_WO1) 690 #define PORT_PA17F_TCC0_WO1 (_UL_(1) << 17) 691 #define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */ 692 #define MUX_PA10F_TCC0_WO2 _L_(5) 693 #define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) 694 #define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10) 695 #define PIN_PA18F_TCC0_WO2 _L_(18) /**< \brief TCC0 signal: WO2 on PA18 mux F */ 696 #define MUX_PA18F_TCC0_WO2 _L_(5) 697 #define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) 698 #define PORT_PA18F_TCC0_WO2 (_UL_(1) << 18) 699 #define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */ 700 #define MUX_PA11F_TCC0_WO3 _L_(5) 701 #define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) 702 #define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11) 703 #define PIN_PA19F_TCC0_WO3 _L_(19) /**< \brief TCC0 signal: WO3 on PA19 mux F */ 704 #define MUX_PA19F_TCC0_WO3 _L_(5) 705 #define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) 706 #define PORT_PA19F_TCC0_WO3 (_UL_(1) << 19) 707 #define PIN_PA22F_TCC0_WO4 _L_(22) /**< \brief TCC0 signal: WO4 on PA22 mux F */ 708 #define MUX_PA22F_TCC0_WO4 _L_(5) 709 #define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) 710 #define PORT_PA22F_TCC0_WO4 (_UL_(1) << 22) 711 #define PIN_PB16F_TCC0_WO4 _L_(48) /**< \brief TCC0 signal: WO4 on PB16 mux F */ 712 #define MUX_PB16F_TCC0_WO4 _L_(5) 713 #define PINMUX_PB16F_TCC0_WO4 ((PIN_PB16F_TCC0_WO4 << 16) | MUX_PB16F_TCC0_WO4) 714 #define PORT_PB16F_TCC0_WO4 (_UL_(1) << 16) 715 #define PIN_PA23F_TCC0_WO5 _L_(23) /**< \brief TCC0 signal: WO5 on PA23 mux F */ 716 #define MUX_PA23F_TCC0_WO5 _L_(5) 717 #define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) 718 #define PORT_PA23F_TCC0_WO5 (_UL_(1) << 23) 719 #define PIN_PB17F_TCC0_WO5 _L_(49) /**< \brief TCC0 signal: WO5 on PB17 mux F */ 720 #define MUX_PB17F_TCC0_WO5 _L_(5) 721 #define PINMUX_PB17F_TCC0_WO5 ((PIN_PB17F_TCC0_WO5 << 16) | MUX_PB17F_TCC0_WO5) 722 #define PORT_PB17F_TCC0_WO5 (_UL_(1) << 17) 723 #define PIN_PA20F_TCC0_WO6 _L_(20) /**< \brief TCC0 signal: WO6 on PA20 mux F */ 724 #define MUX_PA20F_TCC0_WO6 _L_(5) 725 #define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6) 726 #define PORT_PA20F_TCC0_WO6 (_UL_(1) << 20) 727 /* ========== PORT definition for TCC1 peripheral ========== */ 728 #define PIN_PA06E_TCC1_WO0 _L_(6) /**< \brief TCC1 signal: WO0 on PA06 mux E */ 729 #define MUX_PA06E_TCC1_WO0 _L_(4) 730 #define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) 731 #define PORT_PA06E_TCC1_WO0 (_UL_(1) << 6) 732 #define PIN_PA10E_TCC1_WO0 _L_(10) /**< \brief TCC1 signal: WO0 on PA10 mux E */ 733 #define MUX_PA10E_TCC1_WO0 _L_(4) 734 #define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) 735 #define PORT_PA10E_TCC1_WO0 (_UL_(1) << 10) 736 #define PIN_PA30E_TCC1_WO0 _L_(30) /**< \brief TCC1 signal: WO0 on PA30 mux E */ 737 #define MUX_PA30E_TCC1_WO0 _L_(4) 738 #define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) 739 #define PORT_PA30E_TCC1_WO0 (_UL_(1) << 30) 740 #define PIN_PA07E_TCC1_WO1 _L_(7) /**< \brief TCC1 signal: WO1 on PA07 mux E */ 741 #define MUX_PA07E_TCC1_WO1 _L_(4) 742 #define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) 743 #define PORT_PA07E_TCC1_WO1 (_UL_(1) << 7) 744 #define PIN_PA11E_TCC1_WO1 _L_(11) /**< \brief TCC1 signal: WO1 on PA11 mux E */ 745 #define MUX_PA11E_TCC1_WO1 _L_(4) 746 #define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) 747 #define PORT_PA11E_TCC1_WO1 (_UL_(1) << 11) 748 #define PIN_PA31E_TCC1_WO1 _L_(31) /**< \brief TCC1 signal: WO1 on PA31 mux E */ 749 #define MUX_PA31E_TCC1_WO1 _L_(4) 750 #define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) 751 #define PORT_PA31E_TCC1_WO1 (_UL_(1) << 31) 752 #define PIN_PA24F_TCC1_WO2 _L_(24) /**< \brief TCC1 signal: WO2 on PA24 mux F */ 753 #define MUX_PA24F_TCC1_WO2 _L_(5) 754 #define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) 755 #define PORT_PA24F_TCC1_WO2 (_UL_(1) << 24) 756 #define PIN_PA25F_TCC1_WO3 _L_(25) /**< \brief TCC1 signal: WO3 on PA25 mux F */ 757 #define MUX_PA25F_TCC1_WO3 _L_(5) 758 #define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) 759 #define PORT_PA25F_TCC1_WO3 (_UL_(1) << 25) 760 /* ========== PORT definition for TCC2 peripheral ========== */ 761 #define PIN_PA12E_TCC2_WO0 _L_(12) /**< \brief TCC2 signal: WO0 on PA12 mux E */ 762 #define MUX_PA12E_TCC2_WO0 _L_(4) 763 #define PINMUX_PA12E_TCC2_WO0 ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0) 764 #define PORT_PA12E_TCC2_WO0 (_UL_(1) << 12) 765 #define PIN_PA16E_TCC2_WO0 _L_(16) /**< \brief TCC2 signal: WO0 on PA16 mux E */ 766 #define MUX_PA16E_TCC2_WO0 _L_(4) 767 #define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) 768 #define PORT_PA16E_TCC2_WO0 (_UL_(1) << 16) 769 #define PIN_PA00E_TCC2_WO0 _L_(0) /**< \brief TCC2 signal: WO0 on PA00 mux E */ 770 #define MUX_PA00E_TCC2_WO0 _L_(4) 771 #define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0) 772 #define PORT_PA00E_TCC2_WO0 (_UL_(1) << 0) 773 #define PIN_PA13E_TCC2_WO1 _L_(13) /**< \brief TCC2 signal: WO1 on PA13 mux E */ 774 #define MUX_PA13E_TCC2_WO1 _L_(4) 775 #define PINMUX_PA13E_TCC2_WO1 ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1) 776 #define PORT_PA13E_TCC2_WO1 (_UL_(1) << 13) 777 #define PIN_PA17E_TCC2_WO1 _L_(17) /**< \brief TCC2 signal: WO1 on PA17 mux E */ 778 #define MUX_PA17E_TCC2_WO1 _L_(4) 779 #define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) 780 #define PORT_PA17E_TCC2_WO1 (_UL_(1) << 17) 781 #define PIN_PA01E_TCC2_WO1 _L_(1) /**< \brief TCC2 signal: WO1 on PA01 mux E */ 782 #define MUX_PA01E_TCC2_WO1 _L_(4) 783 #define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1) 784 #define PORT_PA01E_TCC2_WO1 (_UL_(1) << 1) 785 /* ========== PORT definition for TC3 peripheral ========== */ 786 #define PIN_PA18E_TC3_WO0 _L_(18) /**< \brief TC3 signal: WO0 on PA18 mux E */ 787 #define MUX_PA18E_TC3_WO0 _L_(4) 788 #define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) 789 #define PORT_PA18E_TC3_WO0 (_UL_(1) << 18) 790 #define PIN_PA14E_TC3_WO0 _L_(14) /**< \brief TC3 signal: WO0 on PA14 mux E */ 791 #define MUX_PA14E_TC3_WO0 _L_(4) 792 #define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) 793 #define PORT_PA14E_TC3_WO0 (_UL_(1) << 14) 794 #define PIN_PA19E_TC3_WO1 _L_(19) /**< \brief TC3 signal: WO1 on PA19 mux E */ 795 #define MUX_PA19E_TC3_WO1 _L_(4) 796 #define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) 797 #define PORT_PA19E_TC3_WO1 (_UL_(1) << 19) 798 #define PIN_PA15E_TC3_WO1 _L_(15) /**< \brief TC3 signal: WO1 on PA15 mux E */ 799 #define MUX_PA15E_TC3_WO1 _L_(4) 800 #define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) 801 #define PORT_PA15E_TC3_WO1 (_UL_(1) << 15) 802 /* ========== PORT definition for TC4 peripheral ========== */ 803 #define PIN_PA22E_TC4_WO0 _L_(22) /**< \brief TC4 signal: WO0 on PA22 mux E */ 804 #define MUX_PA22E_TC4_WO0 _L_(4) 805 #define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) 806 #define PORT_PA22E_TC4_WO0 (_UL_(1) << 22) 807 #define PIN_PB08E_TC4_WO0 _L_(40) /**< \brief TC4 signal: WO0 on PB08 mux E */ 808 #define MUX_PB08E_TC4_WO0 _L_(4) 809 #define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) 810 #define PORT_PB08E_TC4_WO0 (_UL_(1) << 8) 811 #define PIN_PA23E_TC4_WO1 _L_(23) /**< \brief TC4 signal: WO1 on PA23 mux E */ 812 #define MUX_PA23E_TC4_WO1 _L_(4) 813 #define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) 814 #define PORT_PA23E_TC4_WO1 (_UL_(1) << 23) 815 #define PIN_PB09E_TC4_WO1 _L_(41) /**< \brief TC4 signal: WO1 on PB09 mux E */ 816 #define MUX_PB09E_TC4_WO1 _L_(4) 817 #define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) 818 #define PORT_PB09E_TC4_WO1 (_UL_(1) << 9) 819 /* ========== PORT definition for TC5 peripheral ========== */ 820 #define PIN_PA24E_TC5_WO0 _L_(24) /**< \brief TC5 signal: WO0 on PA24 mux E */ 821 #define MUX_PA24E_TC5_WO0 _L_(4) 822 #define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) 823 #define PORT_PA24E_TC5_WO0 (_UL_(1) << 24) 824 #define PIN_PB14E_TC5_WO0 _L_(46) /**< \brief TC5 signal: WO0 on PB14 mux E */ 825 #define MUX_PB14E_TC5_WO0 _L_(4) 826 #define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0) 827 #define PORT_PB14E_TC5_WO0 (_UL_(1) << 14) 828 #define PIN_PA25E_TC5_WO1 _L_(25) /**< \brief TC5 signal: WO1 on PA25 mux E */ 829 #define MUX_PA25E_TC5_WO1 _L_(4) 830 #define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) 831 #define PORT_PA25E_TC5_WO1 (_UL_(1) << 25) 832 #define PIN_PB15E_TC5_WO1 _L_(47) /**< \brief TC5 signal: WO1 on PB15 mux E */ 833 #define MUX_PB15E_TC5_WO1 _L_(4) 834 #define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1) 835 #define PORT_PB15E_TC5_WO1 (_UL_(1) << 15) 836 /* ========== PORT definition for TC6 peripheral ========== */ 837 #define PIN_PB02E_TC6_WO0 _L_(34) /**< \brief TC6 signal: WO0 on PB02 mux E */ 838 #define MUX_PB02E_TC6_WO0 _L_(4) 839 #define PINMUX_PB02E_TC6_WO0 ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0) 840 #define PORT_PB02E_TC6_WO0 (_UL_(1) << 2) 841 #define PIN_PB16E_TC6_WO0 _L_(48) /**< \brief TC6 signal: WO0 on PB16 mux E */ 842 #define MUX_PB16E_TC6_WO0 _L_(4) 843 #define PINMUX_PB16E_TC6_WO0 ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0) 844 #define PORT_PB16E_TC6_WO0 (_UL_(1) << 16) 845 #define PIN_PB03E_TC6_WO1 _L_(35) /**< \brief TC6 signal: WO1 on PB03 mux E */ 846 #define MUX_PB03E_TC6_WO1 _L_(4) 847 #define PINMUX_PB03E_TC6_WO1 ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1) 848 #define PORT_PB03E_TC6_WO1 (_UL_(1) << 3) 849 #define PIN_PB17E_TC6_WO1 _L_(49) /**< \brief TC6 signal: WO1 on PB17 mux E */ 850 #define MUX_PB17E_TC6_WO1 _L_(4) 851 #define PINMUX_PB17E_TC6_WO1 ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1) 852 #define PORT_PB17E_TC6_WO1 (_UL_(1) << 17) 853 /* ========== PORT definition for TC7 peripheral ========== */ 854 #define PIN_PA20E_TC7_WO0 _L_(20) /**< \brief TC7 signal: WO0 on PA20 mux E */ 855 #define MUX_PA20E_TC7_WO0 _L_(4) 856 #define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0) 857 #define PORT_PA20E_TC7_WO0 (_UL_(1) << 20) 858 #define PIN_PB00E_TC7_WO0 _L_(32) /**< \brief TC7 signal: WO0 on PB00 mux E */ 859 #define MUX_PB00E_TC7_WO0 _L_(4) 860 #define PINMUX_PB00E_TC7_WO0 ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0) 861 #define PORT_PB00E_TC7_WO0 (_UL_(1) << 0) 862 #define PIN_PB22E_TC7_WO0 _L_(54) /**< \brief TC7 signal: WO0 on PB22 mux E */ 863 #define MUX_PB22E_TC7_WO0 _L_(4) 864 #define PINMUX_PB22E_TC7_WO0 ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0) 865 #define PORT_PB22E_TC7_WO0 (_UL_(1) << 22) 866 #define PIN_PB23E_TC7_WO1 _L_(55) /**< \brief TC7 signal: WO1 on PB23 mux E */ 867 #define MUX_PB23E_TC7_WO1 _L_(4) 868 #define PINMUX_PB23E_TC7_WO1 ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1) 869 #define PORT_PB23E_TC7_WO1 (_UL_(1) << 23) 870 /* ========== PORT definition for ADC peripheral ========== */ 871 #define PIN_PB08B_ADC_AIN2 _L_(40) /**< \brief ADC signal: AIN2 on PB08 mux B */ 872 #define MUX_PB08B_ADC_AIN2 _L_(1) 873 #define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2) 874 #define PORT_PB08B_ADC_AIN2 (_UL_(1) << 8) 875 #define PIN_PB09B_ADC_AIN3 _L_(41) /**< \brief ADC signal: AIN3 on PB09 mux B */ 876 #define MUX_PB09B_ADC_AIN3 _L_(1) 877 #define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3) 878 #define PORT_PB09B_ADC_AIN3 (_UL_(1) << 9) 879 #define PIN_PA04B_ADC_AIN4 _L_(4) /**< \brief ADC signal: AIN4 on PA04 mux B */ 880 #define MUX_PA04B_ADC_AIN4 _L_(1) 881 #define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) 882 #define PORT_PA04B_ADC_AIN4 (_UL_(1) << 4) 883 #define PIN_PA05B_ADC_AIN5 _L_(5) /**< \brief ADC signal: AIN5 on PA05 mux B */ 884 #define MUX_PA05B_ADC_AIN5 _L_(1) 885 #define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) 886 #define PORT_PA05B_ADC_AIN5 (_UL_(1) << 5) 887 #define PIN_PA06B_ADC_AIN6 _L_(6) /**< \brief ADC signal: AIN6 on PA06 mux B */ 888 #define MUX_PA06B_ADC_AIN6 _L_(1) 889 #define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) 890 #define PORT_PA06B_ADC_AIN6 (_UL_(1) << 6) 891 #define PIN_PA07B_ADC_AIN7 _L_(7) /**< \brief ADC signal: AIN7 on PA07 mux B */ 892 #define MUX_PA07B_ADC_AIN7 _L_(1) 893 #define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) 894 #define PORT_PA07B_ADC_AIN7 (_UL_(1) << 7) 895 #define PIN_PB00B_ADC_AIN8 _L_(32) /**< \brief ADC signal: AIN8 on PB00 mux B */ 896 #define MUX_PB00B_ADC_AIN8 _L_(1) 897 #define PINMUX_PB00B_ADC_AIN8 ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8) 898 #define PORT_PB00B_ADC_AIN8 (_UL_(1) << 0) 899 #define PIN_PB02B_ADC_AIN10 _L_(34) /**< \brief ADC signal: AIN10 on PB02 mux B */ 900 #define MUX_PB02B_ADC_AIN10 _L_(1) 901 #define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10) 902 #define PORT_PB02B_ADC_AIN10 (_UL_(1) << 2) 903 #define PIN_PB03B_ADC_AIN11 _L_(35) /**< \brief ADC signal: AIN11 on PB03 mux B */ 904 #define MUX_PB03B_ADC_AIN11 _L_(1) 905 #define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11) 906 #define PORT_PB03B_ADC_AIN11 (_UL_(1) << 3) 907 #define PIN_PA08B_ADC_AIN16 _L_(8) /**< \brief ADC signal: AIN16 on PA08 mux B */ 908 #define MUX_PA08B_ADC_AIN16 _L_(1) 909 #define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) 910 #define PORT_PA08B_ADC_AIN16 (_UL_(1) << 8) 911 #define PIN_PA09B_ADC_AIN17 _L_(9) /**< \brief ADC signal: AIN17 on PA09 mux B */ 912 #define MUX_PA09B_ADC_AIN17 _L_(1) 913 #define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) 914 #define PORT_PA09B_ADC_AIN17 (_UL_(1) << 9) 915 #define PIN_PA10B_ADC_AIN18 _L_(10) /**< \brief ADC signal: AIN18 on PA10 mux B */ 916 #define MUX_PA10B_ADC_AIN18 _L_(1) 917 #define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) 918 #define PORT_PA10B_ADC_AIN18 (_UL_(1) << 10) 919 #define PIN_PA11B_ADC_AIN19 _L_(11) /**< \brief ADC signal: AIN19 on PA11 mux B */ 920 #define MUX_PA11B_ADC_AIN19 _L_(1) 921 #define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) 922 #define PORT_PA11B_ADC_AIN19 (_UL_(1) << 11) 923 #define PIN_PA04B_ADC_VREFP _L_(4) /**< \brief ADC signal: VREFP on PA04 mux B */ 924 #define MUX_PA04B_ADC_VREFP _L_(1) 925 #define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP) 926 #define PORT_PA04B_ADC_VREFP (_UL_(1) << 4) 927 /* ========== PORT definition for AC peripheral ========== */ 928 #define PIN_PA04B_AC_AIN0 _L_(4) /**< \brief AC signal: AIN0 on PA04 mux B */ 929 #define MUX_PA04B_AC_AIN0 _L_(1) 930 #define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) 931 #define PORT_PA04B_AC_AIN0 (_UL_(1) << 4) 932 #define PIN_PA05B_AC_AIN1 _L_(5) /**< \brief AC signal: AIN1 on PA05 mux B */ 933 #define MUX_PA05B_AC_AIN1 _L_(1) 934 #define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) 935 #define PORT_PA05B_AC_AIN1 (_UL_(1) << 5) 936 #define PIN_PA06B_AC_AIN2 _L_(6) /**< \brief AC signal: AIN2 on PA06 mux B */ 937 #define MUX_PA06B_AC_AIN2 _L_(1) 938 #define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) 939 #define PORT_PA06B_AC_AIN2 (_UL_(1) << 6) 940 #define PIN_PA07B_AC_AIN3 _L_(7) /**< \brief AC signal: AIN3 on PA07 mux B */ 941 #define MUX_PA07B_AC_AIN3 _L_(1) 942 #define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) 943 #define PORT_PA07B_AC_AIN3 (_UL_(1) << 7) 944 #define PIN_PA12H_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux H */ 945 #define MUX_PA12H_AC_CMP0 _L_(7) 946 #define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0) 947 #define PORT_PA12H_AC_CMP0 (_UL_(1) << 12) 948 #define PIN_PA18H_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux H */ 949 #define MUX_PA18H_AC_CMP0 _L_(7) 950 #define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) 951 #define PORT_PA18H_AC_CMP0 (_UL_(1) << 18) 952 #define PIN_PA13H_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux H */ 953 #define MUX_PA13H_AC_CMP1 _L_(7) 954 #define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1) 955 #define PORT_PA13H_AC_CMP1 (_UL_(1) << 13) 956 #define PIN_PA19H_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux H */ 957 #define MUX_PA19H_AC_CMP1 _L_(7) 958 #define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) 959 #define PORT_PA19H_AC_CMP1 (_UL_(1) << 19) 960 /* ========== PORT definition for RFCTRL peripheral ========== */ 961 #define PIN_PA08F_RFCTRL_FECTRL0 _L_(8) /**< \brief RFCTRL signal: FECTRL0 on PA08 mux F */ 962 #define MUX_PA08F_RFCTRL_FECTRL0 _L_(5) 963 #define PINMUX_PA08F_RFCTRL_FECTRL0 ((PIN_PA08F_RFCTRL_FECTRL0 << 16) | MUX_PA08F_RFCTRL_FECTRL0) 964 #define PORT_PA08F_RFCTRL_FECTRL0 (_UL_(1) << 8) 965 #define PIN_PA09F_RFCTRL_FECTRL1 _L_(9) /**< \brief RFCTRL signal: FECTRL1 on PA09 mux F */ 966 #define MUX_PA09F_RFCTRL_FECTRL1 _L_(5) 967 #define PINMUX_PA09F_RFCTRL_FECTRL1 ((PIN_PA09F_RFCTRL_FECTRL1 << 16) | MUX_PA09F_RFCTRL_FECTRL1) 968 #define PORT_PA09F_RFCTRL_FECTRL1 (_UL_(1) << 9) 969 #define PIN_PA12F_RFCTRL_FECTRL2 _L_(12) /**< \brief RFCTRL signal: FECTRL2 on PA12 mux F */ 970 #define MUX_PA12F_RFCTRL_FECTRL2 _L_(5) 971 #define PINMUX_PA12F_RFCTRL_FECTRL2 ((PIN_PA12F_RFCTRL_FECTRL2 << 16) | MUX_PA12F_RFCTRL_FECTRL2) 972 #define PORT_PA12F_RFCTRL_FECTRL2 (_UL_(1) << 12) 973 #define PIN_PA13F_RFCTRL_FECTRL3 _L_(13) /**< \brief RFCTRL signal: FECTRL3 on PA13 mux F */ 974 #define MUX_PA13F_RFCTRL_FECTRL3 _L_(5) 975 #define PINMUX_PA13F_RFCTRL_FECTRL3 ((PIN_PA13F_RFCTRL_FECTRL3 << 16) | MUX_PA13F_RFCTRL_FECTRL3) 976 #define PORT_PA13F_RFCTRL_FECTRL3 (_UL_(1) << 13) 977 #define PIN_PA14F_RFCTRL_FECTRL4 _L_(14) /**< \brief RFCTRL signal: FECTRL4 on PA14 mux F */ 978 #define MUX_PA14F_RFCTRL_FECTRL4 _L_(5) 979 #define PINMUX_PA14F_RFCTRL_FECTRL4 ((PIN_PA14F_RFCTRL_FECTRL4 << 16) | MUX_PA14F_RFCTRL_FECTRL4) 980 #define PORT_PA14F_RFCTRL_FECTRL4 (_UL_(1) << 14) 981 #define PIN_PA15F_RFCTRL_FECTRL5 _L_(15) /**< \brief RFCTRL signal: FECTRL5 on PA15 mux F */ 982 #define MUX_PA15F_RFCTRL_FECTRL5 _L_(5) 983 #define PINMUX_PA15F_RFCTRL_FECTRL5 ((PIN_PA15F_RFCTRL_FECTRL5 << 16) | MUX_PA15F_RFCTRL_FECTRL5) 984 #define PORT_PA15F_RFCTRL_FECTRL5 (_UL_(1) << 15) 985 986 #endif /* _SAMR21G17A_PIO_ */ 987
