1 /** 2 * \file 3 * 4 * \brief Instance description for DSU 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAMR21_DSU_INSTANCE_ 30 #define _SAMR21_DSU_INSTANCE_ 31 32 /* ========== Register definition for DSU peripheral ========== */ 33 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 34 #define REG_DSU_CTRL (0x41002000) /**< \brief (DSU) Control */ 35 #define REG_DSU_STATUSA (0x41002001) /**< \brief (DSU) Status A */ 36 #define REG_DSU_STATUSB (0x41002002) /**< \brief (DSU) Status B */ 37 #define REG_DSU_ADDR (0x41002004) /**< \brief (DSU) Address */ 38 #define REG_DSU_LENGTH (0x41002008) /**< \brief (DSU) Length */ 39 #define REG_DSU_DATA (0x4100200C) /**< \brief (DSU) Data */ 40 #define REG_DSU_DCC0 (0x41002010) /**< \brief (DSU) Debug Communication Channel 0 */ 41 #define REG_DSU_DCC1 (0x41002014) /**< \brief (DSU) Debug Communication Channel 1 */ 42 #define REG_DSU_DID (0x41002018) /**< \brief (DSU) Device Identification */ 43 #define REG_DSU_ENTRY0 (0x41003000) /**< \brief (DSU) Coresight ROM Table Entry 0 */ 44 #define REG_DSU_ENTRY1 (0x41003004) /**< \brief (DSU) Coresight ROM Table Entry 1 */ 45 #define REG_DSU_END (0x41003008) /**< \brief (DSU) Coresight ROM Table End */ 46 #define REG_DSU_MEMTYPE (0x41003FCC) /**< \brief (DSU) Coresight ROM Table Memory Type */ 47 #define REG_DSU_PID4 (0x41003FD0) /**< \brief (DSU) Peripheral Identification 4 */ 48 #define REG_DSU_PID0 (0x41003FE0) /**< \brief (DSU) Peripheral Identification 0 */ 49 #define REG_DSU_PID1 (0x41003FE4) /**< \brief (DSU) Peripheral Identification 1 */ 50 #define REG_DSU_PID2 (0x41003FE8) /**< \brief (DSU) Peripheral Identification 2 */ 51 #define REG_DSU_PID3 (0x41003FEC) /**< \brief (DSU) Peripheral Identification 3 */ 52 #define REG_DSU_CID0 (0x41003FF0) /**< \brief (DSU) Component Identification 0 */ 53 #define REG_DSU_CID1 (0x41003FF4) /**< \brief (DSU) Component Identification 1 */ 54 #define REG_DSU_CID2 (0x41003FF8) /**< \brief (DSU) Component Identification 2 */ 55 #define REG_DSU_CID3 (0x41003FFC) /**< \brief (DSU) Component Identification 3 */ 56 #else 57 #define REG_DSU_CTRL (*(WoReg8 *)0x41002000UL) /**< \brief (DSU) Control */ 58 #define REG_DSU_STATUSA (*(RwReg8 *)0x41002001UL) /**< \brief (DSU) Status A */ 59 #define REG_DSU_STATUSB (*(RoReg8 *)0x41002002UL) /**< \brief (DSU) Status B */ 60 #define REG_DSU_ADDR (*(RwReg *)0x41002004UL) /**< \brief (DSU) Address */ 61 #define REG_DSU_LENGTH (*(RwReg *)0x41002008UL) /**< \brief (DSU) Length */ 62 #define REG_DSU_DATA (*(RwReg *)0x4100200CUL) /**< \brief (DSU) Data */ 63 #define REG_DSU_DCC0 (*(RwReg *)0x41002010UL) /**< \brief (DSU) Debug Communication Channel 0 */ 64 #define REG_DSU_DCC1 (*(RwReg *)0x41002014UL) /**< \brief (DSU) Debug Communication Channel 1 */ 65 #define REG_DSU_DID (*(RoReg *)0x41002018UL) /**< \brief (DSU) Device Identification */ 66 #define REG_DSU_ENTRY0 (*(RoReg *)0x41003000UL) /**< \brief (DSU) Coresight ROM Table Entry 0 */ 67 #define REG_DSU_ENTRY1 (*(RoReg *)0x41003004UL) /**< \brief (DSU) Coresight ROM Table Entry 1 */ 68 #define REG_DSU_END (*(RoReg *)0x41003008UL) /**< \brief (DSU) Coresight ROM Table End */ 69 #define REG_DSU_MEMTYPE (*(RoReg *)0x41003FCCUL) /**< \brief (DSU) Coresight ROM Table Memory Type */ 70 #define REG_DSU_PID4 (*(RoReg *)0x41003FD0UL) /**< \brief (DSU) Peripheral Identification 4 */ 71 #define REG_DSU_PID0 (*(RoReg *)0x41003FE0UL) /**< \brief (DSU) Peripheral Identification 0 */ 72 #define REG_DSU_PID1 (*(RoReg *)0x41003FE4UL) /**< \brief (DSU) Peripheral Identification 1 */ 73 #define REG_DSU_PID2 (*(RoReg *)0x41003FE8UL) /**< \brief (DSU) Peripheral Identification 2 */ 74 #define REG_DSU_PID3 (*(RoReg *)0x41003FECUL) /**< \brief (DSU) Peripheral Identification 3 */ 75 #define REG_DSU_CID0 (*(RoReg *)0x41003FF0UL) /**< \brief (DSU) Component Identification 0 */ 76 #define REG_DSU_CID1 (*(RoReg *)0x41003FF4UL) /**< \brief (DSU) Component Identification 1 */ 77 #define REG_DSU_CID2 (*(RoReg *)0x41003FF8UL) /**< \brief (DSU) Component Identification 2 */ 78 #define REG_DSU_CID3 (*(RoReg *)0x41003FFCUL) /**< \brief (DSU) Component Identification 3 */ 79 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 80 81 /* ========== Instance parameters for DSU peripheral ========== */ 82 #define DSU_CLK_HSB_ID 3 // Index of AHB clock in PM.AHBMASK register 83 84 #endif /* _SAMR21_DSU_INSTANCE_ */ 85
