1 /** 2 * \file 3 * 4 * \brief Component description for WDT 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAMD21_WDT_COMPONENT_ 30 #define _SAMD21_WDT_COMPONENT_ 31 32 /* ========================================================================== */ 33 /** SOFTWARE API DEFINITION FOR WDT */ 34 /* ========================================================================== */ 35 /** \addtogroup SAMD21_WDT Watchdog Timer */ 36 /*@{*/ 37 38 #define WDT_U2203 39 #define REV_WDT 0x200 40 41 /* -------- WDT_CTRL : (WDT Offset: 0x0) (R/W 8) Control -------- */ 42 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 43 typedef union { 44 struct { 45 uint8_t :1; /*!< bit: 0 Reserved */ 46 uint8_t ENABLE:1; /*!< bit: 1 Enable */ 47 uint8_t WEN:1; /*!< bit: 2 Watchdog Timer Window Mode Enable */ 48 uint8_t :4; /*!< bit: 3.. 6 Reserved */ 49 uint8_t ALWAYSON:1; /*!< bit: 7 Always-On */ 50 } bit; /*!< Structure used for bit access */ 51 uint8_t reg; /*!< Type used for register access */ 52 } WDT_CTRL_Type; 53 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 54 55 #define WDT_CTRL_OFFSET 0x0 /**< \brief (WDT_CTRL offset) Control */ 56 #define WDT_CTRL_RESETVALUE _U_(0x00) /**< \brief (WDT_CTRL reset_value) Control */ 57 58 #define WDT_CTRL_ENABLE_Pos 1 /**< \brief (WDT_CTRL) Enable */ 59 #define WDT_CTRL_ENABLE (_U_(0x1) << WDT_CTRL_ENABLE_Pos) 60 #define WDT_CTRL_WEN_Pos 2 /**< \brief (WDT_CTRL) Watchdog Timer Window Mode Enable */ 61 #define WDT_CTRL_WEN (_U_(0x1) << WDT_CTRL_WEN_Pos) 62 #define WDT_CTRL_ALWAYSON_Pos 7 /**< \brief (WDT_CTRL) Always-On */ 63 #define WDT_CTRL_ALWAYSON (_U_(0x1) << WDT_CTRL_ALWAYSON_Pos) 64 #define WDT_CTRL_MASK _U_(0x86) /**< \brief (WDT_CTRL) MASK Register */ 65 66 /* -------- WDT_CONFIG : (WDT Offset: 0x1) (R/W 8) Configuration -------- */ 67 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 68 typedef union { 69 struct { 70 uint8_t PER:4; /*!< bit: 0.. 3 Time-Out Period */ 71 uint8_t WINDOW:4; /*!< bit: 4.. 7 Window Mode Time-Out Period */ 72 } bit; /*!< Structure used for bit access */ 73 uint8_t reg; /*!< Type used for register access */ 74 } WDT_CONFIG_Type; 75 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 76 77 #define WDT_CONFIG_OFFSET 0x1 /**< \brief (WDT_CONFIG offset) Configuration */ 78 #define WDT_CONFIG_RESETVALUE _U_(0xBB) /**< \brief (WDT_CONFIG reset_value) Configuration */ 79 80 #define WDT_CONFIG_PER_Pos 0 /**< \brief (WDT_CONFIG) Time-Out Period */ 81 #define WDT_CONFIG_PER_Msk (_U_(0xF) << WDT_CONFIG_PER_Pos) 82 #define WDT_CONFIG_PER(value) (WDT_CONFIG_PER_Msk & ((value) << WDT_CONFIG_PER_Pos)) 83 #define WDT_CONFIG_PER_8_Val _U_(0x0) /**< \brief (WDT_CONFIG) 8 clock cycles */ 84 #define WDT_CONFIG_PER_16_Val _U_(0x1) /**< \brief (WDT_CONFIG) 16 clock cycles */ 85 #define WDT_CONFIG_PER_32_Val _U_(0x2) /**< \brief (WDT_CONFIG) 32 clock cycles */ 86 #define WDT_CONFIG_PER_64_Val _U_(0x3) /**< \brief (WDT_CONFIG) 64 clock cycles */ 87 #define WDT_CONFIG_PER_128_Val _U_(0x4) /**< \brief (WDT_CONFIG) 128 clock cycles */ 88 #define WDT_CONFIG_PER_256_Val _U_(0x5) /**< \brief (WDT_CONFIG) 256 clock cycles */ 89 #define WDT_CONFIG_PER_512_Val _U_(0x6) /**< \brief (WDT_CONFIG) 512 clock cycles */ 90 #define WDT_CONFIG_PER_1K_Val _U_(0x7) /**< \brief (WDT_CONFIG) 1024 clock cycles */ 91 #define WDT_CONFIG_PER_2K_Val _U_(0x8) /**< \brief (WDT_CONFIG) 2048 clock cycles */ 92 #define WDT_CONFIG_PER_4K_Val _U_(0x9) /**< \brief (WDT_CONFIG) 4096 clock cycles */ 93 #define WDT_CONFIG_PER_8K_Val _U_(0xA) /**< \brief (WDT_CONFIG) 8192 clock cycles */ 94 #define WDT_CONFIG_PER_16K_Val _U_(0xB) /**< \brief (WDT_CONFIG) 16384 clock cycles */ 95 #define WDT_CONFIG_PER_8 (WDT_CONFIG_PER_8_Val << WDT_CONFIG_PER_Pos) 96 #define WDT_CONFIG_PER_16 (WDT_CONFIG_PER_16_Val << WDT_CONFIG_PER_Pos) 97 #define WDT_CONFIG_PER_32 (WDT_CONFIG_PER_32_Val << WDT_CONFIG_PER_Pos) 98 #define WDT_CONFIG_PER_64 (WDT_CONFIG_PER_64_Val << WDT_CONFIG_PER_Pos) 99 #define WDT_CONFIG_PER_128 (WDT_CONFIG_PER_128_Val << WDT_CONFIG_PER_Pos) 100 #define WDT_CONFIG_PER_256 (WDT_CONFIG_PER_256_Val << WDT_CONFIG_PER_Pos) 101 #define WDT_CONFIG_PER_512 (WDT_CONFIG_PER_512_Val << WDT_CONFIG_PER_Pos) 102 #define WDT_CONFIG_PER_1K (WDT_CONFIG_PER_1K_Val << WDT_CONFIG_PER_Pos) 103 #define WDT_CONFIG_PER_2K (WDT_CONFIG_PER_2K_Val << WDT_CONFIG_PER_Pos) 104 #define WDT_CONFIG_PER_4K (WDT_CONFIG_PER_4K_Val << WDT_CONFIG_PER_Pos) 105 #define WDT_CONFIG_PER_8K (WDT_CONFIG_PER_8K_Val << WDT_CONFIG_PER_Pos) 106 #define WDT_CONFIG_PER_16K (WDT_CONFIG_PER_16K_Val << WDT_CONFIG_PER_Pos) 107 #define WDT_CONFIG_WINDOW_Pos 4 /**< \brief (WDT_CONFIG) Window Mode Time-Out Period */ 108 #define WDT_CONFIG_WINDOW_Msk (_U_(0xF) << WDT_CONFIG_WINDOW_Pos) 109 #define WDT_CONFIG_WINDOW(value) (WDT_CONFIG_WINDOW_Msk & ((value) << WDT_CONFIG_WINDOW_Pos)) 110 #define WDT_CONFIG_WINDOW_8_Val _U_(0x0) /**< \brief (WDT_CONFIG) 8 clock cycles */ 111 #define WDT_CONFIG_WINDOW_16_Val _U_(0x1) /**< \brief (WDT_CONFIG) 16 clock cycles */ 112 #define WDT_CONFIG_WINDOW_32_Val _U_(0x2) /**< \brief (WDT_CONFIG) 32 clock cycles */ 113 #define WDT_CONFIG_WINDOW_64_Val _U_(0x3) /**< \brief (WDT_CONFIG) 64 clock cycles */ 114 #define WDT_CONFIG_WINDOW_128_Val _U_(0x4) /**< \brief (WDT_CONFIG) 128 clock cycles */ 115 #define WDT_CONFIG_WINDOW_256_Val _U_(0x5) /**< \brief (WDT_CONFIG) 256 clock cycles */ 116 #define WDT_CONFIG_WINDOW_512_Val _U_(0x6) /**< \brief (WDT_CONFIG) 512 clock cycles */ 117 #define WDT_CONFIG_WINDOW_1K_Val _U_(0x7) /**< \brief (WDT_CONFIG) 1024 clock cycles */ 118 #define WDT_CONFIG_WINDOW_2K_Val _U_(0x8) /**< \brief (WDT_CONFIG) 2048 clock cycles */ 119 #define WDT_CONFIG_WINDOW_4K_Val _U_(0x9) /**< \brief (WDT_CONFIG) 4096 clock cycles */ 120 #define WDT_CONFIG_WINDOW_8K_Val _U_(0xA) /**< \brief (WDT_CONFIG) 8192 clock cycles */ 121 #define WDT_CONFIG_WINDOW_16K_Val _U_(0xB) /**< \brief (WDT_CONFIG) 16384 clock cycles */ 122 #define WDT_CONFIG_WINDOW_8 (WDT_CONFIG_WINDOW_8_Val << WDT_CONFIG_WINDOW_Pos) 123 #define WDT_CONFIG_WINDOW_16 (WDT_CONFIG_WINDOW_16_Val << WDT_CONFIG_WINDOW_Pos) 124 #define WDT_CONFIG_WINDOW_32 (WDT_CONFIG_WINDOW_32_Val << WDT_CONFIG_WINDOW_Pos) 125 #define WDT_CONFIG_WINDOW_64 (WDT_CONFIG_WINDOW_64_Val << WDT_CONFIG_WINDOW_Pos) 126 #define WDT_CONFIG_WINDOW_128 (WDT_CONFIG_WINDOW_128_Val << WDT_CONFIG_WINDOW_Pos) 127 #define WDT_CONFIG_WINDOW_256 (WDT_CONFIG_WINDOW_256_Val << WDT_CONFIG_WINDOW_Pos) 128 #define WDT_CONFIG_WINDOW_512 (WDT_CONFIG_WINDOW_512_Val << WDT_CONFIG_WINDOW_Pos) 129 #define WDT_CONFIG_WINDOW_1K (WDT_CONFIG_WINDOW_1K_Val << WDT_CONFIG_WINDOW_Pos) 130 #define WDT_CONFIG_WINDOW_2K (WDT_CONFIG_WINDOW_2K_Val << WDT_CONFIG_WINDOW_Pos) 131 #define WDT_CONFIG_WINDOW_4K (WDT_CONFIG_WINDOW_4K_Val << WDT_CONFIG_WINDOW_Pos) 132 #define WDT_CONFIG_WINDOW_8K (WDT_CONFIG_WINDOW_8K_Val << WDT_CONFIG_WINDOW_Pos) 133 #define WDT_CONFIG_WINDOW_16K (WDT_CONFIG_WINDOW_16K_Val << WDT_CONFIG_WINDOW_Pos) 134 #define WDT_CONFIG_MASK _U_(0xFF) /**< \brief (WDT_CONFIG) MASK Register */ 135 136 /* -------- WDT_EWCTRL : (WDT Offset: 0x2) (R/W 8) Early Warning Interrupt Control -------- */ 137 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 138 typedef union { 139 struct { 140 uint8_t EWOFFSET:4; /*!< bit: 0.. 3 Early Warning Interrupt Time Offset */ 141 uint8_t :4; /*!< bit: 4.. 7 Reserved */ 142 } bit; /*!< Structure used for bit access */ 143 uint8_t reg; /*!< Type used for register access */ 144 } WDT_EWCTRL_Type; 145 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 146 147 #define WDT_EWCTRL_OFFSET 0x2 /**< \brief (WDT_EWCTRL offset) Early Warning Interrupt Control */ 148 #define WDT_EWCTRL_RESETVALUE _U_(0x0B) /**< \brief (WDT_EWCTRL reset_value) Early Warning Interrupt Control */ 149 150 #define WDT_EWCTRL_EWOFFSET_Pos 0 /**< \brief (WDT_EWCTRL) Early Warning Interrupt Time Offset */ 151 #define WDT_EWCTRL_EWOFFSET_Msk (_U_(0xF) << WDT_EWCTRL_EWOFFSET_Pos) 152 #define WDT_EWCTRL_EWOFFSET(value) (WDT_EWCTRL_EWOFFSET_Msk & ((value) << WDT_EWCTRL_EWOFFSET_Pos)) 153 #define WDT_EWCTRL_EWOFFSET_8_Val _U_(0x0) /**< \brief (WDT_EWCTRL) 8 clock cycles */ 154 #define WDT_EWCTRL_EWOFFSET_16_Val _U_(0x1) /**< \brief (WDT_EWCTRL) 16 clock cycles */ 155 #define WDT_EWCTRL_EWOFFSET_32_Val _U_(0x2) /**< \brief (WDT_EWCTRL) 32 clock cycles */ 156 #define WDT_EWCTRL_EWOFFSET_64_Val _U_(0x3) /**< \brief (WDT_EWCTRL) 64 clock cycles */ 157 #define WDT_EWCTRL_EWOFFSET_128_Val _U_(0x4) /**< \brief (WDT_EWCTRL) 128 clock cycles */ 158 #define WDT_EWCTRL_EWOFFSET_256_Val _U_(0x5) /**< \brief (WDT_EWCTRL) 256 clock cycles */ 159 #define WDT_EWCTRL_EWOFFSET_512_Val _U_(0x6) /**< \brief (WDT_EWCTRL) 512 clock cycles */ 160 #define WDT_EWCTRL_EWOFFSET_1K_Val _U_(0x7) /**< \brief (WDT_EWCTRL) 1024 clock cycles */ 161 #define WDT_EWCTRL_EWOFFSET_2K_Val _U_(0x8) /**< \brief (WDT_EWCTRL) 2048 clock cycles */ 162 #define WDT_EWCTRL_EWOFFSET_4K_Val _U_(0x9) /**< \brief (WDT_EWCTRL) 4096 clock cycles */ 163 #define WDT_EWCTRL_EWOFFSET_8K_Val _U_(0xA) /**< \brief (WDT_EWCTRL) 8192 clock cycles */ 164 #define WDT_EWCTRL_EWOFFSET_16K_Val _U_(0xB) /**< \brief (WDT_EWCTRL) 16384 clock cycles */ 165 #define WDT_EWCTRL_EWOFFSET_8 (WDT_EWCTRL_EWOFFSET_8_Val << WDT_EWCTRL_EWOFFSET_Pos) 166 #define WDT_EWCTRL_EWOFFSET_16 (WDT_EWCTRL_EWOFFSET_16_Val << WDT_EWCTRL_EWOFFSET_Pos) 167 #define WDT_EWCTRL_EWOFFSET_32 (WDT_EWCTRL_EWOFFSET_32_Val << WDT_EWCTRL_EWOFFSET_Pos) 168 #define WDT_EWCTRL_EWOFFSET_64 (WDT_EWCTRL_EWOFFSET_64_Val << WDT_EWCTRL_EWOFFSET_Pos) 169 #define WDT_EWCTRL_EWOFFSET_128 (WDT_EWCTRL_EWOFFSET_128_Val << WDT_EWCTRL_EWOFFSET_Pos) 170 #define WDT_EWCTRL_EWOFFSET_256 (WDT_EWCTRL_EWOFFSET_256_Val << WDT_EWCTRL_EWOFFSET_Pos) 171 #define WDT_EWCTRL_EWOFFSET_512 (WDT_EWCTRL_EWOFFSET_512_Val << WDT_EWCTRL_EWOFFSET_Pos) 172 #define WDT_EWCTRL_EWOFFSET_1K (WDT_EWCTRL_EWOFFSET_1K_Val << WDT_EWCTRL_EWOFFSET_Pos) 173 #define WDT_EWCTRL_EWOFFSET_2K (WDT_EWCTRL_EWOFFSET_2K_Val << WDT_EWCTRL_EWOFFSET_Pos) 174 #define WDT_EWCTRL_EWOFFSET_4K (WDT_EWCTRL_EWOFFSET_4K_Val << WDT_EWCTRL_EWOFFSET_Pos) 175 #define WDT_EWCTRL_EWOFFSET_8K (WDT_EWCTRL_EWOFFSET_8K_Val << WDT_EWCTRL_EWOFFSET_Pos) 176 #define WDT_EWCTRL_EWOFFSET_16K (WDT_EWCTRL_EWOFFSET_16K_Val << WDT_EWCTRL_EWOFFSET_Pos) 177 #define WDT_EWCTRL_MASK _U_(0x0F) /**< \brief (WDT_EWCTRL) MASK Register */ 178 179 /* -------- WDT_INTENCLR : (WDT Offset: 0x4) (R/W 8) Interrupt Enable Clear -------- */ 180 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 181 typedef union { 182 struct { 183 uint8_t EW:1; /*!< bit: 0 Early Warning Interrupt Enable */ 184 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 185 } bit; /*!< Structure used for bit access */ 186 uint8_t reg; /*!< Type used for register access */ 187 } WDT_INTENCLR_Type; 188 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 189 190 #define WDT_INTENCLR_OFFSET 0x4 /**< \brief (WDT_INTENCLR offset) Interrupt Enable Clear */ 191 #define WDT_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (WDT_INTENCLR reset_value) Interrupt Enable Clear */ 192 193 #define WDT_INTENCLR_EW_Pos 0 /**< \brief (WDT_INTENCLR) Early Warning Interrupt Enable */ 194 #define WDT_INTENCLR_EW (_U_(0x1) << WDT_INTENCLR_EW_Pos) 195 #define WDT_INTENCLR_MASK _U_(0x01) /**< \brief (WDT_INTENCLR) MASK Register */ 196 197 /* -------- WDT_INTENSET : (WDT Offset: 0x5) (R/W 8) Interrupt Enable Set -------- */ 198 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 199 typedef union { 200 struct { 201 uint8_t EW:1; /*!< bit: 0 Early Warning Interrupt Enable */ 202 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 203 } bit; /*!< Structure used for bit access */ 204 uint8_t reg; /*!< Type used for register access */ 205 } WDT_INTENSET_Type; 206 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 207 208 #define WDT_INTENSET_OFFSET 0x5 /**< \brief (WDT_INTENSET offset) Interrupt Enable Set */ 209 #define WDT_INTENSET_RESETVALUE _U_(0x00) /**< \brief (WDT_INTENSET reset_value) Interrupt Enable Set */ 210 211 #define WDT_INTENSET_EW_Pos 0 /**< \brief (WDT_INTENSET) Early Warning Interrupt Enable */ 212 #define WDT_INTENSET_EW (_U_(0x1) << WDT_INTENSET_EW_Pos) 213 #define WDT_INTENSET_MASK _U_(0x01) /**< \brief (WDT_INTENSET) MASK Register */ 214 215 /* -------- WDT_INTFLAG : (WDT Offset: 0x6) (R/W 8) Interrupt Flag Status and Clear -------- */ 216 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 217 typedef union { // __I to avoid read-modify-write on write-to-clear register 218 struct { 219 __I uint8_t EW:1; /*!< bit: 0 Early Warning */ 220 __I uint8_t :7; /*!< bit: 1.. 7 Reserved */ 221 } bit; /*!< Structure used for bit access */ 222 uint8_t reg; /*!< Type used for register access */ 223 } WDT_INTFLAG_Type; 224 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 225 226 #define WDT_INTFLAG_OFFSET 0x6 /**< \brief (WDT_INTFLAG offset) Interrupt Flag Status and Clear */ 227 #define WDT_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (WDT_INTFLAG reset_value) Interrupt Flag Status and Clear */ 228 229 #define WDT_INTFLAG_EW_Pos 0 /**< \brief (WDT_INTFLAG) Early Warning */ 230 #define WDT_INTFLAG_EW (_U_(0x1) << WDT_INTFLAG_EW_Pos) 231 #define WDT_INTFLAG_MASK _U_(0x01) /**< \brief (WDT_INTFLAG) MASK Register */ 232 233 /* -------- WDT_STATUS : (WDT Offset: 0x7) (R/ 8) Status -------- */ 234 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 235 typedef union { 236 struct { 237 uint8_t :7; /*!< bit: 0.. 6 Reserved */ 238 uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */ 239 } bit; /*!< Structure used for bit access */ 240 uint8_t reg; /*!< Type used for register access */ 241 } WDT_STATUS_Type; 242 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 243 244 #define WDT_STATUS_OFFSET 0x7 /**< \brief (WDT_STATUS offset) Status */ 245 #define WDT_STATUS_RESETVALUE _U_(0x00) /**< \brief (WDT_STATUS reset_value) Status */ 246 247 #define WDT_STATUS_SYNCBUSY_Pos 7 /**< \brief (WDT_STATUS) Synchronization Busy */ 248 #define WDT_STATUS_SYNCBUSY (_U_(0x1) << WDT_STATUS_SYNCBUSY_Pos) 249 #define WDT_STATUS_MASK _U_(0x80) /**< \brief (WDT_STATUS) MASK Register */ 250 251 /* -------- WDT_CLEAR : (WDT Offset: 0x8) ( /W 8) Clear -------- */ 252 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 253 typedef union { 254 struct { 255 uint8_t CLEAR:8; /*!< bit: 0.. 7 Watchdog Clear */ 256 } bit; /*!< Structure used for bit access */ 257 uint8_t reg; /*!< Type used for register access */ 258 } WDT_CLEAR_Type; 259 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 260 261 #define WDT_CLEAR_OFFSET 0x8 /**< \brief (WDT_CLEAR offset) Clear */ 262 #define WDT_CLEAR_RESETVALUE _U_(0x00) /**< \brief (WDT_CLEAR reset_value) Clear */ 263 264 #define WDT_CLEAR_CLEAR_Pos 0 /**< \brief (WDT_CLEAR) Watchdog Clear */ 265 #define WDT_CLEAR_CLEAR_Msk (_U_(0xFF) << WDT_CLEAR_CLEAR_Pos) 266 #define WDT_CLEAR_CLEAR(value) (WDT_CLEAR_CLEAR_Msk & ((value) << WDT_CLEAR_CLEAR_Pos)) 267 #define WDT_CLEAR_CLEAR_KEY_Val _U_(0xA5) /**< \brief (WDT_CLEAR) Clear Key */ 268 #define WDT_CLEAR_CLEAR_KEY (WDT_CLEAR_CLEAR_KEY_Val << WDT_CLEAR_CLEAR_Pos) 269 #define WDT_CLEAR_MASK _U_(0xFF) /**< \brief (WDT_CLEAR) MASK Register */ 270 271 /** \brief WDT hardware registers */ 272 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 273 typedef struct { 274 __IO WDT_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */ 275 __IO WDT_CONFIG_Type CONFIG; /**< \brief Offset: 0x1 (R/W 8) Configuration */ 276 __IO WDT_EWCTRL_Type EWCTRL; /**< \brief Offset: 0x2 (R/W 8) Early Warning Interrupt Control */ 277 RoReg8 Reserved1[0x1]; 278 __IO WDT_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x4 (R/W 8) Interrupt Enable Clear */ 279 __IO WDT_INTENSET_Type INTENSET; /**< \brief Offset: 0x5 (R/W 8) Interrupt Enable Set */ 280 __IO WDT_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x6 (R/W 8) Interrupt Flag Status and Clear */ 281 __I WDT_STATUS_Type STATUS; /**< \brief Offset: 0x7 (R/ 8) Status */ 282 __O WDT_CLEAR_Type CLEAR; /**< \brief Offset: 0x8 ( /W 8) Clear */ 283 } Wdt; 284 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 285 286 /*@}*/ 287 288 #endif /* _SAMD21_WDT_COMPONENT_ */ 289
