1 /** 2 * \file 3 * 4 * \brief Component description for RTC 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAMD21_RTC_COMPONENT_ 30 #define _SAMD21_RTC_COMPONENT_ 31 32 /* ========================================================================== */ 33 /** SOFTWARE API DEFINITION FOR RTC */ 34 /* ========================================================================== */ 35 /** \addtogroup SAMD21_RTC Real-Time Counter */ 36 /*@{*/ 37 38 #define RTC_U2202 39 #define REV_RTC 0x101 40 41 /* -------- RTC_MODE0_CTRL : (RTC Offset: 0x00) (R/W 16) MODE0 MODE0 Control -------- */ 42 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 43 typedef union { 44 struct { 45 uint16_t SWRST:1; /*!< bit: 0 Software Reset */ 46 uint16_t ENABLE:1; /*!< bit: 1 Enable */ 47 uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */ 48 uint16_t :3; /*!< bit: 4.. 6 Reserved */ 49 uint16_t MATCHCLR:1; /*!< bit: 7 Clear on Match */ 50 uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */ 51 uint16_t :4; /*!< bit: 12..15 Reserved */ 52 } bit; /*!< Structure used for bit access */ 53 uint16_t reg; /*!< Type used for register access */ 54 } RTC_MODE0_CTRL_Type; 55 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 56 57 #define RTC_MODE0_CTRL_OFFSET 0x00 /**< \brief (RTC_MODE0_CTRL offset) MODE0 Control */ 58 #define RTC_MODE0_CTRL_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE0_CTRL reset_value) MODE0 Control */ 59 60 #define RTC_MODE0_CTRL_SWRST_Pos 0 /**< \brief (RTC_MODE0_CTRL) Software Reset */ 61 #define RTC_MODE0_CTRL_SWRST (_U_(0x1) << RTC_MODE0_CTRL_SWRST_Pos) 62 #define RTC_MODE0_CTRL_ENABLE_Pos 1 /**< \brief (RTC_MODE0_CTRL) Enable */ 63 #define RTC_MODE0_CTRL_ENABLE (_U_(0x1) << RTC_MODE0_CTRL_ENABLE_Pos) 64 #define RTC_MODE0_CTRL_MODE_Pos 2 /**< \brief (RTC_MODE0_CTRL) Operating Mode */ 65 #define RTC_MODE0_CTRL_MODE_Msk (_U_(0x3) << RTC_MODE0_CTRL_MODE_Pos) 66 #define RTC_MODE0_CTRL_MODE(value) (RTC_MODE0_CTRL_MODE_Msk & ((value) << RTC_MODE0_CTRL_MODE_Pos)) 67 #define RTC_MODE0_CTRL_MODE_COUNT32_Val _U_(0x0) /**< \brief (RTC_MODE0_CTRL) Mode 0: 32-bit Counter */ 68 #define RTC_MODE0_CTRL_MODE_COUNT16_Val _U_(0x1) /**< \brief (RTC_MODE0_CTRL) Mode 1: 16-bit Counter */ 69 #define RTC_MODE0_CTRL_MODE_CLOCK_Val _U_(0x2) /**< \brief (RTC_MODE0_CTRL) Mode 2: Clock/Calendar */ 70 #define RTC_MODE0_CTRL_MODE_COUNT32 (RTC_MODE0_CTRL_MODE_COUNT32_Val << RTC_MODE0_CTRL_MODE_Pos) 71 #define RTC_MODE0_CTRL_MODE_COUNT16 (RTC_MODE0_CTRL_MODE_COUNT16_Val << RTC_MODE0_CTRL_MODE_Pos) 72 #define RTC_MODE0_CTRL_MODE_CLOCK (RTC_MODE0_CTRL_MODE_CLOCK_Val << RTC_MODE0_CTRL_MODE_Pos) 73 #define RTC_MODE0_CTRL_MATCHCLR_Pos 7 /**< \brief (RTC_MODE0_CTRL) Clear on Match */ 74 #define RTC_MODE0_CTRL_MATCHCLR (_U_(0x1) << RTC_MODE0_CTRL_MATCHCLR_Pos) 75 #define RTC_MODE0_CTRL_PRESCALER_Pos 8 /**< \brief (RTC_MODE0_CTRL) Prescaler */ 76 #define RTC_MODE0_CTRL_PRESCALER_Msk (_U_(0xF) << RTC_MODE0_CTRL_PRESCALER_Pos) 77 #define RTC_MODE0_CTRL_PRESCALER(value) (RTC_MODE0_CTRL_PRESCALER_Msk & ((value) << RTC_MODE0_CTRL_PRESCALER_Pos)) 78 #define RTC_MODE0_CTRL_PRESCALER_DIV1_Val _U_(0x0) /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/1 */ 79 #define RTC_MODE0_CTRL_PRESCALER_DIV2_Val _U_(0x1) /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/2 */ 80 #define RTC_MODE0_CTRL_PRESCALER_DIV4_Val _U_(0x2) /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/4 */ 81 #define RTC_MODE0_CTRL_PRESCALER_DIV8_Val _U_(0x3) /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/8 */ 82 #define RTC_MODE0_CTRL_PRESCALER_DIV16_Val _U_(0x4) /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/16 */ 83 #define RTC_MODE0_CTRL_PRESCALER_DIV32_Val _U_(0x5) /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/32 */ 84 #define RTC_MODE0_CTRL_PRESCALER_DIV64_Val _U_(0x6) /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/64 */ 85 #define RTC_MODE0_CTRL_PRESCALER_DIV128_Val _U_(0x7) /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/128 */ 86 #define RTC_MODE0_CTRL_PRESCALER_DIV256_Val _U_(0x8) /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/256 */ 87 #define RTC_MODE0_CTRL_PRESCALER_DIV512_Val _U_(0x9) /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/512 */ 88 #define RTC_MODE0_CTRL_PRESCALER_DIV1024_Val _U_(0xA) /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/1024 */ 89 #define RTC_MODE0_CTRL_PRESCALER_DIV1 (RTC_MODE0_CTRL_PRESCALER_DIV1_Val << RTC_MODE0_CTRL_PRESCALER_Pos) 90 #define RTC_MODE0_CTRL_PRESCALER_DIV2 (RTC_MODE0_CTRL_PRESCALER_DIV2_Val << RTC_MODE0_CTRL_PRESCALER_Pos) 91 #define RTC_MODE0_CTRL_PRESCALER_DIV4 (RTC_MODE0_CTRL_PRESCALER_DIV4_Val << RTC_MODE0_CTRL_PRESCALER_Pos) 92 #define RTC_MODE0_CTRL_PRESCALER_DIV8 (RTC_MODE0_CTRL_PRESCALER_DIV8_Val << RTC_MODE0_CTRL_PRESCALER_Pos) 93 #define RTC_MODE0_CTRL_PRESCALER_DIV16 (RTC_MODE0_CTRL_PRESCALER_DIV16_Val << RTC_MODE0_CTRL_PRESCALER_Pos) 94 #define RTC_MODE0_CTRL_PRESCALER_DIV32 (RTC_MODE0_CTRL_PRESCALER_DIV32_Val << RTC_MODE0_CTRL_PRESCALER_Pos) 95 #define RTC_MODE0_CTRL_PRESCALER_DIV64 (RTC_MODE0_CTRL_PRESCALER_DIV64_Val << RTC_MODE0_CTRL_PRESCALER_Pos) 96 #define RTC_MODE0_CTRL_PRESCALER_DIV128 (RTC_MODE0_CTRL_PRESCALER_DIV128_Val << RTC_MODE0_CTRL_PRESCALER_Pos) 97 #define RTC_MODE0_CTRL_PRESCALER_DIV256 (RTC_MODE0_CTRL_PRESCALER_DIV256_Val << RTC_MODE0_CTRL_PRESCALER_Pos) 98 #define RTC_MODE0_CTRL_PRESCALER_DIV512 (RTC_MODE0_CTRL_PRESCALER_DIV512_Val << RTC_MODE0_CTRL_PRESCALER_Pos) 99 #define RTC_MODE0_CTRL_PRESCALER_DIV1024 (RTC_MODE0_CTRL_PRESCALER_DIV1024_Val << RTC_MODE0_CTRL_PRESCALER_Pos) 100 #define RTC_MODE0_CTRL_MASK _U_(0x0F8F) /**< \brief (RTC_MODE0_CTRL) MASK Register */ 101 102 /* -------- RTC_MODE1_CTRL : (RTC Offset: 0x00) (R/W 16) MODE1 MODE1 Control -------- */ 103 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 104 typedef union { 105 struct { 106 uint16_t SWRST:1; /*!< bit: 0 Software Reset */ 107 uint16_t ENABLE:1; /*!< bit: 1 Enable */ 108 uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */ 109 uint16_t :4; /*!< bit: 4.. 7 Reserved */ 110 uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */ 111 uint16_t :4; /*!< bit: 12..15 Reserved */ 112 } bit; /*!< Structure used for bit access */ 113 uint16_t reg; /*!< Type used for register access */ 114 } RTC_MODE1_CTRL_Type; 115 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 116 117 #define RTC_MODE1_CTRL_OFFSET 0x00 /**< \brief (RTC_MODE1_CTRL offset) MODE1 Control */ 118 #define RTC_MODE1_CTRL_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE1_CTRL reset_value) MODE1 Control */ 119 120 #define RTC_MODE1_CTRL_SWRST_Pos 0 /**< \brief (RTC_MODE1_CTRL) Software Reset */ 121 #define RTC_MODE1_CTRL_SWRST (_U_(0x1) << RTC_MODE1_CTRL_SWRST_Pos) 122 #define RTC_MODE1_CTRL_ENABLE_Pos 1 /**< \brief (RTC_MODE1_CTRL) Enable */ 123 #define RTC_MODE1_CTRL_ENABLE (_U_(0x1) << RTC_MODE1_CTRL_ENABLE_Pos) 124 #define RTC_MODE1_CTRL_MODE_Pos 2 /**< \brief (RTC_MODE1_CTRL) Operating Mode */ 125 #define RTC_MODE1_CTRL_MODE_Msk (_U_(0x3) << RTC_MODE1_CTRL_MODE_Pos) 126 #define RTC_MODE1_CTRL_MODE(value) (RTC_MODE1_CTRL_MODE_Msk & ((value) << RTC_MODE1_CTRL_MODE_Pos)) 127 #define RTC_MODE1_CTRL_MODE_COUNT32_Val _U_(0x0) /**< \brief (RTC_MODE1_CTRL) Mode 0: 32-bit Counter */ 128 #define RTC_MODE1_CTRL_MODE_COUNT16_Val _U_(0x1) /**< \brief (RTC_MODE1_CTRL) Mode 1: 16-bit Counter */ 129 #define RTC_MODE1_CTRL_MODE_CLOCK_Val _U_(0x2) /**< \brief (RTC_MODE1_CTRL) Mode 2: Clock/Calendar */ 130 #define RTC_MODE1_CTRL_MODE_COUNT32 (RTC_MODE1_CTRL_MODE_COUNT32_Val << RTC_MODE1_CTRL_MODE_Pos) 131 #define RTC_MODE1_CTRL_MODE_COUNT16 (RTC_MODE1_CTRL_MODE_COUNT16_Val << RTC_MODE1_CTRL_MODE_Pos) 132 #define RTC_MODE1_CTRL_MODE_CLOCK (RTC_MODE1_CTRL_MODE_CLOCK_Val << RTC_MODE1_CTRL_MODE_Pos) 133 #define RTC_MODE1_CTRL_PRESCALER_Pos 8 /**< \brief (RTC_MODE1_CTRL) Prescaler */ 134 #define RTC_MODE1_CTRL_PRESCALER_Msk (_U_(0xF) << RTC_MODE1_CTRL_PRESCALER_Pos) 135 #define RTC_MODE1_CTRL_PRESCALER(value) (RTC_MODE1_CTRL_PRESCALER_Msk & ((value) << RTC_MODE1_CTRL_PRESCALER_Pos)) 136 #define RTC_MODE1_CTRL_PRESCALER_DIV1_Val _U_(0x0) /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/1 */ 137 #define RTC_MODE1_CTRL_PRESCALER_DIV2_Val _U_(0x1) /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/2 */ 138 #define RTC_MODE1_CTRL_PRESCALER_DIV4_Val _U_(0x2) /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/4 */ 139 #define RTC_MODE1_CTRL_PRESCALER_DIV8_Val _U_(0x3) /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/8 */ 140 #define RTC_MODE1_CTRL_PRESCALER_DIV16_Val _U_(0x4) /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/16 */ 141 #define RTC_MODE1_CTRL_PRESCALER_DIV32_Val _U_(0x5) /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/32 */ 142 #define RTC_MODE1_CTRL_PRESCALER_DIV64_Val _U_(0x6) /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/64 */ 143 #define RTC_MODE1_CTRL_PRESCALER_DIV128_Val _U_(0x7) /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/128 */ 144 #define RTC_MODE1_CTRL_PRESCALER_DIV256_Val _U_(0x8) /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/256 */ 145 #define RTC_MODE1_CTRL_PRESCALER_DIV512_Val _U_(0x9) /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/512 */ 146 #define RTC_MODE1_CTRL_PRESCALER_DIV1024_Val _U_(0xA) /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/1024 */ 147 #define RTC_MODE1_CTRL_PRESCALER_DIV1 (RTC_MODE1_CTRL_PRESCALER_DIV1_Val << RTC_MODE1_CTRL_PRESCALER_Pos) 148 #define RTC_MODE1_CTRL_PRESCALER_DIV2 (RTC_MODE1_CTRL_PRESCALER_DIV2_Val << RTC_MODE1_CTRL_PRESCALER_Pos) 149 #define RTC_MODE1_CTRL_PRESCALER_DIV4 (RTC_MODE1_CTRL_PRESCALER_DIV4_Val << RTC_MODE1_CTRL_PRESCALER_Pos) 150 #define RTC_MODE1_CTRL_PRESCALER_DIV8 (RTC_MODE1_CTRL_PRESCALER_DIV8_Val << RTC_MODE1_CTRL_PRESCALER_Pos) 151 #define RTC_MODE1_CTRL_PRESCALER_DIV16 (RTC_MODE1_CTRL_PRESCALER_DIV16_Val << RTC_MODE1_CTRL_PRESCALER_Pos) 152 #define RTC_MODE1_CTRL_PRESCALER_DIV32 (RTC_MODE1_CTRL_PRESCALER_DIV32_Val << RTC_MODE1_CTRL_PRESCALER_Pos) 153 #define RTC_MODE1_CTRL_PRESCALER_DIV64 (RTC_MODE1_CTRL_PRESCALER_DIV64_Val << RTC_MODE1_CTRL_PRESCALER_Pos) 154 #define RTC_MODE1_CTRL_PRESCALER_DIV128 (RTC_MODE1_CTRL_PRESCALER_DIV128_Val << RTC_MODE1_CTRL_PRESCALER_Pos) 155 #define RTC_MODE1_CTRL_PRESCALER_DIV256 (RTC_MODE1_CTRL_PRESCALER_DIV256_Val << RTC_MODE1_CTRL_PRESCALER_Pos) 156 #define RTC_MODE1_CTRL_PRESCALER_DIV512 (RTC_MODE1_CTRL_PRESCALER_DIV512_Val << RTC_MODE1_CTRL_PRESCALER_Pos) 157 #define RTC_MODE1_CTRL_PRESCALER_DIV1024 (RTC_MODE1_CTRL_PRESCALER_DIV1024_Val << RTC_MODE1_CTRL_PRESCALER_Pos) 158 #define RTC_MODE1_CTRL_MASK _U_(0x0F0F) /**< \brief (RTC_MODE1_CTRL) MASK Register */ 159 160 /* -------- RTC_MODE2_CTRL : (RTC Offset: 0x00) (R/W 16) MODE2 MODE2 Control -------- */ 161 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 162 typedef union { 163 struct { 164 uint16_t SWRST:1; /*!< bit: 0 Software Reset */ 165 uint16_t ENABLE:1; /*!< bit: 1 Enable */ 166 uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */ 167 uint16_t :2; /*!< bit: 4.. 5 Reserved */ 168 uint16_t CLKREP:1; /*!< bit: 6 Clock Representation */ 169 uint16_t MATCHCLR:1; /*!< bit: 7 Clear on Match */ 170 uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */ 171 uint16_t :4; /*!< bit: 12..15 Reserved */ 172 } bit; /*!< Structure used for bit access */ 173 uint16_t reg; /*!< Type used for register access */ 174 } RTC_MODE2_CTRL_Type; 175 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 176 177 #define RTC_MODE2_CTRL_OFFSET 0x00 /**< \brief (RTC_MODE2_CTRL offset) MODE2 Control */ 178 #define RTC_MODE2_CTRL_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE2_CTRL reset_value) MODE2 Control */ 179 180 #define RTC_MODE2_CTRL_SWRST_Pos 0 /**< \brief (RTC_MODE2_CTRL) Software Reset */ 181 #define RTC_MODE2_CTRL_SWRST (_U_(0x1) << RTC_MODE2_CTRL_SWRST_Pos) 182 #define RTC_MODE2_CTRL_ENABLE_Pos 1 /**< \brief (RTC_MODE2_CTRL) Enable */ 183 #define RTC_MODE2_CTRL_ENABLE (_U_(0x1) << RTC_MODE2_CTRL_ENABLE_Pos) 184 #define RTC_MODE2_CTRL_MODE_Pos 2 /**< \brief (RTC_MODE2_CTRL) Operating Mode */ 185 #define RTC_MODE2_CTRL_MODE_Msk (_U_(0x3) << RTC_MODE2_CTRL_MODE_Pos) 186 #define RTC_MODE2_CTRL_MODE(value) (RTC_MODE2_CTRL_MODE_Msk & ((value) << RTC_MODE2_CTRL_MODE_Pos)) 187 #define RTC_MODE2_CTRL_MODE_COUNT32_Val _U_(0x0) /**< \brief (RTC_MODE2_CTRL) Mode 0: 32-bit Counter */ 188 #define RTC_MODE2_CTRL_MODE_COUNT16_Val _U_(0x1) /**< \brief (RTC_MODE2_CTRL) Mode 1: 16-bit Counter */ 189 #define RTC_MODE2_CTRL_MODE_CLOCK_Val _U_(0x2) /**< \brief (RTC_MODE2_CTRL) Mode 2: Clock/Calendar */ 190 #define RTC_MODE2_CTRL_MODE_COUNT32 (RTC_MODE2_CTRL_MODE_COUNT32_Val << RTC_MODE2_CTRL_MODE_Pos) 191 #define RTC_MODE2_CTRL_MODE_COUNT16 (RTC_MODE2_CTRL_MODE_COUNT16_Val << RTC_MODE2_CTRL_MODE_Pos) 192 #define RTC_MODE2_CTRL_MODE_CLOCK (RTC_MODE2_CTRL_MODE_CLOCK_Val << RTC_MODE2_CTRL_MODE_Pos) 193 #define RTC_MODE2_CTRL_CLKREP_Pos 6 /**< \brief (RTC_MODE2_CTRL) Clock Representation */ 194 #define RTC_MODE2_CTRL_CLKREP (_U_(0x1) << RTC_MODE2_CTRL_CLKREP_Pos) 195 #define RTC_MODE2_CTRL_MATCHCLR_Pos 7 /**< \brief (RTC_MODE2_CTRL) Clear on Match */ 196 #define RTC_MODE2_CTRL_MATCHCLR (_U_(0x1) << RTC_MODE2_CTRL_MATCHCLR_Pos) 197 #define RTC_MODE2_CTRL_PRESCALER_Pos 8 /**< \brief (RTC_MODE2_CTRL) Prescaler */ 198 #define RTC_MODE2_CTRL_PRESCALER_Msk (_U_(0xF) << RTC_MODE2_CTRL_PRESCALER_Pos) 199 #define RTC_MODE2_CTRL_PRESCALER(value) (RTC_MODE2_CTRL_PRESCALER_Msk & ((value) << RTC_MODE2_CTRL_PRESCALER_Pos)) 200 #define RTC_MODE2_CTRL_PRESCALER_DIV1_Val _U_(0x0) /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/1 */ 201 #define RTC_MODE2_CTRL_PRESCALER_DIV2_Val _U_(0x1) /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/2 */ 202 #define RTC_MODE2_CTRL_PRESCALER_DIV4_Val _U_(0x2) /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/4 */ 203 #define RTC_MODE2_CTRL_PRESCALER_DIV8_Val _U_(0x3) /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/8 */ 204 #define RTC_MODE2_CTRL_PRESCALER_DIV16_Val _U_(0x4) /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/16 */ 205 #define RTC_MODE2_CTRL_PRESCALER_DIV32_Val _U_(0x5) /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/32 */ 206 #define RTC_MODE2_CTRL_PRESCALER_DIV64_Val _U_(0x6) /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/64 */ 207 #define RTC_MODE2_CTRL_PRESCALER_DIV128_Val _U_(0x7) /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/128 */ 208 #define RTC_MODE2_CTRL_PRESCALER_DIV256_Val _U_(0x8) /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/256 */ 209 #define RTC_MODE2_CTRL_PRESCALER_DIV512_Val _U_(0x9) /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/512 */ 210 #define RTC_MODE2_CTRL_PRESCALER_DIV1024_Val _U_(0xA) /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/1024 */ 211 #define RTC_MODE2_CTRL_PRESCALER_DIV1 (RTC_MODE2_CTRL_PRESCALER_DIV1_Val << RTC_MODE2_CTRL_PRESCALER_Pos) 212 #define RTC_MODE2_CTRL_PRESCALER_DIV2 (RTC_MODE2_CTRL_PRESCALER_DIV2_Val << RTC_MODE2_CTRL_PRESCALER_Pos) 213 #define RTC_MODE2_CTRL_PRESCALER_DIV4 (RTC_MODE2_CTRL_PRESCALER_DIV4_Val << RTC_MODE2_CTRL_PRESCALER_Pos) 214 #define RTC_MODE2_CTRL_PRESCALER_DIV8 (RTC_MODE2_CTRL_PRESCALER_DIV8_Val << RTC_MODE2_CTRL_PRESCALER_Pos) 215 #define RTC_MODE2_CTRL_PRESCALER_DIV16 (RTC_MODE2_CTRL_PRESCALER_DIV16_Val << RTC_MODE2_CTRL_PRESCALER_Pos) 216 #define RTC_MODE2_CTRL_PRESCALER_DIV32 (RTC_MODE2_CTRL_PRESCALER_DIV32_Val << RTC_MODE2_CTRL_PRESCALER_Pos) 217 #define RTC_MODE2_CTRL_PRESCALER_DIV64 (RTC_MODE2_CTRL_PRESCALER_DIV64_Val << RTC_MODE2_CTRL_PRESCALER_Pos) 218 #define RTC_MODE2_CTRL_PRESCALER_DIV128 (RTC_MODE2_CTRL_PRESCALER_DIV128_Val << RTC_MODE2_CTRL_PRESCALER_Pos) 219 #define RTC_MODE2_CTRL_PRESCALER_DIV256 (RTC_MODE2_CTRL_PRESCALER_DIV256_Val << RTC_MODE2_CTRL_PRESCALER_Pos) 220 #define RTC_MODE2_CTRL_PRESCALER_DIV512 (RTC_MODE2_CTRL_PRESCALER_DIV512_Val << RTC_MODE2_CTRL_PRESCALER_Pos) 221 #define RTC_MODE2_CTRL_PRESCALER_DIV1024 (RTC_MODE2_CTRL_PRESCALER_DIV1024_Val << RTC_MODE2_CTRL_PRESCALER_Pos) 222 #define RTC_MODE2_CTRL_MASK _U_(0x0FCF) /**< \brief (RTC_MODE2_CTRL) MASK Register */ 223 224 /* -------- RTC_READREQ : (RTC Offset: 0x02) (R/W 16) Read Request -------- */ 225 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 226 typedef union { 227 struct { 228 uint16_t ADDR:6; /*!< bit: 0.. 5 Address */ 229 uint16_t :8; /*!< bit: 6..13 Reserved */ 230 uint16_t RCONT:1; /*!< bit: 14 Read Continuously */ 231 uint16_t RREQ:1; /*!< bit: 15 Read Request */ 232 } bit; /*!< Structure used for bit access */ 233 uint16_t reg; /*!< Type used for register access */ 234 } RTC_READREQ_Type; 235 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 236 237 #define RTC_READREQ_OFFSET 0x02 /**< \brief (RTC_READREQ offset) Read Request */ 238 #define RTC_READREQ_RESETVALUE _U_(0x0010) /**< \brief (RTC_READREQ reset_value) Read Request */ 239 240 #define RTC_READREQ_ADDR_Pos 0 /**< \brief (RTC_READREQ) Address */ 241 #define RTC_READREQ_ADDR_Msk (_U_(0x3F) << RTC_READREQ_ADDR_Pos) 242 #define RTC_READREQ_ADDR(value) (RTC_READREQ_ADDR_Msk & ((value) << RTC_READREQ_ADDR_Pos)) 243 #define RTC_READREQ_RCONT_Pos 14 /**< \brief (RTC_READREQ) Read Continuously */ 244 #define RTC_READREQ_RCONT (_U_(0x1) << RTC_READREQ_RCONT_Pos) 245 #define RTC_READREQ_RREQ_Pos 15 /**< \brief (RTC_READREQ) Read Request */ 246 #define RTC_READREQ_RREQ (_U_(0x1) << RTC_READREQ_RREQ_Pos) 247 #define RTC_READREQ_MASK _U_(0xC03F) /**< \brief (RTC_READREQ) MASK Register */ 248 249 /* -------- RTC_MODE0_EVCTRL : (RTC Offset: 0x04) (R/W 16) MODE0 MODE0 Event Control -------- */ 250 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 251 typedef union { 252 struct { 253 uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */ 254 uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */ 255 uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */ 256 uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */ 257 uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */ 258 uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */ 259 uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */ 260 uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */ 261 uint16_t CMPEO0:1; /*!< bit: 8 Compare 0 Event Output Enable */ 262 uint16_t :6; /*!< bit: 9..14 Reserved */ 263 uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */ 264 } bit; /*!< Structure used for bit access */ 265 struct { 266 uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */ 267 uint16_t CMPEO:1; /*!< bit: 8 Compare x Event Output Enable */ 268 uint16_t :7; /*!< bit: 9..15 Reserved */ 269 } vec; /*!< Structure used for vec access */ 270 uint16_t reg; /*!< Type used for register access */ 271 } RTC_MODE0_EVCTRL_Type; 272 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 273 274 #define RTC_MODE0_EVCTRL_OFFSET 0x04 /**< \brief (RTC_MODE0_EVCTRL offset) MODE0 Event Control */ 275 #define RTC_MODE0_EVCTRL_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE0_EVCTRL reset_value) MODE0 Event Control */ 276 277 #define RTC_MODE0_EVCTRL_PEREO0_Pos 0 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 0 Event Output Enable */ 278 #define RTC_MODE0_EVCTRL_PEREO0 (1 << RTC_MODE0_EVCTRL_PEREO0_Pos) 279 #define RTC_MODE0_EVCTRL_PEREO1_Pos 1 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 1 Event Output Enable */ 280 #define RTC_MODE0_EVCTRL_PEREO1 (1 << RTC_MODE0_EVCTRL_PEREO1_Pos) 281 #define RTC_MODE0_EVCTRL_PEREO2_Pos 2 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 2 Event Output Enable */ 282 #define RTC_MODE0_EVCTRL_PEREO2 (1 << RTC_MODE0_EVCTRL_PEREO2_Pos) 283 #define RTC_MODE0_EVCTRL_PEREO3_Pos 3 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 3 Event Output Enable */ 284 #define RTC_MODE0_EVCTRL_PEREO3 (1 << RTC_MODE0_EVCTRL_PEREO3_Pos) 285 #define RTC_MODE0_EVCTRL_PEREO4_Pos 4 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 4 Event Output Enable */ 286 #define RTC_MODE0_EVCTRL_PEREO4 (1 << RTC_MODE0_EVCTRL_PEREO4_Pos) 287 #define RTC_MODE0_EVCTRL_PEREO5_Pos 5 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 5 Event Output Enable */ 288 #define RTC_MODE0_EVCTRL_PEREO5 (1 << RTC_MODE0_EVCTRL_PEREO5_Pos) 289 #define RTC_MODE0_EVCTRL_PEREO6_Pos 6 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 6 Event Output Enable */ 290 #define RTC_MODE0_EVCTRL_PEREO6 (1 << RTC_MODE0_EVCTRL_PEREO6_Pos) 291 #define RTC_MODE0_EVCTRL_PEREO7_Pos 7 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 7 Event Output Enable */ 292 #define RTC_MODE0_EVCTRL_PEREO7 (1 << RTC_MODE0_EVCTRL_PEREO7_Pos) 293 #define RTC_MODE0_EVCTRL_PEREO_Pos 0 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval x Event Output Enable */ 294 #define RTC_MODE0_EVCTRL_PEREO_Msk (_U_(0xFF) << RTC_MODE0_EVCTRL_PEREO_Pos) 295 #define RTC_MODE0_EVCTRL_PEREO(value) (RTC_MODE0_EVCTRL_PEREO_Msk & ((value) << RTC_MODE0_EVCTRL_PEREO_Pos)) 296 #define RTC_MODE0_EVCTRL_CMPEO0_Pos 8 /**< \brief (RTC_MODE0_EVCTRL) Compare 0 Event Output Enable */ 297 #define RTC_MODE0_EVCTRL_CMPEO0 (1 << RTC_MODE0_EVCTRL_CMPEO0_Pos) 298 #define RTC_MODE0_EVCTRL_CMPEO_Pos 8 /**< \brief (RTC_MODE0_EVCTRL) Compare x Event Output Enable */ 299 #define RTC_MODE0_EVCTRL_CMPEO_Msk (_U_(0x1) << RTC_MODE0_EVCTRL_CMPEO_Pos) 300 #define RTC_MODE0_EVCTRL_CMPEO(value) (RTC_MODE0_EVCTRL_CMPEO_Msk & ((value) << RTC_MODE0_EVCTRL_CMPEO_Pos)) 301 #define RTC_MODE0_EVCTRL_OVFEO_Pos 15 /**< \brief (RTC_MODE0_EVCTRL) Overflow Event Output Enable */ 302 #define RTC_MODE0_EVCTRL_OVFEO (_U_(0x1) << RTC_MODE0_EVCTRL_OVFEO_Pos) 303 #define RTC_MODE0_EVCTRL_MASK _U_(0x81FF) /**< \brief (RTC_MODE0_EVCTRL) MASK Register */ 304 305 /* -------- RTC_MODE1_EVCTRL : (RTC Offset: 0x04) (R/W 16) MODE1 MODE1 Event Control -------- */ 306 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 307 typedef union { 308 struct { 309 uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */ 310 uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */ 311 uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */ 312 uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */ 313 uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */ 314 uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */ 315 uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */ 316 uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */ 317 uint16_t CMPEO0:1; /*!< bit: 8 Compare 0 Event Output Enable */ 318 uint16_t CMPEO1:1; /*!< bit: 9 Compare 1 Event Output Enable */ 319 uint16_t :5; /*!< bit: 10..14 Reserved */ 320 uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */ 321 } bit; /*!< Structure used for bit access */ 322 struct { 323 uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */ 324 uint16_t CMPEO:2; /*!< bit: 8.. 9 Compare x Event Output Enable */ 325 uint16_t :6; /*!< bit: 10..15 Reserved */ 326 } vec; /*!< Structure used for vec access */ 327 uint16_t reg; /*!< Type used for register access */ 328 } RTC_MODE1_EVCTRL_Type; 329 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 330 331 #define RTC_MODE1_EVCTRL_OFFSET 0x04 /**< \brief (RTC_MODE1_EVCTRL offset) MODE1 Event Control */ 332 #define RTC_MODE1_EVCTRL_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE1_EVCTRL reset_value) MODE1 Event Control */ 333 334 #define RTC_MODE1_EVCTRL_PEREO0_Pos 0 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 0 Event Output Enable */ 335 #define RTC_MODE1_EVCTRL_PEREO0 (1 << RTC_MODE1_EVCTRL_PEREO0_Pos) 336 #define RTC_MODE1_EVCTRL_PEREO1_Pos 1 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 1 Event Output Enable */ 337 #define RTC_MODE1_EVCTRL_PEREO1 (1 << RTC_MODE1_EVCTRL_PEREO1_Pos) 338 #define RTC_MODE1_EVCTRL_PEREO2_Pos 2 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 2 Event Output Enable */ 339 #define RTC_MODE1_EVCTRL_PEREO2 (1 << RTC_MODE1_EVCTRL_PEREO2_Pos) 340 #define RTC_MODE1_EVCTRL_PEREO3_Pos 3 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 3 Event Output Enable */ 341 #define RTC_MODE1_EVCTRL_PEREO3 (1 << RTC_MODE1_EVCTRL_PEREO3_Pos) 342 #define RTC_MODE1_EVCTRL_PEREO4_Pos 4 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 4 Event Output Enable */ 343 #define RTC_MODE1_EVCTRL_PEREO4 (1 << RTC_MODE1_EVCTRL_PEREO4_Pos) 344 #define RTC_MODE1_EVCTRL_PEREO5_Pos 5 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 5 Event Output Enable */ 345 #define RTC_MODE1_EVCTRL_PEREO5 (1 << RTC_MODE1_EVCTRL_PEREO5_Pos) 346 #define RTC_MODE1_EVCTRL_PEREO6_Pos 6 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 6 Event Output Enable */ 347 #define RTC_MODE1_EVCTRL_PEREO6 (1 << RTC_MODE1_EVCTRL_PEREO6_Pos) 348 #define RTC_MODE1_EVCTRL_PEREO7_Pos 7 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 7 Event Output Enable */ 349 #define RTC_MODE1_EVCTRL_PEREO7 (1 << RTC_MODE1_EVCTRL_PEREO7_Pos) 350 #define RTC_MODE1_EVCTRL_PEREO_Pos 0 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval x Event Output Enable */ 351 #define RTC_MODE1_EVCTRL_PEREO_Msk (_U_(0xFF) << RTC_MODE1_EVCTRL_PEREO_Pos) 352 #define RTC_MODE1_EVCTRL_PEREO(value) (RTC_MODE1_EVCTRL_PEREO_Msk & ((value) << RTC_MODE1_EVCTRL_PEREO_Pos)) 353 #define RTC_MODE1_EVCTRL_CMPEO0_Pos 8 /**< \brief (RTC_MODE1_EVCTRL) Compare 0 Event Output Enable */ 354 #define RTC_MODE1_EVCTRL_CMPEO0 (1 << RTC_MODE1_EVCTRL_CMPEO0_Pos) 355 #define RTC_MODE1_EVCTRL_CMPEO1_Pos 9 /**< \brief (RTC_MODE1_EVCTRL) Compare 1 Event Output Enable */ 356 #define RTC_MODE1_EVCTRL_CMPEO1 (1 << RTC_MODE1_EVCTRL_CMPEO1_Pos) 357 #define RTC_MODE1_EVCTRL_CMPEO_Pos 8 /**< \brief (RTC_MODE1_EVCTRL) Compare x Event Output Enable */ 358 #define RTC_MODE1_EVCTRL_CMPEO_Msk (_U_(0x3) << RTC_MODE1_EVCTRL_CMPEO_Pos) 359 #define RTC_MODE1_EVCTRL_CMPEO(value) (RTC_MODE1_EVCTRL_CMPEO_Msk & ((value) << RTC_MODE1_EVCTRL_CMPEO_Pos)) 360 #define RTC_MODE1_EVCTRL_OVFEO_Pos 15 /**< \brief (RTC_MODE1_EVCTRL) Overflow Event Output Enable */ 361 #define RTC_MODE1_EVCTRL_OVFEO (_U_(0x1) << RTC_MODE1_EVCTRL_OVFEO_Pos) 362 #define RTC_MODE1_EVCTRL_MASK _U_(0x83FF) /**< \brief (RTC_MODE1_EVCTRL) MASK Register */ 363 364 /* -------- RTC_MODE2_EVCTRL : (RTC Offset: 0x04) (R/W 16) MODE2 MODE2 Event Control -------- */ 365 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 366 typedef union { 367 struct { 368 uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */ 369 uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */ 370 uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */ 371 uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */ 372 uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */ 373 uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */ 374 uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */ 375 uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */ 376 uint16_t ALARMEO0:1; /*!< bit: 8 Alarm 0 Event Output Enable */ 377 uint16_t :6; /*!< bit: 9..14 Reserved */ 378 uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */ 379 } bit; /*!< Structure used for bit access */ 380 struct { 381 uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */ 382 uint16_t ALARMEO:1; /*!< bit: 8 Alarm x Event Output Enable */ 383 uint16_t :7; /*!< bit: 9..15 Reserved */ 384 } vec; /*!< Structure used for vec access */ 385 uint16_t reg; /*!< Type used for register access */ 386 } RTC_MODE2_EVCTRL_Type; 387 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 388 389 #define RTC_MODE2_EVCTRL_OFFSET 0x04 /**< \brief (RTC_MODE2_EVCTRL offset) MODE2 Event Control */ 390 #define RTC_MODE2_EVCTRL_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE2_EVCTRL reset_value) MODE2 Event Control */ 391 392 #define RTC_MODE2_EVCTRL_PEREO0_Pos 0 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 0 Event Output Enable */ 393 #define RTC_MODE2_EVCTRL_PEREO0 (1 << RTC_MODE2_EVCTRL_PEREO0_Pos) 394 #define RTC_MODE2_EVCTRL_PEREO1_Pos 1 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 1 Event Output Enable */ 395 #define RTC_MODE2_EVCTRL_PEREO1 (1 << RTC_MODE2_EVCTRL_PEREO1_Pos) 396 #define RTC_MODE2_EVCTRL_PEREO2_Pos 2 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 2 Event Output Enable */ 397 #define RTC_MODE2_EVCTRL_PEREO2 (1 << RTC_MODE2_EVCTRL_PEREO2_Pos) 398 #define RTC_MODE2_EVCTRL_PEREO3_Pos 3 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 3 Event Output Enable */ 399 #define RTC_MODE2_EVCTRL_PEREO3 (1 << RTC_MODE2_EVCTRL_PEREO3_Pos) 400 #define RTC_MODE2_EVCTRL_PEREO4_Pos 4 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 4 Event Output Enable */ 401 #define RTC_MODE2_EVCTRL_PEREO4 (1 << RTC_MODE2_EVCTRL_PEREO4_Pos) 402 #define RTC_MODE2_EVCTRL_PEREO5_Pos 5 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 5 Event Output Enable */ 403 #define RTC_MODE2_EVCTRL_PEREO5 (1 << RTC_MODE2_EVCTRL_PEREO5_Pos) 404 #define RTC_MODE2_EVCTRL_PEREO6_Pos 6 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 6 Event Output Enable */ 405 #define RTC_MODE2_EVCTRL_PEREO6 (1 << RTC_MODE2_EVCTRL_PEREO6_Pos) 406 #define RTC_MODE2_EVCTRL_PEREO7_Pos 7 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 7 Event Output Enable */ 407 #define RTC_MODE2_EVCTRL_PEREO7 (1 << RTC_MODE2_EVCTRL_PEREO7_Pos) 408 #define RTC_MODE2_EVCTRL_PEREO_Pos 0 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval x Event Output Enable */ 409 #define RTC_MODE2_EVCTRL_PEREO_Msk (_U_(0xFF) << RTC_MODE2_EVCTRL_PEREO_Pos) 410 #define RTC_MODE2_EVCTRL_PEREO(value) (RTC_MODE2_EVCTRL_PEREO_Msk & ((value) << RTC_MODE2_EVCTRL_PEREO_Pos)) 411 #define RTC_MODE2_EVCTRL_ALARMEO0_Pos 8 /**< \brief (RTC_MODE2_EVCTRL) Alarm 0 Event Output Enable */ 412 #define RTC_MODE2_EVCTRL_ALARMEO0 (1 << RTC_MODE2_EVCTRL_ALARMEO0_Pos) 413 #define RTC_MODE2_EVCTRL_ALARMEO_Pos 8 /**< \brief (RTC_MODE2_EVCTRL) Alarm x Event Output Enable */ 414 #define RTC_MODE2_EVCTRL_ALARMEO_Msk (_U_(0x1) << RTC_MODE2_EVCTRL_ALARMEO_Pos) 415 #define RTC_MODE2_EVCTRL_ALARMEO(value) (RTC_MODE2_EVCTRL_ALARMEO_Msk & ((value) << RTC_MODE2_EVCTRL_ALARMEO_Pos)) 416 #define RTC_MODE2_EVCTRL_OVFEO_Pos 15 /**< \brief (RTC_MODE2_EVCTRL) Overflow Event Output Enable */ 417 #define RTC_MODE2_EVCTRL_OVFEO (_U_(0x1) << RTC_MODE2_EVCTRL_OVFEO_Pos) 418 #define RTC_MODE2_EVCTRL_MASK _U_(0x81FF) /**< \brief (RTC_MODE2_EVCTRL) MASK Register */ 419 420 /* -------- RTC_MODE0_INTENCLR : (RTC Offset: 0x06) (R/W 8) MODE0 MODE0 Interrupt Enable Clear -------- */ 421 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 422 typedef union { 423 struct { 424 uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */ 425 uint8_t :5; /*!< bit: 1.. 5 Reserved */ 426 uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */ 427 uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */ 428 } bit; /*!< Structure used for bit access */ 429 struct { 430 uint8_t CMP:1; /*!< bit: 0 Compare x Interrupt Enable */ 431 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 432 } vec; /*!< Structure used for vec access */ 433 uint8_t reg; /*!< Type used for register access */ 434 } RTC_MODE0_INTENCLR_Type; 435 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 436 437 #define RTC_MODE0_INTENCLR_OFFSET 0x06 /**< \brief (RTC_MODE0_INTENCLR offset) MODE0 Interrupt Enable Clear */ 438 #define RTC_MODE0_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (RTC_MODE0_INTENCLR reset_value) MODE0 Interrupt Enable Clear */ 439 440 #define RTC_MODE0_INTENCLR_CMP0_Pos 0 /**< \brief (RTC_MODE0_INTENCLR) Compare 0 Interrupt Enable */ 441 #define RTC_MODE0_INTENCLR_CMP0 (1 << RTC_MODE0_INTENCLR_CMP0_Pos) 442 #define RTC_MODE0_INTENCLR_CMP_Pos 0 /**< \brief (RTC_MODE0_INTENCLR) Compare x Interrupt Enable */ 443 #define RTC_MODE0_INTENCLR_CMP_Msk (_U_(0x1) << RTC_MODE0_INTENCLR_CMP_Pos) 444 #define RTC_MODE0_INTENCLR_CMP(value) (RTC_MODE0_INTENCLR_CMP_Msk & ((value) << RTC_MODE0_INTENCLR_CMP_Pos)) 445 #define RTC_MODE0_INTENCLR_SYNCRDY_Pos 6 /**< \brief (RTC_MODE0_INTENCLR) Synchronization Ready Interrupt Enable */ 446 #define RTC_MODE0_INTENCLR_SYNCRDY (_U_(0x1) << RTC_MODE0_INTENCLR_SYNCRDY_Pos) 447 #define RTC_MODE0_INTENCLR_OVF_Pos 7 /**< \brief (RTC_MODE0_INTENCLR) Overflow Interrupt Enable */ 448 #define RTC_MODE0_INTENCLR_OVF (_U_(0x1) << RTC_MODE0_INTENCLR_OVF_Pos) 449 #define RTC_MODE0_INTENCLR_MASK _U_(0xC1) /**< \brief (RTC_MODE0_INTENCLR) MASK Register */ 450 451 /* -------- RTC_MODE1_INTENCLR : (RTC Offset: 0x06) (R/W 8) MODE1 MODE1 Interrupt Enable Clear -------- */ 452 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 453 typedef union { 454 struct { 455 uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */ 456 uint8_t CMP1:1; /*!< bit: 1 Compare 1 Interrupt Enable */ 457 uint8_t :4; /*!< bit: 2.. 5 Reserved */ 458 uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */ 459 uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */ 460 } bit; /*!< Structure used for bit access */ 461 struct { 462 uint8_t CMP:2; /*!< bit: 0.. 1 Compare x Interrupt Enable */ 463 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 464 } vec; /*!< Structure used for vec access */ 465 uint8_t reg; /*!< Type used for register access */ 466 } RTC_MODE1_INTENCLR_Type; 467 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 468 469 #define RTC_MODE1_INTENCLR_OFFSET 0x06 /**< \brief (RTC_MODE1_INTENCLR offset) MODE1 Interrupt Enable Clear */ 470 #define RTC_MODE1_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (RTC_MODE1_INTENCLR reset_value) MODE1 Interrupt Enable Clear */ 471 472 #define RTC_MODE1_INTENCLR_CMP0_Pos 0 /**< \brief (RTC_MODE1_INTENCLR) Compare 0 Interrupt Enable */ 473 #define RTC_MODE1_INTENCLR_CMP0 (1 << RTC_MODE1_INTENCLR_CMP0_Pos) 474 #define RTC_MODE1_INTENCLR_CMP1_Pos 1 /**< \brief (RTC_MODE1_INTENCLR) Compare 1 Interrupt Enable */ 475 #define RTC_MODE1_INTENCLR_CMP1 (1 << RTC_MODE1_INTENCLR_CMP1_Pos) 476 #define RTC_MODE1_INTENCLR_CMP_Pos 0 /**< \brief (RTC_MODE1_INTENCLR) Compare x Interrupt Enable */ 477 #define RTC_MODE1_INTENCLR_CMP_Msk (_U_(0x3) << RTC_MODE1_INTENCLR_CMP_Pos) 478 #define RTC_MODE1_INTENCLR_CMP(value) (RTC_MODE1_INTENCLR_CMP_Msk & ((value) << RTC_MODE1_INTENCLR_CMP_Pos)) 479 #define RTC_MODE1_INTENCLR_SYNCRDY_Pos 6 /**< \brief (RTC_MODE1_INTENCLR) Synchronization Ready Interrupt Enable */ 480 #define RTC_MODE1_INTENCLR_SYNCRDY (_U_(0x1) << RTC_MODE1_INTENCLR_SYNCRDY_Pos) 481 #define RTC_MODE1_INTENCLR_OVF_Pos 7 /**< \brief (RTC_MODE1_INTENCLR) Overflow Interrupt Enable */ 482 #define RTC_MODE1_INTENCLR_OVF (_U_(0x1) << RTC_MODE1_INTENCLR_OVF_Pos) 483 #define RTC_MODE1_INTENCLR_MASK _U_(0xC3) /**< \brief (RTC_MODE1_INTENCLR) MASK Register */ 484 485 /* -------- RTC_MODE2_INTENCLR : (RTC Offset: 0x06) (R/W 8) MODE2 MODE2 Interrupt Enable Clear -------- */ 486 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 487 typedef union { 488 struct { 489 uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 Interrupt Enable */ 490 uint8_t :5; /*!< bit: 1.. 5 Reserved */ 491 uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */ 492 uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */ 493 } bit; /*!< Structure used for bit access */ 494 struct { 495 uint8_t ALARM:1; /*!< bit: 0 Alarm x Interrupt Enable */ 496 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 497 } vec; /*!< Structure used for vec access */ 498 uint8_t reg; /*!< Type used for register access */ 499 } RTC_MODE2_INTENCLR_Type; 500 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 501 502 #define RTC_MODE2_INTENCLR_OFFSET 0x06 /**< \brief (RTC_MODE2_INTENCLR offset) MODE2 Interrupt Enable Clear */ 503 #define RTC_MODE2_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (RTC_MODE2_INTENCLR reset_value) MODE2 Interrupt Enable Clear */ 504 505 #define RTC_MODE2_INTENCLR_ALARM0_Pos 0 /**< \brief (RTC_MODE2_INTENCLR) Alarm 0 Interrupt Enable */ 506 #define RTC_MODE2_INTENCLR_ALARM0 (1 << RTC_MODE2_INTENCLR_ALARM0_Pos) 507 #define RTC_MODE2_INTENCLR_ALARM_Pos 0 /**< \brief (RTC_MODE2_INTENCLR) Alarm x Interrupt Enable */ 508 #define RTC_MODE2_INTENCLR_ALARM_Msk (_U_(0x1) << RTC_MODE2_INTENCLR_ALARM_Pos) 509 #define RTC_MODE2_INTENCLR_ALARM(value) (RTC_MODE2_INTENCLR_ALARM_Msk & ((value) << RTC_MODE2_INTENCLR_ALARM_Pos)) 510 #define RTC_MODE2_INTENCLR_SYNCRDY_Pos 6 /**< \brief (RTC_MODE2_INTENCLR) Synchronization Ready Interrupt Enable */ 511 #define RTC_MODE2_INTENCLR_SYNCRDY (_U_(0x1) << RTC_MODE2_INTENCLR_SYNCRDY_Pos) 512 #define RTC_MODE2_INTENCLR_OVF_Pos 7 /**< \brief (RTC_MODE2_INTENCLR) Overflow Interrupt Enable */ 513 #define RTC_MODE2_INTENCLR_OVF (_U_(0x1) << RTC_MODE2_INTENCLR_OVF_Pos) 514 #define RTC_MODE2_INTENCLR_MASK _U_(0xC1) /**< \brief (RTC_MODE2_INTENCLR) MASK Register */ 515 516 /* -------- RTC_MODE0_INTENSET : (RTC Offset: 0x07) (R/W 8) MODE0 MODE0 Interrupt Enable Set -------- */ 517 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 518 typedef union { 519 struct { 520 uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */ 521 uint8_t :5; /*!< bit: 1.. 5 Reserved */ 522 uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */ 523 uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */ 524 } bit; /*!< Structure used for bit access */ 525 struct { 526 uint8_t CMP:1; /*!< bit: 0 Compare x Interrupt Enable */ 527 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 528 } vec; /*!< Structure used for vec access */ 529 uint8_t reg; /*!< Type used for register access */ 530 } RTC_MODE0_INTENSET_Type; 531 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 532 533 #define RTC_MODE0_INTENSET_OFFSET 0x07 /**< \brief (RTC_MODE0_INTENSET offset) MODE0 Interrupt Enable Set */ 534 #define RTC_MODE0_INTENSET_RESETVALUE _U_(0x00) /**< \brief (RTC_MODE0_INTENSET reset_value) MODE0 Interrupt Enable Set */ 535 536 #define RTC_MODE0_INTENSET_CMP0_Pos 0 /**< \brief (RTC_MODE0_INTENSET) Compare 0 Interrupt Enable */ 537 #define RTC_MODE0_INTENSET_CMP0 (1 << RTC_MODE0_INTENSET_CMP0_Pos) 538 #define RTC_MODE0_INTENSET_CMP_Pos 0 /**< \brief (RTC_MODE0_INTENSET) Compare x Interrupt Enable */ 539 #define RTC_MODE0_INTENSET_CMP_Msk (_U_(0x1) << RTC_MODE0_INTENSET_CMP_Pos) 540 #define RTC_MODE0_INTENSET_CMP(value) (RTC_MODE0_INTENSET_CMP_Msk & ((value) << RTC_MODE0_INTENSET_CMP_Pos)) 541 #define RTC_MODE0_INTENSET_SYNCRDY_Pos 6 /**< \brief (RTC_MODE0_INTENSET) Synchronization Ready Interrupt Enable */ 542 #define RTC_MODE0_INTENSET_SYNCRDY (_U_(0x1) << RTC_MODE0_INTENSET_SYNCRDY_Pos) 543 #define RTC_MODE0_INTENSET_OVF_Pos 7 /**< \brief (RTC_MODE0_INTENSET) Overflow Interrupt Enable */ 544 #define RTC_MODE0_INTENSET_OVF (_U_(0x1) << RTC_MODE0_INTENSET_OVF_Pos) 545 #define RTC_MODE0_INTENSET_MASK _U_(0xC1) /**< \brief (RTC_MODE0_INTENSET) MASK Register */ 546 547 /* -------- RTC_MODE1_INTENSET : (RTC Offset: 0x07) (R/W 8) MODE1 MODE1 Interrupt Enable Set -------- */ 548 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 549 typedef union { 550 struct { 551 uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */ 552 uint8_t CMP1:1; /*!< bit: 1 Compare 1 Interrupt Enable */ 553 uint8_t :4; /*!< bit: 2.. 5 Reserved */ 554 uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */ 555 uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */ 556 } bit; /*!< Structure used for bit access */ 557 struct { 558 uint8_t CMP:2; /*!< bit: 0.. 1 Compare x Interrupt Enable */ 559 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 560 } vec; /*!< Structure used for vec access */ 561 uint8_t reg; /*!< Type used for register access */ 562 } RTC_MODE1_INTENSET_Type; 563 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 564 565 #define RTC_MODE1_INTENSET_OFFSET 0x07 /**< \brief (RTC_MODE1_INTENSET offset) MODE1 Interrupt Enable Set */ 566 #define RTC_MODE1_INTENSET_RESETVALUE _U_(0x00) /**< \brief (RTC_MODE1_INTENSET reset_value) MODE1 Interrupt Enable Set */ 567 568 #define RTC_MODE1_INTENSET_CMP0_Pos 0 /**< \brief (RTC_MODE1_INTENSET) Compare 0 Interrupt Enable */ 569 #define RTC_MODE1_INTENSET_CMP0 (1 << RTC_MODE1_INTENSET_CMP0_Pos) 570 #define RTC_MODE1_INTENSET_CMP1_Pos 1 /**< \brief (RTC_MODE1_INTENSET) Compare 1 Interrupt Enable */ 571 #define RTC_MODE1_INTENSET_CMP1 (1 << RTC_MODE1_INTENSET_CMP1_Pos) 572 #define RTC_MODE1_INTENSET_CMP_Pos 0 /**< \brief (RTC_MODE1_INTENSET) Compare x Interrupt Enable */ 573 #define RTC_MODE1_INTENSET_CMP_Msk (_U_(0x3) << RTC_MODE1_INTENSET_CMP_Pos) 574 #define RTC_MODE1_INTENSET_CMP(value) (RTC_MODE1_INTENSET_CMP_Msk & ((value) << RTC_MODE1_INTENSET_CMP_Pos)) 575 #define RTC_MODE1_INTENSET_SYNCRDY_Pos 6 /**< \brief (RTC_MODE1_INTENSET) Synchronization Ready Interrupt Enable */ 576 #define RTC_MODE1_INTENSET_SYNCRDY (_U_(0x1) << RTC_MODE1_INTENSET_SYNCRDY_Pos) 577 #define RTC_MODE1_INTENSET_OVF_Pos 7 /**< \brief (RTC_MODE1_INTENSET) Overflow Interrupt Enable */ 578 #define RTC_MODE1_INTENSET_OVF (_U_(0x1) << RTC_MODE1_INTENSET_OVF_Pos) 579 #define RTC_MODE1_INTENSET_MASK _U_(0xC3) /**< \brief (RTC_MODE1_INTENSET) MASK Register */ 580 581 /* -------- RTC_MODE2_INTENSET : (RTC Offset: 0x07) (R/W 8) MODE2 MODE2 Interrupt Enable Set -------- */ 582 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 583 typedef union { 584 struct { 585 uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 Interrupt Enable */ 586 uint8_t :5; /*!< bit: 1.. 5 Reserved */ 587 uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */ 588 uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */ 589 } bit; /*!< Structure used for bit access */ 590 struct { 591 uint8_t ALARM:1; /*!< bit: 0 Alarm x Interrupt Enable */ 592 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 593 } vec; /*!< Structure used for vec access */ 594 uint8_t reg; /*!< Type used for register access */ 595 } RTC_MODE2_INTENSET_Type; 596 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 597 598 #define RTC_MODE2_INTENSET_OFFSET 0x07 /**< \brief (RTC_MODE2_INTENSET offset) MODE2 Interrupt Enable Set */ 599 #define RTC_MODE2_INTENSET_RESETVALUE _U_(0x00) /**< \brief (RTC_MODE2_INTENSET reset_value) MODE2 Interrupt Enable Set */ 600 601 #define RTC_MODE2_INTENSET_ALARM0_Pos 0 /**< \brief (RTC_MODE2_INTENSET) Alarm 0 Interrupt Enable */ 602 #define RTC_MODE2_INTENSET_ALARM0 (1 << RTC_MODE2_INTENSET_ALARM0_Pos) 603 #define RTC_MODE2_INTENSET_ALARM_Pos 0 /**< \brief (RTC_MODE2_INTENSET) Alarm x Interrupt Enable */ 604 #define RTC_MODE2_INTENSET_ALARM_Msk (_U_(0x1) << RTC_MODE2_INTENSET_ALARM_Pos) 605 #define RTC_MODE2_INTENSET_ALARM(value) (RTC_MODE2_INTENSET_ALARM_Msk & ((value) << RTC_MODE2_INTENSET_ALARM_Pos)) 606 #define RTC_MODE2_INTENSET_SYNCRDY_Pos 6 /**< \brief (RTC_MODE2_INTENSET) Synchronization Ready Interrupt Enable */ 607 #define RTC_MODE2_INTENSET_SYNCRDY (_U_(0x1) << RTC_MODE2_INTENSET_SYNCRDY_Pos) 608 #define RTC_MODE2_INTENSET_OVF_Pos 7 /**< \brief (RTC_MODE2_INTENSET) Overflow Interrupt Enable */ 609 #define RTC_MODE2_INTENSET_OVF (_U_(0x1) << RTC_MODE2_INTENSET_OVF_Pos) 610 #define RTC_MODE2_INTENSET_MASK _U_(0xC1) /**< \brief (RTC_MODE2_INTENSET) MASK Register */ 611 612 /* -------- RTC_MODE0_INTFLAG : (RTC Offset: 0x08) (R/W 8) MODE0 MODE0 Interrupt Flag Status and Clear -------- */ 613 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 614 typedef union { // __I to avoid read-modify-write on write-to-clear register 615 struct { 616 __I uint8_t CMP0:1; /*!< bit: 0 Compare 0 */ 617 __I uint8_t :5; /*!< bit: 1.. 5 Reserved */ 618 __I uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */ 619 __I uint8_t OVF:1; /*!< bit: 7 Overflow */ 620 } bit; /*!< Structure used for bit access */ 621 struct { 622 __I uint8_t CMP:1; /*!< bit: 0 Compare x */ 623 __I uint8_t :7; /*!< bit: 1.. 7 Reserved */ 624 } vec; /*!< Structure used for vec access */ 625 uint8_t reg; /*!< Type used for register access */ 626 } RTC_MODE0_INTFLAG_Type; 627 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 628 629 #define RTC_MODE0_INTFLAG_OFFSET 0x08 /**< \brief (RTC_MODE0_INTFLAG offset) MODE0 Interrupt Flag Status and Clear */ 630 #define RTC_MODE0_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (RTC_MODE0_INTFLAG reset_value) MODE0 Interrupt Flag Status and Clear */ 631 632 #define RTC_MODE0_INTFLAG_CMP0_Pos 0 /**< \brief (RTC_MODE0_INTFLAG) Compare 0 */ 633 #define RTC_MODE0_INTFLAG_CMP0 (1 << RTC_MODE0_INTFLAG_CMP0_Pos) 634 #define RTC_MODE0_INTFLAG_CMP_Pos 0 /**< \brief (RTC_MODE0_INTFLAG) Compare x */ 635 #define RTC_MODE0_INTFLAG_CMP_Msk (_U_(0x1) << RTC_MODE0_INTFLAG_CMP_Pos) 636 #define RTC_MODE0_INTFLAG_CMP(value) (RTC_MODE0_INTFLAG_CMP_Msk & ((value) << RTC_MODE0_INTFLAG_CMP_Pos)) 637 #define RTC_MODE0_INTFLAG_SYNCRDY_Pos 6 /**< \brief (RTC_MODE0_INTFLAG) Synchronization Ready */ 638 #define RTC_MODE0_INTFLAG_SYNCRDY (_U_(0x1) << RTC_MODE0_INTFLAG_SYNCRDY_Pos) 639 #define RTC_MODE0_INTFLAG_OVF_Pos 7 /**< \brief (RTC_MODE0_INTFLAG) Overflow */ 640 #define RTC_MODE0_INTFLAG_OVF (_U_(0x1) << RTC_MODE0_INTFLAG_OVF_Pos) 641 #define RTC_MODE0_INTFLAG_MASK _U_(0xC1) /**< \brief (RTC_MODE0_INTFLAG) MASK Register */ 642 643 /* -------- RTC_MODE1_INTFLAG : (RTC Offset: 0x08) (R/W 8) MODE1 MODE1 Interrupt Flag Status and Clear -------- */ 644 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 645 typedef union { // __I to avoid read-modify-write on write-to-clear register 646 struct { 647 __I uint8_t CMP0:1; /*!< bit: 0 Compare 0 */ 648 __I uint8_t CMP1:1; /*!< bit: 1 Compare 1 */ 649 __I uint8_t :4; /*!< bit: 2.. 5 Reserved */ 650 __I uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */ 651 __I uint8_t OVF:1; /*!< bit: 7 Overflow */ 652 } bit; /*!< Structure used for bit access */ 653 struct { 654 __I uint8_t CMP:2; /*!< bit: 0.. 1 Compare x */ 655 __I uint8_t :6; /*!< bit: 2.. 7 Reserved */ 656 } vec; /*!< Structure used for vec access */ 657 uint8_t reg; /*!< Type used for register access */ 658 } RTC_MODE1_INTFLAG_Type; 659 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 660 661 #define RTC_MODE1_INTFLAG_OFFSET 0x08 /**< \brief (RTC_MODE1_INTFLAG offset) MODE1 Interrupt Flag Status and Clear */ 662 #define RTC_MODE1_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (RTC_MODE1_INTFLAG reset_value) MODE1 Interrupt Flag Status and Clear */ 663 664 #define RTC_MODE1_INTFLAG_CMP0_Pos 0 /**< \brief (RTC_MODE1_INTFLAG) Compare 0 */ 665 #define RTC_MODE1_INTFLAG_CMP0 (1 << RTC_MODE1_INTFLAG_CMP0_Pos) 666 #define RTC_MODE1_INTFLAG_CMP1_Pos 1 /**< \brief (RTC_MODE1_INTFLAG) Compare 1 */ 667 #define RTC_MODE1_INTFLAG_CMP1 (1 << RTC_MODE1_INTFLAG_CMP1_Pos) 668 #define RTC_MODE1_INTFLAG_CMP_Pos 0 /**< \brief (RTC_MODE1_INTFLAG) Compare x */ 669 #define RTC_MODE1_INTFLAG_CMP_Msk (_U_(0x3) << RTC_MODE1_INTFLAG_CMP_Pos) 670 #define RTC_MODE1_INTFLAG_CMP(value) (RTC_MODE1_INTFLAG_CMP_Msk & ((value) << RTC_MODE1_INTFLAG_CMP_Pos)) 671 #define RTC_MODE1_INTFLAG_SYNCRDY_Pos 6 /**< \brief (RTC_MODE1_INTFLAG) Synchronization Ready */ 672 #define RTC_MODE1_INTFLAG_SYNCRDY (_U_(0x1) << RTC_MODE1_INTFLAG_SYNCRDY_Pos) 673 #define RTC_MODE1_INTFLAG_OVF_Pos 7 /**< \brief (RTC_MODE1_INTFLAG) Overflow */ 674 #define RTC_MODE1_INTFLAG_OVF (_U_(0x1) << RTC_MODE1_INTFLAG_OVF_Pos) 675 #define RTC_MODE1_INTFLAG_MASK _U_(0xC3) /**< \brief (RTC_MODE1_INTFLAG) MASK Register */ 676 677 /* -------- RTC_MODE2_INTFLAG : (RTC Offset: 0x08) (R/W 8) MODE2 MODE2 Interrupt Flag Status and Clear -------- */ 678 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 679 typedef union { // __I to avoid read-modify-write on write-to-clear register 680 struct { 681 __I uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 */ 682 __I uint8_t :5; /*!< bit: 1.. 5 Reserved */ 683 __I uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */ 684 __I uint8_t OVF:1; /*!< bit: 7 Overflow */ 685 } bit; /*!< Structure used for bit access */ 686 struct { 687 __I uint8_t ALARM:1; /*!< bit: 0 Alarm x */ 688 __I uint8_t :7; /*!< bit: 1.. 7 Reserved */ 689 } vec; /*!< Structure used for vec access */ 690 uint8_t reg; /*!< Type used for register access */ 691 } RTC_MODE2_INTFLAG_Type; 692 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 693 694 #define RTC_MODE2_INTFLAG_OFFSET 0x08 /**< \brief (RTC_MODE2_INTFLAG offset) MODE2 Interrupt Flag Status and Clear */ 695 #define RTC_MODE2_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (RTC_MODE2_INTFLAG reset_value) MODE2 Interrupt Flag Status and Clear */ 696 697 #define RTC_MODE2_INTFLAG_ALARM0_Pos 0 /**< \brief (RTC_MODE2_INTFLAG) Alarm 0 */ 698 #define RTC_MODE2_INTFLAG_ALARM0 (1 << RTC_MODE2_INTFLAG_ALARM0_Pos) 699 #define RTC_MODE2_INTFLAG_ALARM_Pos 0 /**< \brief (RTC_MODE2_INTFLAG) Alarm x */ 700 #define RTC_MODE2_INTFLAG_ALARM_Msk (_U_(0x1) << RTC_MODE2_INTFLAG_ALARM_Pos) 701 #define RTC_MODE2_INTFLAG_ALARM(value) (RTC_MODE2_INTFLAG_ALARM_Msk & ((value) << RTC_MODE2_INTFLAG_ALARM_Pos)) 702 #define RTC_MODE2_INTFLAG_SYNCRDY_Pos 6 /**< \brief (RTC_MODE2_INTFLAG) Synchronization Ready */ 703 #define RTC_MODE2_INTFLAG_SYNCRDY (_U_(0x1) << RTC_MODE2_INTFLAG_SYNCRDY_Pos) 704 #define RTC_MODE2_INTFLAG_OVF_Pos 7 /**< \brief (RTC_MODE2_INTFLAG) Overflow */ 705 #define RTC_MODE2_INTFLAG_OVF (_U_(0x1) << RTC_MODE2_INTFLAG_OVF_Pos) 706 #define RTC_MODE2_INTFLAG_MASK _U_(0xC1) /**< \brief (RTC_MODE2_INTFLAG) MASK Register */ 707 708 /* -------- RTC_STATUS : (RTC Offset: 0x0A) (R/W 8) Status -------- */ 709 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 710 typedef union { 711 struct { 712 uint8_t :7; /*!< bit: 0.. 6 Reserved */ 713 uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */ 714 } bit; /*!< Structure used for bit access */ 715 uint8_t reg; /*!< Type used for register access */ 716 } RTC_STATUS_Type; 717 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 718 719 #define RTC_STATUS_OFFSET 0x0A /**< \brief (RTC_STATUS offset) Status */ 720 #define RTC_STATUS_RESETVALUE _U_(0x00) /**< \brief (RTC_STATUS reset_value) Status */ 721 722 #define RTC_STATUS_SYNCBUSY_Pos 7 /**< \brief (RTC_STATUS) Synchronization Busy */ 723 #define RTC_STATUS_SYNCBUSY (_U_(0x1) << RTC_STATUS_SYNCBUSY_Pos) 724 #define RTC_STATUS_MASK _U_(0x80) /**< \brief (RTC_STATUS) MASK Register */ 725 726 /* -------- RTC_DBGCTRL : (RTC Offset: 0x0B) (R/W 8) Debug Control -------- */ 727 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 728 typedef union { 729 struct { 730 uint8_t DBGRUN:1; /*!< bit: 0 Run During Debug */ 731 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 732 } bit; /*!< Structure used for bit access */ 733 uint8_t reg; /*!< Type used for register access */ 734 } RTC_DBGCTRL_Type; 735 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 736 737 #define RTC_DBGCTRL_OFFSET 0x0B /**< \brief (RTC_DBGCTRL offset) Debug Control */ 738 #define RTC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (RTC_DBGCTRL reset_value) Debug Control */ 739 740 #define RTC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (RTC_DBGCTRL) Run During Debug */ 741 #define RTC_DBGCTRL_DBGRUN (_U_(0x1) << RTC_DBGCTRL_DBGRUN_Pos) 742 #define RTC_DBGCTRL_MASK _U_(0x01) /**< \brief (RTC_DBGCTRL) MASK Register */ 743 744 /* -------- RTC_FREQCORR : (RTC Offset: 0x0C) (R/W 8) Frequency Correction -------- */ 745 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 746 typedef union { 747 struct { 748 uint8_t VALUE:7; /*!< bit: 0.. 6 Correction Value */ 749 uint8_t SIGN:1; /*!< bit: 7 Correction Sign */ 750 } bit; /*!< Structure used for bit access */ 751 uint8_t reg; /*!< Type used for register access */ 752 } RTC_FREQCORR_Type; 753 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 754 755 #define RTC_FREQCORR_OFFSET 0x0C /**< \brief (RTC_FREQCORR offset) Frequency Correction */ 756 #define RTC_FREQCORR_RESETVALUE _U_(0x00) /**< \brief (RTC_FREQCORR reset_value) Frequency Correction */ 757 758 #define RTC_FREQCORR_VALUE_Pos 0 /**< \brief (RTC_FREQCORR) Correction Value */ 759 #define RTC_FREQCORR_VALUE_Msk (_U_(0x7F) << RTC_FREQCORR_VALUE_Pos) 760 #define RTC_FREQCORR_VALUE(value) (RTC_FREQCORR_VALUE_Msk & ((value) << RTC_FREQCORR_VALUE_Pos)) 761 #define RTC_FREQCORR_SIGN_Pos 7 /**< \brief (RTC_FREQCORR) Correction Sign */ 762 #define RTC_FREQCORR_SIGN (_U_(0x1) << RTC_FREQCORR_SIGN_Pos) 763 #define RTC_FREQCORR_MASK _U_(0xFF) /**< \brief (RTC_FREQCORR) MASK Register */ 764 765 /* -------- RTC_MODE0_COUNT : (RTC Offset: 0x10) (R/W 32) MODE0 MODE0 Counter Value -------- */ 766 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 767 typedef union { 768 struct { 769 uint32_t COUNT:32; /*!< bit: 0..31 Counter Value */ 770 } bit; /*!< Structure used for bit access */ 771 uint32_t reg; /*!< Type used for register access */ 772 } RTC_MODE0_COUNT_Type; 773 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 774 775 #define RTC_MODE0_COUNT_OFFSET 0x10 /**< \brief (RTC_MODE0_COUNT offset) MODE0 Counter Value */ 776 #define RTC_MODE0_COUNT_RESETVALUE _U_(0x00000000) /**< \brief (RTC_MODE0_COUNT reset_value) MODE0 Counter Value */ 777 778 #define RTC_MODE0_COUNT_COUNT_Pos 0 /**< \brief (RTC_MODE0_COUNT) Counter Value */ 779 #define RTC_MODE0_COUNT_COUNT_Msk (_U_(0xFFFFFFFF) << RTC_MODE0_COUNT_COUNT_Pos) 780 #define RTC_MODE0_COUNT_COUNT(value) (RTC_MODE0_COUNT_COUNT_Msk & ((value) << RTC_MODE0_COUNT_COUNT_Pos)) 781 #define RTC_MODE0_COUNT_MASK _U_(0xFFFFFFFF) /**< \brief (RTC_MODE0_COUNT) MASK Register */ 782 783 /* -------- RTC_MODE1_COUNT : (RTC Offset: 0x10) (R/W 16) MODE1 MODE1 Counter Value -------- */ 784 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 785 typedef union { 786 struct { 787 uint16_t COUNT:16; /*!< bit: 0..15 Counter Value */ 788 } bit; /*!< Structure used for bit access */ 789 uint16_t reg; /*!< Type used for register access */ 790 } RTC_MODE1_COUNT_Type; 791 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 792 793 #define RTC_MODE1_COUNT_OFFSET 0x10 /**< \brief (RTC_MODE1_COUNT offset) MODE1 Counter Value */ 794 #define RTC_MODE1_COUNT_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE1_COUNT reset_value) MODE1 Counter Value */ 795 796 #define RTC_MODE1_COUNT_COUNT_Pos 0 /**< \brief (RTC_MODE1_COUNT) Counter Value */ 797 #define RTC_MODE1_COUNT_COUNT_Msk (_U_(0xFFFF) << RTC_MODE1_COUNT_COUNT_Pos) 798 #define RTC_MODE1_COUNT_COUNT(value) (RTC_MODE1_COUNT_COUNT_Msk & ((value) << RTC_MODE1_COUNT_COUNT_Pos)) 799 #define RTC_MODE1_COUNT_MASK _U_(0xFFFF) /**< \brief (RTC_MODE1_COUNT) MASK Register */ 800 801 /* -------- RTC_MODE2_CLOCK : (RTC Offset: 0x10) (R/W 32) MODE2 MODE2 Clock Value -------- */ 802 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 803 typedef union { 804 struct { 805 uint32_t SECOND:6; /*!< bit: 0.. 5 Second */ 806 uint32_t MINUTE:6; /*!< bit: 6..11 Minute */ 807 uint32_t HOUR:5; /*!< bit: 12..16 Hour */ 808 uint32_t DAY:5; /*!< bit: 17..21 Day */ 809 uint32_t MONTH:4; /*!< bit: 22..25 Month */ 810 uint32_t YEAR:6; /*!< bit: 26..31 Year */ 811 } bit; /*!< Structure used for bit access */ 812 uint32_t reg; /*!< Type used for register access */ 813 } RTC_MODE2_CLOCK_Type; 814 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 815 816 #define RTC_MODE2_CLOCK_OFFSET 0x10 /**< \brief (RTC_MODE2_CLOCK offset) MODE2 Clock Value */ 817 #define RTC_MODE2_CLOCK_RESETVALUE _U_(0x00000000) /**< \brief (RTC_MODE2_CLOCK reset_value) MODE2 Clock Value */ 818 819 #define RTC_MODE2_CLOCK_SECOND_Pos 0 /**< \brief (RTC_MODE2_CLOCK) Second */ 820 #define RTC_MODE2_CLOCK_SECOND_Msk (_U_(0x3F) << RTC_MODE2_CLOCK_SECOND_Pos) 821 #define RTC_MODE2_CLOCK_SECOND(value) (RTC_MODE2_CLOCK_SECOND_Msk & ((value) << RTC_MODE2_CLOCK_SECOND_Pos)) 822 #define RTC_MODE2_CLOCK_MINUTE_Pos 6 /**< \brief (RTC_MODE2_CLOCK) Minute */ 823 #define RTC_MODE2_CLOCK_MINUTE_Msk (_U_(0x3F) << RTC_MODE2_CLOCK_MINUTE_Pos) 824 #define RTC_MODE2_CLOCK_MINUTE(value) (RTC_MODE2_CLOCK_MINUTE_Msk & ((value) << RTC_MODE2_CLOCK_MINUTE_Pos)) 825 #define RTC_MODE2_CLOCK_HOUR_Pos 12 /**< \brief (RTC_MODE2_CLOCK) Hour */ 826 #define RTC_MODE2_CLOCK_HOUR_Msk (_U_(0x1F) << RTC_MODE2_CLOCK_HOUR_Pos) 827 #define RTC_MODE2_CLOCK_HOUR(value) (RTC_MODE2_CLOCK_HOUR_Msk & ((value) << RTC_MODE2_CLOCK_HOUR_Pos)) 828 #define RTC_MODE2_CLOCK_HOUR_AM_Val _U_(0x0) /**< \brief (RTC_MODE2_CLOCK) AM when CLKREP in 12-hour */ 829 #define RTC_MODE2_CLOCK_HOUR_PM_Val _U_(0x10) /**< \brief (RTC_MODE2_CLOCK) PM when CLKREP in 12-hour */ 830 #define RTC_MODE2_CLOCK_HOUR_AM (RTC_MODE2_CLOCK_HOUR_AM_Val << RTC_MODE2_CLOCK_HOUR_Pos) 831 #define RTC_MODE2_CLOCK_HOUR_PM (RTC_MODE2_CLOCK_HOUR_PM_Val << RTC_MODE2_CLOCK_HOUR_Pos) 832 #define RTC_MODE2_CLOCK_DAY_Pos 17 /**< \brief (RTC_MODE2_CLOCK) Day */ 833 #define RTC_MODE2_CLOCK_DAY_Msk (_U_(0x1F) << RTC_MODE2_CLOCK_DAY_Pos) 834 #define RTC_MODE2_CLOCK_DAY(value) (RTC_MODE2_CLOCK_DAY_Msk & ((value) << RTC_MODE2_CLOCK_DAY_Pos)) 835 #define RTC_MODE2_CLOCK_MONTH_Pos 22 /**< \brief (RTC_MODE2_CLOCK) Month */ 836 #define RTC_MODE2_CLOCK_MONTH_Msk (_U_(0xF) << RTC_MODE2_CLOCK_MONTH_Pos) 837 #define RTC_MODE2_CLOCK_MONTH(value) (RTC_MODE2_CLOCK_MONTH_Msk & ((value) << RTC_MODE2_CLOCK_MONTH_Pos)) 838 #define RTC_MODE2_CLOCK_YEAR_Pos 26 /**< \brief (RTC_MODE2_CLOCK) Year */ 839 #define RTC_MODE2_CLOCK_YEAR_Msk (_U_(0x3F) << RTC_MODE2_CLOCK_YEAR_Pos) 840 #define RTC_MODE2_CLOCK_YEAR(value) (RTC_MODE2_CLOCK_YEAR_Msk & ((value) << RTC_MODE2_CLOCK_YEAR_Pos)) 841 #define RTC_MODE2_CLOCK_MASK _U_(0xFFFFFFFF) /**< \brief (RTC_MODE2_CLOCK) MASK Register */ 842 843 /* -------- RTC_MODE1_PER : (RTC Offset: 0x14) (R/W 16) MODE1 MODE1 Counter Period -------- */ 844 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 845 typedef union { 846 struct { 847 uint16_t PER:16; /*!< bit: 0..15 Counter Period */ 848 } bit; /*!< Structure used for bit access */ 849 uint16_t reg; /*!< Type used for register access */ 850 } RTC_MODE1_PER_Type; 851 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 852 853 #define RTC_MODE1_PER_OFFSET 0x14 /**< \brief (RTC_MODE1_PER offset) MODE1 Counter Period */ 854 #define RTC_MODE1_PER_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE1_PER reset_value) MODE1 Counter Period */ 855 856 #define RTC_MODE1_PER_PER_Pos 0 /**< \brief (RTC_MODE1_PER) Counter Period */ 857 #define RTC_MODE1_PER_PER_Msk (_U_(0xFFFF) << RTC_MODE1_PER_PER_Pos) 858 #define RTC_MODE1_PER_PER(value) (RTC_MODE1_PER_PER_Msk & ((value) << RTC_MODE1_PER_PER_Pos)) 859 #define RTC_MODE1_PER_MASK _U_(0xFFFF) /**< \brief (RTC_MODE1_PER) MASK Register */ 860 861 /* -------- RTC_MODE0_COMP : (RTC Offset: 0x18) (R/W 32) MODE0 MODE0 Compare n Value -------- */ 862 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 863 typedef union { 864 struct { 865 uint32_t COMP:32; /*!< bit: 0..31 Compare Value */ 866 } bit; /*!< Structure used for bit access */ 867 uint32_t reg; /*!< Type used for register access */ 868 } RTC_MODE0_COMP_Type; 869 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 870 871 #define RTC_MODE0_COMP_OFFSET 0x18 /**< \brief (RTC_MODE0_COMP offset) MODE0 Compare n Value */ 872 #define RTC_MODE0_COMP_RESETVALUE _U_(0x00000000) /**< \brief (RTC_MODE0_COMP reset_value) MODE0 Compare n Value */ 873 874 #define RTC_MODE0_COMP_COMP_Pos 0 /**< \brief (RTC_MODE0_COMP) Compare Value */ 875 #define RTC_MODE0_COMP_COMP_Msk (_U_(0xFFFFFFFF) << RTC_MODE0_COMP_COMP_Pos) 876 #define RTC_MODE0_COMP_COMP(value) (RTC_MODE0_COMP_COMP_Msk & ((value) << RTC_MODE0_COMP_COMP_Pos)) 877 #define RTC_MODE0_COMP_MASK _U_(0xFFFFFFFF) /**< \brief (RTC_MODE0_COMP) MASK Register */ 878 879 /* -------- RTC_MODE1_COMP : (RTC Offset: 0x18) (R/W 16) MODE1 MODE1 Compare n Value -------- */ 880 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 881 typedef union { 882 struct { 883 uint16_t COMP:16; /*!< bit: 0..15 Compare Value */ 884 } bit; /*!< Structure used for bit access */ 885 uint16_t reg; /*!< Type used for register access */ 886 } RTC_MODE1_COMP_Type; 887 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 888 889 #define RTC_MODE1_COMP_OFFSET 0x18 /**< \brief (RTC_MODE1_COMP offset) MODE1 Compare n Value */ 890 #define RTC_MODE1_COMP_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE1_COMP reset_value) MODE1 Compare n Value */ 891 892 #define RTC_MODE1_COMP_COMP_Pos 0 /**< \brief (RTC_MODE1_COMP) Compare Value */ 893 #define RTC_MODE1_COMP_COMP_Msk (_U_(0xFFFF) << RTC_MODE1_COMP_COMP_Pos) 894 #define RTC_MODE1_COMP_COMP(value) (RTC_MODE1_COMP_COMP_Msk & ((value) << RTC_MODE1_COMP_COMP_Pos)) 895 #define RTC_MODE1_COMP_MASK _U_(0xFFFF) /**< \brief (RTC_MODE1_COMP) MASK Register */ 896 897 /* -------- RTC_MODE2_ALARM : (RTC Offset: 0x18) (R/W 32) MODE2 MODE2_ALARM Alarm n Value -------- */ 898 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 899 typedef union { 900 struct { 901 uint32_t SECOND:6; /*!< bit: 0.. 5 Second */ 902 uint32_t MINUTE:6; /*!< bit: 6..11 Minute */ 903 uint32_t HOUR:5; /*!< bit: 12..16 Hour */ 904 uint32_t DAY:5; /*!< bit: 17..21 Day */ 905 uint32_t MONTH:4; /*!< bit: 22..25 Month */ 906 uint32_t YEAR:6; /*!< bit: 26..31 Year */ 907 } bit; /*!< Structure used for bit access */ 908 uint32_t reg; /*!< Type used for register access */ 909 } RTC_MODE2_ALARM_Type; 910 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 911 912 #define RTC_MODE2_ALARM_OFFSET 0x18 /**< \brief (RTC_MODE2_ALARM offset) MODE2_ALARM Alarm n Value */ 913 #define RTC_MODE2_ALARM_RESETVALUE _U_(0x00000000) /**< \brief (RTC_MODE2_ALARM reset_value) MODE2_ALARM Alarm n Value */ 914 915 #define RTC_MODE2_ALARM_SECOND_Pos 0 /**< \brief (RTC_MODE2_ALARM) Second */ 916 #define RTC_MODE2_ALARM_SECOND_Msk (_U_(0x3F) << RTC_MODE2_ALARM_SECOND_Pos) 917 #define RTC_MODE2_ALARM_SECOND(value) (RTC_MODE2_ALARM_SECOND_Msk & ((value) << RTC_MODE2_ALARM_SECOND_Pos)) 918 #define RTC_MODE2_ALARM_MINUTE_Pos 6 /**< \brief (RTC_MODE2_ALARM) Minute */ 919 #define RTC_MODE2_ALARM_MINUTE_Msk (_U_(0x3F) << RTC_MODE2_ALARM_MINUTE_Pos) 920 #define RTC_MODE2_ALARM_MINUTE(value) (RTC_MODE2_ALARM_MINUTE_Msk & ((value) << RTC_MODE2_ALARM_MINUTE_Pos)) 921 #define RTC_MODE2_ALARM_HOUR_Pos 12 /**< \brief (RTC_MODE2_ALARM) Hour */ 922 #define RTC_MODE2_ALARM_HOUR_Msk (_U_(0x1F) << RTC_MODE2_ALARM_HOUR_Pos) 923 #define RTC_MODE2_ALARM_HOUR(value) (RTC_MODE2_ALARM_HOUR_Msk & ((value) << RTC_MODE2_ALARM_HOUR_Pos)) 924 #define RTC_MODE2_ALARM_HOUR_AM_Val _U_(0x0) /**< \brief (RTC_MODE2_ALARM) Morning hour */ 925 #define RTC_MODE2_ALARM_HOUR_PM_Val _U_(0x10) /**< \brief (RTC_MODE2_ALARM) Afternoon hour */ 926 #define RTC_MODE2_ALARM_HOUR_AM (RTC_MODE2_ALARM_HOUR_AM_Val << RTC_MODE2_ALARM_HOUR_Pos) 927 #define RTC_MODE2_ALARM_HOUR_PM (RTC_MODE2_ALARM_HOUR_PM_Val << RTC_MODE2_ALARM_HOUR_Pos) 928 #define RTC_MODE2_ALARM_DAY_Pos 17 /**< \brief (RTC_MODE2_ALARM) Day */ 929 #define RTC_MODE2_ALARM_DAY_Msk (_U_(0x1F) << RTC_MODE2_ALARM_DAY_Pos) 930 #define RTC_MODE2_ALARM_DAY(value) (RTC_MODE2_ALARM_DAY_Msk & ((value) << RTC_MODE2_ALARM_DAY_Pos)) 931 #define RTC_MODE2_ALARM_MONTH_Pos 22 /**< \brief (RTC_MODE2_ALARM) Month */ 932 #define RTC_MODE2_ALARM_MONTH_Msk (_U_(0xF) << RTC_MODE2_ALARM_MONTH_Pos) 933 #define RTC_MODE2_ALARM_MONTH(value) (RTC_MODE2_ALARM_MONTH_Msk & ((value) << RTC_MODE2_ALARM_MONTH_Pos)) 934 #define RTC_MODE2_ALARM_YEAR_Pos 26 /**< \brief (RTC_MODE2_ALARM) Year */ 935 #define RTC_MODE2_ALARM_YEAR_Msk (_U_(0x3F) << RTC_MODE2_ALARM_YEAR_Pos) 936 #define RTC_MODE2_ALARM_YEAR(value) (RTC_MODE2_ALARM_YEAR_Msk & ((value) << RTC_MODE2_ALARM_YEAR_Pos)) 937 #define RTC_MODE2_ALARM_MASK _U_(0xFFFFFFFF) /**< \brief (RTC_MODE2_ALARM) MASK Register */ 938 939 /* -------- RTC_MODE2_MASK : (RTC Offset: 0x1C) (R/W 8) MODE2 MODE2_ALARM Alarm n Mask -------- */ 940 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 941 typedef union { 942 struct { 943 uint8_t SEL:3; /*!< bit: 0.. 2 Alarm Mask Selection */ 944 uint8_t :5; /*!< bit: 3.. 7 Reserved */ 945 } bit; /*!< Structure used for bit access */ 946 uint8_t reg; /*!< Type used for register access */ 947 } RTC_MODE2_MASK_Type; 948 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 949 950 #define RTC_MODE2_MASK_OFFSET 0x1C /**< \brief (RTC_MODE2_MASK offset) MODE2_ALARM Alarm n Mask */ 951 #define RTC_MODE2_MASK_RESETVALUE _U_(0x00) /**< \brief (RTC_MODE2_MASK reset_value) MODE2_ALARM Alarm n Mask */ 952 953 #define RTC_MODE2_MASK_SEL_Pos 0 /**< \brief (RTC_MODE2_MASK) Alarm Mask Selection */ 954 #define RTC_MODE2_MASK_SEL_Msk (_U_(0x7) << RTC_MODE2_MASK_SEL_Pos) 955 #define RTC_MODE2_MASK_SEL(value) (RTC_MODE2_MASK_SEL_Msk & ((value) << RTC_MODE2_MASK_SEL_Pos)) 956 #define RTC_MODE2_MASK_SEL_OFF_Val _U_(0x0) /**< \brief (RTC_MODE2_MASK) Alarm Disabled */ 957 #define RTC_MODE2_MASK_SEL_SS_Val _U_(0x1) /**< \brief (RTC_MODE2_MASK) Match seconds only */ 958 #define RTC_MODE2_MASK_SEL_MMSS_Val _U_(0x2) /**< \brief (RTC_MODE2_MASK) Match seconds and minutes only */ 959 #define RTC_MODE2_MASK_SEL_HHMMSS_Val _U_(0x3) /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, and hours only */ 960 #define RTC_MODE2_MASK_SEL_DDHHMMSS_Val _U_(0x4) /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, hours, and days only */ 961 #define RTC_MODE2_MASK_SEL_MMDDHHMMSS_Val _U_(0x5) /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, hours, days, and months only */ 962 #define RTC_MODE2_MASK_SEL_YYMMDDHHMMSS_Val _U_(0x6) /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, hours, days, months, and years */ 963 #define RTC_MODE2_MASK_SEL_OFF (RTC_MODE2_MASK_SEL_OFF_Val << RTC_MODE2_MASK_SEL_Pos) 964 #define RTC_MODE2_MASK_SEL_SS (RTC_MODE2_MASK_SEL_SS_Val << RTC_MODE2_MASK_SEL_Pos) 965 #define RTC_MODE2_MASK_SEL_MMSS (RTC_MODE2_MASK_SEL_MMSS_Val << RTC_MODE2_MASK_SEL_Pos) 966 #define RTC_MODE2_MASK_SEL_HHMMSS (RTC_MODE2_MASK_SEL_HHMMSS_Val << RTC_MODE2_MASK_SEL_Pos) 967 #define RTC_MODE2_MASK_SEL_DDHHMMSS (RTC_MODE2_MASK_SEL_DDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos) 968 #define RTC_MODE2_MASK_SEL_MMDDHHMMSS (RTC_MODE2_MASK_SEL_MMDDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos) 969 #define RTC_MODE2_MASK_SEL_YYMMDDHHMMSS (RTC_MODE2_MASK_SEL_YYMMDDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos) 970 #define RTC_MODE2_MASK_MASK _U_(0x07) /**< \brief (RTC_MODE2_MASK) MASK Register */ 971 972 /** \brief RtcMode2Alarm hardware registers */ 973 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 974 typedef struct { 975 __IO RTC_MODE2_ALARM_Type ALARM; /**< \brief Offset: 0x00 (R/W 32) MODE2_ALARM Alarm n Value */ 976 __IO RTC_MODE2_MASK_Type MASK; /**< \brief Offset: 0x04 (R/W 8) MODE2_ALARM Alarm n Mask */ 977 RoReg8 Reserved1[0x3]; 978 } RtcMode2Alarm; 979 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 980 981 /** \brief RTC_MODE0 hardware registers */ 982 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 983 typedef struct { /* 32-bit Counter with Single 32-bit Compare */ 984 __IO RTC_MODE0_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE0 Control */ 985 __IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */ 986 __IO RTC_MODE0_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE0 Event Control */ 987 __IO RTC_MODE0_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE0 Interrupt Enable Clear */ 988 __IO RTC_MODE0_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE0 Interrupt Enable Set */ 989 __IO RTC_MODE0_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE0 Interrupt Flag Status and Clear */ 990 RoReg8 Reserved1[0x1]; 991 __IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */ 992 __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */ 993 __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */ 994 RoReg8 Reserved2[0x3]; 995 __IO RTC_MODE0_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 32) MODE0 Counter Value */ 996 RoReg8 Reserved3[0x4]; 997 __IO RTC_MODE0_COMP_Type COMP[1]; /**< \brief Offset: 0x18 (R/W 32) MODE0 Compare n Value */ 998 } RtcMode0; 999 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1000 1001 /** \brief RTC_MODE1 hardware registers */ 1002 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1003 typedef struct { /* 16-bit Counter with Two 16-bit Compares */ 1004 __IO RTC_MODE1_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE1 Control */ 1005 __IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */ 1006 __IO RTC_MODE1_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE1 Event Control */ 1007 __IO RTC_MODE1_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE1 Interrupt Enable Clear */ 1008 __IO RTC_MODE1_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE1 Interrupt Enable Set */ 1009 __IO RTC_MODE1_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE1 Interrupt Flag Status and Clear */ 1010 RoReg8 Reserved1[0x1]; 1011 __IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */ 1012 __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */ 1013 __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */ 1014 RoReg8 Reserved2[0x3]; 1015 __IO RTC_MODE1_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 16) MODE1 Counter Value */ 1016 RoReg8 Reserved3[0x2]; 1017 __IO RTC_MODE1_PER_Type PER; /**< \brief Offset: 0x14 (R/W 16) MODE1 Counter Period */ 1018 RoReg8 Reserved4[0x2]; 1019 __IO RTC_MODE1_COMP_Type COMP[2]; /**< \brief Offset: 0x18 (R/W 16) MODE1 Compare n Value */ 1020 } RtcMode1; 1021 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1022 1023 /** \brief RTC_MODE2 hardware registers */ 1024 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1025 typedef struct { /* Clock/Calendar with Alarm */ 1026 __IO RTC_MODE2_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE2 Control */ 1027 __IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */ 1028 __IO RTC_MODE2_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE2 Event Control */ 1029 __IO RTC_MODE2_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE2 Interrupt Enable Clear */ 1030 __IO RTC_MODE2_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE2 Interrupt Enable Set */ 1031 __IO RTC_MODE2_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE2 Interrupt Flag Status and Clear */ 1032 RoReg8 Reserved1[0x1]; 1033 __IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */ 1034 __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */ 1035 __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */ 1036 RoReg8 Reserved2[0x3]; 1037 __IO RTC_MODE2_CLOCK_Type CLOCK; /**< \brief Offset: 0x10 (R/W 32) MODE2 Clock Value */ 1038 RoReg8 Reserved3[0x4]; 1039 RtcMode2Alarm Mode2Alarm[1]; /**< \brief Offset: 0x18 RtcMode2Alarm groups [ALARM_NUM] */ 1040 } RtcMode2; 1041 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1042 1043 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1044 typedef union { 1045 RtcMode0 MODE0; /**< \brief Offset: 0x00 32-bit Counter with Single 32-bit Compare */ 1046 RtcMode1 MODE1; /**< \brief Offset: 0x00 16-bit Counter with Two 16-bit Compares */ 1047 RtcMode2 MODE2; /**< \brief Offset: 0x00 Clock/Calendar with Alarm */ 1048 } Rtc; 1049 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1050 1051 /*@}*/ 1052 1053 #endif /* _SAMD21_RTC_COMPONENT_ */ 1054
