1 /** 2 * \file 3 * 4 * \brief Peripheral I/O description for SAMD20G16 5 * 6 * Copyright (c) 2017 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAMD20G16_PIO_ 31 #define _SAMD20G16_PIO_ 32 33 #define PIN_PA00 0 /**< \brief Pin Number for PA00 */ 34 #define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */ 35 #define PIN_PA01 1 /**< \brief Pin Number for PA01 */ 36 #define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */ 37 #define PIN_PA02 2 /**< \brief Pin Number for PA02 */ 38 #define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */ 39 #define PIN_PA03 3 /**< \brief Pin Number for PA03 */ 40 #define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */ 41 #define PIN_PA04 4 /**< \brief Pin Number for PA04 */ 42 #define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */ 43 #define PIN_PA05 5 /**< \brief Pin Number for PA05 */ 44 #define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */ 45 #define PIN_PA06 6 /**< \brief Pin Number for PA06 */ 46 #define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */ 47 #define PIN_PA07 7 /**< \brief Pin Number for PA07 */ 48 #define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */ 49 #define PIN_PA08 8 /**< \brief Pin Number for PA08 */ 50 #define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */ 51 #define PIN_PA09 9 /**< \brief Pin Number for PA09 */ 52 #define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */ 53 #define PIN_PA10 10 /**< \brief Pin Number for PA10 */ 54 #define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */ 55 #define PIN_PA11 11 /**< \brief Pin Number for PA11 */ 56 #define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */ 57 #define PIN_PA12 12 /**< \brief Pin Number for PA12 */ 58 #define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */ 59 #define PIN_PA13 13 /**< \brief Pin Number for PA13 */ 60 #define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */ 61 #define PIN_PA14 14 /**< \brief Pin Number for PA14 */ 62 #define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */ 63 #define PIN_PA15 15 /**< \brief Pin Number for PA15 */ 64 #define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */ 65 #define PIN_PA16 16 /**< \brief Pin Number for PA16 */ 66 #define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */ 67 #define PIN_PA17 17 /**< \brief Pin Number for PA17 */ 68 #define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */ 69 #define PIN_PA18 18 /**< \brief Pin Number for PA18 */ 70 #define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */ 71 #define PIN_PA19 19 /**< \brief Pin Number for PA19 */ 72 #define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */ 73 #define PIN_PA20 20 /**< \brief Pin Number for PA20 */ 74 #define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */ 75 #define PIN_PA21 21 /**< \brief Pin Number for PA21 */ 76 #define PORT_PA21 (_UL_(1) << 21) /**< \brief PORT Mask for PA21 */ 77 #define PIN_PA22 22 /**< \brief Pin Number for PA22 */ 78 #define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */ 79 #define PIN_PA23 23 /**< \brief Pin Number for PA23 */ 80 #define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */ 81 #define PIN_PA24 24 /**< \brief Pin Number for PA24 */ 82 #define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */ 83 #define PIN_PA25 25 /**< \brief Pin Number for PA25 */ 84 #define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */ 85 #define PIN_PA27 27 /**< \brief Pin Number for PA27 */ 86 #define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */ 87 #define PIN_PA28 28 /**< \brief Pin Number for PA28 */ 88 #define PORT_PA28 (_UL_(1) << 28) /**< \brief PORT Mask for PA28 */ 89 #define PIN_PA30 30 /**< \brief Pin Number for PA30 */ 90 #define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */ 91 #define PIN_PA31 31 /**< \brief Pin Number for PA31 */ 92 #define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */ 93 #define PIN_PB02 34 /**< \brief Pin Number for PB02 */ 94 #define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */ 95 #define PIN_PB03 35 /**< \brief Pin Number for PB03 */ 96 #define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */ 97 #define PIN_PB08 40 /**< \brief Pin Number for PB08 */ 98 #define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */ 99 #define PIN_PB09 41 /**< \brief Pin Number for PB09 */ 100 #define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */ 101 #define PIN_PB10 42 /**< \brief Pin Number for PB10 */ 102 #define PORT_PB10 (_UL_(1) << 10) /**< \brief PORT Mask for PB10 */ 103 #define PIN_PB11 43 /**< \brief Pin Number for PB11 */ 104 #define PORT_PB11 (_UL_(1) << 11) /**< \brief PORT Mask for PB11 */ 105 #define PIN_PB22 54 /**< \brief Pin Number for PB22 */ 106 #define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */ 107 #define PIN_PB23 55 /**< \brief Pin Number for PB23 */ 108 #define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */ 109 /* ========== PORT definition for GCLK peripheral ========== */ 110 #define PIN_PB22H_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux H */ 111 #define MUX_PB22H_GCLK_IO0 _L_(7) 112 #define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0) 113 #define PORT_PB22H_GCLK_IO0 (_UL_(1) << 22) 114 #define PIN_PA14H_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux H */ 115 #define MUX_PA14H_GCLK_IO0 _L_(7) 116 #define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) 117 #define PORT_PA14H_GCLK_IO0 (_UL_(1) << 14) 118 #define PIN_PA27H_GCLK_IO0 _L_(27) /**< \brief GCLK signal: IO0 on PA27 mux H */ 119 #define MUX_PA27H_GCLK_IO0 _L_(7) 120 #define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) 121 #define PORT_PA27H_GCLK_IO0 (_UL_(1) << 27) 122 #define PIN_PA28H_GCLK_IO0 _L_(28) /**< \brief GCLK signal: IO0 on PA28 mux H */ 123 #define MUX_PA28H_GCLK_IO0 _L_(7) 124 #define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0) 125 #define PORT_PA28H_GCLK_IO0 (_UL_(1) << 28) 126 #define PIN_PA30H_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux H */ 127 #define MUX_PA30H_GCLK_IO0 _L_(7) 128 #define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) 129 #define PORT_PA30H_GCLK_IO0 (_UL_(1) << 30) 130 #define PIN_PB23H_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux H */ 131 #define MUX_PB23H_GCLK_IO1 _L_(7) 132 #define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1) 133 #define PORT_PB23H_GCLK_IO1 (_UL_(1) << 23) 134 #define PIN_PA15H_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux H */ 135 #define MUX_PA15H_GCLK_IO1 _L_(7) 136 #define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) 137 #define PORT_PA15H_GCLK_IO1 (_UL_(1) << 15) 138 #define PIN_PA16H_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux H */ 139 #define MUX_PA16H_GCLK_IO2 _L_(7) 140 #define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) 141 #define PORT_PA16H_GCLK_IO2 (_UL_(1) << 16) 142 #define PIN_PA17H_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux H */ 143 #define MUX_PA17H_GCLK_IO3 _L_(7) 144 #define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) 145 #define PORT_PA17H_GCLK_IO3 (_UL_(1) << 17) 146 #define PIN_PA10H_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux H */ 147 #define MUX_PA10H_GCLK_IO4 _L_(7) 148 #define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) 149 #define PORT_PA10H_GCLK_IO4 (_UL_(1) << 10) 150 #define PIN_PA20H_GCLK_IO4 _L_(20) /**< \brief GCLK signal: IO4 on PA20 mux H */ 151 #define MUX_PA20H_GCLK_IO4 _L_(7) 152 #define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4) 153 #define PORT_PA20H_GCLK_IO4 (_UL_(1) << 20) 154 #define PIN_PB10H_GCLK_IO4 _L_(42) /**< \brief GCLK signal: IO4 on PB10 mux H */ 155 #define MUX_PB10H_GCLK_IO4 _L_(7) 156 #define PINMUX_PB10H_GCLK_IO4 ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4) 157 #define PORT_PB10H_GCLK_IO4 (_UL_(1) << 10) 158 #define PIN_PA11H_GCLK_IO5 _L_(11) /**< \brief GCLK signal: IO5 on PA11 mux H */ 159 #define MUX_PA11H_GCLK_IO5 _L_(7) 160 #define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) 161 #define PORT_PA11H_GCLK_IO5 (_UL_(1) << 11) 162 #define PIN_PA21H_GCLK_IO5 _L_(21) /**< \brief GCLK signal: IO5 on PA21 mux H */ 163 #define MUX_PA21H_GCLK_IO5 _L_(7) 164 #define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5) 165 #define PORT_PA21H_GCLK_IO5 (_UL_(1) << 21) 166 #define PIN_PB11H_GCLK_IO5 _L_(43) /**< \brief GCLK signal: IO5 on PB11 mux H */ 167 #define MUX_PB11H_GCLK_IO5 _L_(7) 168 #define PINMUX_PB11H_GCLK_IO5 ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5) 169 #define PORT_PB11H_GCLK_IO5 (_UL_(1) << 11) 170 #define PIN_PA22H_GCLK_IO6 _L_(22) /**< \brief GCLK signal: IO6 on PA22 mux H */ 171 #define MUX_PA22H_GCLK_IO6 _L_(7) 172 #define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6) 173 #define PORT_PA22H_GCLK_IO6 (_UL_(1) << 22) 174 #define PIN_PA23H_GCLK_IO7 _L_(23) /**< \brief GCLK signal: IO7 on PA23 mux H */ 175 #define MUX_PA23H_GCLK_IO7 _L_(7) 176 #define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7) 177 #define PORT_PA23H_GCLK_IO7 (_UL_(1) << 23) 178 /* ========== PORT definition for EIC peripheral ========== */ 179 #define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */ 180 #define MUX_PA16A_EIC_EXTINT0 _L_(0) 181 #define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) 182 #define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16) 183 #define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ 184 #define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */ 185 #define MUX_PA00A_EIC_EXTINT0 _L_(0) 186 #define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) 187 #define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0) 188 #define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */ 189 #define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */ 190 #define MUX_PA17A_EIC_EXTINT1 _L_(0) 191 #define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) 192 #define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17) 193 #define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ 194 #define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */ 195 #define MUX_PA01A_EIC_EXTINT1 _L_(0) 196 #define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) 197 #define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1) 198 #define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */ 199 #define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */ 200 #define MUX_PA02A_EIC_EXTINT2 _L_(0) 201 #define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) 202 #define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2) 203 #define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */ 204 #define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */ 205 #define MUX_PA18A_EIC_EXTINT2 _L_(0) 206 #define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) 207 #define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18) 208 #define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ 209 #define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */ 210 #define MUX_PB02A_EIC_EXTINT2 _L_(0) 211 #define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) 212 #define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2) 213 #define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */ 214 #define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */ 215 #define MUX_PA03A_EIC_EXTINT3 _L_(0) 216 #define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) 217 #define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3) 218 #define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */ 219 #define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */ 220 #define MUX_PA19A_EIC_EXTINT3 _L_(0) 221 #define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) 222 #define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19) 223 #define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ 224 #define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */ 225 #define MUX_PB03A_EIC_EXTINT3 _L_(0) 226 #define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) 227 #define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3) 228 #define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */ 229 #define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */ 230 #define MUX_PA04A_EIC_EXTINT4 _L_(0) 231 #define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) 232 #define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4) 233 #define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */ 234 #define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */ 235 #define MUX_PA20A_EIC_EXTINT4 _L_(0) 236 #define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) 237 #define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20) 238 #define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */ 239 #define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */ 240 #define MUX_PA05A_EIC_EXTINT5 _L_(0) 241 #define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) 242 #define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5) 243 #define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */ 244 #define PIN_PA21A_EIC_EXTINT5 _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */ 245 #define MUX_PA21A_EIC_EXTINT5 _L_(0) 246 #define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) 247 #define PORT_PA21A_EIC_EXTINT5 (_UL_(1) << 21) 248 #define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */ 249 #define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */ 250 #define MUX_PA06A_EIC_EXTINT6 _L_(0) 251 #define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) 252 #define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6) 253 #define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ 254 #define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */ 255 #define MUX_PA22A_EIC_EXTINT6 _L_(0) 256 #define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) 257 #define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22) 258 #define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */ 259 #define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */ 260 #define MUX_PB22A_EIC_EXTINT6 _L_(0) 261 #define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) 262 #define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22) 263 #define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */ 264 #define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */ 265 #define MUX_PA07A_EIC_EXTINT7 _L_(0) 266 #define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) 267 #define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7) 268 #define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ 269 #define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */ 270 #define MUX_PA23A_EIC_EXTINT7 _L_(0) 271 #define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) 272 #define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23) 273 #define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */ 274 #define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */ 275 #define MUX_PB23A_EIC_EXTINT7 _L_(0) 276 #define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) 277 #define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23) 278 #define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */ 279 #define PIN_PA28A_EIC_EXTINT8 _L_(28) /**< \brief EIC signal: EXTINT8 on PA28 mux A */ 280 #define MUX_PA28A_EIC_EXTINT8 _L_(0) 281 #define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8) 282 #define PORT_PA28A_EIC_EXTINT8 (_UL_(1) << 28) 283 #define PIN_PA28A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PA28 External Interrupt Line */ 284 #define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */ 285 #define MUX_PB08A_EIC_EXTINT8 _L_(0) 286 #define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) 287 #define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8) 288 #define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */ 289 #define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */ 290 #define MUX_PA09A_EIC_EXTINT9 _L_(0) 291 #define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) 292 #define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9) 293 #define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */ 294 #define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */ 295 #define MUX_PB09A_EIC_EXTINT9 _L_(0) 296 #define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) 297 #define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9) 298 #define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */ 299 #define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */ 300 #define MUX_PA10A_EIC_EXTINT10 _L_(0) 301 #define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) 302 #define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10) 303 #define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */ 304 #define PIN_PA30A_EIC_EXTINT10 _L_(30) /**< \brief EIC signal: EXTINT10 on PA30 mux A */ 305 #define MUX_PA30A_EIC_EXTINT10 _L_(0) 306 #define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) 307 #define PORT_PA30A_EIC_EXTINT10 (_UL_(1) << 30) 308 #define PIN_PA30A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */ 309 #define PIN_PB10A_EIC_EXTINT10 _L_(42) /**< \brief EIC signal: EXTINT10 on PB10 mux A */ 310 #define MUX_PB10A_EIC_EXTINT10 _L_(0) 311 #define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) 312 #define PORT_PB10A_EIC_EXTINT10 (_UL_(1) << 10) 313 #define PIN_PB10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PB10 External Interrupt Line */ 314 #define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */ 315 #define MUX_PA11A_EIC_EXTINT11 _L_(0) 316 #define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) 317 #define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11) 318 #define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */ 319 #define PIN_PA31A_EIC_EXTINT11 _L_(31) /**< \brief EIC signal: EXTINT11 on PA31 mux A */ 320 #define MUX_PA31A_EIC_EXTINT11 _L_(0) 321 #define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) 322 #define PORT_PA31A_EIC_EXTINT11 (_UL_(1) << 31) 323 #define PIN_PA31A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */ 324 #define PIN_PB11A_EIC_EXTINT11 _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */ 325 #define MUX_PB11A_EIC_EXTINT11 _L_(0) 326 #define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) 327 #define PORT_PB11A_EIC_EXTINT11 (_UL_(1) << 11) 328 #define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */ 329 #define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */ 330 #define MUX_PA12A_EIC_EXTINT12 _L_(0) 331 #define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) 332 #define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12) 333 #define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */ 334 #define PIN_PA24A_EIC_EXTINT12 _L_(24) /**< \brief EIC signal: EXTINT12 on PA24 mux A */ 335 #define MUX_PA24A_EIC_EXTINT12 _L_(0) 336 #define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) 337 #define PORT_PA24A_EIC_EXTINT12 (_UL_(1) << 24) 338 #define PIN_PA24A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */ 339 #define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */ 340 #define MUX_PA13A_EIC_EXTINT13 _L_(0) 341 #define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) 342 #define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13) 343 #define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */ 344 #define PIN_PA25A_EIC_EXTINT13 _L_(25) /**< \brief EIC signal: EXTINT13 on PA25 mux A */ 345 #define MUX_PA25A_EIC_EXTINT13 _L_(0) 346 #define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) 347 #define PORT_PA25A_EIC_EXTINT13 (_UL_(1) << 25) 348 #define PIN_PA25A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */ 349 #define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */ 350 #define MUX_PA14A_EIC_EXTINT14 _L_(0) 351 #define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) 352 #define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14) 353 #define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */ 354 #define PIN_PA27A_EIC_EXTINT15 _L_(27) /**< \brief EIC signal: EXTINT15 on PA27 mux A */ 355 #define MUX_PA27A_EIC_EXTINT15 _L_(0) 356 #define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) 357 #define PORT_PA27A_EIC_EXTINT15 (_UL_(1) << 27) 358 #define PIN_PA27A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */ 359 #define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */ 360 #define MUX_PA15A_EIC_EXTINT15 _L_(0) 361 #define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) 362 #define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15) 363 #define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */ 364 #define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */ 365 #define MUX_PA08A_EIC_NMI _L_(0) 366 #define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) 367 #define PORT_PA08A_EIC_NMI (_UL_(1) << 8) 368 /* ========== PORT definition for SERCOM0 peripheral ========== */ 369 #define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ 370 #define MUX_PA04D_SERCOM0_PAD0 _L_(3) 371 #define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) 372 #define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4) 373 #define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ 374 #define MUX_PA08C_SERCOM0_PAD0 _L_(2) 375 #define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) 376 #define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8) 377 #define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ 378 #define MUX_PA05D_SERCOM0_PAD1 _L_(3) 379 #define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) 380 #define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5) 381 #define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ 382 #define MUX_PA09C_SERCOM0_PAD1 _L_(2) 383 #define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) 384 #define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9) 385 #define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ 386 #define MUX_PA06D_SERCOM0_PAD2 _L_(3) 387 #define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) 388 #define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6) 389 #define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ 390 #define MUX_PA10C_SERCOM0_PAD2 _L_(2) 391 #define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) 392 #define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10) 393 #define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ 394 #define MUX_PA07D_SERCOM0_PAD3 _L_(3) 395 #define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) 396 #define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7) 397 #define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ 398 #define MUX_PA11C_SERCOM0_PAD3 _L_(2) 399 #define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) 400 #define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11) 401 /* ========== PORT definition for SERCOM1 peripheral ========== */ 402 #define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ 403 #define MUX_PA16C_SERCOM1_PAD0 _L_(2) 404 #define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) 405 #define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16) 406 #define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ 407 #define MUX_PA00D_SERCOM1_PAD0 _L_(3) 408 #define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) 409 #define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0) 410 #define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ 411 #define MUX_PA17C_SERCOM1_PAD1 _L_(2) 412 #define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) 413 #define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17) 414 #define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ 415 #define MUX_PA01D_SERCOM1_PAD1 _L_(3) 416 #define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) 417 #define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1) 418 #define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ 419 #define MUX_PA30D_SERCOM1_PAD2 _L_(3) 420 #define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) 421 #define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30) 422 #define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ 423 #define MUX_PA18C_SERCOM1_PAD2 _L_(2) 424 #define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) 425 #define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18) 426 #define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ 427 #define MUX_PA31D_SERCOM1_PAD3 _L_(3) 428 #define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) 429 #define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31) 430 #define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ 431 #define MUX_PA19C_SERCOM1_PAD3 _L_(2) 432 #define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) 433 #define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19) 434 /* ========== PORT definition for SERCOM2 peripheral ========== */ 435 #define PIN_PA08D_SERCOM2_PAD0 _L_(8) /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ 436 #define MUX_PA08D_SERCOM2_PAD0 _L_(3) 437 #define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) 438 #define PORT_PA08D_SERCOM2_PAD0 (_UL_(1) << 8) 439 #define PIN_PA12C_SERCOM2_PAD0 _L_(12) /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ 440 #define MUX_PA12C_SERCOM2_PAD0 _L_(2) 441 #define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) 442 #define PORT_PA12C_SERCOM2_PAD0 (_UL_(1) << 12) 443 #define PIN_PA09D_SERCOM2_PAD1 _L_(9) /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ 444 #define MUX_PA09D_SERCOM2_PAD1 _L_(3) 445 #define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) 446 #define PORT_PA09D_SERCOM2_PAD1 (_UL_(1) << 9) 447 #define PIN_PA13C_SERCOM2_PAD1 _L_(13) /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ 448 #define MUX_PA13C_SERCOM2_PAD1 _L_(2) 449 #define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) 450 #define PORT_PA13C_SERCOM2_PAD1 (_UL_(1) << 13) 451 #define PIN_PA10D_SERCOM2_PAD2 _L_(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ 452 #define MUX_PA10D_SERCOM2_PAD2 _L_(3) 453 #define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) 454 #define PORT_PA10D_SERCOM2_PAD2 (_UL_(1) << 10) 455 #define PIN_PA14C_SERCOM2_PAD2 _L_(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ 456 #define MUX_PA14C_SERCOM2_PAD2 _L_(2) 457 #define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) 458 #define PORT_PA14C_SERCOM2_PAD2 (_UL_(1) << 14) 459 #define PIN_PA11D_SERCOM2_PAD3 _L_(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ 460 #define MUX_PA11D_SERCOM2_PAD3 _L_(3) 461 #define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) 462 #define PORT_PA11D_SERCOM2_PAD3 (_UL_(1) << 11) 463 #define PIN_PA15C_SERCOM2_PAD3 _L_(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ 464 #define MUX_PA15C_SERCOM2_PAD3 _L_(2) 465 #define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) 466 #define PORT_PA15C_SERCOM2_PAD3 (_UL_(1) << 15) 467 /* ========== PORT definition for SERCOM3 peripheral ========== */ 468 #define PIN_PA16D_SERCOM3_PAD0 _L_(16) /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ 469 #define MUX_PA16D_SERCOM3_PAD0 _L_(3) 470 #define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) 471 #define PORT_PA16D_SERCOM3_PAD0 (_UL_(1) << 16) 472 #define PIN_PA22C_SERCOM3_PAD0 _L_(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ 473 #define MUX_PA22C_SERCOM3_PAD0 _L_(2) 474 #define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) 475 #define PORT_PA22C_SERCOM3_PAD0 (_UL_(1) << 22) 476 #define PIN_PA17D_SERCOM3_PAD1 _L_(17) /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ 477 #define MUX_PA17D_SERCOM3_PAD1 _L_(3) 478 #define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) 479 #define PORT_PA17D_SERCOM3_PAD1 (_UL_(1) << 17) 480 #define PIN_PA23C_SERCOM3_PAD1 _L_(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ 481 #define MUX_PA23C_SERCOM3_PAD1 _L_(2) 482 #define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) 483 #define PORT_PA23C_SERCOM3_PAD1 (_UL_(1) << 23) 484 #define PIN_PA18D_SERCOM3_PAD2 _L_(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ 485 #define MUX_PA18D_SERCOM3_PAD2 _L_(3) 486 #define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) 487 #define PORT_PA18D_SERCOM3_PAD2 (_UL_(1) << 18) 488 #define PIN_PA20D_SERCOM3_PAD2 _L_(20) /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ 489 #define MUX_PA20D_SERCOM3_PAD2 _L_(3) 490 #define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) 491 #define PORT_PA20D_SERCOM3_PAD2 (_UL_(1) << 20) 492 #define PIN_PA24C_SERCOM3_PAD2 _L_(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ 493 #define MUX_PA24C_SERCOM3_PAD2 _L_(2) 494 #define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) 495 #define PORT_PA24C_SERCOM3_PAD2 (_UL_(1) << 24) 496 #define PIN_PA19D_SERCOM3_PAD3 _L_(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ 497 #define MUX_PA19D_SERCOM3_PAD3 _L_(3) 498 #define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) 499 #define PORT_PA19D_SERCOM3_PAD3 (_UL_(1) << 19) 500 #define PIN_PA21D_SERCOM3_PAD3 _L_(21) /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ 501 #define MUX_PA21D_SERCOM3_PAD3 _L_(3) 502 #define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) 503 #define PORT_PA21D_SERCOM3_PAD3 (_UL_(1) << 21) 504 #define PIN_PA25C_SERCOM3_PAD3 _L_(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ 505 #define MUX_PA25C_SERCOM3_PAD3 _L_(2) 506 #define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) 507 #define PORT_PA25C_SERCOM3_PAD3 (_UL_(1) << 25) 508 /* ========== PORT definition for SERCOM4 peripheral ========== */ 509 #define PIN_PA12D_SERCOM4_PAD0 _L_(12) /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */ 510 #define MUX_PA12D_SERCOM4_PAD0 _L_(3) 511 #define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0) 512 #define PORT_PA12D_SERCOM4_PAD0 (_UL_(1) << 12) 513 #define PIN_PB08D_SERCOM4_PAD0 _L_(40) /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ 514 #define MUX_PB08D_SERCOM4_PAD0 _L_(3) 515 #define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) 516 #define PORT_PB08D_SERCOM4_PAD0 (_UL_(1) << 8) 517 #define PIN_PA13D_SERCOM4_PAD1 _L_(13) /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */ 518 #define MUX_PA13D_SERCOM4_PAD1 _L_(3) 519 #define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1) 520 #define PORT_PA13D_SERCOM4_PAD1 (_UL_(1) << 13) 521 #define PIN_PB09D_SERCOM4_PAD1 _L_(41) /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ 522 #define MUX_PB09D_SERCOM4_PAD1 _L_(3) 523 #define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) 524 #define PORT_PB09D_SERCOM4_PAD1 (_UL_(1) << 9) 525 #define PIN_PA14D_SERCOM4_PAD2 _L_(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ 526 #define MUX_PA14D_SERCOM4_PAD2 _L_(3) 527 #define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) 528 #define PORT_PA14D_SERCOM4_PAD2 (_UL_(1) << 14) 529 #define PIN_PB10D_SERCOM4_PAD2 _L_(42) /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ 530 #define MUX_PB10D_SERCOM4_PAD2 _L_(3) 531 #define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) 532 #define PORT_PB10D_SERCOM4_PAD2 (_UL_(1) << 10) 533 #define PIN_PA15D_SERCOM4_PAD3 _L_(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ 534 #define MUX_PA15D_SERCOM4_PAD3 _L_(3) 535 #define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) 536 #define PORT_PA15D_SERCOM4_PAD3 (_UL_(1) << 15) 537 #define PIN_PB11D_SERCOM4_PAD3 _L_(43) /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ 538 #define MUX_PB11D_SERCOM4_PAD3 _L_(3) 539 #define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) 540 #define PORT_PB11D_SERCOM4_PAD3 (_UL_(1) << 11) 541 /* ========== PORT definition for SERCOM5 peripheral ========== */ 542 #define PIN_PA22D_SERCOM5_PAD0 _L_(22) /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */ 543 #define MUX_PA22D_SERCOM5_PAD0 _L_(3) 544 #define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0) 545 #define PORT_PA22D_SERCOM5_PAD0 (_UL_(1) << 22) 546 #define PIN_PB02D_SERCOM5_PAD0 _L_(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ 547 #define MUX_PB02D_SERCOM5_PAD0 _L_(3) 548 #define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) 549 #define PORT_PB02D_SERCOM5_PAD0 (_UL_(1) << 2) 550 #define PIN_PA23D_SERCOM5_PAD1 _L_(23) /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */ 551 #define MUX_PA23D_SERCOM5_PAD1 _L_(3) 552 #define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1) 553 #define PORT_PA23D_SERCOM5_PAD1 (_UL_(1) << 23) 554 #define PIN_PB03D_SERCOM5_PAD1 _L_(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ 555 #define MUX_PB03D_SERCOM5_PAD1 _L_(3) 556 #define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) 557 #define PORT_PB03D_SERCOM5_PAD1 (_UL_(1) << 3) 558 #define PIN_PA24D_SERCOM5_PAD2 _L_(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ 559 #define MUX_PA24D_SERCOM5_PAD2 _L_(3) 560 #define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) 561 #define PORT_PA24D_SERCOM5_PAD2 (_UL_(1) << 24) 562 #define PIN_PB22D_SERCOM5_PAD2 _L_(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ 563 #define MUX_PB22D_SERCOM5_PAD2 _L_(3) 564 #define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) 565 #define PORT_PB22D_SERCOM5_PAD2 (_UL_(1) << 22) 566 #define PIN_PA20C_SERCOM5_PAD2 _L_(20) /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ 567 #define MUX_PA20C_SERCOM5_PAD2 _L_(2) 568 #define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) 569 #define PORT_PA20C_SERCOM5_PAD2 (_UL_(1) << 20) 570 #define PIN_PA25D_SERCOM5_PAD3 _L_(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ 571 #define MUX_PA25D_SERCOM5_PAD3 _L_(3) 572 #define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) 573 #define PORT_PA25D_SERCOM5_PAD3 (_UL_(1) << 25) 574 #define PIN_PB23D_SERCOM5_PAD3 _L_(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ 575 #define MUX_PB23D_SERCOM5_PAD3 _L_(3) 576 #define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) 577 #define PORT_PB23D_SERCOM5_PAD3 (_UL_(1) << 23) 578 #define PIN_PA21C_SERCOM5_PAD3 _L_(21) /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ 579 #define MUX_PA21C_SERCOM5_PAD3 _L_(2) 580 #define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) 581 #define PORT_PA21C_SERCOM5_PAD3 (_UL_(1) << 21) 582 /* ========== PORT definition for TC0 peripheral ========== */ 583 #define PIN_PA04F_TC0_WO0 _L_(4) /**< \brief TC0 signal: WO0 on PA04 mux F */ 584 #define MUX_PA04F_TC0_WO0 _L_(5) 585 #define PINMUX_PA04F_TC0_WO0 ((PIN_PA04F_TC0_WO0 << 16) | MUX_PA04F_TC0_WO0) 586 #define PORT_PA04F_TC0_WO0 (_UL_(1) << 4) 587 #define PIN_PA08E_TC0_WO0 _L_(8) /**< \brief TC0 signal: WO0 on PA08 mux E */ 588 #define MUX_PA08E_TC0_WO0 _L_(4) 589 #define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0) 590 #define PORT_PA08E_TC0_WO0 (_UL_(1) << 8) 591 #define PIN_PA05F_TC0_WO1 _L_(5) /**< \brief TC0 signal: WO1 on PA05 mux F */ 592 #define MUX_PA05F_TC0_WO1 _L_(5) 593 #define PINMUX_PA05F_TC0_WO1 ((PIN_PA05F_TC0_WO1 << 16) | MUX_PA05F_TC0_WO1) 594 #define PORT_PA05F_TC0_WO1 (_UL_(1) << 5) 595 #define PIN_PA09E_TC0_WO1 _L_(9) /**< \brief TC0 signal: WO1 on PA09 mux E */ 596 #define MUX_PA09E_TC0_WO1 _L_(4) 597 #define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1) 598 #define PORT_PA09E_TC0_WO1 (_UL_(1) << 9) 599 /* ========== PORT definition for TC1 peripheral ========== */ 600 #define PIN_PA06F_TC1_WO0 _L_(6) /**< \brief TC1 signal: WO0 on PA06 mux F */ 601 #define MUX_PA06F_TC1_WO0 _L_(5) 602 #define PINMUX_PA06F_TC1_WO0 ((PIN_PA06F_TC1_WO0 << 16) | MUX_PA06F_TC1_WO0) 603 #define PORT_PA06F_TC1_WO0 (_UL_(1) << 6) 604 #define PIN_PA30F_TC1_WO0 _L_(30) /**< \brief TC1 signal: WO0 on PA30 mux F */ 605 #define MUX_PA30F_TC1_WO0 _L_(5) 606 #define PINMUX_PA30F_TC1_WO0 ((PIN_PA30F_TC1_WO0 << 16) | MUX_PA30F_TC1_WO0) 607 #define PORT_PA30F_TC1_WO0 (_UL_(1) << 30) 608 #define PIN_PA10E_TC1_WO0 _L_(10) /**< \brief TC1 signal: WO0 on PA10 mux E */ 609 #define MUX_PA10E_TC1_WO0 _L_(4) 610 #define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0) 611 #define PORT_PA10E_TC1_WO0 (_UL_(1) << 10) 612 #define PIN_PA07F_TC1_WO1 _L_(7) /**< \brief TC1 signal: WO1 on PA07 mux F */ 613 #define MUX_PA07F_TC1_WO1 _L_(5) 614 #define PINMUX_PA07F_TC1_WO1 ((PIN_PA07F_TC1_WO1 << 16) | MUX_PA07F_TC1_WO1) 615 #define PORT_PA07F_TC1_WO1 (_UL_(1) << 7) 616 #define PIN_PA31F_TC1_WO1 _L_(31) /**< \brief TC1 signal: WO1 on PA31 mux F */ 617 #define MUX_PA31F_TC1_WO1 _L_(5) 618 #define PINMUX_PA31F_TC1_WO1 ((PIN_PA31F_TC1_WO1 << 16) | MUX_PA31F_TC1_WO1) 619 #define PORT_PA31F_TC1_WO1 (_UL_(1) << 31) 620 #define PIN_PA11E_TC1_WO1 _L_(11) /**< \brief TC1 signal: WO1 on PA11 mux E */ 621 #define MUX_PA11E_TC1_WO1 _L_(4) 622 #define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1) 623 #define PORT_PA11E_TC1_WO1 (_UL_(1) << 11) 624 /* ========== PORT definition for TC2 peripheral ========== */ 625 #define PIN_PA16F_TC2_WO0 _L_(16) /**< \brief TC2 signal: WO0 on PA16 mux F */ 626 #define MUX_PA16F_TC2_WO0 _L_(5) 627 #define PINMUX_PA16F_TC2_WO0 ((PIN_PA16F_TC2_WO0 << 16) | MUX_PA16F_TC2_WO0) 628 #define PORT_PA16F_TC2_WO0 (_UL_(1) << 16) 629 #define PIN_PA12E_TC2_WO0 _L_(12) /**< \brief TC2 signal: WO0 on PA12 mux E */ 630 #define MUX_PA12E_TC2_WO0 _L_(4) 631 #define PINMUX_PA12E_TC2_WO0 ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0) 632 #define PORT_PA12E_TC2_WO0 (_UL_(1) << 12) 633 #define PIN_PA00F_TC2_WO0 _L_(0) /**< \brief TC2 signal: WO0 on PA00 mux F */ 634 #define MUX_PA00F_TC2_WO0 _L_(5) 635 #define PINMUX_PA00F_TC2_WO0 ((PIN_PA00F_TC2_WO0 << 16) | MUX_PA00F_TC2_WO0) 636 #define PORT_PA00F_TC2_WO0 (_UL_(1) << 0) 637 #define PIN_PA17F_TC2_WO1 _L_(17) /**< \brief TC2 signal: WO1 on PA17 mux F */ 638 #define MUX_PA17F_TC2_WO1 _L_(5) 639 #define PINMUX_PA17F_TC2_WO1 ((PIN_PA17F_TC2_WO1 << 16) | MUX_PA17F_TC2_WO1) 640 #define PORT_PA17F_TC2_WO1 (_UL_(1) << 17) 641 #define PIN_PA13E_TC2_WO1 _L_(13) /**< \brief TC2 signal: WO1 on PA13 mux E */ 642 #define MUX_PA13E_TC2_WO1 _L_(4) 643 #define PINMUX_PA13E_TC2_WO1 ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1) 644 #define PORT_PA13E_TC2_WO1 (_UL_(1) << 13) 645 #define PIN_PA01F_TC2_WO1 _L_(1) /**< \brief TC2 signal: WO1 on PA01 mux F */ 646 #define MUX_PA01F_TC2_WO1 _L_(5) 647 #define PINMUX_PA01F_TC2_WO1 ((PIN_PA01F_TC2_WO1 << 16) | MUX_PA01F_TC2_WO1) 648 #define PORT_PA01F_TC2_WO1 (_UL_(1) << 1) 649 /* ========== PORT definition for TC3 peripheral ========== */ 650 #define PIN_PA18F_TC3_WO0 _L_(18) /**< \brief TC3 signal: WO0 on PA18 mux F */ 651 #define MUX_PA18F_TC3_WO0 _L_(5) 652 #define PINMUX_PA18F_TC3_WO0 ((PIN_PA18F_TC3_WO0 << 16) | MUX_PA18F_TC3_WO0) 653 #define PORT_PA18F_TC3_WO0 (_UL_(1) << 18) 654 #define PIN_PA14E_TC3_WO0 _L_(14) /**< \brief TC3 signal: WO0 on PA14 mux E */ 655 #define MUX_PA14E_TC3_WO0 _L_(4) 656 #define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) 657 #define PORT_PA14E_TC3_WO0 (_UL_(1) << 14) 658 #define PIN_PA19F_TC3_WO1 _L_(19) /**< \brief TC3 signal: WO1 on PA19 mux F */ 659 #define MUX_PA19F_TC3_WO1 _L_(5) 660 #define PINMUX_PA19F_TC3_WO1 ((PIN_PA19F_TC3_WO1 << 16) | MUX_PA19F_TC3_WO1) 661 #define PORT_PA19F_TC3_WO1 (_UL_(1) << 19) 662 #define PIN_PA15E_TC3_WO1 _L_(15) /**< \brief TC3 signal: WO1 on PA15 mux E */ 663 #define MUX_PA15E_TC3_WO1 _L_(4) 664 #define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) 665 #define PORT_PA15E_TC3_WO1 (_UL_(1) << 15) 666 /* ========== PORT definition for TC4 peripheral ========== */ 667 #define PIN_PA22F_TC4_WO0 _L_(22) /**< \brief TC4 signal: WO0 on PA22 mux F */ 668 #define MUX_PA22F_TC4_WO0 _L_(5) 669 #define PINMUX_PA22F_TC4_WO0 ((PIN_PA22F_TC4_WO0 << 16) | MUX_PA22F_TC4_WO0) 670 #define PORT_PA22F_TC4_WO0 (_UL_(1) << 22) 671 #define PIN_PB08F_TC4_WO0 _L_(40) /**< \brief TC4 signal: WO0 on PB08 mux F */ 672 #define MUX_PB08F_TC4_WO0 _L_(5) 673 #define PINMUX_PB08F_TC4_WO0 ((PIN_PB08F_TC4_WO0 << 16) | MUX_PB08F_TC4_WO0) 674 #define PORT_PB08F_TC4_WO0 (_UL_(1) << 8) 675 #define PIN_PA23F_TC4_WO1 _L_(23) /**< \brief TC4 signal: WO1 on PA23 mux F */ 676 #define MUX_PA23F_TC4_WO1 _L_(5) 677 #define PINMUX_PA23F_TC4_WO1 ((PIN_PA23F_TC4_WO1 << 16) | MUX_PA23F_TC4_WO1) 678 #define PORT_PA23F_TC4_WO1 (_UL_(1) << 23) 679 #define PIN_PB09F_TC4_WO1 _L_(41) /**< \brief TC4 signal: WO1 on PB09 mux F */ 680 #define MUX_PB09F_TC4_WO1 _L_(5) 681 #define PINMUX_PB09F_TC4_WO1 ((PIN_PB09F_TC4_WO1 << 16) | MUX_PB09F_TC4_WO1) 682 #define PORT_PB09F_TC4_WO1 (_UL_(1) << 9) 683 /* ========== PORT definition for TC5 peripheral ========== */ 684 #define PIN_PA24F_TC5_WO0 _L_(24) /**< \brief TC5 signal: WO0 on PA24 mux F */ 685 #define MUX_PA24F_TC5_WO0 _L_(5) 686 #define PINMUX_PA24F_TC5_WO0 ((PIN_PA24F_TC5_WO0 << 16) | MUX_PA24F_TC5_WO0) 687 #define PORT_PA24F_TC5_WO0 (_UL_(1) << 24) 688 #define PIN_PB10F_TC5_WO0 _L_(42) /**< \brief TC5 signal: WO0 on PB10 mux F */ 689 #define MUX_PB10F_TC5_WO0 _L_(5) 690 #define PINMUX_PB10F_TC5_WO0 ((PIN_PB10F_TC5_WO0 << 16) | MUX_PB10F_TC5_WO0) 691 #define PORT_PB10F_TC5_WO0 (_UL_(1) << 10) 692 #define PIN_PA25F_TC5_WO1 _L_(25) /**< \brief TC5 signal: WO1 on PA25 mux F */ 693 #define MUX_PA25F_TC5_WO1 _L_(5) 694 #define PINMUX_PA25F_TC5_WO1 ((PIN_PA25F_TC5_WO1 << 16) | MUX_PA25F_TC5_WO1) 695 #define PORT_PA25F_TC5_WO1 (_UL_(1) << 25) 696 #define PIN_PB11F_TC5_WO1 _L_(43) /**< \brief TC5 signal: WO1 on PB11 mux F */ 697 #define MUX_PB11F_TC5_WO1 _L_(5) 698 #define PINMUX_PB11F_TC5_WO1 ((PIN_PB11F_TC5_WO1 << 16) | MUX_PB11F_TC5_WO1) 699 #define PORT_PB11F_TC5_WO1 (_UL_(1) << 11) 700 /* ========== PORT definition for ADC peripheral ========== */ 701 #define PIN_PA02B_ADC_AIN0 _L_(2) /**< \brief ADC signal: AIN0 on PA02 mux B */ 702 #define MUX_PA02B_ADC_AIN0 _L_(1) 703 #define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) 704 #define PORT_PA02B_ADC_AIN0 (_UL_(1) << 2) 705 #define PIN_PA03B_ADC_AIN1 _L_(3) /**< \brief ADC signal: AIN1 on PA03 mux B */ 706 #define MUX_PA03B_ADC_AIN1 _L_(1) 707 #define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) 708 #define PORT_PA03B_ADC_AIN1 (_UL_(1) << 3) 709 #define PIN_PB08B_ADC_AIN2 _L_(40) /**< \brief ADC signal: AIN2 on PB08 mux B */ 710 #define MUX_PB08B_ADC_AIN2 _L_(1) 711 #define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2) 712 #define PORT_PB08B_ADC_AIN2 (_UL_(1) << 8) 713 #define PIN_PB09B_ADC_AIN3 _L_(41) /**< \brief ADC signal: AIN3 on PB09 mux B */ 714 #define MUX_PB09B_ADC_AIN3 _L_(1) 715 #define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3) 716 #define PORT_PB09B_ADC_AIN3 (_UL_(1) << 9) 717 #define PIN_PA04B_ADC_AIN4 _L_(4) /**< \brief ADC signal: AIN4 on PA04 mux B */ 718 #define MUX_PA04B_ADC_AIN4 _L_(1) 719 #define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) 720 #define PORT_PA04B_ADC_AIN4 (_UL_(1) << 4) 721 #define PIN_PA05B_ADC_AIN5 _L_(5) /**< \brief ADC signal: AIN5 on PA05 mux B */ 722 #define MUX_PA05B_ADC_AIN5 _L_(1) 723 #define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) 724 #define PORT_PA05B_ADC_AIN5 (_UL_(1) << 5) 725 #define PIN_PA06B_ADC_AIN6 _L_(6) /**< \brief ADC signal: AIN6 on PA06 mux B */ 726 #define MUX_PA06B_ADC_AIN6 _L_(1) 727 #define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) 728 #define PORT_PA06B_ADC_AIN6 (_UL_(1) << 6) 729 #define PIN_PA07B_ADC_AIN7 _L_(7) /**< \brief ADC signal: AIN7 on PA07 mux B */ 730 #define MUX_PA07B_ADC_AIN7 _L_(1) 731 #define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) 732 #define PORT_PA07B_ADC_AIN7 (_UL_(1) << 7) 733 #define PIN_PB02B_ADC_AIN10 _L_(34) /**< \brief ADC signal: AIN10 on PB02 mux B */ 734 #define MUX_PB02B_ADC_AIN10 _L_(1) 735 #define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10) 736 #define PORT_PB02B_ADC_AIN10 (_UL_(1) << 2) 737 #define PIN_PB03B_ADC_AIN11 _L_(35) /**< \brief ADC signal: AIN11 on PB03 mux B */ 738 #define MUX_PB03B_ADC_AIN11 _L_(1) 739 #define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11) 740 #define PORT_PB03B_ADC_AIN11 (_UL_(1) << 3) 741 #define PIN_PA08B_ADC_AIN16 _L_(8) /**< \brief ADC signal: AIN16 on PA08 mux B */ 742 #define MUX_PA08B_ADC_AIN16 _L_(1) 743 #define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) 744 #define PORT_PA08B_ADC_AIN16 (_UL_(1) << 8) 745 #define PIN_PA09B_ADC_AIN17 _L_(9) /**< \brief ADC signal: AIN17 on PA09 mux B */ 746 #define MUX_PA09B_ADC_AIN17 _L_(1) 747 #define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) 748 #define PORT_PA09B_ADC_AIN17 (_UL_(1) << 9) 749 #define PIN_PA10B_ADC_AIN18 _L_(10) /**< \brief ADC signal: AIN18 on PA10 mux B */ 750 #define MUX_PA10B_ADC_AIN18 _L_(1) 751 #define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) 752 #define PORT_PA10B_ADC_AIN18 (_UL_(1) << 10) 753 #define PIN_PA11B_ADC_AIN19 _L_(11) /**< \brief ADC signal: AIN19 on PA11 mux B */ 754 #define MUX_PA11B_ADC_AIN19 _L_(1) 755 #define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) 756 #define PORT_PA11B_ADC_AIN19 (_UL_(1) << 11) 757 #define PIN_PA04B_ADC_VREFP _L_(4) /**< \brief ADC signal: VREFP on PA04 mux B */ 758 #define MUX_PA04B_ADC_VREFP _L_(1) 759 #define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP) 760 #define PORT_PA04B_ADC_VREFP (_UL_(1) << 4) 761 /* ========== PORT definition for AC peripheral ========== */ 762 #define PIN_PA04B_AC_AIN0 _L_(4) /**< \brief AC signal: AIN0 on PA04 mux B */ 763 #define MUX_PA04B_AC_AIN0 _L_(1) 764 #define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) 765 #define PORT_PA04B_AC_AIN0 (_UL_(1) << 4) 766 #define PIN_PA05B_AC_AIN1 _L_(5) /**< \brief AC signal: AIN1 on PA05 mux B */ 767 #define MUX_PA05B_AC_AIN1 _L_(1) 768 #define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) 769 #define PORT_PA05B_AC_AIN1 (_UL_(1) << 5) 770 #define PIN_PA06B_AC_AIN2 _L_(6) /**< \brief AC signal: AIN2 on PA06 mux B */ 771 #define MUX_PA06B_AC_AIN2 _L_(1) 772 #define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) 773 #define PORT_PA06B_AC_AIN2 (_UL_(1) << 6) 774 #define PIN_PA07B_AC_AIN3 _L_(7) /**< \brief AC signal: AIN3 on PA07 mux B */ 775 #define MUX_PA07B_AC_AIN3 _L_(1) 776 #define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) 777 #define PORT_PA07B_AC_AIN3 (_UL_(1) << 7) 778 #define PIN_PA12H_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux H */ 779 #define MUX_PA12H_AC_CMP0 _L_(7) 780 #define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0) 781 #define PORT_PA12H_AC_CMP0 (_UL_(1) << 12) 782 #define PIN_PA18H_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux H */ 783 #define MUX_PA18H_AC_CMP0 _L_(7) 784 #define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) 785 #define PORT_PA18H_AC_CMP0 (_UL_(1) << 18) 786 #define PIN_PA13H_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux H */ 787 #define MUX_PA13H_AC_CMP1 _L_(7) 788 #define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1) 789 #define PORT_PA13H_AC_CMP1 (_UL_(1) << 13) 790 #define PIN_PA19H_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux H */ 791 #define MUX_PA19H_AC_CMP1 _L_(7) 792 #define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) 793 #define PORT_PA19H_AC_CMP1 (_UL_(1) << 19) 794 /* ========== PORT definition for DAC peripheral ========== */ 795 #define PIN_PA02B_DAC_VOUT _L_(2) /**< \brief DAC signal: VOUT on PA02 mux B */ 796 #define MUX_PA02B_DAC_VOUT _L_(1) 797 #define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT) 798 #define PORT_PA02B_DAC_VOUT (_UL_(1) << 2) 799 #define PIN_PA03B_DAC_VREFP _L_(3) /**< \brief DAC signal: VREFP on PA03 mux B */ 800 #define MUX_PA03B_DAC_VREFP _L_(1) 801 #define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP) 802 #define PORT_PA03B_DAC_VREFP (_UL_(1) << 3) 803 804 #endif /* _SAMD20G16_PIO_ */ 805
