1 /** 2 * \file 3 * 4 * \brief Instance description for SERCOM0 5 * 6 * Copyright (c) 2017 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAMD20_SERCOM0_INSTANCE_ 31 #define _SAMD20_SERCOM0_INSTANCE_ 32 33 /* ========== Register definition for SERCOM0 peripheral ========== */ 34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 35 #define REG_SERCOM0_I2CM_CTRLA (0x42000800) /**< \brief (SERCOM0) I2CM Control A */ 36 #define REG_SERCOM0_I2CM_CTRLB (0x42000804) /**< \brief (SERCOM0) I2CM Control B */ 37 #define REG_SERCOM0_I2CM_DBGCTRL (0x42000808) /**< \brief (SERCOM0) I2CM Debug Control */ 38 #define REG_SERCOM0_I2CM_BAUD (0x4200080A) /**< \brief (SERCOM0) I2CM Baud Rate */ 39 #define REG_SERCOM0_I2CM_INTENCLR (0x4200080C) /**< \brief (SERCOM0) I2CM Interrupt Enable Clear */ 40 #define REG_SERCOM0_I2CM_INTENSET (0x4200080D) /**< \brief (SERCOM0) I2CM Interrupt Enable Set */ 41 #define REG_SERCOM0_I2CM_INTFLAG (0x4200080E) /**< \brief (SERCOM0) I2CM Interrupt Flag Status and Clear */ 42 #define REG_SERCOM0_I2CM_STATUS (0x42000810) /**< \brief (SERCOM0) I2CM Status */ 43 #define REG_SERCOM0_I2CM_ADDR (0x42000814) /**< \brief (SERCOM0) I2CM Address */ 44 #define REG_SERCOM0_I2CM_DATA (0x42000818) /**< \brief (SERCOM0) I2CM Data */ 45 #define REG_SERCOM0_I2CS_CTRLA (0x42000800) /**< \brief (SERCOM0) I2CS Control A */ 46 #define REG_SERCOM0_I2CS_CTRLB (0x42000804) /**< \brief (SERCOM0) I2CS Control B */ 47 #define REG_SERCOM0_I2CS_INTENCLR (0x4200080C) /**< \brief (SERCOM0) I2CS Interrupt Enable Clear */ 48 #define REG_SERCOM0_I2CS_INTENSET (0x4200080D) /**< \brief (SERCOM0) I2CS Interrupt Enable Set */ 49 #define REG_SERCOM0_I2CS_INTFLAG (0x4200080E) /**< \brief (SERCOM0) I2CS Interrupt Flag Status and Clear */ 50 #define REG_SERCOM0_I2CS_STATUS (0x42000810) /**< \brief (SERCOM0) I2CS Status */ 51 #define REG_SERCOM0_I2CS_ADDR (0x42000814) /**< \brief (SERCOM0) I2CS Address */ 52 #define REG_SERCOM0_I2CS_DATA (0x42000818) /**< \brief (SERCOM0) I2CS Data */ 53 #define REG_SERCOM0_SPI_CTRLA (0x42000800) /**< \brief (SERCOM0) SPI Control A */ 54 #define REG_SERCOM0_SPI_CTRLB (0x42000804) /**< \brief (SERCOM0) SPI Control B */ 55 #define REG_SERCOM0_SPI_DBGCTRL (0x42000808) /**< \brief (SERCOM0) SPI Debug Control */ 56 #define REG_SERCOM0_SPI_BAUD (0x4200080A) /**< \brief (SERCOM0) SPI Baud Rate */ 57 #define REG_SERCOM0_SPI_INTENCLR (0x4200080C) /**< \brief (SERCOM0) SPI Interrupt Enable Clear */ 58 #define REG_SERCOM0_SPI_INTENSET (0x4200080D) /**< \brief (SERCOM0) SPI Interrupt Enable Set */ 59 #define REG_SERCOM0_SPI_INTFLAG (0x4200080E) /**< \brief (SERCOM0) SPI Interrupt Flag Status and Clear */ 60 #define REG_SERCOM0_SPI_STATUS (0x42000810) /**< \brief (SERCOM0) SPI Status */ 61 #define REG_SERCOM0_SPI_ADDR (0x42000814) /**< \brief (SERCOM0) SPI Address */ 62 #define REG_SERCOM0_SPI_DATA (0x42000818) /**< \brief (SERCOM0) SPI Data */ 63 #define REG_SERCOM0_USART_CTRLA (0x42000800) /**< \brief (SERCOM0) USART Control A */ 64 #define REG_SERCOM0_USART_CTRLB (0x42000804) /**< \brief (SERCOM0) USART Control B */ 65 #define REG_SERCOM0_USART_DBGCTRL (0x42000808) /**< \brief (SERCOM0) USART Debug Control */ 66 #define REG_SERCOM0_USART_BAUD (0x4200080A) /**< \brief (SERCOM0) USART Baud */ 67 #define REG_SERCOM0_USART_INTENCLR (0x4200080C) /**< \brief (SERCOM0) USART Interrupt Enable Clear */ 68 #define REG_SERCOM0_USART_INTENSET (0x4200080D) /**< \brief (SERCOM0) USART Interrupt Enable Set */ 69 #define REG_SERCOM0_USART_INTFLAG (0x4200080E) /**< \brief (SERCOM0) USART Interrupt Flag Status and Clear */ 70 #define REG_SERCOM0_USART_STATUS (0x42000810) /**< \brief (SERCOM0) USART Status */ 71 #define REG_SERCOM0_USART_DATA (0x42000818) /**< \brief (SERCOM0) USART Data */ 72 #else 73 #define REG_SERCOM0_I2CM_CTRLA (*(RwReg *)0x42000800UL) /**< \brief (SERCOM0) I2CM Control A */ 74 #define REG_SERCOM0_I2CM_CTRLB (*(RwReg *)0x42000804UL) /**< \brief (SERCOM0) I2CM Control B */ 75 #define REG_SERCOM0_I2CM_DBGCTRL (*(RwReg8 *)0x42000808UL) /**< \brief (SERCOM0) I2CM Debug Control */ 76 #define REG_SERCOM0_I2CM_BAUD (*(RwReg16*)0x4200080AUL) /**< \brief (SERCOM0) I2CM Baud Rate */ 77 #define REG_SERCOM0_I2CM_INTENCLR (*(RwReg8 *)0x4200080CUL) /**< \brief (SERCOM0) I2CM Interrupt Enable Clear */ 78 #define REG_SERCOM0_I2CM_INTENSET (*(RwReg8 *)0x4200080DUL) /**< \brief (SERCOM0) I2CM Interrupt Enable Set */ 79 #define REG_SERCOM0_I2CM_INTFLAG (*(RwReg8 *)0x4200080EUL) /**< \brief (SERCOM0) I2CM Interrupt Flag Status and Clear */ 80 #define REG_SERCOM0_I2CM_STATUS (*(RwReg16*)0x42000810UL) /**< \brief (SERCOM0) I2CM Status */ 81 #define REG_SERCOM0_I2CM_ADDR (*(RwReg8 *)0x42000814UL) /**< \brief (SERCOM0) I2CM Address */ 82 #define REG_SERCOM0_I2CM_DATA (*(RwReg8 *)0x42000818UL) /**< \brief (SERCOM0) I2CM Data */ 83 #define REG_SERCOM0_I2CS_CTRLA (*(RwReg *)0x42000800UL) /**< \brief (SERCOM0) I2CS Control A */ 84 #define REG_SERCOM0_I2CS_CTRLB (*(RwReg *)0x42000804UL) /**< \brief (SERCOM0) I2CS Control B */ 85 #define REG_SERCOM0_I2CS_INTENCLR (*(RwReg8 *)0x4200080CUL) /**< \brief (SERCOM0) I2CS Interrupt Enable Clear */ 86 #define REG_SERCOM0_I2CS_INTENSET (*(RwReg8 *)0x4200080DUL) /**< \brief (SERCOM0) I2CS Interrupt Enable Set */ 87 #define REG_SERCOM0_I2CS_INTFLAG (*(RwReg8 *)0x4200080EUL) /**< \brief (SERCOM0) I2CS Interrupt Flag Status and Clear */ 88 #define REG_SERCOM0_I2CS_STATUS (*(RwReg16*)0x42000810UL) /**< \brief (SERCOM0) I2CS Status */ 89 #define REG_SERCOM0_I2CS_ADDR (*(RwReg *)0x42000814UL) /**< \brief (SERCOM0) I2CS Address */ 90 #define REG_SERCOM0_I2CS_DATA (*(RwReg8 *)0x42000818UL) /**< \brief (SERCOM0) I2CS Data */ 91 #define REG_SERCOM0_SPI_CTRLA (*(RwReg *)0x42000800UL) /**< \brief (SERCOM0) SPI Control A */ 92 #define REG_SERCOM0_SPI_CTRLB (*(RwReg *)0x42000804UL) /**< \brief (SERCOM0) SPI Control B */ 93 #define REG_SERCOM0_SPI_DBGCTRL (*(RwReg8 *)0x42000808UL) /**< \brief (SERCOM0) SPI Debug Control */ 94 #define REG_SERCOM0_SPI_BAUD (*(RwReg8 *)0x4200080AUL) /**< \brief (SERCOM0) SPI Baud Rate */ 95 #define REG_SERCOM0_SPI_INTENCLR (*(RwReg8 *)0x4200080CUL) /**< \brief (SERCOM0) SPI Interrupt Enable Clear */ 96 #define REG_SERCOM0_SPI_INTENSET (*(RwReg8 *)0x4200080DUL) /**< \brief (SERCOM0) SPI Interrupt Enable Set */ 97 #define REG_SERCOM0_SPI_INTFLAG (*(RwReg8 *)0x4200080EUL) /**< \brief (SERCOM0) SPI Interrupt Flag Status and Clear */ 98 #define REG_SERCOM0_SPI_STATUS (*(RwReg16*)0x42000810UL) /**< \brief (SERCOM0) SPI Status */ 99 #define REG_SERCOM0_SPI_ADDR (*(RwReg *)0x42000814UL) /**< \brief (SERCOM0) SPI Address */ 100 #define REG_SERCOM0_SPI_DATA (*(RwReg16*)0x42000818UL) /**< \brief (SERCOM0) SPI Data */ 101 #define REG_SERCOM0_USART_CTRLA (*(RwReg *)0x42000800UL) /**< \brief (SERCOM0) USART Control A */ 102 #define REG_SERCOM0_USART_CTRLB (*(RwReg *)0x42000804UL) /**< \brief (SERCOM0) USART Control B */ 103 #define REG_SERCOM0_USART_DBGCTRL (*(RwReg8 *)0x42000808UL) /**< \brief (SERCOM0) USART Debug Control */ 104 #define REG_SERCOM0_USART_BAUD (*(RwReg16*)0x4200080AUL) /**< \brief (SERCOM0) USART Baud */ 105 #define REG_SERCOM0_USART_INTENCLR (*(RwReg8 *)0x4200080CUL) /**< \brief (SERCOM0) USART Interrupt Enable Clear */ 106 #define REG_SERCOM0_USART_INTENSET (*(RwReg8 *)0x4200080DUL) /**< \brief (SERCOM0) USART Interrupt Enable Set */ 107 #define REG_SERCOM0_USART_INTFLAG (*(RwReg8 *)0x4200080EUL) /**< \brief (SERCOM0) USART Interrupt Flag Status and Clear */ 108 #define REG_SERCOM0_USART_STATUS (*(RwReg16*)0x42000810UL) /**< \brief (SERCOM0) USART Status */ 109 #define REG_SERCOM0_USART_DATA (*(RwReg16*)0x42000818UL) /**< \brief (SERCOM0) USART Data */ 110 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 111 112 /* ========== Instance parameters for SERCOM0 peripheral ========== */ 113 #define SERCOM0_GCLK_ID_CORE 13 114 #define SERCOM0_GCLK_ID_SLOW 12 115 #define SERCOM0_INT_MSB 3 116 #define SERCOM0_PMSB 3 117 118 #endif /* _SAMD20_SERCOM0_INSTANCE_ */ 119
