1 /** 2 * \file 3 * 4 * \brief Instance description for UART3 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \license_stop 27 * 28 */ 29 30 /* file generated from device description version 2019-01-18T21:21:15Z */ 31 #ifndef _SAMV71_UART3_INSTANCE_H_ 32 #define _SAMV71_UART3_INSTANCE_H_ 33 34 /* ========== Register definition for UART3 peripheral ========== */ 35 #if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 36 37 #define REG_UART3_CR (0x400E1C00) /**< (UART3) Control Register */ 38 #define REG_UART3_MR (0x400E1C04) /**< (UART3) Mode Register */ 39 #define REG_UART3_IER (0x400E1C08) /**< (UART3) Interrupt Enable Register */ 40 #define REG_UART3_IDR (0x400E1C0C) /**< (UART3) Interrupt Disable Register */ 41 #define REG_UART3_IMR (0x400E1C10) /**< (UART3) Interrupt Mask Register */ 42 #define REG_UART3_SR (0x400E1C14) /**< (UART3) Status Register */ 43 #define REG_UART3_RHR (0x400E1C18) /**< (UART3) Receive Holding Register */ 44 #define REG_UART3_THR (0x400E1C1C) /**< (UART3) Transmit Holding Register */ 45 #define REG_UART3_BRGR (0x400E1C20) /**< (UART3) Baud Rate Generator Register */ 46 #define REG_UART3_CMPR (0x400E1C24) /**< (UART3) Comparison Register */ 47 #define REG_UART3_WPMR (0x400E1CE4) /**< (UART3) Write Protection Mode Register */ 48 49 #else 50 51 #define REG_UART3_CR (*(__O uint32_t*)0x400E1C00U) /**< (UART3) Control Register */ 52 #define REG_UART3_MR (*(__IO uint32_t*)0x400E1C04U) /**< (UART3) Mode Register */ 53 #define REG_UART3_IER (*(__O uint32_t*)0x400E1C08U) /**< (UART3) Interrupt Enable Register */ 54 #define REG_UART3_IDR (*(__O uint32_t*)0x400E1C0CU) /**< (UART3) Interrupt Disable Register */ 55 #define REG_UART3_IMR (*(__I uint32_t*)0x400E1C10U) /**< (UART3) Interrupt Mask Register */ 56 #define REG_UART3_SR (*(__I uint32_t*)0x400E1C14U) /**< (UART3) Status Register */ 57 #define REG_UART3_RHR (*(__I uint32_t*)0x400E1C18U) /**< (UART3) Receive Holding Register */ 58 #define REG_UART3_THR (*(__O uint32_t*)0x400E1C1CU) /**< (UART3) Transmit Holding Register */ 59 #define REG_UART3_BRGR (*(__IO uint32_t*)0x400E1C20U) /**< (UART3) Baud Rate Generator Register */ 60 #define REG_UART3_CMPR (*(__IO uint32_t*)0x400E1C24U) /**< (UART3) Comparison Register */ 61 #define REG_UART3_WPMR (*(__IO uint32_t*)0x400E1CE4U) /**< (UART3) Write Protection Mode Register */ 62 63 #endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 64 65 /* ========== Instance Parameter definitions for UART3 peripheral ========== */ 66 #define UART3_DMAC_ID_RX 27 67 #define UART3_DMAC_ID_TX 26 68 #define UART3_INSTANCE_ID 45 69 #define UART3_CLOCK_ID 45 70 #define UART3_BRSRCCK_PERIPH_CLK 0 /* MCK */ 71 #define UART3_BRSRCCK_PMC_PCK 0 /* PCK4 */ 72 73 #endif /* _SAMV71_UART3_INSTANCE_ */ 74
