1 /** 2 * \file 3 * 4 * \brief Instance description for TWIHS0 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \license_stop 27 * 28 */ 29 30 /* file generated from device description version 2019-01-18T21:21:15Z */ 31 #ifndef _SAMV71_TWIHS0_INSTANCE_H_ 32 #define _SAMV71_TWIHS0_INSTANCE_H_ 33 34 /* ========== Register definition for TWIHS0 peripheral ========== */ 35 #if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 36 37 #define REG_TWIHS0_CR (0x40018000) /**< (TWIHS0) Control Register */ 38 #define REG_TWIHS0_MMR (0x40018004) /**< (TWIHS0) Master Mode Register */ 39 #define REG_TWIHS0_SMR (0x40018008) /**< (TWIHS0) Slave Mode Register */ 40 #define REG_TWIHS0_IADR (0x4001800C) /**< (TWIHS0) Internal Address Register */ 41 #define REG_TWIHS0_CWGR (0x40018010) /**< (TWIHS0) Clock Waveform Generator Register */ 42 #define REG_TWIHS0_SR (0x40018020) /**< (TWIHS0) Status Register */ 43 #define REG_TWIHS0_IER (0x40018024) /**< (TWIHS0) Interrupt Enable Register */ 44 #define REG_TWIHS0_IDR (0x40018028) /**< (TWIHS0) Interrupt Disable Register */ 45 #define REG_TWIHS0_IMR (0x4001802C) /**< (TWIHS0) Interrupt Mask Register */ 46 #define REG_TWIHS0_RHR (0x40018030) /**< (TWIHS0) Receive Holding Register */ 47 #define REG_TWIHS0_THR (0x40018034) /**< (TWIHS0) Transmit Holding Register */ 48 #define REG_TWIHS0_SMBTR (0x40018038) /**< (TWIHS0) SMBus Timing Register */ 49 #define REG_TWIHS0_FILTR (0x40018044) /**< (TWIHS0) Filter Register */ 50 #define REG_TWIHS0_SWMR (0x4001804C) /**< (TWIHS0) SleepWalking Matching Register */ 51 #define REG_TWIHS0_WPMR (0x400180E4) /**< (TWIHS0) Write Protection Mode Register */ 52 #define REG_TWIHS0_WPSR (0x400180E8) /**< (TWIHS0) Write Protection Status Register */ 53 54 #else 55 56 #define REG_TWIHS0_CR (*(__O uint32_t*)0x40018000U) /**< (TWIHS0) Control Register */ 57 #define REG_TWIHS0_MMR (*(__IO uint32_t*)0x40018004U) /**< (TWIHS0) Master Mode Register */ 58 #define REG_TWIHS0_SMR (*(__IO uint32_t*)0x40018008U) /**< (TWIHS0) Slave Mode Register */ 59 #define REG_TWIHS0_IADR (*(__IO uint32_t*)0x4001800CU) /**< (TWIHS0) Internal Address Register */ 60 #define REG_TWIHS0_CWGR (*(__IO uint32_t*)0x40018010U) /**< (TWIHS0) Clock Waveform Generator Register */ 61 #define REG_TWIHS0_SR (*(__I uint32_t*)0x40018020U) /**< (TWIHS0) Status Register */ 62 #define REG_TWIHS0_IER (*(__O uint32_t*)0x40018024U) /**< (TWIHS0) Interrupt Enable Register */ 63 #define REG_TWIHS0_IDR (*(__O uint32_t*)0x40018028U) /**< (TWIHS0) Interrupt Disable Register */ 64 #define REG_TWIHS0_IMR (*(__I uint32_t*)0x4001802CU) /**< (TWIHS0) Interrupt Mask Register */ 65 #define REG_TWIHS0_RHR (*(__I uint32_t*)0x40018030U) /**< (TWIHS0) Receive Holding Register */ 66 #define REG_TWIHS0_THR (*(__O uint32_t*)0x40018034U) /**< (TWIHS0) Transmit Holding Register */ 67 #define REG_TWIHS0_SMBTR (*(__IO uint32_t*)0x40018038U) /**< (TWIHS0) SMBus Timing Register */ 68 #define REG_TWIHS0_FILTR (*(__IO uint32_t*)0x40018044U) /**< (TWIHS0) Filter Register */ 69 #define REG_TWIHS0_SWMR (*(__IO uint32_t*)0x4001804CU) /**< (TWIHS0) SleepWalking Matching Register */ 70 #define REG_TWIHS0_WPMR (*(__IO uint32_t*)0x400180E4U) /**< (TWIHS0) Write Protection Mode Register */ 71 #define REG_TWIHS0_WPSR (*(__I uint32_t*)0x400180E8U) /**< (TWIHS0) Write Protection Status Register */ 72 73 #endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 74 75 /* ========== Instance Parameter definitions for TWIHS0 peripheral ========== */ 76 #define TWIHS0_DMAC_ID_RX 15 77 #define TWIHS0_DMAC_ID_TX 14 78 #define TWIHS0_INSTANCE_ID 19 79 #define TWIHS0_CLOCK_ID 19 80 81 #endif /* _SAMV71_TWIHS0_INSTANCE_ */ 82
