1 /** 2 * \file 3 * 4 * \brief Instance description for SSC 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \license_stop 27 * 28 */ 29 30 /* file generated from device description version 2019-01-18T21:21:15Z */ 31 #ifndef _SAMV71_SSC_INSTANCE_H_ 32 #define _SAMV71_SSC_INSTANCE_H_ 33 34 /* ========== Register definition for SSC peripheral ========== */ 35 #if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 36 37 #define REG_SSC_CR (0x40004000) /**< (SSC) Control Register */ 38 #define REG_SSC_CMR (0x40004004) /**< (SSC) Clock Mode Register */ 39 #define REG_SSC_RCMR (0x40004010) /**< (SSC) Receive Clock Mode Register */ 40 #define REG_SSC_RFMR (0x40004014) /**< (SSC) Receive Frame Mode Register */ 41 #define REG_SSC_TCMR (0x40004018) /**< (SSC) Transmit Clock Mode Register */ 42 #define REG_SSC_TFMR (0x4000401C) /**< (SSC) Transmit Frame Mode Register */ 43 #define REG_SSC_RHR (0x40004020) /**< (SSC) Receive Holding Register */ 44 #define REG_SSC_THR (0x40004024) /**< (SSC) Transmit Holding Register */ 45 #define REG_SSC_RSHR (0x40004030) /**< (SSC) Receive Sync. Holding Register */ 46 #define REG_SSC_TSHR (0x40004034) /**< (SSC) Transmit Sync. Holding Register */ 47 #define REG_SSC_RC0R (0x40004038) /**< (SSC) Receive Compare 0 Register */ 48 #define REG_SSC_RC1R (0x4000403C) /**< (SSC) Receive Compare 1 Register */ 49 #define REG_SSC_SR (0x40004040) /**< (SSC) Status Register */ 50 #define REG_SSC_IER (0x40004044) /**< (SSC) Interrupt Enable Register */ 51 #define REG_SSC_IDR (0x40004048) /**< (SSC) Interrupt Disable Register */ 52 #define REG_SSC_IMR (0x4000404C) /**< (SSC) Interrupt Mask Register */ 53 #define REG_SSC_WPMR (0x400040E4) /**< (SSC) Write Protection Mode Register */ 54 #define REG_SSC_WPSR (0x400040E8) /**< (SSC) Write Protection Status Register */ 55 56 #else 57 58 #define REG_SSC_CR (*(__O uint32_t*)0x40004000U) /**< (SSC) Control Register */ 59 #define REG_SSC_CMR (*(__IO uint32_t*)0x40004004U) /**< (SSC) Clock Mode Register */ 60 #define REG_SSC_RCMR (*(__IO uint32_t*)0x40004010U) /**< (SSC) Receive Clock Mode Register */ 61 #define REG_SSC_RFMR (*(__IO uint32_t*)0x40004014U) /**< (SSC) Receive Frame Mode Register */ 62 #define REG_SSC_TCMR (*(__IO uint32_t*)0x40004018U) /**< (SSC) Transmit Clock Mode Register */ 63 #define REG_SSC_TFMR (*(__IO uint32_t*)0x4000401CU) /**< (SSC) Transmit Frame Mode Register */ 64 #define REG_SSC_RHR (*(__I uint32_t*)0x40004020U) /**< (SSC) Receive Holding Register */ 65 #define REG_SSC_THR (*(__O uint32_t*)0x40004024U) /**< (SSC) Transmit Holding Register */ 66 #define REG_SSC_RSHR (*(__I uint32_t*)0x40004030U) /**< (SSC) Receive Sync. Holding Register */ 67 #define REG_SSC_TSHR (*(__IO uint32_t*)0x40004034U) /**< (SSC) Transmit Sync. Holding Register */ 68 #define REG_SSC_RC0R (*(__IO uint32_t*)0x40004038U) /**< (SSC) Receive Compare 0 Register */ 69 #define REG_SSC_RC1R (*(__IO uint32_t*)0x4000403CU) /**< (SSC) Receive Compare 1 Register */ 70 #define REG_SSC_SR (*(__I uint32_t*)0x40004040U) /**< (SSC) Status Register */ 71 #define REG_SSC_IER (*(__O uint32_t*)0x40004044U) /**< (SSC) Interrupt Enable Register */ 72 #define REG_SSC_IDR (*(__O uint32_t*)0x40004048U) /**< (SSC) Interrupt Disable Register */ 73 #define REG_SSC_IMR (*(__I uint32_t*)0x4000404CU) /**< (SSC) Interrupt Mask Register */ 74 #define REG_SSC_WPMR (*(__IO uint32_t*)0x400040E4U) /**< (SSC) Write Protection Mode Register */ 75 #define REG_SSC_WPSR (*(__I uint32_t*)0x400040E8U) /**< (SSC) Write Protection Status Register */ 76 77 #endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 78 79 /* ========== Instance Parameter definitions for SSC peripheral ========== */ 80 #define SSC_DMAC_ID_RX 33 81 #define SSC_DMAC_ID_TX 32 82 #define SSC_INSTANCE_ID 22 83 #define SSC_CLOCK_ID 22 84 85 #endif /* _SAMV71_SSC_INSTANCE_ */ 86
