1 /** 2 * \file 3 * 4 * \brief Instance description for SPI0 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \license_stop 27 * 28 */ 29 30 /* file generated from device description version 2019-01-18T21:21:15Z */ 31 #ifndef _SAMV71_SPI0_INSTANCE_H_ 32 #define _SAMV71_SPI0_INSTANCE_H_ 33 34 /* ========== Register definition for SPI0 peripheral ========== */ 35 #if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 36 37 #define REG_SPI0_CR (0x40008000) /**< (SPI0) Control Register */ 38 #define REG_SPI0_MR (0x40008004) /**< (SPI0) Mode Register */ 39 #define REG_SPI0_RDR (0x40008008) /**< (SPI0) Receive Data Register */ 40 #define REG_SPI0_TDR (0x4000800C) /**< (SPI0) Transmit Data Register */ 41 #define REG_SPI0_SR (0x40008010) /**< (SPI0) Status Register */ 42 #define REG_SPI0_IER (0x40008014) /**< (SPI0) Interrupt Enable Register */ 43 #define REG_SPI0_IDR (0x40008018) /**< (SPI0) Interrupt Disable Register */ 44 #define REG_SPI0_IMR (0x4000801C) /**< (SPI0) Interrupt Mask Register */ 45 #define REG_SPI0_CSR (0x40008030) /**< (SPI0) Chip Select Register */ 46 #define REG_SPI0_CSR0 (0x40008030) /**< (SPI0) Chip Select Register 0 */ 47 #define REG_SPI0_CSR1 (0x40008034) /**< (SPI0) Chip Select Register 1 */ 48 #define REG_SPI0_CSR2 (0x40008038) /**< (SPI0) Chip Select Register 2 */ 49 #define REG_SPI0_CSR3 (0x4000803C) /**< (SPI0) Chip Select Register 3 */ 50 #define REG_SPI0_WPMR (0x400080E4) /**< (SPI0) Write Protection Mode Register */ 51 #define REG_SPI0_WPSR (0x400080E8) /**< (SPI0) Write Protection Status Register */ 52 53 #else 54 55 #define REG_SPI0_CR (*(__O uint32_t*)0x40008000U) /**< (SPI0) Control Register */ 56 #define REG_SPI0_MR (*(__IO uint32_t*)0x40008004U) /**< (SPI0) Mode Register */ 57 #define REG_SPI0_RDR (*(__I uint32_t*)0x40008008U) /**< (SPI0) Receive Data Register */ 58 #define REG_SPI0_TDR (*(__O uint32_t*)0x4000800CU) /**< (SPI0) Transmit Data Register */ 59 #define REG_SPI0_SR (*(__I uint32_t*)0x40008010U) /**< (SPI0) Status Register */ 60 #define REG_SPI0_IER (*(__O uint32_t*)0x40008014U) /**< (SPI0) Interrupt Enable Register */ 61 #define REG_SPI0_IDR (*(__O uint32_t*)0x40008018U) /**< (SPI0) Interrupt Disable Register */ 62 #define REG_SPI0_IMR (*(__I uint32_t*)0x4000801CU) /**< (SPI0) Interrupt Mask Register */ 63 #define REG_SPI0_CSR (*(__IO uint32_t*)0x40008030U) /**< (SPI0) Chip Select Register */ 64 #define REG_SPI0_CSR0 (*(__IO uint32_t*)0x40008030U) /**< (SPI0) Chip Select Register 0 */ 65 #define REG_SPI0_CSR1 (*(__IO uint32_t*)0x40008034U) /**< (SPI0) Chip Select Register 1 */ 66 #define REG_SPI0_CSR2 (*(__IO uint32_t*)0x40008038U) /**< (SPI0) Chip Select Register 2 */ 67 #define REG_SPI0_CSR3 (*(__IO uint32_t*)0x4000803CU) /**< (SPI0) Chip Select Register 3 */ 68 #define REG_SPI0_WPMR (*(__IO uint32_t*)0x400080E4U) /**< (SPI0) Write Protection Mode Register */ 69 #define REG_SPI0_WPSR (*(__I uint32_t*)0x400080E8U) /**< (SPI0) Write Protection Status Register */ 70 71 #endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 72 73 /* ========== Instance Parameter definitions for SPI0 peripheral ========== */ 74 #define SPI0_DMAC_ID_RX 2 75 #define SPI0_DMAC_ID_TX 1 76 #define SPI0_INSTANCE_ID 21 77 #define SPI0_CLOCK_ID 21 78 79 #endif /* _SAMV71_SPI0_INSTANCE_ */ 80
