1 /** 2 * \file 3 * 4 * \brief Instance description for SMC 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \license_stop 27 * 28 */ 29 30 /* file generated from device description version 2019-01-18T21:21:15Z */ 31 #ifndef _SAMV71_SMC_INSTANCE_H_ 32 #define _SAMV71_SMC_INSTANCE_H_ 33 34 /* ========== Register definition for SMC peripheral ========== */ 35 #if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 36 37 #define REG_SMC_SETUP0 (0x40080000) /**< (SMC) SMC Setup Register 0 */ 38 #define REG_SMC_PULSE0 (0x40080004) /**< (SMC) SMC Pulse Register 0 */ 39 #define REG_SMC_CYCLE0 (0x40080008) /**< (SMC) SMC Cycle Register 0 */ 40 #define REG_SMC_MODE0 (0x4008000C) /**< (SMC) SMC Mode Register 0 */ 41 #define REG_SMC_SETUP1 (0x40080010) /**< (SMC) SMC Setup Register 1 */ 42 #define REG_SMC_PULSE1 (0x40080014) /**< (SMC) SMC Pulse Register 1 */ 43 #define REG_SMC_CYCLE1 (0x40080018) /**< (SMC) SMC Cycle Register 1 */ 44 #define REG_SMC_MODE1 (0x4008001C) /**< (SMC) SMC Mode Register 1 */ 45 #define REG_SMC_SETUP2 (0x40080020) /**< (SMC) SMC Setup Register 2 */ 46 #define REG_SMC_PULSE2 (0x40080024) /**< (SMC) SMC Pulse Register 2 */ 47 #define REG_SMC_CYCLE2 (0x40080028) /**< (SMC) SMC Cycle Register 2 */ 48 #define REG_SMC_MODE2 (0x4008002C) /**< (SMC) SMC Mode Register 2 */ 49 #define REG_SMC_SETUP3 (0x40080030) /**< (SMC) SMC Setup Register 3 */ 50 #define REG_SMC_PULSE3 (0x40080034) /**< (SMC) SMC Pulse Register 3 */ 51 #define REG_SMC_CYCLE3 (0x40080038) /**< (SMC) SMC Cycle Register 3 */ 52 #define REG_SMC_MODE3 (0x4008003C) /**< (SMC) SMC Mode Register 3 */ 53 #define REG_SMC_OCMS (0x40080080) /**< (SMC) SMC Off-Chip Memory Scrambling Register */ 54 #define REG_SMC_KEY1 (0x40080084) /**< (SMC) SMC Off-Chip Memory Scrambling KEY1 Register */ 55 #define REG_SMC_KEY2 (0x40080088) /**< (SMC) SMC Off-Chip Memory Scrambling KEY2 Register */ 56 #define REG_SMC_WPMR (0x400800E4) /**< (SMC) SMC Write Protection Mode Register */ 57 #define REG_SMC_WPSR (0x400800E8) /**< (SMC) SMC Write Protection Status Register */ 58 59 #else 60 61 #define REG_SMC_SETUP0 (*(__IO uint32_t*)0x40080000U) /**< (SMC) SMC Setup Register 0 */ 62 #define REG_SMC_PULSE0 (*(__IO uint32_t*)0x40080004U) /**< (SMC) SMC Pulse Register 0 */ 63 #define REG_SMC_CYCLE0 (*(__IO uint32_t*)0x40080008U) /**< (SMC) SMC Cycle Register 0 */ 64 #define REG_SMC_MODE0 (*(__IO uint32_t*)0x4008000CU) /**< (SMC) SMC Mode Register 0 */ 65 #define REG_SMC_SETUP1 (*(__IO uint32_t*)0x40080010U) /**< (SMC) SMC Setup Register 1 */ 66 #define REG_SMC_PULSE1 (*(__IO uint32_t*)0x40080014U) /**< (SMC) SMC Pulse Register 1 */ 67 #define REG_SMC_CYCLE1 (*(__IO uint32_t*)0x40080018U) /**< (SMC) SMC Cycle Register 1 */ 68 #define REG_SMC_MODE1 (*(__IO uint32_t*)0x4008001CU) /**< (SMC) SMC Mode Register 1 */ 69 #define REG_SMC_SETUP2 (*(__IO uint32_t*)0x40080020U) /**< (SMC) SMC Setup Register 2 */ 70 #define REG_SMC_PULSE2 (*(__IO uint32_t*)0x40080024U) /**< (SMC) SMC Pulse Register 2 */ 71 #define REG_SMC_CYCLE2 (*(__IO uint32_t*)0x40080028U) /**< (SMC) SMC Cycle Register 2 */ 72 #define REG_SMC_MODE2 (*(__IO uint32_t*)0x4008002CU) /**< (SMC) SMC Mode Register 2 */ 73 #define REG_SMC_SETUP3 (*(__IO uint32_t*)0x40080030U) /**< (SMC) SMC Setup Register 3 */ 74 #define REG_SMC_PULSE3 (*(__IO uint32_t*)0x40080034U) /**< (SMC) SMC Pulse Register 3 */ 75 #define REG_SMC_CYCLE3 (*(__IO uint32_t*)0x40080038U) /**< (SMC) SMC Cycle Register 3 */ 76 #define REG_SMC_MODE3 (*(__IO uint32_t*)0x4008003CU) /**< (SMC) SMC Mode Register 3 */ 77 #define REG_SMC_OCMS (*(__IO uint32_t*)0x40080080U) /**< (SMC) SMC Off-Chip Memory Scrambling Register */ 78 #define REG_SMC_KEY1 (*(__O uint32_t*)0x40080084U) /**< (SMC) SMC Off-Chip Memory Scrambling KEY1 Register */ 79 #define REG_SMC_KEY2 (*(__O uint32_t*)0x40080088U) /**< (SMC) SMC Off-Chip Memory Scrambling KEY2 Register */ 80 #define REG_SMC_WPMR (*(__IO uint32_t*)0x400800E4U) /**< (SMC) SMC Write Protection Mode Register */ 81 #define REG_SMC_WPSR (*(__I uint32_t*)0x400800E8U) /**< (SMC) SMC Write Protection Status Register */ 82 83 #endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 84 85 /* ========== Instance Parameter definitions for SMC peripheral ========== */ 86 #define SMC_INSTANCE_ID 9 87 #define SMC_CLOCK_ID 9 88 89 #endif /* _SAMV71_SMC_INSTANCE_ */ 90
