1 /** 2 * \file 3 * 4 * \brief Instance description for QSPI 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \license_stop 27 * 28 */ 29 30 /* file generated from device description version 2019-01-18T21:21:15Z */ 31 #ifndef _SAMV71_QSPI_INSTANCE_H_ 32 #define _SAMV71_QSPI_INSTANCE_H_ 33 34 /* ========== Register definition for QSPI peripheral ========== */ 35 #if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 36 37 #define REG_QSPI_CR (0x4007C000) /**< (QSPI) Control Register */ 38 #define REG_QSPI_MR (0x4007C004) /**< (QSPI) Mode Register */ 39 #define REG_QSPI_RDR (0x4007C008) /**< (QSPI) Receive Data Register */ 40 #define REG_QSPI_TDR (0x4007C00C) /**< (QSPI) Transmit Data Register */ 41 #define REG_QSPI_SR (0x4007C010) /**< (QSPI) Status Register */ 42 #define REG_QSPI_IER (0x4007C014) /**< (QSPI) Interrupt Enable Register */ 43 #define REG_QSPI_IDR (0x4007C018) /**< (QSPI) Interrupt Disable Register */ 44 #define REG_QSPI_IMR (0x4007C01C) /**< (QSPI) Interrupt Mask Register */ 45 #define REG_QSPI_SCR (0x4007C020) /**< (QSPI) Serial Clock Register */ 46 #define REG_QSPI_IAR (0x4007C030) /**< (QSPI) Instruction Address Register */ 47 #define REG_QSPI_ICR (0x4007C034) /**< (QSPI) Instruction Code Register */ 48 #define REG_QSPI_IFR (0x4007C038) /**< (QSPI) Instruction Frame Register */ 49 #define REG_QSPI_SMR (0x4007C040) /**< (QSPI) Scrambling Mode Register */ 50 #define REG_QSPI_SKR (0x4007C044) /**< (QSPI) Scrambling Key Register */ 51 #define REG_QSPI_WPMR (0x4007C0E4) /**< (QSPI) Write Protection Mode Register */ 52 #define REG_QSPI_WPSR (0x4007C0E8) /**< (QSPI) Write Protection Status Register */ 53 54 #else 55 56 #define REG_QSPI_CR (*(__O uint32_t*)0x4007C000U) /**< (QSPI) Control Register */ 57 #define REG_QSPI_MR (*(__IO uint32_t*)0x4007C004U) /**< (QSPI) Mode Register */ 58 #define REG_QSPI_RDR (*(__I uint32_t*)0x4007C008U) /**< (QSPI) Receive Data Register */ 59 #define REG_QSPI_TDR (*(__O uint32_t*)0x4007C00CU) /**< (QSPI) Transmit Data Register */ 60 #define REG_QSPI_SR (*(__I uint32_t*)0x4007C010U) /**< (QSPI) Status Register */ 61 #define REG_QSPI_IER (*(__O uint32_t*)0x4007C014U) /**< (QSPI) Interrupt Enable Register */ 62 #define REG_QSPI_IDR (*(__O uint32_t*)0x4007C018U) /**< (QSPI) Interrupt Disable Register */ 63 #define REG_QSPI_IMR (*(__I uint32_t*)0x4007C01CU) /**< (QSPI) Interrupt Mask Register */ 64 #define REG_QSPI_SCR (*(__IO uint32_t*)0x4007C020U) /**< (QSPI) Serial Clock Register */ 65 #define REG_QSPI_IAR (*(__IO uint32_t*)0x4007C030U) /**< (QSPI) Instruction Address Register */ 66 #define REG_QSPI_ICR (*(__IO uint32_t*)0x4007C034U) /**< (QSPI) Instruction Code Register */ 67 #define REG_QSPI_IFR (*(__IO uint32_t*)0x4007C038U) /**< (QSPI) Instruction Frame Register */ 68 #define REG_QSPI_SMR (*(__IO uint32_t*)0x4007C040U) /**< (QSPI) Scrambling Mode Register */ 69 #define REG_QSPI_SKR (*(__O uint32_t*)0x4007C044U) /**< (QSPI) Scrambling Key Register */ 70 #define REG_QSPI_WPMR (*(__IO uint32_t*)0x4007C0E4U) /**< (QSPI) Write Protection Mode Register */ 71 #define REG_QSPI_WPSR (*(__I uint32_t*)0x4007C0E8U) /**< (QSPI) Write Protection Status Register */ 72 73 #endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 74 75 /* ========== Instance Parameter definitions for QSPI peripheral ========== */ 76 #define QSPI_DMAC_ID_RX 6 77 #define QSPI_DMAC_ID_TX 5 78 #define QSPI_INSTANCE_ID 43 79 #define QSPI_CLOCK_ID 43 80 81 #endif /* _SAMV71_QSPI_INSTANCE_ */ 82
