1 /** 2 * \file 3 * 4 * \brief Component description for GMAC 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \license_stop 27 * 28 */ 29 30 /* file generated from device description version 2017-01-08T14:00:00Z */ 31 #ifndef _SAMV71_GMAC_COMPONENT_H_ 32 #define _SAMV71_GMAC_COMPONENT_H_ 33 #define _SAMV71_GMAC_COMPONENT_ /**< \deprecated Backward compatibility for ASF */ 34 35 /** \addtogroup SAMV_SAMV71 Gigabit Ethernet MAC 36 * @{ 37 */ 38 /* ========================================================================== */ 39 /** SOFTWARE API DEFINITION FOR GMAC */ 40 /* ========================================================================== */ 41 #ifndef COMPONENT_TYPEDEF_STYLE 42 #define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/ 43 #endif 44 45 #define GMAC_11046 /**< (GMAC) Module ID */ 46 #define REV_GMAC P /**< (GMAC) Module revision */ 47 48 /* -------- GMAC_SAB : (GMAC Offset: 0x00) (R/W 32) Specific Address 1 Bottom Register -------- */ 49 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 50 #if COMPONENT_TYPEDEF_STYLE == 'N' 51 typedef union { 52 struct { 53 uint32_t ADDR:32; /**< bit: 0..31 Specific Address 1 */ 54 } bit; /**< Structure used for bit access */ 55 uint32_t reg; /**< Type used for register access */ 56 } GMAC_SAB_Type; 57 #endif 58 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 59 60 #define GMAC_SAB_OFFSET (0x00) /**< (GMAC_SAB) Specific Address 1 Bottom Register Offset */ 61 62 #define GMAC_SAB_ADDR_Pos 0 /**< (GMAC_SAB) Specific Address 1 Position */ 63 #define GMAC_SAB_ADDR_Msk (_U_(0xFFFFFFFF) << GMAC_SAB_ADDR_Pos) /**< (GMAC_SAB) Specific Address 1 Mask */ 64 #define GMAC_SAB_ADDR(value) (GMAC_SAB_ADDR_Msk & ((value) << GMAC_SAB_ADDR_Pos)) 65 #define GMAC_SAB_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_SAB) Register MASK (Use GMAC_SAB_Msk instead) */ 66 #define GMAC_SAB_Msk _U_(0xFFFFFFFF) /**< (GMAC_SAB) Register Mask */ 67 68 69 /* -------- GMAC_SAT : (GMAC Offset: 0x04) (R/W 32) Specific Address 1 Top Register -------- */ 70 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 71 #if COMPONENT_TYPEDEF_STYLE == 'N' 72 typedef union { 73 struct { 74 uint32_t ADDR:16; /**< bit: 0..15 Specific Address 1 */ 75 uint32_t :16; /**< bit: 16..31 Reserved */ 76 } bit; /**< Structure used for bit access */ 77 uint32_t reg; /**< Type used for register access */ 78 } GMAC_SAT_Type; 79 #endif 80 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 81 82 #define GMAC_SAT_OFFSET (0x04) /**< (GMAC_SAT) Specific Address 1 Top Register Offset */ 83 84 #define GMAC_SAT_ADDR_Pos 0 /**< (GMAC_SAT) Specific Address 1 Position */ 85 #define GMAC_SAT_ADDR_Msk (_U_(0xFFFF) << GMAC_SAT_ADDR_Pos) /**< (GMAC_SAT) Specific Address 1 Mask */ 86 #define GMAC_SAT_ADDR(value) (GMAC_SAT_ADDR_Msk & ((value) << GMAC_SAT_ADDR_Pos)) 87 #define GMAC_SAT_MASK _U_(0xFFFF) /**< \deprecated (GMAC_SAT) Register MASK (Use GMAC_SAT_Msk instead) */ 88 #define GMAC_SAT_Msk _U_(0xFFFF) /**< (GMAC_SAT) Register Mask */ 89 90 91 /* -------- GMAC_NCR : (GMAC Offset: 0x00) (R/W 32) Network Control Register -------- */ 92 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 93 #if COMPONENT_TYPEDEF_STYLE == 'N' 94 typedef union { 95 struct { 96 uint32_t :1; /**< bit: 0 Reserved */ 97 uint32_t LBL:1; /**< bit: 1 Loop Back Local */ 98 uint32_t RXEN:1; /**< bit: 2 Receive Enable */ 99 uint32_t TXEN:1; /**< bit: 3 Transmit Enable */ 100 uint32_t MPE:1; /**< bit: 4 Management Port Enable */ 101 uint32_t CLRSTAT:1; /**< bit: 5 Clear Statistics Registers */ 102 uint32_t INCSTAT:1; /**< bit: 6 Increment Statistics Registers */ 103 uint32_t WESTAT:1; /**< bit: 7 Write Enable for Statistics Registers */ 104 uint32_t BP:1; /**< bit: 8 Back pressure */ 105 uint32_t TSTART:1; /**< bit: 9 Start Transmission */ 106 uint32_t THALT:1; /**< bit: 10 Transmit Halt */ 107 uint32_t TXPF:1; /**< bit: 11 Transmit Pause Frame */ 108 uint32_t TXZQPF:1; /**< bit: 12 Transmit Zero Quantum Pause Frame */ 109 uint32_t :2; /**< bit: 13..14 Reserved */ 110 uint32_t SRTSM:1; /**< bit: 15 Store Receive Time Stamp to Memory */ 111 uint32_t ENPBPR:1; /**< bit: 16 Enable PFC Priority-based Pause Reception */ 112 uint32_t TXPBPF:1; /**< bit: 17 Transmit PFC Priority-based Pause Frame */ 113 uint32_t FNP:1; /**< bit: 18 Flush Next Packet */ 114 uint32_t :13; /**< bit: 19..31 Reserved */ 115 } bit; /**< Structure used for bit access */ 116 uint32_t reg; /**< Type used for register access */ 117 } GMAC_NCR_Type; 118 #endif 119 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 120 121 #define GMAC_NCR_OFFSET (0x00) /**< (GMAC_NCR) Network Control Register Offset */ 122 123 #define GMAC_NCR_LBL_Pos 1 /**< (GMAC_NCR) Loop Back Local Position */ 124 #define GMAC_NCR_LBL_Msk (_U_(0x1) << GMAC_NCR_LBL_Pos) /**< (GMAC_NCR) Loop Back Local Mask */ 125 #define GMAC_NCR_LBL GMAC_NCR_LBL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCR_LBL_Msk instead */ 126 #define GMAC_NCR_RXEN_Pos 2 /**< (GMAC_NCR) Receive Enable Position */ 127 #define GMAC_NCR_RXEN_Msk (_U_(0x1) << GMAC_NCR_RXEN_Pos) /**< (GMAC_NCR) Receive Enable Mask */ 128 #define GMAC_NCR_RXEN GMAC_NCR_RXEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCR_RXEN_Msk instead */ 129 #define GMAC_NCR_TXEN_Pos 3 /**< (GMAC_NCR) Transmit Enable Position */ 130 #define GMAC_NCR_TXEN_Msk (_U_(0x1) << GMAC_NCR_TXEN_Pos) /**< (GMAC_NCR) Transmit Enable Mask */ 131 #define GMAC_NCR_TXEN GMAC_NCR_TXEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCR_TXEN_Msk instead */ 132 #define GMAC_NCR_MPE_Pos 4 /**< (GMAC_NCR) Management Port Enable Position */ 133 #define GMAC_NCR_MPE_Msk (_U_(0x1) << GMAC_NCR_MPE_Pos) /**< (GMAC_NCR) Management Port Enable Mask */ 134 #define GMAC_NCR_MPE GMAC_NCR_MPE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCR_MPE_Msk instead */ 135 #define GMAC_NCR_CLRSTAT_Pos 5 /**< (GMAC_NCR) Clear Statistics Registers Position */ 136 #define GMAC_NCR_CLRSTAT_Msk (_U_(0x1) << GMAC_NCR_CLRSTAT_Pos) /**< (GMAC_NCR) Clear Statistics Registers Mask */ 137 #define GMAC_NCR_CLRSTAT GMAC_NCR_CLRSTAT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCR_CLRSTAT_Msk instead */ 138 #define GMAC_NCR_INCSTAT_Pos 6 /**< (GMAC_NCR) Increment Statistics Registers Position */ 139 #define GMAC_NCR_INCSTAT_Msk (_U_(0x1) << GMAC_NCR_INCSTAT_Pos) /**< (GMAC_NCR) Increment Statistics Registers Mask */ 140 #define GMAC_NCR_INCSTAT GMAC_NCR_INCSTAT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCR_INCSTAT_Msk instead */ 141 #define GMAC_NCR_WESTAT_Pos 7 /**< (GMAC_NCR) Write Enable for Statistics Registers Position */ 142 #define GMAC_NCR_WESTAT_Msk (_U_(0x1) << GMAC_NCR_WESTAT_Pos) /**< (GMAC_NCR) Write Enable for Statistics Registers Mask */ 143 #define GMAC_NCR_WESTAT GMAC_NCR_WESTAT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCR_WESTAT_Msk instead */ 144 #define GMAC_NCR_BP_Pos 8 /**< (GMAC_NCR) Back pressure Position */ 145 #define GMAC_NCR_BP_Msk (_U_(0x1) << GMAC_NCR_BP_Pos) /**< (GMAC_NCR) Back pressure Mask */ 146 #define GMAC_NCR_BP GMAC_NCR_BP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCR_BP_Msk instead */ 147 #define GMAC_NCR_TSTART_Pos 9 /**< (GMAC_NCR) Start Transmission Position */ 148 #define GMAC_NCR_TSTART_Msk (_U_(0x1) << GMAC_NCR_TSTART_Pos) /**< (GMAC_NCR) Start Transmission Mask */ 149 #define GMAC_NCR_TSTART GMAC_NCR_TSTART_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCR_TSTART_Msk instead */ 150 #define GMAC_NCR_THALT_Pos 10 /**< (GMAC_NCR) Transmit Halt Position */ 151 #define GMAC_NCR_THALT_Msk (_U_(0x1) << GMAC_NCR_THALT_Pos) /**< (GMAC_NCR) Transmit Halt Mask */ 152 #define GMAC_NCR_THALT GMAC_NCR_THALT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCR_THALT_Msk instead */ 153 #define GMAC_NCR_TXPF_Pos 11 /**< (GMAC_NCR) Transmit Pause Frame Position */ 154 #define GMAC_NCR_TXPF_Msk (_U_(0x1) << GMAC_NCR_TXPF_Pos) /**< (GMAC_NCR) Transmit Pause Frame Mask */ 155 #define GMAC_NCR_TXPF GMAC_NCR_TXPF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCR_TXPF_Msk instead */ 156 #define GMAC_NCR_TXZQPF_Pos 12 /**< (GMAC_NCR) Transmit Zero Quantum Pause Frame Position */ 157 #define GMAC_NCR_TXZQPF_Msk (_U_(0x1) << GMAC_NCR_TXZQPF_Pos) /**< (GMAC_NCR) Transmit Zero Quantum Pause Frame Mask */ 158 #define GMAC_NCR_TXZQPF GMAC_NCR_TXZQPF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCR_TXZQPF_Msk instead */ 159 #define GMAC_NCR_SRTSM_Pos 15 /**< (GMAC_NCR) Store Receive Time Stamp to Memory Position */ 160 #define GMAC_NCR_SRTSM_Msk (_U_(0x1) << GMAC_NCR_SRTSM_Pos) /**< (GMAC_NCR) Store Receive Time Stamp to Memory Mask */ 161 #define GMAC_NCR_SRTSM GMAC_NCR_SRTSM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCR_SRTSM_Msk instead */ 162 #define GMAC_NCR_ENPBPR_Pos 16 /**< (GMAC_NCR) Enable PFC Priority-based Pause Reception Position */ 163 #define GMAC_NCR_ENPBPR_Msk (_U_(0x1) << GMAC_NCR_ENPBPR_Pos) /**< (GMAC_NCR) Enable PFC Priority-based Pause Reception Mask */ 164 #define GMAC_NCR_ENPBPR GMAC_NCR_ENPBPR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCR_ENPBPR_Msk instead */ 165 #define GMAC_NCR_TXPBPF_Pos 17 /**< (GMAC_NCR) Transmit PFC Priority-based Pause Frame Position */ 166 #define GMAC_NCR_TXPBPF_Msk (_U_(0x1) << GMAC_NCR_TXPBPF_Pos) /**< (GMAC_NCR) Transmit PFC Priority-based Pause Frame Mask */ 167 #define GMAC_NCR_TXPBPF GMAC_NCR_TXPBPF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCR_TXPBPF_Msk instead */ 168 #define GMAC_NCR_FNP_Pos 18 /**< (GMAC_NCR) Flush Next Packet Position */ 169 #define GMAC_NCR_FNP_Msk (_U_(0x1) << GMAC_NCR_FNP_Pos) /**< (GMAC_NCR) Flush Next Packet Mask */ 170 #define GMAC_NCR_FNP GMAC_NCR_FNP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCR_FNP_Msk instead */ 171 #define GMAC_NCR_MASK _U_(0x79FFE) /**< \deprecated (GMAC_NCR) Register MASK (Use GMAC_NCR_Msk instead) */ 172 #define GMAC_NCR_Msk _U_(0x79FFE) /**< (GMAC_NCR) Register Mask */ 173 174 175 /* -------- GMAC_NCFGR : (GMAC Offset: 0x04) (R/W 32) Network Configuration Register -------- */ 176 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 177 #if COMPONENT_TYPEDEF_STYLE == 'N' 178 typedef union { 179 struct { 180 uint32_t SPD:1; /**< bit: 0 Speed */ 181 uint32_t FD:1; /**< bit: 1 Full Duplex */ 182 uint32_t DNVLAN:1; /**< bit: 2 Discard Non-VLAN FRAMES */ 183 uint32_t JFRAME:1; /**< bit: 3 Jumbo Frame Size */ 184 uint32_t CAF:1; /**< bit: 4 Copy All Frames */ 185 uint32_t NBC:1; /**< bit: 5 No Broadcast */ 186 uint32_t MTIHEN:1; /**< bit: 6 Multicast Hash Enable */ 187 uint32_t UNIHEN:1; /**< bit: 7 Unicast Hash Enable */ 188 uint32_t MAXFS:1; /**< bit: 8 1536 Maximum Frame Size */ 189 uint32_t :3; /**< bit: 9..11 Reserved */ 190 uint32_t RTY:1; /**< bit: 12 Retry Test */ 191 uint32_t PEN:1; /**< bit: 13 Pause Enable */ 192 uint32_t RXBUFO:2; /**< bit: 14..15 Receive Buffer Offset */ 193 uint32_t LFERD:1; /**< bit: 16 Length Field Error Frame Discard */ 194 uint32_t RFCS:1; /**< bit: 17 Remove FCS */ 195 uint32_t CLK:3; /**< bit: 18..20 MDC CLock Division */ 196 uint32_t DBW:2; /**< bit: 21..22 Data Bus Width */ 197 uint32_t DCPF:1; /**< bit: 23 Disable Copy of Pause Frames */ 198 uint32_t RXCOEN:1; /**< bit: 24 Receive Checksum Offload Enable */ 199 uint32_t EFRHD:1; /**< bit: 25 Enable Frames Received in Half Duplex */ 200 uint32_t IRXFCS:1; /**< bit: 26 Ignore RX FCS */ 201 uint32_t :1; /**< bit: 27 Reserved */ 202 uint32_t IPGSEN:1; /**< bit: 28 IP Stretch Enable */ 203 uint32_t RXBP:1; /**< bit: 29 Receive Bad Preamble */ 204 uint32_t IRXER:1; /**< bit: 30 Ignore IPG GRXER */ 205 uint32_t :1; /**< bit: 31 Reserved */ 206 } bit; /**< Structure used for bit access */ 207 uint32_t reg; /**< Type used for register access */ 208 } GMAC_NCFGR_Type; 209 #endif 210 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 211 212 #define GMAC_NCFGR_OFFSET (0x04) /**< (GMAC_NCFGR) Network Configuration Register Offset */ 213 214 #define GMAC_NCFGR_SPD_Pos 0 /**< (GMAC_NCFGR) Speed Position */ 215 #define GMAC_NCFGR_SPD_Msk (_U_(0x1) << GMAC_NCFGR_SPD_Pos) /**< (GMAC_NCFGR) Speed Mask */ 216 #define GMAC_NCFGR_SPD GMAC_NCFGR_SPD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCFGR_SPD_Msk instead */ 217 #define GMAC_NCFGR_FD_Pos 1 /**< (GMAC_NCFGR) Full Duplex Position */ 218 #define GMAC_NCFGR_FD_Msk (_U_(0x1) << GMAC_NCFGR_FD_Pos) /**< (GMAC_NCFGR) Full Duplex Mask */ 219 #define GMAC_NCFGR_FD GMAC_NCFGR_FD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCFGR_FD_Msk instead */ 220 #define GMAC_NCFGR_DNVLAN_Pos 2 /**< (GMAC_NCFGR) Discard Non-VLAN FRAMES Position */ 221 #define GMAC_NCFGR_DNVLAN_Msk (_U_(0x1) << GMAC_NCFGR_DNVLAN_Pos) /**< (GMAC_NCFGR) Discard Non-VLAN FRAMES Mask */ 222 #define GMAC_NCFGR_DNVLAN GMAC_NCFGR_DNVLAN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCFGR_DNVLAN_Msk instead */ 223 #define GMAC_NCFGR_JFRAME_Pos 3 /**< (GMAC_NCFGR) Jumbo Frame Size Position */ 224 #define GMAC_NCFGR_JFRAME_Msk (_U_(0x1) << GMAC_NCFGR_JFRAME_Pos) /**< (GMAC_NCFGR) Jumbo Frame Size Mask */ 225 #define GMAC_NCFGR_JFRAME GMAC_NCFGR_JFRAME_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCFGR_JFRAME_Msk instead */ 226 #define GMAC_NCFGR_CAF_Pos 4 /**< (GMAC_NCFGR) Copy All Frames Position */ 227 #define GMAC_NCFGR_CAF_Msk (_U_(0x1) << GMAC_NCFGR_CAF_Pos) /**< (GMAC_NCFGR) Copy All Frames Mask */ 228 #define GMAC_NCFGR_CAF GMAC_NCFGR_CAF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCFGR_CAF_Msk instead */ 229 #define GMAC_NCFGR_NBC_Pos 5 /**< (GMAC_NCFGR) No Broadcast Position */ 230 #define GMAC_NCFGR_NBC_Msk (_U_(0x1) << GMAC_NCFGR_NBC_Pos) /**< (GMAC_NCFGR) No Broadcast Mask */ 231 #define GMAC_NCFGR_NBC GMAC_NCFGR_NBC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCFGR_NBC_Msk instead */ 232 #define GMAC_NCFGR_MTIHEN_Pos 6 /**< (GMAC_NCFGR) Multicast Hash Enable Position */ 233 #define GMAC_NCFGR_MTIHEN_Msk (_U_(0x1) << GMAC_NCFGR_MTIHEN_Pos) /**< (GMAC_NCFGR) Multicast Hash Enable Mask */ 234 #define GMAC_NCFGR_MTIHEN GMAC_NCFGR_MTIHEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCFGR_MTIHEN_Msk instead */ 235 #define GMAC_NCFGR_UNIHEN_Pos 7 /**< (GMAC_NCFGR) Unicast Hash Enable Position */ 236 #define GMAC_NCFGR_UNIHEN_Msk (_U_(0x1) << GMAC_NCFGR_UNIHEN_Pos) /**< (GMAC_NCFGR) Unicast Hash Enable Mask */ 237 #define GMAC_NCFGR_UNIHEN GMAC_NCFGR_UNIHEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCFGR_UNIHEN_Msk instead */ 238 #define GMAC_NCFGR_MAXFS_Pos 8 /**< (GMAC_NCFGR) 1536 Maximum Frame Size Position */ 239 #define GMAC_NCFGR_MAXFS_Msk (_U_(0x1) << GMAC_NCFGR_MAXFS_Pos) /**< (GMAC_NCFGR) 1536 Maximum Frame Size Mask */ 240 #define GMAC_NCFGR_MAXFS GMAC_NCFGR_MAXFS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCFGR_MAXFS_Msk instead */ 241 #define GMAC_NCFGR_RTY_Pos 12 /**< (GMAC_NCFGR) Retry Test Position */ 242 #define GMAC_NCFGR_RTY_Msk (_U_(0x1) << GMAC_NCFGR_RTY_Pos) /**< (GMAC_NCFGR) Retry Test Mask */ 243 #define GMAC_NCFGR_RTY GMAC_NCFGR_RTY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCFGR_RTY_Msk instead */ 244 #define GMAC_NCFGR_PEN_Pos 13 /**< (GMAC_NCFGR) Pause Enable Position */ 245 #define GMAC_NCFGR_PEN_Msk (_U_(0x1) << GMAC_NCFGR_PEN_Pos) /**< (GMAC_NCFGR) Pause Enable Mask */ 246 #define GMAC_NCFGR_PEN GMAC_NCFGR_PEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCFGR_PEN_Msk instead */ 247 #define GMAC_NCFGR_RXBUFO_Pos 14 /**< (GMAC_NCFGR) Receive Buffer Offset Position */ 248 #define GMAC_NCFGR_RXBUFO_Msk (_U_(0x3) << GMAC_NCFGR_RXBUFO_Pos) /**< (GMAC_NCFGR) Receive Buffer Offset Mask */ 249 #define GMAC_NCFGR_RXBUFO(value) (GMAC_NCFGR_RXBUFO_Msk & ((value) << GMAC_NCFGR_RXBUFO_Pos)) 250 #define GMAC_NCFGR_LFERD_Pos 16 /**< (GMAC_NCFGR) Length Field Error Frame Discard Position */ 251 #define GMAC_NCFGR_LFERD_Msk (_U_(0x1) << GMAC_NCFGR_LFERD_Pos) /**< (GMAC_NCFGR) Length Field Error Frame Discard Mask */ 252 #define GMAC_NCFGR_LFERD GMAC_NCFGR_LFERD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCFGR_LFERD_Msk instead */ 253 #define GMAC_NCFGR_RFCS_Pos 17 /**< (GMAC_NCFGR) Remove FCS Position */ 254 #define GMAC_NCFGR_RFCS_Msk (_U_(0x1) << GMAC_NCFGR_RFCS_Pos) /**< (GMAC_NCFGR) Remove FCS Mask */ 255 #define GMAC_NCFGR_RFCS GMAC_NCFGR_RFCS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCFGR_RFCS_Msk instead */ 256 #define GMAC_NCFGR_CLK_Pos 18 /**< (GMAC_NCFGR) MDC CLock Division Position */ 257 #define GMAC_NCFGR_CLK_Msk (_U_(0x7) << GMAC_NCFGR_CLK_Pos) /**< (GMAC_NCFGR) MDC CLock Division Mask */ 258 #define GMAC_NCFGR_CLK(value) (GMAC_NCFGR_CLK_Msk & ((value) << GMAC_NCFGR_CLK_Pos)) 259 #define GMAC_NCFGR_CLK_MCK_8_Val _U_(0x0) /**< (GMAC_NCFGR) MCK divided by 8 (MCK up to 20 MHz) */ 260 #define GMAC_NCFGR_CLK_MCK_16_Val _U_(0x1) /**< (GMAC_NCFGR) MCK divided by 16 (MCK up to 40 MHz) */ 261 #define GMAC_NCFGR_CLK_MCK_32_Val _U_(0x2) /**< (GMAC_NCFGR) MCK divided by 32 (MCK up to 80 MHz) */ 262 #define GMAC_NCFGR_CLK_MCK_48_Val _U_(0x3) /**< (GMAC_NCFGR) MCK divided by 48 (MCK up to 120 MHz) */ 263 #define GMAC_NCFGR_CLK_MCK_64_Val _U_(0x4) /**< (GMAC_NCFGR) MCK divided by 64 (MCK up to 160 MHz) */ 264 #define GMAC_NCFGR_CLK_MCK_96_Val _U_(0x5) /**< (GMAC_NCFGR) MCK divided by 96 (MCK up to 240 MHz) */ 265 #define GMAC_NCFGR_CLK_MCK_8 (GMAC_NCFGR_CLK_MCK_8_Val << GMAC_NCFGR_CLK_Pos) /**< (GMAC_NCFGR) MCK divided by 8 (MCK up to 20 MHz) Position */ 266 #define GMAC_NCFGR_CLK_MCK_16 (GMAC_NCFGR_CLK_MCK_16_Val << GMAC_NCFGR_CLK_Pos) /**< (GMAC_NCFGR) MCK divided by 16 (MCK up to 40 MHz) Position */ 267 #define GMAC_NCFGR_CLK_MCK_32 (GMAC_NCFGR_CLK_MCK_32_Val << GMAC_NCFGR_CLK_Pos) /**< (GMAC_NCFGR) MCK divided by 32 (MCK up to 80 MHz) Position */ 268 #define GMAC_NCFGR_CLK_MCK_48 (GMAC_NCFGR_CLK_MCK_48_Val << GMAC_NCFGR_CLK_Pos) /**< (GMAC_NCFGR) MCK divided by 48 (MCK up to 120 MHz) Position */ 269 #define GMAC_NCFGR_CLK_MCK_64 (GMAC_NCFGR_CLK_MCK_64_Val << GMAC_NCFGR_CLK_Pos) /**< (GMAC_NCFGR) MCK divided by 64 (MCK up to 160 MHz) Position */ 270 #define GMAC_NCFGR_CLK_MCK_96 (GMAC_NCFGR_CLK_MCK_96_Val << GMAC_NCFGR_CLK_Pos) /**< (GMAC_NCFGR) MCK divided by 96 (MCK up to 240 MHz) Position */ 271 #define GMAC_NCFGR_DBW_Pos 21 /**< (GMAC_NCFGR) Data Bus Width Position */ 272 #define GMAC_NCFGR_DBW_Msk (_U_(0x3) << GMAC_NCFGR_DBW_Pos) /**< (GMAC_NCFGR) Data Bus Width Mask */ 273 #define GMAC_NCFGR_DBW(value) (GMAC_NCFGR_DBW_Msk & ((value) << GMAC_NCFGR_DBW_Pos)) 274 #define GMAC_NCFGR_DCPF_Pos 23 /**< (GMAC_NCFGR) Disable Copy of Pause Frames Position */ 275 #define GMAC_NCFGR_DCPF_Msk (_U_(0x1) << GMAC_NCFGR_DCPF_Pos) /**< (GMAC_NCFGR) Disable Copy of Pause Frames Mask */ 276 #define GMAC_NCFGR_DCPF GMAC_NCFGR_DCPF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCFGR_DCPF_Msk instead */ 277 #define GMAC_NCFGR_RXCOEN_Pos 24 /**< (GMAC_NCFGR) Receive Checksum Offload Enable Position */ 278 #define GMAC_NCFGR_RXCOEN_Msk (_U_(0x1) << GMAC_NCFGR_RXCOEN_Pos) /**< (GMAC_NCFGR) Receive Checksum Offload Enable Mask */ 279 #define GMAC_NCFGR_RXCOEN GMAC_NCFGR_RXCOEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCFGR_RXCOEN_Msk instead */ 280 #define GMAC_NCFGR_EFRHD_Pos 25 /**< (GMAC_NCFGR) Enable Frames Received in Half Duplex Position */ 281 #define GMAC_NCFGR_EFRHD_Msk (_U_(0x1) << GMAC_NCFGR_EFRHD_Pos) /**< (GMAC_NCFGR) Enable Frames Received in Half Duplex Mask */ 282 #define GMAC_NCFGR_EFRHD GMAC_NCFGR_EFRHD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCFGR_EFRHD_Msk instead */ 283 #define GMAC_NCFGR_IRXFCS_Pos 26 /**< (GMAC_NCFGR) Ignore RX FCS Position */ 284 #define GMAC_NCFGR_IRXFCS_Msk (_U_(0x1) << GMAC_NCFGR_IRXFCS_Pos) /**< (GMAC_NCFGR) Ignore RX FCS Mask */ 285 #define GMAC_NCFGR_IRXFCS GMAC_NCFGR_IRXFCS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCFGR_IRXFCS_Msk instead */ 286 #define GMAC_NCFGR_IPGSEN_Pos 28 /**< (GMAC_NCFGR) IP Stretch Enable Position */ 287 #define GMAC_NCFGR_IPGSEN_Msk (_U_(0x1) << GMAC_NCFGR_IPGSEN_Pos) /**< (GMAC_NCFGR) IP Stretch Enable Mask */ 288 #define GMAC_NCFGR_IPGSEN GMAC_NCFGR_IPGSEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCFGR_IPGSEN_Msk instead */ 289 #define GMAC_NCFGR_RXBP_Pos 29 /**< (GMAC_NCFGR) Receive Bad Preamble Position */ 290 #define GMAC_NCFGR_RXBP_Msk (_U_(0x1) << GMAC_NCFGR_RXBP_Pos) /**< (GMAC_NCFGR) Receive Bad Preamble Mask */ 291 #define GMAC_NCFGR_RXBP GMAC_NCFGR_RXBP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCFGR_RXBP_Msk instead */ 292 #define GMAC_NCFGR_IRXER_Pos 30 /**< (GMAC_NCFGR) Ignore IPG GRXER Position */ 293 #define GMAC_NCFGR_IRXER_Msk (_U_(0x1) << GMAC_NCFGR_IRXER_Pos) /**< (GMAC_NCFGR) Ignore IPG GRXER Mask */ 294 #define GMAC_NCFGR_IRXER GMAC_NCFGR_IRXER_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCFGR_IRXER_Msk instead */ 295 #define GMAC_NCFGR_MASK _U_(0x77FFF1FF) /**< \deprecated (GMAC_NCFGR) Register MASK (Use GMAC_NCFGR_Msk instead) */ 296 #define GMAC_NCFGR_Msk _U_(0x77FFF1FF) /**< (GMAC_NCFGR) Register Mask */ 297 298 299 /* -------- GMAC_NSR : (GMAC Offset: 0x08) (R/ 32) Network Status Register -------- */ 300 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 301 #if COMPONENT_TYPEDEF_STYLE == 'N' 302 typedef union { 303 struct { 304 uint32_t :1; /**< bit: 0 Reserved */ 305 uint32_t MDIO:1; /**< bit: 1 MDIO Input Status */ 306 uint32_t IDLE:1; /**< bit: 2 PHY Management Logic Idle */ 307 uint32_t :29; /**< bit: 3..31 Reserved */ 308 } bit; /**< Structure used for bit access */ 309 uint32_t reg; /**< Type used for register access */ 310 } GMAC_NSR_Type; 311 #endif 312 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 313 314 #define GMAC_NSR_OFFSET (0x08) /**< (GMAC_NSR) Network Status Register Offset */ 315 316 #define GMAC_NSR_MDIO_Pos 1 /**< (GMAC_NSR) MDIO Input Status Position */ 317 #define GMAC_NSR_MDIO_Msk (_U_(0x1) << GMAC_NSR_MDIO_Pos) /**< (GMAC_NSR) MDIO Input Status Mask */ 318 #define GMAC_NSR_MDIO GMAC_NSR_MDIO_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NSR_MDIO_Msk instead */ 319 #define GMAC_NSR_IDLE_Pos 2 /**< (GMAC_NSR) PHY Management Logic Idle Position */ 320 #define GMAC_NSR_IDLE_Msk (_U_(0x1) << GMAC_NSR_IDLE_Pos) /**< (GMAC_NSR) PHY Management Logic Idle Mask */ 321 #define GMAC_NSR_IDLE GMAC_NSR_IDLE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NSR_IDLE_Msk instead */ 322 #define GMAC_NSR_MASK _U_(0x06) /**< \deprecated (GMAC_NSR) Register MASK (Use GMAC_NSR_Msk instead) */ 323 #define GMAC_NSR_Msk _U_(0x06) /**< (GMAC_NSR) Register Mask */ 324 325 326 /* -------- GMAC_UR : (GMAC Offset: 0x0c) (R/W 32) User Register -------- */ 327 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 328 #if COMPONENT_TYPEDEF_STYLE == 'N' 329 typedef union { 330 struct { 331 uint32_t RMII:1; /**< bit: 0 Reduced MII Mode */ 332 uint32_t :31; /**< bit: 1..31 Reserved */ 333 } bit; /**< Structure used for bit access */ 334 uint32_t reg; /**< Type used for register access */ 335 } GMAC_UR_Type; 336 #endif 337 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 338 339 #define GMAC_UR_OFFSET (0x0C) /**< (GMAC_UR) User Register Offset */ 340 341 #define GMAC_UR_RMII_Pos 0 /**< (GMAC_UR) Reduced MII Mode Position */ 342 #define GMAC_UR_RMII_Msk (_U_(0x1) << GMAC_UR_RMII_Pos) /**< (GMAC_UR) Reduced MII Mode Mask */ 343 #define GMAC_UR_RMII GMAC_UR_RMII_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_UR_RMII_Msk instead */ 344 #define GMAC_UR_MASK _U_(0x01) /**< \deprecated (GMAC_UR) Register MASK (Use GMAC_UR_Msk instead) */ 345 #define GMAC_UR_Msk _U_(0x01) /**< (GMAC_UR) Register Mask */ 346 347 348 /* -------- GMAC_DCFGR : (GMAC Offset: 0x10) (R/W 32) DMA Configuration Register -------- */ 349 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 350 #if COMPONENT_TYPEDEF_STYLE == 'N' 351 typedef union { 352 struct { 353 uint32_t FBLDO:5; /**< bit: 0..4 Fixed Burst Length for DMA Data Operations: */ 354 uint32_t :1; /**< bit: 5 Reserved */ 355 uint32_t ESMA:1; /**< bit: 6 Endian Swap Mode Enable for Management Descriptor Accesses */ 356 uint32_t ESPA:1; /**< bit: 7 Endian Swap Mode Enable for Packet Data Accesses */ 357 uint32_t RXBMS:2; /**< bit: 8..9 Receiver Packet Buffer Memory Size Select */ 358 uint32_t TXPBMS:1; /**< bit: 10 Transmitter Packet Buffer Memory Size Select */ 359 uint32_t TXCOEN:1; /**< bit: 11 Transmitter Checksum Generation Offload Enable */ 360 uint32_t :4; /**< bit: 12..15 Reserved */ 361 uint32_t DRBS:8; /**< bit: 16..23 DMA Receive Buffer Size */ 362 uint32_t DDRP:1; /**< bit: 24 DMA Discard Receive Packets */ 363 uint32_t :7; /**< bit: 25..31 Reserved */ 364 } bit; /**< Structure used for bit access */ 365 uint32_t reg; /**< Type used for register access */ 366 } GMAC_DCFGR_Type; 367 #endif 368 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 369 370 #define GMAC_DCFGR_OFFSET (0x10) /**< (GMAC_DCFGR) DMA Configuration Register Offset */ 371 372 #define GMAC_DCFGR_FBLDO_Pos 0 /**< (GMAC_DCFGR) Fixed Burst Length for DMA Data Operations: Position */ 373 #define GMAC_DCFGR_FBLDO_Msk (_U_(0x1F) << GMAC_DCFGR_FBLDO_Pos) /**< (GMAC_DCFGR) Fixed Burst Length for DMA Data Operations: Mask */ 374 #define GMAC_DCFGR_FBLDO(value) (GMAC_DCFGR_FBLDO_Msk & ((value) << GMAC_DCFGR_FBLDO_Pos)) 375 #define GMAC_DCFGR_FBLDO_SINGLE_Val _U_(0x1) /**< (GMAC_DCFGR) 00001: Always use SINGLE AHB bursts */ 376 #define GMAC_DCFGR_FBLDO_INCR4_Val _U_(0x4) /**< (GMAC_DCFGR) 001xx: Attempt to use INCR4 AHB bursts (Default) */ 377 #define GMAC_DCFGR_FBLDO_INCR8_Val _U_(0x8) /**< (GMAC_DCFGR) 01xxx: Attempt to use INCR8 AHB bursts */ 378 #define GMAC_DCFGR_FBLDO_INCR16_Val _U_(0x10) /**< (GMAC_DCFGR) 1xxxx: Attempt to use INCR16 AHB bursts */ 379 #define GMAC_DCFGR_FBLDO_SINGLE (GMAC_DCFGR_FBLDO_SINGLE_Val << GMAC_DCFGR_FBLDO_Pos) /**< (GMAC_DCFGR) 00001: Always use SINGLE AHB bursts Position */ 380 #define GMAC_DCFGR_FBLDO_INCR4 (GMAC_DCFGR_FBLDO_INCR4_Val << GMAC_DCFGR_FBLDO_Pos) /**< (GMAC_DCFGR) 001xx: Attempt to use INCR4 AHB bursts (Default) Position */ 381 #define GMAC_DCFGR_FBLDO_INCR8 (GMAC_DCFGR_FBLDO_INCR8_Val << GMAC_DCFGR_FBLDO_Pos) /**< (GMAC_DCFGR) 01xxx: Attempt to use INCR8 AHB bursts Position */ 382 #define GMAC_DCFGR_FBLDO_INCR16 (GMAC_DCFGR_FBLDO_INCR16_Val << GMAC_DCFGR_FBLDO_Pos) /**< (GMAC_DCFGR) 1xxxx: Attempt to use INCR16 AHB bursts Position */ 383 #define GMAC_DCFGR_ESMA_Pos 6 /**< (GMAC_DCFGR) Endian Swap Mode Enable for Management Descriptor Accesses Position */ 384 #define GMAC_DCFGR_ESMA_Msk (_U_(0x1) << GMAC_DCFGR_ESMA_Pos) /**< (GMAC_DCFGR) Endian Swap Mode Enable for Management Descriptor Accesses Mask */ 385 #define GMAC_DCFGR_ESMA GMAC_DCFGR_ESMA_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_DCFGR_ESMA_Msk instead */ 386 #define GMAC_DCFGR_ESPA_Pos 7 /**< (GMAC_DCFGR) Endian Swap Mode Enable for Packet Data Accesses Position */ 387 #define GMAC_DCFGR_ESPA_Msk (_U_(0x1) << GMAC_DCFGR_ESPA_Pos) /**< (GMAC_DCFGR) Endian Swap Mode Enable for Packet Data Accesses Mask */ 388 #define GMAC_DCFGR_ESPA GMAC_DCFGR_ESPA_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_DCFGR_ESPA_Msk instead */ 389 #define GMAC_DCFGR_RXBMS_Pos 8 /**< (GMAC_DCFGR) Receiver Packet Buffer Memory Size Select Position */ 390 #define GMAC_DCFGR_RXBMS_Msk (_U_(0x3) << GMAC_DCFGR_RXBMS_Pos) /**< (GMAC_DCFGR) Receiver Packet Buffer Memory Size Select Mask */ 391 #define GMAC_DCFGR_RXBMS(value) (GMAC_DCFGR_RXBMS_Msk & ((value) << GMAC_DCFGR_RXBMS_Pos)) 392 #define GMAC_DCFGR_RXBMS_EIGHTH_Val _U_(0x0) /**< (GMAC_DCFGR) 4/8 Kbyte Memory Size */ 393 #define GMAC_DCFGR_RXBMS_QUARTER_Val _U_(0x1) /**< (GMAC_DCFGR) 4/4 Kbytes Memory Size */ 394 #define GMAC_DCFGR_RXBMS_HALF_Val _U_(0x2) /**< (GMAC_DCFGR) 4/2 Kbytes Memory Size */ 395 #define GMAC_DCFGR_RXBMS_FULL_Val _U_(0x3) /**< (GMAC_DCFGR) 4 Kbytes Memory Size */ 396 #define GMAC_DCFGR_RXBMS_EIGHTH (GMAC_DCFGR_RXBMS_EIGHTH_Val << GMAC_DCFGR_RXBMS_Pos) /**< (GMAC_DCFGR) 4/8 Kbyte Memory Size Position */ 397 #define GMAC_DCFGR_RXBMS_QUARTER (GMAC_DCFGR_RXBMS_QUARTER_Val << GMAC_DCFGR_RXBMS_Pos) /**< (GMAC_DCFGR) 4/4 Kbytes Memory Size Position */ 398 #define GMAC_DCFGR_RXBMS_HALF (GMAC_DCFGR_RXBMS_HALF_Val << GMAC_DCFGR_RXBMS_Pos) /**< (GMAC_DCFGR) 4/2 Kbytes Memory Size Position */ 399 #define GMAC_DCFGR_RXBMS_FULL (GMAC_DCFGR_RXBMS_FULL_Val << GMAC_DCFGR_RXBMS_Pos) /**< (GMAC_DCFGR) 4 Kbytes Memory Size Position */ 400 #define GMAC_DCFGR_TXPBMS_Pos 10 /**< (GMAC_DCFGR) Transmitter Packet Buffer Memory Size Select Position */ 401 #define GMAC_DCFGR_TXPBMS_Msk (_U_(0x1) << GMAC_DCFGR_TXPBMS_Pos) /**< (GMAC_DCFGR) Transmitter Packet Buffer Memory Size Select Mask */ 402 #define GMAC_DCFGR_TXPBMS GMAC_DCFGR_TXPBMS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_DCFGR_TXPBMS_Msk instead */ 403 #define GMAC_DCFGR_TXCOEN_Pos 11 /**< (GMAC_DCFGR) Transmitter Checksum Generation Offload Enable Position */ 404 #define GMAC_DCFGR_TXCOEN_Msk (_U_(0x1) << GMAC_DCFGR_TXCOEN_Pos) /**< (GMAC_DCFGR) Transmitter Checksum Generation Offload Enable Mask */ 405 #define GMAC_DCFGR_TXCOEN GMAC_DCFGR_TXCOEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_DCFGR_TXCOEN_Msk instead */ 406 #define GMAC_DCFGR_DRBS_Pos 16 /**< (GMAC_DCFGR) DMA Receive Buffer Size Position */ 407 #define GMAC_DCFGR_DRBS_Msk (_U_(0xFF) << GMAC_DCFGR_DRBS_Pos) /**< (GMAC_DCFGR) DMA Receive Buffer Size Mask */ 408 #define GMAC_DCFGR_DRBS(value) (GMAC_DCFGR_DRBS_Msk & ((value) << GMAC_DCFGR_DRBS_Pos)) 409 #define GMAC_DCFGR_DDRP_Pos 24 /**< (GMAC_DCFGR) DMA Discard Receive Packets Position */ 410 #define GMAC_DCFGR_DDRP_Msk (_U_(0x1) << GMAC_DCFGR_DDRP_Pos) /**< (GMAC_DCFGR) DMA Discard Receive Packets Mask */ 411 #define GMAC_DCFGR_DDRP GMAC_DCFGR_DDRP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_DCFGR_DDRP_Msk instead */ 412 #define GMAC_DCFGR_MASK _U_(0x1FF0FDF) /**< \deprecated (GMAC_DCFGR) Register MASK (Use GMAC_DCFGR_Msk instead) */ 413 #define GMAC_DCFGR_Msk _U_(0x1FF0FDF) /**< (GMAC_DCFGR) Register Mask */ 414 415 416 /* -------- GMAC_TSR : (GMAC Offset: 0x14) (R/W 32) Transmit Status Register -------- */ 417 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 418 #if COMPONENT_TYPEDEF_STYLE == 'N' 419 typedef union { 420 struct { 421 uint32_t UBR:1; /**< bit: 0 Used Bit Read */ 422 uint32_t COL:1; /**< bit: 1 Collision Occurred */ 423 uint32_t RLE:1; /**< bit: 2 Retry Limit Exceeded */ 424 uint32_t TXGO:1; /**< bit: 3 Transmit Go */ 425 uint32_t TFC:1; /**< bit: 4 Transmit Frame Corruption Due to AHB Error */ 426 uint32_t TXCOMP:1; /**< bit: 5 Transmit Complete */ 427 uint32_t :2; /**< bit: 6..7 Reserved */ 428 uint32_t HRESP:1; /**< bit: 8 HRESP Not OK */ 429 uint32_t :23; /**< bit: 9..31 Reserved */ 430 } bit; /**< Structure used for bit access */ 431 uint32_t reg; /**< Type used for register access */ 432 } GMAC_TSR_Type; 433 #endif 434 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 435 436 #define GMAC_TSR_OFFSET (0x14) /**< (GMAC_TSR) Transmit Status Register Offset */ 437 438 #define GMAC_TSR_UBR_Pos 0 /**< (GMAC_TSR) Used Bit Read Position */ 439 #define GMAC_TSR_UBR_Msk (_U_(0x1) << GMAC_TSR_UBR_Pos) /**< (GMAC_TSR) Used Bit Read Mask */ 440 #define GMAC_TSR_UBR GMAC_TSR_UBR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_TSR_UBR_Msk instead */ 441 #define GMAC_TSR_COL_Pos 1 /**< (GMAC_TSR) Collision Occurred Position */ 442 #define GMAC_TSR_COL_Msk (_U_(0x1) << GMAC_TSR_COL_Pos) /**< (GMAC_TSR) Collision Occurred Mask */ 443 #define GMAC_TSR_COL GMAC_TSR_COL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_TSR_COL_Msk instead */ 444 #define GMAC_TSR_RLE_Pos 2 /**< (GMAC_TSR) Retry Limit Exceeded Position */ 445 #define GMAC_TSR_RLE_Msk (_U_(0x1) << GMAC_TSR_RLE_Pos) /**< (GMAC_TSR) Retry Limit Exceeded Mask */ 446 #define GMAC_TSR_RLE GMAC_TSR_RLE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_TSR_RLE_Msk instead */ 447 #define GMAC_TSR_TXGO_Pos 3 /**< (GMAC_TSR) Transmit Go Position */ 448 #define GMAC_TSR_TXGO_Msk (_U_(0x1) << GMAC_TSR_TXGO_Pos) /**< (GMAC_TSR) Transmit Go Mask */ 449 #define GMAC_TSR_TXGO GMAC_TSR_TXGO_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_TSR_TXGO_Msk instead */ 450 #define GMAC_TSR_TFC_Pos 4 /**< (GMAC_TSR) Transmit Frame Corruption Due to AHB Error Position */ 451 #define GMAC_TSR_TFC_Msk (_U_(0x1) << GMAC_TSR_TFC_Pos) /**< (GMAC_TSR) Transmit Frame Corruption Due to AHB Error Mask */ 452 #define GMAC_TSR_TFC GMAC_TSR_TFC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_TSR_TFC_Msk instead */ 453 #define GMAC_TSR_TXCOMP_Pos 5 /**< (GMAC_TSR) Transmit Complete Position */ 454 #define GMAC_TSR_TXCOMP_Msk (_U_(0x1) << GMAC_TSR_TXCOMP_Pos) /**< (GMAC_TSR) Transmit Complete Mask */ 455 #define GMAC_TSR_TXCOMP GMAC_TSR_TXCOMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_TSR_TXCOMP_Msk instead */ 456 #define GMAC_TSR_HRESP_Pos 8 /**< (GMAC_TSR) HRESP Not OK Position */ 457 #define GMAC_TSR_HRESP_Msk (_U_(0x1) << GMAC_TSR_HRESP_Pos) /**< (GMAC_TSR) HRESP Not OK Mask */ 458 #define GMAC_TSR_HRESP GMAC_TSR_HRESP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_TSR_HRESP_Msk instead */ 459 #define GMAC_TSR_MASK _U_(0x13F) /**< \deprecated (GMAC_TSR) Register MASK (Use GMAC_TSR_Msk instead) */ 460 #define GMAC_TSR_Msk _U_(0x13F) /**< (GMAC_TSR) Register Mask */ 461 462 463 /* -------- GMAC_RBQB : (GMAC Offset: 0x18) (R/W 32) Receive Buffer Queue Base Address Register -------- */ 464 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 465 #if COMPONENT_TYPEDEF_STYLE == 'N' 466 typedef union { 467 struct { 468 uint32_t :2; /**< bit: 0..1 Reserved */ 469 uint32_t ADDR:30; /**< bit: 2..31 Receive Buffer Queue Base Address */ 470 } bit; /**< Structure used for bit access */ 471 uint32_t reg; /**< Type used for register access */ 472 } GMAC_RBQB_Type; 473 #endif 474 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 475 476 #define GMAC_RBQB_OFFSET (0x18) /**< (GMAC_RBQB) Receive Buffer Queue Base Address Register Offset */ 477 478 #define GMAC_RBQB_ADDR_Pos 2 /**< (GMAC_RBQB) Receive Buffer Queue Base Address Position */ 479 #define GMAC_RBQB_ADDR_Msk (_U_(0x3FFFFFFF) << GMAC_RBQB_ADDR_Pos) /**< (GMAC_RBQB) Receive Buffer Queue Base Address Mask */ 480 #define GMAC_RBQB_ADDR(value) (GMAC_RBQB_ADDR_Msk & ((value) << GMAC_RBQB_ADDR_Pos)) 481 #define GMAC_RBQB_MASK _U_(0xFFFFFFFC) /**< \deprecated (GMAC_RBQB) Register MASK (Use GMAC_RBQB_Msk instead) */ 482 #define GMAC_RBQB_Msk _U_(0xFFFFFFFC) /**< (GMAC_RBQB) Register Mask */ 483 484 485 /* -------- GMAC_TBQB : (GMAC Offset: 0x1c) (R/W 32) Transmit Buffer Queue Base Address Register -------- */ 486 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 487 #if COMPONENT_TYPEDEF_STYLE == 'N' 488 typedef union { 489 struct { 490 uint32_t :2; /**< bit: 0..1 Reserved */ 491 uint32_t ADDR:30; /**< bit: 2..31 Transmit Buffer Queue Base Address */ 492 } bit; /**< Structure used for bit access */ 493 uint32_t reg; /**< Type used for register access */ 494 } GMAC_TBQB_Type; 495 #endif 496 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 497 498 #define GMAC_TBQB_OFFSET (0x1C) /**< (GMAC_TBQB) Transmit Buffer Queue Base Address Register Offset */ 499 500 #define GMAC_TBQB_ADDR_Pos 2 /**< (GMAC_TBQB) Transmit Buffer Queue Base Address Position */ 501 #define GMAC_TBQB_ADDR_Msk (_U_(0x3FFFFFFF) << GMAC_TBQB_ADDR_Pos) /**< (GMAC_TBQB) Transmit Buffer Queue Base Address Mask */ 502 #define GMAC_TBQB_ADDR(value) (GMAC_TBQB_ADDR_Msk & ((value) << GMAC_TBQB_ADDR_Pos)) 503 #define GMAC_TBQB_MASK _U_(0xFFFFFFFC) /**< \deprecated (GMAC_TBQB) Register MASK (Use GMAC_TBQB_Msk instead) */ 504 #define GMAC_TBQB_Msk _U_(0xFFFFFFFC) /**< (GMAC_TBQB) Register Mask */ 505 506 507 /* -------- GMAC_RSR : (GMAC Offset: 0x20) (R/W 32) Receive Status Register -------- */ 508 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 509 #if COMPONENT_TYPEDEF_STYLE == 'N' 510 typedef union { 511 struct { 512 uint32_t BNA:1; /**< bit: 0 Buffer Not Available */ 513 uint32_t REC:1; /**< bit: 1 Frame Received */ 514 uint32_t RXOVR:1; /**< bit: 2 Receive Overrun */ 515 uint32_t HNO:1; /**< bit: 3 HRESP Not OK */ 516 uint32_t :28; /**< bit: 4..31 Reserved */ 517 } bit; /**< Structure used for bit access */ 518 uint32_t reg; /**< Type used for register access */ 519 } GMAC_RSR_Type; 520 #endif 521 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 522 523 #define GMAC_RSR_OFFSET (0x20) /**< (GMAC_RSR) Receive Status Register Offset */ 524 525 #define GMAC_RSR_BNA_Pos 0 /**< (GMAC_RSR) Buffer Not Available Position */ 526 #define GMAC_RSR_BNA_Msk (_U_(0x1) << GMAC_RSR_BNA_Pos) /**< (GMAC_RSR) Buffer Not Available Mask */ 527 #define GMAC_RSR_BNA GMAC_RSR_BNA_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_RSR_BNA_Msk instead */ 528 #define GMAC_RSR_REC_Pos 1 /**< (GMAC_RSR) Frame Received Position */ 529 #define GMAC_RSR_REC_Msk (_U_(0x1) << GMAC_RSR_REC_Pos) /**< (GMAC_RSR) Frame Received Mask */ 530 #define GMAC_RSR_REC GMAC_RSR_REC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_RSR_REC_Msk instead */ 531 #define GMAC_RSR_RXOVR_Pos 2 /**< (GMAC_RSR) Receive Overrun Position */ 532 #define GMAC_RSR_RXOVR_Msk (_U_(0x1) << GMAC_RSR_RXOVR_Pos) /**< (GMAC_RSR) Receive Overrun Mask */ 533 #define GMAC_RSR_RXOVR GMAC_RSR_RXOVR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_RSR_RXOVR_Msk instead */ 534 #define GMAC_RSR_HNO_Pos 3 /**< (GMAC_RSR) HRESP Not OK Position */ 535 #define GMAC_RSR_HNO_Msk (_U_(0x1) << GMAC_RSR_HNO_Pos) /**< (GMAC_RSR) HRESP Not OK Mask */ 536 #define GMAC_RSR_HNO GMAC_RSR_HNO_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_RSR_HNO_Msk instead */ 537 #define GMAC_RSR_MASK _U_(0x0F) /**< \deprecated (GMAC_RSR) Register MASK (Use GMAC_RSR_Msk instead) */ 538 #define GMAC_RSR_Msk _U_(0x0F) /**< (GMAC_RSR) Register Mask */ 539 540 541 /* -------- GMAC_ISR : (GMAC Offset: 0x24) (R/ 32) Interrupt Status Register -------- */ 542 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 543 #if COMPONENT_TYPEDEF_STYLE == 'N' 544 typedef union { 545 struct { 546 uint32_t MFS:1; /**< bit: 0 Management Frame Sent */ 547 uint32_t RCOMP:1; /**< bit: 1 Receive Complete */ 548 uint32_t RXUBR:1; /**< bit: 2 RX Used Bit Read */ 549 uint32_t TXUBR:1; /**< bit: 3 TX Used Bit Read */ 550 uint32_t TUR:1; /**< bit: 4 Transmit Underrun */ 551 uint32_t RLEX:1; /**< bit: 5 Retry Limit Exceeded */ 552 uint32_t TFC:1; /**< bit: 6 Transmit Frame Corruption Due to AHB Error */ 553 uint32_t TCOMP:1; /**< bit: 7 Transmit Complete */ 554 uint32_t :2; /**< bit: 8..9 Reserved */ 555 uint32_t ROVR:1; /**< bit: 10 Receive Overrun */ 556 uint32_t HRESP:1; /**< bit: 11 HRESP Not OK */ 557 uint32_t PFNZ:1; /**< bit: 12 Pause Frame with Non-zero Pause Quantum Received */ 558 uint32_t PTZ:1; /**< bit: 13 Pause Time Zero */ 559 uint32_t PFTR:1; /**< bit: 14 Pause Frame Transmitted */ 560 uint32_t :3; /**< bit: 15..17 Reserved */ 561 uint32_t DRQFR:1; /**< bit: 18 PTP Delay Request Frame Received */ 562 uint32_t SFR:1; /**< bit: 19 PTP Sync Frame Received */ 563 uint32_t DRQFT:1; /**< bit: 20 PTP Delay Request Frame Transmitted */ 564 uint32_t SFT:1; /**< bit: 21 PTP Sync Frame Transmitted */ 565 uint32_t PDRQFR:1; /**< bit: 22 PDelay Request Frame Received */ 566 uint32_t PDRSFR:1; /**< bit: 23 PDelay Response Frame Received */ 567 uint32_t PDRQFT:1; /**< bit: 24 PDelay Request Frame Transmitted */ 568 uint32_t PDRSFT:1; /**< bit: 25 PDelay Response Frame Transmitted */ 569 uint32_t SRI:1; /**< bit: 26 TSU Seconds Register Increment */ 570 uint32_t :1; /**< bit: 27 Reserved */ 571 uint32_t WOL:1; /**< bit: 28 Wake On LAN */ 572 uint32_t :3; /**< bit: 29..31 Reserved */ 573 } bit; /**< Structure used for bit access */ 574 uint32_t reg; /**< Type used for register access */ 575 } GMAC_ISR_Type; 576 #endif 577 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 578 579 #define GMAC_ISR_OFFSET (0x24) /**< (GMAC_ISR) Interrupt Status Register Offset */ 580 581 #define GMAC_ISR_MFS_Pos 0 /**< (GMAC_ISR) Management Frame Sent Position */ 582 #define GMAC_ISR_MFS_Msk (_U_(0x1) << GMAC_ISR_MFS_Pos) /**< (GMAC_ISR) Management Frame Sent Mask */ 583 #define GMAC_ISR_MFS GMAC_ISR_MFS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISR_MFS_Msk instead */ 584 #define GMAC_ISR_RCOMP_Pos 1 /**< (GMAC_ISR) Receive Complete Position */ 585 #define GMAC_ISR_RCOMP_Msk (_U_(0x1) << GMAC_ISR_RCOMP_Pos) /**< (GMAC_ISR) Receive Complete Mask */ 586 #define GMAC_ISR_RCOMP GMAC_ISR_RCOMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISR_RCOMP_Msk instead */ 587 #define GMAC_ISR_RXUBR_Pos 2 /**< (GMAC_ISR) RX Used Bit Read Position */ 588 #define GMAC_ISR_RXUBR_Msk (_U_(0x1) << GMAC_ISR_RXUBR_Pos) /**< (GMAC_ISR) RX Used Bit Read Mask */ 589 #define GMAC_ISR_RXUBR GMAC_ISR_RXUBR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISR_RXUBR_Msk instead */ 590 #define GMAC_ISR_TXUBR_Pos 3 /**< (GMAC_ISR) TX Used Bit Read Position */ 591 #define GMAC_ISR_TXUBR_Msk (_U_(0x1) << GMAC_ISR_TXUBR_Pos) /**< (GMAC_ISR) TX Used Bit Read Mask */ 592 #define GMAC_ISR_TXUBR GMAC_ISR_TXUBR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISR_TXUBR_Msk instead */ 593 #define GMAC_ISR_TUR_Pos 4 /**< (GMAC_ISR) Transmit Underrun Position */ 594 #define GMAC_ISR_TUR_Msk (_U_(0x1) << GMAC_ISR_TUR_Pos) /**< (GMAC_ISR) Transmit Underrun Mask */ 595 #define GMAC_ISR_TUR GMAC_ISR_TUR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISR_TUR_Msk instead */ 596 #define GMAC_ISR_RLEX_Pos 5 /**< (GMAC_ISR) Retry Limit Exceeded Position */ 597 #define GMAC_ISR_RLEX_Msk (_U_(0x1) << GMAC_ISR_RLEX_Pos) /**< (GMAC_ISR) Retry Limit Exceeded Mask */ 598 #define GMAC_ISR_RLEX GMAC_ISR_RLEX_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISR_RLEX_Msk instead */ 599 #define GMAC_ISR_TFC_Pos 6 /**< (GMAC_ISR) Transmit Frame Corruption Due to AHB Error Position */ 600 #define GMAC_ISR_TFC_Msk (_U_(0x1) << GMAC_ISR_TFC_Pos) /**< (GMAC_ISR) Transmit Frame Corruption Due to AHB Error Mask */ 601 #define GMAC_ISR_TFC GMAC_ISR_TFC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISR_TFC_Msk instead */ 602 #define GMAC_ISR_TCOMP_Pos 7 /**< (GMAC_ISR) Transmit Complete Position */ 603 #define GMAC_ISR_TCOMP_Msk (_U_(0x1) << GMAC_ISR_TCOMP_Pos) /**< (GMAC_ISR) Transmit Complete Mask */ 604 #define GMAC_ISR_TCOMP GMAC_ISR_TCOMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISR_TCOMP_Msk instead */ 605 #define GMAC_ISR_ROVR_Pos 10 /**< (GMAC_ISR) Receive Overrun Position */ 606 #define GMAC_ISR_ROVR_Msk (_U_(0x1) << GMAC_ISR_ROVR_Pos) /**< (GMAC_ISR) Receive Overrun Mask */ 607 #define GMAC_ISR_ROVR GMAC_ISR_ROVR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISR_ROVR_Msk instead */ 608 #define GMAC_ISR_HRESP_Pos 11 /**< (GMAC_ISR) HRESP Not OK Position */ 609 #define GMAC_ISR_HRESP_Msk (_U_(0x1) << GMAC_ISR_HRESP_Pos) /**< (GMAC_ISR) HRESP Not OK Mask */ 610 #define GMAC_ISR_HRESP GMAC_ISR_HRESP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISR_HRESP_Msk instead */ 611 #define GMAC_ISR_PFNZ_Pos 12 /**< (GMAC_ISR) Pause Frame with Non-zero Pause Quantum Received Position */ 612 #define GMAC_ISR_PFNZ_Msk (_U_(0x1) << GMAC_ISR_PFNZ_Pos) /**< (GMAC_ISR) Pause Frame with Non-zero Pause Quantum Received Mask */ 613 #define GMAC_ISR_PFNZ GMAC_ISR_PFNZ_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISR_PFNZ_Msk instead */ 614 #define GMAC_ISR_PTZ_Pos 13 /**< (GMAC_ISR) Pause Time Zero Position */ 615 #define GMAC_ISR_PTZ_Msk (_U_(0x1) << GMAC_ISR_PTZ_Pos) /**< (GMAC_ISR) Pause Time Zero Mask */ 616 #define GMAC_ISR_PTZ GMAC_ISR_PTZ_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISR_PTZ_Msk instead */ 617 #define GMAC_ISR_PFTR_Pos 14 /**< (GMAC_ISR) Pause Frame Transmitted Position */ 618 #define GMAC_ISR_PFTR_Msk (_U_(0x1) << GMAC_ISR_PFTR_Pos) /**< (GMAC_ISR) Pause Frame Transmitted Mask */ 619 #define GMAC_ISR_PFTR GMAC_ISR_PFTR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISR_PFTR_Msk instead */ 620 #define GMAC_ISR_DRQFR_Pos 18 /**< (GMAC_ISR) PTP Delay Request Frame Received Position */ 621 #define GMAC_ISR_DRQFR_Msk (_U_(0x1) << GMAC_ISR_DRQFR_Pos) /**< (GMAC_ISR) PTP Delay Request Frame Received Mask */ 622 #define GMAC_ISR_DRQFR GMAC_ISR_DRQFR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISR_DRQFR_Msk instead */ 623 #define GMAC_ISR_SFR_Pos 19 /**< (GMAC_ISR) PTP Sync Frame Received Position */ 624 #define GMAC_ISR_SFR_Msk (_U_(0x1) << GMAC_ISR_SFR_Pos) /**< (GMAC_ISR) PTP Sync Frame Received Mask */ 625 #define GMAC_ISR_SFR GMAC_ISR_SFR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISR_SFR_Msk instead */ 626 #define GMAC_ISR_DRQFT_Pos 20 /**< (GMAC_ISR) PTP Delay Request Frame Transmitted Position */ 627 #define GMAC_ISR_DRQFT_Msk (_U_(0x1) << GMAC_ISR_DRQFT_Pos) /**< (GMAC_ISR) PTP Delay Request Frame Transmitted Mask */ 628 #define GMAC_ISR_DRQFT GMAC_ISR_DRQFT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISR_DRQFT_Msk instead */ 629 #define GMAC_ISR_SFT_Pos 21 /**< (GMAC_ISR) PTP Sync Frame Transmitted Position */ 630 #define GMAC_ISR_SFT_Msk (_U_(0x1) << GMAC_ISR_SFT_Pos) /**< (GMAC_ISR) PTP Sync Frame Transmitted Mask */ 631 #define GMAC_ISR_SFT GMAC_ISR_SFT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISR_SFT_Msk instead */ 632 #define GMAC_ISR_PDRQFR_Pos 22 /**< (GMAC_ISR) PDelay Request Frame Received Position */ 633 #define GMAC_ISR_PDRQFR_Msk (_U_(0x1) << GMAC_ISR_PDRQFR_Pos) /**< (GMAC_ISR) PDelay Request Frame Received Mask */ 634 #define GMAC_ISR_PDRQFR GMAC_ISR_PDRQFR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISR_PDRQFR_Msk instead */ 635 #define GMAC_ISR_PDRSFR_Pos 23 /**< (GMAC_ISR) PDelay Response Frame Received Position */ 636 #define GMAC_ISR_PDRSFR_Msk (_U_(0x1) << GMAC_ISR_PDRSFR_Pos) /**< (GMAC_ISR) PDelay Response Frame Received Mask */ 637 #define GMAC_ISR_PDRSFR GMAC_ISR_PDRSFR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISR_PDRSFR_Msk instead */ 638 #define GMAC_ISR_PDRQFT_Pos 24 /**< (GMAC_ISR) PDelay Request Frame Transmitted Position */ 639 #define GMAC_ISR_PDRQFT_Msk (_U_(0x1) << GMAC_ISR_PDRQFT_Pos) /**< (GMAC_ISR) PDelay Request Frame Transmitted Mask */ 640 #define GMAC_ISR_PDRQFT GMAC_ISR_PDRQFT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISR_PDRQFT_Msk instead */ 641 #define GMAC_ISR_PDRSFT_Pos 25 /**< (GMAC_ISR) PDelay Response Frame Transmitted Position */ 642 #define GMAC_ISR_PDRSFT_Msk (_U_(0x1) << GMAC_ISR_PDRSFT_Pos) /**< (GMAC_ISR) PDelay Response Frame Transmitted Mask */ 643 #define GMAC_ISR_PDRSFT GMAC_ISR_PDRSFT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISR_PDRSFT_Msk instead */ 644 #define GMAC_ISR_SRI_Pos 26 /**< (GMAC_ISR) TSU Seconds Register Increment Position */ 645 #define GMAC_ISR_SRI_Msk (_U_(0x1) << GMAC_ISR_SRI_Pos) /**< (GMAC_ISR) TSU Seconds Register Increment Mask */ 646 #define GMAC_ISR_SRI GMAC_ISR_SRI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISR_SRI_Msk instead */ 647 #define GMAC_ISR_WOL_Pos 28 /**< (GMAC_ISR) Wake On LAN Position */ 648 #define GMAC_ISR_WOL_Msk (_U_(0x1) << GMAC_ISR_WOL_Pos) /**< (GMAC_ISR) Wake On LAN Mask */ 649 #define GMAC_ISR_WOL GMAC_ISR_WOL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISR_WOL_Msk instead */ 650 #define GMAC_ISR_MASK _U_(0x17FC7CFF) /**< \deprecated (GMAC_ISR) Register MASK (Use GMAC_ISR_Msk instead) */ 651 #define GMAC_ISR_Msk _U_(0x17FC7CFF) /**< (GMAC_ISR) Register Mask */ 652 653 654 /* -------- GMAC_IER : (GMAC Offset: 0x28) (/W 32) Interrupt Enable Register -------- */ 655 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 656 #if COMPONENT_TYPEDEF_STYLE == 'N' 657 typedef union { 658 struct { 659 uint32_t MFS:1; /**< bit: 0 Management Frame Sent */ 660 uint32_t RCOMP:1; /**< bit: 1 Receive Complete */ 661 uint32_t RXUBR:1; /**< bit: 2 RX Used Bit Read */ 662 uint32_t TXUBR:1; /**< bit: 3 TX Used Bit Read */ 663 uint32_t TUR:1; /**< bit: 4 Transmit Underrun */ 664 uint32_t RLEX:1; /**< bit: 5 Retry Limit Exceeded or Late Collision */ 665 uint32_t TFC:1; /**< bit: 6 Transmit Frame Corruption Due to AHB Error */ 666 uint32_t TCOMP:1; /**< bit: 7 Transmit Complete */ 667 uint32_t :2; /**< bit: 8..9 Reserved */ 668 uint32_t ROVR:1; /**< bit: 10 Receive Overrun */ 669 uint32_t HRESP:1; /**< bit: 11 HRESP Not OK */ 670 uint32_t PFNZ:1; /**< bit: 12 Pause Frame with Non-zero Pause Quantum Received */ 671 uint32_t PTZ:1; /**< bit: 13 Pause Time Zero */ 672 uint32_t PFTR:1; /**< bit: 14 Pause Frame Transmitted */ 673 uint32_t EXINT:1; /**< bit: 15 External Interrupt */ 674 uint32_t :2; /**< bit: 16..17 Reserved */ 675 uint32_t DRQFR:1; /**< bit: 18 PTP Delay Request Frame Received */ 676 uint32_t SFR:1; /**< bit: 19 PTP Sync Frame Received */ 677 uint32_t DRQFT:1; /**< bit: 20 PTP Delay Request Frame Transmitted */ 678 uint32_t SFT:1; /**< bit: 21 PTP Sync Frame Transmitted */ 679 uint32_t PDRQFR:1; /**< bit: 22 PDelay Request Frame Received */ 680 uint32_t PDRSFR:1; /**< bit: 23 PDelay Response Frame Received */ 681 uint32_t PDRQFT:1; /**< bit: 24 PDelay Request Frame Transmitted */ 682 uint32_t PDRSFT:1; /**< bit: 25 PDelay Response Frame Transmitted */ 683 uint32_t SRI:1; /**< bit: 26 TSU Seconds Register Increment */ 684 uint32_t RXLPISBC:1; /**< bit: 27 Enable RX LPI Indication */ 685 uint32_t WOL:1; /**< bit: 28 Wake On LAN */ 686 uint32_t TSUTIMCOMP:1; /**< bit: 29 TSU Timer Comparison */ 687 uint32_t :2; /**< bit: 30..31 Reserved */ 688 } bit; /**< Structure used for bit access */ 689 uint32_t reg; /**< Type used for register access */ 690 } GMAC_IER_Type; 691 #endif 692 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 693 694 #define GMAC_IER_OFFSET (0x28) /**< (GMAC_IER) Interrupt Enable Register Offset */ 695 696 #define GMAC_IER_MFS_Pos 0 /**< (GMAC_IER) Management Frame Sent Position */ 697 #define GMAC_IER_MFS_Msk (_U_(0x1) << GMAC_IER_MFS_Pos) /**< (GMAC_IER) Management Frame Sent Mask */ 698 #define GMAC_IER_MFS GMAC_IER_MFS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IER_MFS_Msk instead */ 699 #define GMAC_IER_RCOMP_Pos 1 /**< (GMAC_IER) Receive Complete Position */ 700 #define GMAC_IER_RCOMP_Msk (_U_(0x1) << GMAC_IER_RCOMP_Pos) /**< (GMAC_IER) Receive Complete Mask */ 701 #define GMAC_IER_RCOMP GMAC_IER_RCOMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IER_RCOMP_Msk instead */ 702 #define GMAC_IER_RXUBR_Pos 2 /**< (GMAC_IER) RX Used Bit Read Position */ 703 #define GMAC_IER_RXUBR_Msk (_U_(0x1) << GMAC_IER_RXUBR_Pos) /**< (GMAC_IER) RX Used Bit Read Mask */ 704 #define GMAC_IER_RXUBR GMAC_IER_RXUBR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IER_RXUBR_Msk instead */ 705 #define GMAC_IER_TXUBR_Pos 3 /**< (GMAC_IER) TX Used Bit Read Position */ 706 #define GMAC_IER_TXUBR_Msk (_U_(0x1) << GMAC_IER_TXUBR_Pos) /**< (GMAC_IER) TX Used Bit Read Mask */ 707 #define GMAC_IER_TXUBR GMAC_IER_TXUBR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IER_TXUBR_Msk instead */ 708 #define GMAC_IER_TUR_Pos 4 /**< (GMAC_IER) Transmit Underrun Position */ 709 #define GMAC_IER_TUR_Msk (_U_(0x1) << GMAC_IER_TUR_Pos) /**< (GMAC_IER) Transmit Underrun Mask */ 710 #define GMAC_IER_TUR GMAC_IER_TUR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IER_TUR_Msk instead */ 711 #define GMAC_IER_RLEX_Pos 5 /**< (GMAC_IER) Retry Limit Exceeded or Late Collision Position */ 712 #define GMAC_IER_RLEX_Msk (_U_(0x1) << GMAC_IER_RLEX_Pos) /**< (GMAC_IER) Retry Limit Exceeded or Late Collision Mask */ 713 #define GMAC_IER_RLEX GMAC_IER_RLEX_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IER_RLEX_Msk instead */ 714 #define GMAC_IER_TFC_Pos 6 /**< (GMAC_IER) Transmit Frame Corruption Due to AHB Error Position */ 715 #define GMAC_IER_TFC_Msk (_U_(0x1) << GMAC_IER_TFC_Pos) /**< (GMAC_IER) Transmit Frame Corruption Due to AHB Error Mask */ 716 #define GMAC_IER_TFC GMAC_IER_TFC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IER_TFC_Msk instead */ 717 #define GMAC_IER_TCOMP_Pos 7 /**< (GMAC_IER) Transmit Complete Position */ 718 #define GMAC_IER_TCOMP_Msk (_U_(0x1) << GMAC_IER_TCOMP_Pos) /**< (GMAC_IER) Transmit Complete Mask */ 719 #define GMAC_IER_TCOMP GMAC_IER_TCOMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IER_TCOMP_Msk instead */ 720 #define GMAC_IER_ROVR_Pos 10 /**< (GMAC_IER) Receive Overrun Position */ 721 #define GMAC_IER_ROVR_Msk (_U_(0x1) << GMAC_IER_ROVR_Pos) /**< (GMAC_IER) Receive Overrun Mask */ 722 #define GMAC_IER_ROVR GMAC_IER_ROVR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IER_ROVR_Msk instead */ 723 #define GMAC_IER_HRESP_Pos 11 /**< (GMAC_IER) HRESP Not OK Position */ 724 #define GMAC_IER_HRESP_Msk (_U_(0x1) << GMAC_IER_HRESP_Pos) /**< (GMAC_IER) HRESP Not OK Mask */ 725 #define GMAC_IER_HRESP GMAC_IER_HRESP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IER_HRESP_Msk instead */ 726 #define GMAC_IER_PFNZ_Pos 12 /**< (GMAC_IER) Pause Frame with Non-zero Pause Quantum Received Position */ 727 #define GMAC_IER_PFNZ_Msk (_U_(0x1) << GMAC_IER_PFNZ_Pos) /**< (GMAC_IER) Pause Frame with Non-zero Pause Quantum Received Mask */ 728 #define GMAC_IER_PFNZ GMAC_IER_PFNZ_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IER_PFNZ_Msk instead */ 729 #define GMAC_IER_PTZ_Pos 13 /**< (GMAC_IER) Pause Time Zero Position */ 730 #define GMAC_IER_PTZ_Msk (_U_(0x1) << GMAC_IER_PTZ_Pos) /**< (GMAC_IER) Pause Time Zero Mask */ 731 #define GMAC_IER_PTZ GMAC_IER_PTZ_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IER_PTZ_Msk instead */ 732 #define GMAC_IER_PFTR_Pos 14 /**< (GMAC_IER) Pause Frame Transmitted Position */ 733 #define GMAC_IER_PFTR_Msk (_U_(0x1) << GMAC_IER_PFTR_Pos) /**< (GMAC_IER) Pause Frame Transmitted Mask */ 734 #define GMAC_IER_PFTR GMAC_IER_PFTR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IER_PFTR_Msk instead */ 735 #define GMAC_IER_EXINT_Pos 15 /**< (GMAC_IER) External Interrupt Position */ 736 #define GMAC_IER_EXINT_Msk (_U_(0x1) << GMAC_IER_EXINT_Pos) /**< (GMAC_IER) External Interrupt Mask */ 737 #define GMAC_IER_EXINT GMAC_IER_EXINT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IER_EXINT_Msk instead */ 738 #define GMAC_IER_DRQFR_Pos 18 /**< (GMAC_IER) PTP Delay Request Frame Received Position */ 739 #define GMAC_IER_DRQFR_Msk (_U_(0x1) << GMAC_IER_DRQFR_Pos) /**< (GMAC_IER) PTP Delay Request Frame Received Mask */ 740 #define GMAC_IER_DRQFR GMAC_IER_DRQFR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IER_DRQFR_Msk instead */ 741 #define GMAC_IER_SFR_Pos 19 /**< (GMAC_IER) PTP Sync Frame Received Position */ 742 #define GMAC_IER_SFR_Msk (_U_(0x1) << GMAC_IER_SFR_Pos) /**< (GMAC_IER) PTP Sync Frame Received Mask */ 743 #define GMAC_IER_SFR GMAC_IER_SFR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IER_SFR_Msk instead */ 744 #define GMAC_IER_DRQFT_Pos 20 /**< (GMAC_IER) PTP Delay Request Frame Transmitted Position */ 745 #define GMAC_IER_DRQFT_Msk (_U_(0x1) << GMAC_IER_DRQFT_Pos) /**< (GMAC_IER) PTP Delay Request Frame Transmitted Mask */ 746 #define GMAC_IER_DRQFT GMAC_IER_DRQFT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IER_DRQFT_Msk instead */ 747 #define GMAC_IER_SFT_Pos 21 /**< (GMAC_IER) PTP Sync Frame Transmitted Position */ 748 #define GMAC_IER_SFT_Msk (_U_(0x1) << GMAC_IER_SFT_Pos) /**< (GMAC_IER) PTP Sync Frame Transmitted Mask */ 749 #define GMAC_IER_SFT GMAC_IER_SFT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IER_SFT_Msk instead */ 750 #define GMAC_IER_PDRQFR_Pos 22 /**< (GMAC_IER) PDelay Request Frame Received Position */ 751 #define GMAC_IER_PDRQFR_Msk (_U_(0x1) << GMAC_IER_PDRQFR_Pos) /**< (GMAC_IER) PDelay Request Frame Received Mask */ 752 #define GMAC_IER_PDRQFR GMAC_IER_PDRQFR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IER_PDRQFR_Msk instead */ 753 #define GMAC_IER_PDRSFR_Pos 23 /**< (GMAC_IER) PDelay Response Frame Received Position */ 754 #define GMAC_IER_PDRSFR_Msk (_U_(0x1) << GMAC_IER_PDRSFR_Pos) /**< (GMAC_IER) PDelay Response Frame Received Mask */ 755 #define GMAC_IER_PDRSFR GMAC_IER_PDRSFR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IER_PDRSFR_Msk instead */ 756 #define GMAC_IER_PDRQFT_Pos 24 /**< (GMAC_IER) PDelay Request Frame Transmitted Position */ 757 #define GMAC_IER_PDRQFT_Msk (_U_(0x1) << GMAC_IER_PDRQFT_Pos) /**< (GMAC_IER) PDelay Request Frame Transmitted Mask */ 758 #define GMAC_IER_PDRQFT GMAC_IER_PDRQFT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IER_PDRQFT_Msk instead */ 759 #define GMAC_IER_PDRSFT_Pos 25 /**< (GMAC_IER) PDelay Response Frame Transmitted Position */ 760 #define GMAC_IER_PDRSFT_Msk (_U_(0x1) << GMAC_IER_PDRSFT_Pos) /**< (GMAC_IER) PDelay Response Frame Transmitted Mask */ 761 #define GMAC_IER_PDRSFT GMAC_IER_PDRSFT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IER_PDRSFT_Msk instead */ 762 #define GMAC_IER_SRI_Pos 26 /**< (GMAC_IER) TSU Seconds Register Increment Position */ 763 #define GMAC_IER_SRI_Msk (_U_(0x1) << GMAC_IER_SRI_Pos) /**< (GMAC_IER) TSU Seconds Register Increment Mask */ 764 #define GMAC_IER_SRI GMAC_IER_SRI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IER_SRI_Msk instead */ 765 #define GMAC_IER_RXLPISBC_Pos 27 /**< (GMAC_IER) Enable RX LPI Indication Position */ 766 #define GMAC_IER_RXLPISBC_Msk (_U_(0x1) << GMAC_IER_RXLPISBC_Pos) /**< (GMAC_IER) Enable RX LPI Indication Mask */ 767 #define GMAC_IER_RXLPISBC GMAC_IER_RXLPISBC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IER_RXLPISBC_Msk instead */ 768 #define GMAC_IER_WOL_Pos 28 /**< (GMAC_IER) Wake On LAN Position */ 769 #define GMAC_IER_WOL_Msk (_U_(0x1) << GMAC_IER_WOL_Pos) /**< (GMAC_IER) Wake On LAN Mask */ 770 #define GMAC_IER_WOL GMAC_IER_WOL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IER_WOL_Msk instead */ 771 #define GMAC_IER_TSUTIMCOMP_Pos 29 /**< (GMAC_IER) TSU Timer Comparison Position */ 772 #define GMAC_IER_TSUTIMCOMP_Msk (_U_(0x1) << GMAC_IER_TSUTIMCOMP_Pos) /**< (GMAC_IER) TSU Timer Comparison Mask */ 773 #define GMAC_IER_TSUTIMCOMP GMAC_IER_TSUTIMCOMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IER_TSUTIMCOMP_Msk instead */ 774 #define GMAC_IER_MASK _U_(0x3FFCFCFF) /**< \deprecated (GMAC_IER) Register MASK (Use GMAC_IER_Msk instead) */ 775 #define GMAC_IER_Msk _U_(0x3FFCFCFF) /**< (GMAC_IER) Register Mask */ 776 777 778 /* -------- GMAC_IDR : (GMAC Offset: 0x2c) (/W 32) Interrupt Disable Register -------- */ 779 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 780 #if COMPONENT_TYPEDEF_STYLE == 'N' 781 typedef union { 782 struct { 783 uint32_t MFS:1; /**< bit: 0 Management Frame Sent */ 784 uint32_t RCOMP:1; /**< bit: 1 Receive Complete */ 785 uint32_t RXUBR:1; /**< bit: 2 RX Used Bit Read */ 786 uint32_t TXUBR:1; /**< bit: 3 TX Used Bit Read */ 787 uint32_t TUR:1; /**< bit: 4 Transmit Underrun */ 788 uint32_t RLEX:1; /**< bit: 5 Retry Limit Exceeded or Late Collision */ 789 uint32_t TFC:1; /**< bit: 6 Transmit Frame Corruption Due to AHB Error */ 790 uint32_t TCOMP:1; /**< bit: 7 Transmit Complete */ 791 uint32_t :2; /**< bit: 8..9 Reserved */ 792 uint32_t ROVR:1; /**< bit: 10 Receive Overrun */ 793 uint32_t HRESP:1; /**< bit: 11 HRESP Not OK */ 794 uint32_t PFNZ:1; /**< bit: 12 Pause Frame with Non-zero Pause Quantum Received */ 795 uint32_t PTZ:1; /**< bit: 13 Pause Time Zero */ 796 uint32_t PFTR:1; /**< bit: 14 Pause Frame Transmitted */ 797 uint32_t EXINT:1; /**< bit: 15 External Interrupt */ 798 uint32_t :2; /**< bit: 16..17 Reserved */ 799 uint32_t DRQFR:1; /**< bit: 18 PTP Delay Request Frame Received */ 800 uint32_t SFR:1; /**< bit: 19 PTP Sync Frame Received */ 801 uint32_t DRQFT:1; /**< bit: 20 PTP Delay Request Frame Transmitted */ 802 uint32_t SFT:1; /**< bit: 21 PTP Sync Frame Transmitted */ 803 uint32_t PDRQFR:1; /**< bit: 22 PDelay Request Frame Received */ 804 uint32_t PDRSFR:1; /**< bit: 23 PDelay Response Frame Received */ 805 uint32_t PDRQFT:1; /**< bit: 24 PDelay Request Frame Transmitted */ 806 uint32_t PDRSFT:1; /**< bit: 25 PDelay Response Frame Transmitted */ 807 uint32_t SRI:1; /**< bit: 26 TSU Seconds Register Increment */ 808 uint32_t RXLPISBC:1; /**< bit: 27 Enable RX LPI Indication */ 809 uint32_t WOL:1; /**< bit: 28 Wake On LAN */ 810 uint32_t TSUTIMCOMP:1; /**< bit: 29 TSU Timer Comparison */ 811 uint32_t :2; /**< bit: 30..31 Reserved */ 812 } bit; /**< Structure used for bit access */ 813 uint32_t reg; /**< Type used for register access */ 814 } GMAC_IDR_Type; 815 #endif 816 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 817 818 #define GMAC_IDR_OFFSET (0x2C) /**< (GMAC_IDR) Interrupt Disable Register Offset */ 819 820 #define GMAC_IDR_MFS_Pos 0 /**< (GMAC_IDR) Management Frame Sent Position */ 821 #define GMAC_IDR_MFS_Msk (_U_(0x1) << GMAC_IDR_MFS_Pos) /**< (GMAC_IDR) Management Frame Sent Mask */ 822 #define GMAC_IDR_MFS GMAC_IDR_MFS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDR_MFS_Msk instead */ 823 #define GMAC_IDR_RCOMP_Pos 1 /**< (GMAC_IDR) Receive Complete Position */ 824 #define GMAC_IDR_RCOMP_Msk (_U_(0x1) << GMAC_IDR_RCOMP_Pos) /**< (GMAC_IDR) Receive Complete Mask */ 825 #define GMAC_IDR_RCOMP GMAC_IDR_RCOMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDR_RCOMP_Msk instead */ 826 #define GMAC_IDR_RXUBR_Pos 2 /**< (GMAC_IDR) RX Used Bit Read Position */ 827 #define GMAC_IDR_RXUBR_Msk (_U_(0x1) << GMAC_IDR_RXUBR_Pos) /**< (GMAC_IDR) RX Used Bit Read Mask */ 828 #define GMAC_IDR_RXUBR GMAC_IDR_RXUBR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDR_RXUBR_Msk instead */ 829 #define GMAC_IDR_TXUBR_Pos 3 /**< (GMAC_IDR) TX Used Bit Read Position */ 830 #define GMAC_IDR_TXUBR_Msk (_U_(0x1) << GMAC_IDR_TXUBR_Pos) /**< (GMAC_IDR) TX Used Bit Read Mask */ 831 #define GMAC_IDR_TXUBR GMAC_IDR_TXUBR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDR_TXUBR_Msk instead */ 832 #define GMAC_IDR_TUR_Pos 4 /**< (GMAC_IDR) Transmit Underrun Position */ 833 #define GMAC_IDR_TUR_Msk (_U_(0x1) << GMAC_IDR_TUR_Pos) /**< (GMAC_IDR) Transmit Underrun Mask */ 834 #define GMAC_IDR_TUR GMAC_IDR_TUR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDR_TUR_Msk instead */ 835 #define GMAC_IDR_RLEX_Pos 5 /**< (GMAC_IDR) Retry Limit Exceeded or Late Collision Position */ 836 #define GMAC_IDR_RLEX_Msk (_U_(0x1) << GMAC_IDR_RLEX_Pos) /**< (GMAC_IDR) Retry Limit Exceeded or Late Collision Mask */ 837 #define GMAC_IDR_RLEX GMAC_IDR_RLEX_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDR_RLEX_Msk instead */ 838 #define GMAC_IDR_TFC_Pos 6 /**< (GMAC_IDR) Transmit Frame Corruption Due to AHB Error Position */ 839 #define GMAC_IDR_TFC_Msk (_U_(0x1) << GMAC_IDR_TFC_Pos) /**< (GMAC_IDR) Transmit Frame Corruption Due to AHB Error Mask */ 840 #define GMAC_IDR_TFC GMAC_IDR_TFC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDR_TFC_Msk instead */ 841 #define GMAC_IDR_TCOMP_Pos 7 /**< (GMAC_IDR) Transmit Complete Position */ 842 #define GMAC_IDR_TCOMP_Msk (_U_(0x1) << GMAC_IDR_TCOMP_Pos) /**< (GMAC_IDR) Transmit Complete Mask */ 843 #define GMAC_IDR_TCOMP GMAC_IDR_TCOMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDR_TCOMP_Msk instead */ 844 #define GMAC_IDR_ROVR_Pos 10 /**< (GMAC_IDR) Receive Overrun Position */ 845 #define GMAC_IDR_ROVR_Msk (_U_(0x1) << GMAC_IDR_ROVR_Pos) /**< (GMAC_IDR) Receive Overrun Mask */ 846 #define GMAC_IDR_ROVR GMAC_IDR_ROVR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDR_ROVR_Msk instead */ 847 #define GMAC_IDR_HRESP_Pos 11 /**< (GMAC_IDR) HRESP Not OK Position */ 848 #define GMAC_IDR_HRESP_Msk (_U_(0x1) << GMAC_IDR_HRESP_Pos) /**< (GMAC_IDR) HRESP Not OK Mask */ 849 #define GMAC_IDR_HRESP GMAC_IDR_HRESP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDR_HRESP_Msk instead */ 850 #define GMAC_IDR_PFNZ_Pos 12 /**< (GMAC_IDR) Pause Frame with Non-zero Pause Quantum Received Position */ 851 #define GMAC_IDR_PFNZ_Msk (_U_(0x1) << GMAC_IDR_PFNZ_Pos) /**< (GMAC_IDR) Pause Frame with Non-zero Pause Quantum Received Mask */ 852 #define GMAC_IDR_PFNZ GMAC_IDR_PFNZ_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDR_PFNZ_Msk instead */ 853 #define GMAC_IDR_PTZ_Pos 13 /**< (GMAC_IDR) Pause Time Zero Position */ 854 #define GMAC_IDR_PTZ_Msk (_U_(0x1) << GMAC_IDR_PTZ_Pos) /**< (GMAC_IDR) Pause Time Zero Mask */ 855 #define GMAC_IDR_PTZ GMAC_IDR_PTZ_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDR_PTZ_Msk instead */ 856 #define GMAC_IDR_PFTR_Pos 14 /**< (GMAC_IDR) Pause Frame Transmitted Position */ 857 #define GMAC_IDR_PFTR_Msk (_U_(0x1) << GMAC_IDR_PFTR_Pos) /**< (GMAC_IDR) Pause Frame Transmitted Mask */ 858 #define GMAC_IDR_PFTR GMAC_IDR_PFTR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDR_PFTR_Msk instead */ 859 #define GMAC_IDR_EXINT_Pos 15 /**< (GMAC_IDR) External Interrupt Position */ 860 #define GMAC_IDR_EXINT_Msk (_U_(0x1) << GMAC_IDR_EXINT_Pos) /**< (GMAC_IDR) External Interrupt Mask */ 861 #define GMAC_IDR_EXINT GMAC_IDR_EXINT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDR_EXINT_Msk instead */ 862 #define GMAC_IDR_DRQFR_Pos 18 /**< (GMAC_IDR) PTP Delay Request Frame Received Position */ 863 #define GMAC_IDR_DRQFR_Msk (_U_(0x1) << GMAC_IDR_DRQFR_Pos) /**< (GMAC_IDR) PTP Delay Request Frame Received Mask */ 864 #define GMAC_IDR_DRQFR GMAC_IDR_DRQFR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDR_DRQFR_Msk instead */ 865 #define GMAC_IDR_SFR_Pos 19 /**< (GMAC_IDR) PTP Sync Frame Received Position */ 866 #define GMAC_IDR_SFR_Msk (_U_(0x1) << GMAC_IDR_SFR_Pos) /**< (GMAC_IDR) PTP Sync Frame Received Mask */ 867 #define GMAC_IDR_SFR GMAC_IDR_SFR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDR_SFR_Msk instead */ 868 #define GMAC_IDR_DRQFT_Pos 20 /**< (GMAC_IDR) PTP Delay Request Frame Transmitted Position */ 869 #define GMAC_IDR_DRQFT_Msk (_U_(0x1) << GMAC_IDR_DRQFT_Pos) /**< (GMAC_IDR) PTP Delay Request Frame Transmitted Mask */ 870 #define GMAC_IDR_DRQFT GMAC_IDR_DRQFT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDR_DRQFT_Msk instead */ 871 #define GMAC_IDR_SFT_Pos 21 /**< (GMAC_IDR) PTP Sync Frame Transmitted Position */ 872 #define GMAC_IDR_SFT_Msk (_U_(0x1) << GMAC_IDR_SFT_Pos) /**< (GMAC_IDR) PTP Sync Frame Transmitted Mask */ 873 #define GMAC_IDR_SFT GMAC_IDR_SFT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDR_SFT_Msk instead */ 874 #define GMAC_IDR_PDRQFR_Pos 22 /**< (GMAC_IDR) PDelay Request Frame Received Position */ 875 #define GMAC_IDR_PDRQFR_Msk (_U_(0x1) << GMAC_IDR_PDRQFR_Pos) /**< (GMAC_IDR) PDelay Request Frame Received Mask */ 876 #define GMAC_IDR_PDRQFR GMAC_IDR_PDRQFR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDR_PDRQFR_Msk instead */ 877 #define GMAC_IDR_PDRSFR_Pos 23 /**< (GMAC_IDR) PDelay Response Frame Received Position */ 878 #define GMAC_IDR_PDRSFR_Msk (_U_(0x1) << GMAC_IDR_PDRSFR_Pos) /**< (GMAC_IDR) PDelay Response Frame Received Mask */ 879 #define GMAC_IDR_PDRSFR GMAC_IDR_PDRSFR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDR_PDRSFR_Msk instead */ 880 #define GMAC_IDR_PDRQFT_Pos 24 /**< (GMAC_IDR) PDelay Request Frame Transmitted Position */ 881 #define GMAC_IDR_PDRQFT_Msk (_U_(0x1) << GMAC_IDR_PDRQFT_Pos) /**< (GMAC_IDR) PDelay Request Frame Transmitted Mask */ 882 #define GMAC_IDR_PDRQFT GMAC_IDR_PDRQFT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDR_PDRQFT_Msk instead */ 883 #define GMAC_IDR_PDRSFT_Pos 25 /**< (GMAC_IDR) PDelay Response Frame Transmitted Position */ 884 #define GMAC_IDR_PDRSFT_Msk (_U_(0x1) << GMAC_IDR_PDRSFT_Pos) /**< (GMAC_IDR) PDelay Response Frame Transmitted Mask */ 885 #define GMAC_IDR_PDRSFT GMAC_IDR_PDRSFT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDR_PDRSFT_Msk instead */ 886 #define GMAC_IDR_SRI_Pos 26 /**< (GMAC_IDR) TSU Seconds Register Increment Position */ 887 #define GMAC_IDR_SRI_Msk (_U_(0x1) << GMAC_IDR_SRI_Pos) /**< (GMAC_IDR) TSU Seconds Register Increment Mask */ 888 #define GMAC_IDR_SRI GMAC_IDR_SRI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDR_SRI_Msk instead */ 889 #define GMAC_IDR_RXLPISBC_Pos 27 /**< (GMAC_IDR) Enable RX LPI Indication Position */ 890 #define GMAC_IDR_RXLPISBC_Msk (_U_(0x1) << GMAC_IDR_RXLPISBC_Pos) /**< (GMAC_IDR) Enable RX LPI Indication Mask */ 891 #define GMAC_IDR_RXLPISBC GMAC_IDR_RXLPISBC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDR_RXLPISBC_Msk instead */ 892 #define GMAC_IDR_WOL_Pos 28 /**< (GMAC_IDR) Wake On LAN Position */ 893 #define GMAC_IDR_WOL_Msk (_U_(0x1) << GMAC_IDR_WOL_Pos) /**< (GMAC_IDR) Wake On LAN Mask */ 894 #define GMAC_IDR_WOL GMAC_IDR_WOL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDR_WOL_Msk instead */ 895 #define GMAC_IDR_TSUTIMCOMP_Pos 29 /**< (GMAC_IDR) TSU Timer Comparison Position */ 896 #define GMAC_IDR_TSUTIMCOMP_Msk (_U_(0x1) << GMAC_IDR_TSUTIMCOMP_Pos) /**< (GMAC_IDR) TSU Timer Comparison Mask */ 897 #define GMAC_IDR_TSUTIMCOMP GMAC_IDR_TSUTIMCOMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDR_TSUTIMCOMP_Msk instead */ 898 #define GMAC_IDR_MASK _U_(0x3FFCFCFF) /**< \deprecated (GMAC_IDR) Register MASK (Use GMAC_IDR_Msk instead) */ 899 #define GMAC_IDR_Msk _U_(0x3FFCFCFF) /**< (GMAC_IDR) Register Mask */ 900 901 902 /* -------- GMAC_IMR : (GMAC Offset: 0x30) (R/W 32) Interrupt Mask Register -------- */ 903 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 904 #if COMPONENT_TYPEDEF_STYLE == 'N' 905 typedef union { 906 struct { 907 uint32_t MFS:1; /**< bit: 0 Management Frame Sent */ 908 uint32_t RCOMP:1; /**< bit: 1 Receive Complete */ 909 uint32_t RXUBR:1; /**< bit: 2 RX Used Bit Read */ 910 uint32_t TXUBR:1; /**< bit: 3 TX Used Bit Read */ 911 uint32_t TUR:1; /**< bit: 4 Transmit Underrun */ 912 uint32_t RLEX:1; /**< bit: 5 Retry Limit Exceeded */ 913 uint32_t TFC:1; /**< bit: 6 Transmit Frame Corruption Due to AHB Error */ 914 uint32_t TCOMP:1; /**< bit: 7 Transmit Complete */ 915 uint32_t :2; /**< bit: 8..9 Reserved */ 916 uint32_t ROVR:1; /**< bit: 10 Receive Overrun */ 917 uint32_t HRESP:1; /**< bit: 11 HRESP Not OK */ 918 uint32_t PFNZ:1; /**< bit: 12 Pause Frame with Non-zero Pause Quantum Received */ 919 uint32_t PTZ:1; /**< bit: 13 Pause Time Zero */ 920 uint32_t PFTR:1; /**< bit: 14 Pause Frame Transmitted */ 921 uint32_t EXINT:1; /**< bit: 15 External Interrupt */ 922 uint32_t :2; /**< bit: 16..17 Reserved */ 923 uint32_t DRQFR:1; /**< bit: 18 PTP Delay Request Frame Received */ 924 uint32_t SFR:1; /**< bit: 19 PTP Sync Frame Received */ 925 uint32_t DRQFT:1; /**< bit: 20 PTP Delay Request Frame Transmitted */ 926 uint32_t SFT:1; /**< bit: 21 PTP Sync Frame Transmitted */ 927 uint32_t PDRQFR:1; /**< bit: 22 PDelay Request Frame Received */ 928 uint32_t PDRSFR:1; /**< bit: 23 PDelay Response Frame Received */ 929 uint32_t PDRQFT:1; /**< bit: 24 PDelay Request Frame Transmitted */ 930 uint32_t PDRSFT:1; /**< bit: 25 PDelay Response Frame Transmitted */ 931 uint32_t SRI:1; /**< bit: 26 TSU Seconds Register Increment */ 932 uint32_t RXLPISBC:1; /**< bit: 27 Enable RX LPI Indication */ 933 uint32_t WOL:1; /**< bit: 28 Wake On LAN */ 934 uint32_t TSUTIMCOMP:1; /**< bit: 29 TSU Timer Comparison */ 935 uint32_t :2; /**< bit: 30..31 Reserved */ 936 } bit; /**< Structure used for bit access */ 937 uint32_t reg; /**< Type used for register access */ 938 } GMAC_IMR_Type; 939 #endif 940 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 941 942 #define GMAC_IMR_OFFSET (0x30) /**< (GMAC_IMR) Interrupt Mask Register Offset */ 943 944 #define GMAC_IMR_MFS_Pos 0 /**< (GMAC_IMR) Management Frame Sent Position */ 945 #define GMAC_IMR_MFS_Msk (_U_(0x1) << GMAC_IMR_MFS_Pos) /**< (GMAC_IMR) Management Frame Sent Mask */ 946 #define GMAC_IMR_MFS GMAC_IMR_MFS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMR_MFS_Msk instead */ 947 #define GMAC_IMR_RCOMP_Pos 1 /**< (GMAC_IMR) Receive Complete Position */ 948 #define GMAC_IMR_RCOMP_Msk (_U_(0x1) << GMAC_IMR_RCOMP_Pos) /**< (GMAC_IMR) Receive Complete Mask */ 949 #define GMAC_IMR_RCOMP GMAC_IMR_RCOMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMR_RCOMP_Msk instead */ 950 #define GMAC_IMR_RXUBR_Pos 2 /**< (GMAC_IMR) RX Used Bit Read Position */ 951 #define GMAC_IMR_RXUBR_Msk (_U_(0x1) << GMAC_IMR_RXUBR_Pos) /**< (GMAC_IMR) RX Used Bit Read Mask */ 952 #define GMAC_IMR_RXUBR GMAC_IMR_RXUBR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMR_RXUBR_Msk instead */ 953 #define GMAC_IMR_TXUBR_Pos 3 /**< (GMAC_IMR) TX Used Bit Read Position */ 954 #define GMAC_IMR_TXUBR_Msk (_U_(0x1) << GMAC_IMR_TXUBR_Pos) /**< (GMAC_IMR) TX Used Bit Read Mask */ 955 #define GMAC_IMR_TXUBR GMAC_IMR_TXUBR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMR_TXUBR_Msk instead */ 956 #define GMAC_IMR_TUR_Pos 4 /**< (GMAC_IMR) Transmit Underrun Position */ 957 #define GMAC_IMR_TUR_Msk (_U_(0x1) << GMAC_IMR_TUR_Pos) /**< (GMAC_IMR) Transmit Underrun Mask */ 958 #define GMAC_IMR_TUR GMAC_IMR_TUR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMR_TUR_Msk instead */ 959 #define GMAC_IMR_RLEX_Pos 5 /**< (GMAC_IMR) Retry Limit Exceeded Position */ 960 #define GMAC_IMR_RLEX_Msk (_U_(0x1) << GMAC_IMR_RLEX_Pos) /**< (GMAC_IMR) Retry Limit Exceeded Mask */ 961 #define GMAC_IMR_RLEX GMAC_IMR_RLEX_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMR_RLEX_Msk instead */ 962 #define GMAC_IMR_TFC_Pos 6 /**< (GMAC_IMR) Transmit Frame Corruption Due to AHB Error Position */ 963 #define GMAC_IMR_TFC_Msk (_U_(0x1) << GMAC_IMR_TFC_Pos) /**< (GMAC_IMR) Transmit Frame Corruption Due to AHB Error Mask */ 964 #define GMAC_IMR_TFC GMAC_IMR_TFC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMR_TFC_Msk instead */ 965 #define GMAC_IMR_TCOMP_Pos 7 /**< (GMAC_IMR) Transmit Complete Position */ 966 #define GMAC_IMR_TCOMP_Msk (_U_(0x1) << GMAC_IMR_TCOMP_Pos) /**< (GMAC_IMR) Transmit Complete Mask */ 967 #define GMAC_IMR_TCOMP GMAC_IMR_TCOMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMR_TCOMP_Msk instead */ 968 #define GMAC_IMR_ROVR_Pos 10 /**< (GMAC_IMR) Receive Overrun Position */ 969 #define GMAC_IMR_ROVR_Msk (_U_(0x1) << GMAC_IMR_ROVR_Pos) /**< (GMAC_IMR) Receive Overrun Mask */ 970 #define GMAC_IMR_ROVR GMAC_IMR_ROVR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMR_ROVR_Msk instead */ 971 #define GMAC_IMR_HRESP_Pos 11 /**< (GMAC_IMR) HRESP Not OK Position */ 972 #define GMAC_IMR_HRESP_Msk (_U_(0x1) << GMAC_IMR_HRESP_Pos) /**< (GMAC_IMR) HRESP Not OK Mask */ 973 #define GMAC_IMR_HRESP GMAC_IMR_HRESP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMR_HRESP_Msk instead */ 974 #define GMAC_IMR_PFNZ_Pos 12 /**< (GMAC_IMR) Pause Frame with Non-zero Pause Quantum Received Position */ 975 #define GMAC_IMR_PFNZ_Msk (_U_(0x1) << GMAC_IMR_PFNZ_Pos) /**< (GMAC_IMR) Pause Frame with Non-zero Pause Quantum Received Mask */ 976 #define GMAC_IMR_PFNZ GMAC_IMR_PFNZ_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMR_PFNZ_Msk instead */ 977 #define GMAC_IMR_PTZ_Pos 13 /**< (GMAC_IMR) Pause Time Zero Position */ 978 #define GMAC_IMR_PTZ_Msk (_U_(0x1) << GMAC_IMR_PTZ_Pos) /**< (GMAC_IMR) Pause Time Zero Mask */ 979 #define GMAC_IMR_PTZ GMAC_IMR_PTZ_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMR_PTZ_Msk instead */ 980 #define GMAC_IMR_PFTR_Pos 14 /**< (GMAC_IMR) Pause Frame Transmitted Position */ 981 #define GMAC_IMR_PFTR_Msk (_U_(0x1) << GMAC_IMR_PFTR_Pos) /**< (GMAC_IMR) Pause Frame Transmitted Mask */ 982 #define GMAC_IMR_PFTR GMAC_IMR_PFTR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMR_PFTR_Msk instead */ 983 #define GMAC_IMR_EXINT_Pos 15 /**< (GMAC_IMR) External Interrupt Position */ 984 #define GMAC_IMR_EXINT_Msk (_U_(0x1) << GMAC_IMR_EXINT_Pos) /**< (GMAC_IMR) External Interrupt Mask */ 985 #define GMAC_IMR_EXINT GMAC_IMR_EXINT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMR_EXINT_Msk instead */ 986 #define GMAC_IMR_DRQFR_Pos 18 /**< (GMAC_IMR) PTP Delay Request Frame Received Position */ 987 #define GMAC_IMR_DRQFR_Msk (_U_(0x1) << GMAC_IMR_DRQFR_Pos) /**< (GMAC_IMR) PTP Delay Request Frame Received Mask */ 988 #define GMAC_IMR_DRQFR GMAC_IMR_DRQFR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMR_DRQFR_Msk instead */ 989 #define GMAC_IMR_SFR_Pos 19 /**< (GMAC_IMR) PTP Sync Frame Received Position */ 990 #define GMAC_IMR_SFR_Msk (_U_(0x1) << GMAC_IMR_SFR_Pos) /**< (GMAC_IMR) PTP Sync Frame Received Mask */ 991 #define GMAC_IMR_SFR GMAC_IMR_SFR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMR_SFR_Msk instead */ 992 #define GMAC_IMR_DRQFT_Pos 20 /**< (GMAC_IMR) PTP Delay Request Frame Transmitted Position */ 993 #define GMAC_IMR_DRQFT_Msk (_U_(0x1) << GMAC_IMR_DRQFT_Pos) /**< (GMAC_IMR) PTP Delay Request Frame Transmitted Mask */ 994 #define GMAC_IMR_DRQFT GMAC_IMR_DRQFT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMR_DRQFT_Msk instead */ 995 #define GMAC_IMR_SFT_Pos 21 /**< (GMAC_IMR) PTP Sync Frame Transmitted Position */ 996 #define GMAC_IMR_SFT_Msk (_U_(0x1) << GMAC_IMR_SFT_Pos) /**< (GMAC_IMR) PTP Sync Frame Transmitted Mask */ 997 #define GMAC_IMR_SFT GMAC_IMR_SFT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMR_SFT_Msk instead */ 998 #define GMAC_IMR_PDRQFR_Pos 22 /**< (GMAC_IMR) PDelay Request Frame Received Position */ 999 #define GMAC_IMR_PDRQFR_Msk (_U_(0x1) << GMAC_IMR_PDRQFR_Pos) /**< (GMAC_IMR) PDelay Request Frame Received Mask */ 1000 #define GMAC_IMR_PDRQFR GMAC_IMR_PDRQFR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMR_PDRQFR_Msk instead */ 1001 #define GMAC_IMR_PDRSFR_Pos 23 /**< (GMAC_IMR) PDelay Response Frame Received Position */ 1002 #define GMAC_IMR_PDRSFR_Msk (_U_(0x1) << GMAC_IMR_PDRSFR_Pos) /**< (GMAC_IMR) PDelay Response Frame Received Mask */ 1003 #define GMAC_IMR_PDRSFR GMAC_IMR_PDRSFR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMR_PDRSFR_Msk instead */ 1004 #define GMAC_IMR_PDRQFT_Pos 24 /**< (GMAC_IMR) PDelay Request Frame Transmitted Position */ 1005 #define GMAC_IMR_PDRQFT_Msk (_U_(0x1) << GMAC_IMR_PDRQFT_Pos) /**< (GMAC_IMR) PDelay Request Frame Transmitted Mask */ 1006 #define GMAC_IMR_PDRQFT GMAC_IMR_PDRQFT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMR_PDRQFT_Msk instead */ 1007 #define GMAC_IMR_PDRSFT_Pos 25 /**< (GMAC_IMR) PDelay Response Frame Transmitted Position */ 1008 #define GMAC_IMR_PDRSFT_Msk (_U_(0x1) << GMAC_IMR_PDRSFT_Pos) /**< (GMAC_IMR) PDelay Response Frame Transmitted Mask */ 1009 #define GMAC_IMR_PDRSFT GMAC_IMR_PDRSFT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMR_PDRSFT_Msk instead */ 1010 #define GMAC_IMR_SRI_Pos 26 /**< (GMAC_IMR) TSU Seconds Register Increment Position */ 1011 #define GMAC_IMR_SRI_Msk (_U_(0x1) << GMAC_IMR_SRI_Pos) /**< (GMAC_IMR) TSU Seconds Register Increment Mask */ 1012 #define GMAC_IMR_SRI GMAC_IMR_SRI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMR_SRI_Msk instead */ 1013 #define GMAC_IMR_RXLPISBC_Pos 27 /**< (GMAC_IMR) Enable RX LPI Indication Position */ 1014 #define GMAC_IMR_RXLPISBC_Msk (_U_(0x1) << GMAC_IMR_RXLPISBC_Pos) /**< (GMAC_IMR) Enable RX LPI Indication Mask */ 1015 #define GMAC_IMR_RXLPISBC GMAC_IMR_RXLPISBC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMR_RXLPISBC_Msk instead */ 1016 #define GMAC_IMR_WOL_Pos 28 /**< (GMAC_IMR) Wake On LAN Position */ 1017 #define GMAC_IMR_WOL_Msk (_U_(0x1) << GMAC_IMR_WOL_Pos) /**< (GMAC_IMR) Wake On LAN Mask */ 1018 #define GMAC_IMR_WOL GMAC_IMR_WOL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMR_WOL_Msk instead */ 1019 #define GMAC_IMR_TSUTIMCOMP_Pos 29 /**< (GMAC_IMR) TSU Timer Comparison Position */ 1020 #define GMAC_IMR_TSUTIMCOMP_Msk (_U_(0x1) << GMAC_IMR_TSUTIMCOMP_Pos) /**< (GMAC_IMR) TSU Timer Comparison Mask */ 1021 #define GMAC_IMR_TSUTIMCOMP GMAC_IMR_TSUTIMCOMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMR_TSUTIMCOMP_Msk instead */ 1022 #define GMAC_IMR_MASK _U_(0x3FFCFCFF) /**< \deprecated (GMAC_IMR) Register MASK (Use GMAC_IMR_Msk instead) */ 1023 #define GMAC_IMR_Msk _U_(0x3FFCFCFF) /**< (GMAC_IMR) Register Mask */ 1024 1025 1026 /* -------- GMAC_MAN : (GMAC Offset: 0x34) (R/W 32) PHY Maintenance Register -------- */ 1027 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1028 #if COMPONENT_TYPEDEF_STYLE == 'N' 1029 typedef union { 1030 struct { 1031 uint32_t DATA:16; /**< bit: 0..15 PHY Data */ 1032 uint32_t WTN:2; /**< bit: 16..17 Write Ten */ 1033 uint32_t REGA:5; /**< bit: 18..22 Register Address */ 1034 uint32_t PHYA:5; /**< bit: 23..27 PHY Address */ 1035 uint32_t OP:2; /**< bit: 28..29 Operation */ 1036 uint32_t CLTTO:1; /**< bit: 30 Clause 22 Operation */ 1037 uint32_t WZO:1; /**< bit: 31 Write ZERO */ 1038 } bit; /**< Structure used for bit access */ 1039 uint32_t reg; /**< Type used for register access */ 1040 } GMAC_MAN_Type; 1041 #endif 1042 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1043 1044 #define GMAC_MAN_OFFSET (0x34) /**< (GMAC_MAN) PHY Maintenance Register Offset */ 1045 1046 #define GMAC_MAN_DATA_Pos 0 /**< (GMAC_MAN) PHY Data Position */ 1047 #define GMAC_MAN_DATA_Msk (_U_(0xFFFF) << GMAC_MAN_DATA_Pos) /**< (GMAC_MAN) PHY Data Mask */ 1048 #define GMAC_MAN_DATA(value) (GMAC_MAN_DATA_Msk & ((value) << GMAC_MAN_DATA_Pos)) 1049 #define GMAC_MAN_WTN_Pos 16 /**< (GMAC_MAN) Write Ten Position */ 1050 #define GMAC_MAN_WTN_Msk (_U_(0x3) << GMAC_MAN_WTN_Pos) /**< (GMAC_MAN) Write Ten Mask */ 1051 #define GMAC_MAN_WTN(value) (GMAC_MAN_WTN_Msk & ((value) << GMAC_MAN_WTN_Pos)) 1052 #define GMAC_MAN_REGA_Pos 18 /**< (GMAC_MAN) Register Address Position */ 1053 #define GMAC_MAN_REGA_Msk (_U_(0x1F) << GMAC_MAN_REGA_Pos) /**< (GMAC_MAN) Register Address Mask */ 1054 #define GMAC_MAN_REGA(value) (GMAC_MAN_REGA_Msk & ((value) << GMAC_MAN_REGA_Pos)) 1055 #define GMAC_MAN_PHYA_Pos 23 /**< (GMAC_MAN) PHY Address Position */ 1056 #define GMAC_MAN_PHYA_Msk (_U_(0x1F) << GMAC_MAN_PHYA_Pos) /**< (GMAC_MAN) PHY Address Mask */ 1057 #define GMAC_MAN_PHYA(value) (GMAC_MAN_PHYA_Msk & ((value) << GMAC_MAN_PHYA_Pos)) 1058 #define GMAC_MAN_OP_Pos 28 /**< (GMAC_MAN) Operation Position */ 1059 #define GMAC_MAN_OP_Msk (_U_(0x3) << GMAC_MAN_OP_Pos) /**< (GMAC_MAN) Operation Mask */ 1060 #define GMAC_MAN_OP(value) (GMAC_MAN_OP_Msk & ((value) << GMAC_MAN_OP_Pos)) 1061 #define GMAC_MAN_CLTTO_Pos 30 /**< (GMAC_MAN) Clause 22 Operation Position */ 1062 #define GMAC_MAN_CLTTO_Msk (_U_(0x1) << GMAC_MAN_CLTTO_Pos) /**< (GMAC_MAN) Clause 22 Operation Mask */ 1063 #define GMAC_MAN_CLTTO GMAC_MAN_CLTTO_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_MAN_CLTTO_Msk instead */ 1064 #define GMAC_MAN_WZO_Pos 31 /**< (GMAC_MAN) Write ZERO Position */ 1065 #define GMAC_MAN_WZO_Msk (_U_(0x1) << GMAC_MAN_WZO_Pos) /**< (GMAC_MAN) Write ZERO Mask */ 1066 #define GMAC_MAN_WZO GMAC_MAN_WZO_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_MAN_WZO_Msk instead */ 1067 #define GMAC_MAN_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_MAN) Register MASK (Use GMAC_MAN_Msk instead) */ 1068 #define GMAC_MAN_Msk _U_(0xFFFFFFFF) /**< (GMAC_MAN) Register Mask */ 1069 1070 1071 /* -------- GMAC_RPQ : (GMAC Offset: 0x38) (R/ 32) Received Pause Quantum Register -------- */ 1072 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1073 #if COMPONENT_TYPEDEF_STYLE == 'N' 1074 typedef union { 1075 struct { 1076 uint32_t RPQ:16; /**< bit: 0..15 Received Pause Quantum */ 1077 uint32_t :16; /**< bit: 16..31 Reserved */ 1078 } bit; /**< Structure used for bit access */ 1079 uint32_t reg; /**< Type used for register access */ 1080 } GMAC_RPQ_Type; 1081 #endif 1082 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1083 1084 #define GMAC_RPQ_OFFSET (0x38) /**< (GMAC_RPQ) Received Pause Quantum Register Offset */ 1085 1086 #define GMAC_RPQ_RPQ_Pos 0 /**< (GMAC_RPQ) Received Pause Quantum Position */ 1087 #define GMAC_RPQ_RPQ_Msk (_U_(0xFFFF) << GMAC_RPQ_RPQ_Pos) /**< (GMAC_RPQ) Received Pause Quantum Mask */ 1088 #define GMAC_RPQ_RPQ(value) (GMAC_RPQ_RPQ_Msk & ((value) << GMAC_RPQ_RPQ_Pos)) 1089 #define GMAC_RPQ_MASK _U_(0xFFFF) /**< \deprecated (GMAC_RPQ) Register MASK (Use GMAC_RPQ_Msk instead) */ 1090 #define GMAC_RPQ_Msk _U_(0xFFFF) /**< (GMAC_RPQ) Register Mask */ 1091 1092 1093 /* -------- GMAC_TPQ : (GMAC Offset: 0x3c) (R/W 32) Transmit Pause Quantum Register -------- */ 1094 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1095 #if COMPONENT_TYPEDEF_STYLE == 'N' 1096 typedef union { 1097 struct { 1098 uint32_t TPQ:16; /**< bit: 0..15 Transmit Pause Quantum */ 1099 uint32_t :16; /**< bit: 16..31 Reserved */ 1100 } bit; /**< Structure used for bit access */ 1101 uint32_t reg; /**< Type used for register access */ 1102 } GMAC_TPQ_Type; 1103 #endif 1104 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1105 1106 #define GMAC_TPQ_OFFSET (0x3C) /**< (GMAC_TPQ) Transmit Pause Quantum Register Offset */ 1107 1108 #define GMAC_TPQ_TPQ_Pos 0 /**< (GMAC_TPQ) Transmit Pause Quantum Position */ 1109 #define GMAC_TPQ_TPQ_Msk (_U_(0xFFFF) << GMAC_TPQ_TPQ_Pos) /**< (GMAC_TPQ) Transmit Pause Quantum Mask */ 1110 #define GMAC_TPQ_TPQ(value) (GMAC_TPQ_TPQ_Msk & ((value) << GMAC_TPQ_TPQ_Pos)) 1111 #define GMAC_TPQ_MASK _U_(0xFFFF) /**< \deprecated (GMAC_TPQ) Register MASK (Use GMAC_TPQ_Msk instead) */ 1112 #define GMAC_TPQ_Msk _U_(0xFFFF) /**< (GMAC_TPQ) Register Mask */ 1113 1114 1115 /* -------- GMAC_TPSF : (GMAC Offset: 0x40) (R/W 32) TX Partial Store and Forward Register -------- */ 1116 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1117 #if COMPONENT_TYPEDEF_STYLE == 'N' 1118 typedef union { 1119 struct { 1120 uint32_t TPB1ADR:12; /**< bit: 0..11 Transmit Partial Store and Forward Address */ 1121 uint32_t :19; /**< bit: 12..30 Reserved */ 1122 uint32_t ENTXP:1; /**< bit: 31 Enable TX Partial Store and Forward Operation */ 1123 } bit; /**< Structure used for bit access */ 1124 uint32_t reg; /**< Type used for register access */ 1125 } GMAC_TPSF_Type; 1126 #endif 1127 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1128 1129 #define GMAC_TPSF_OFFSET (0x40) /**< (GMAC_TPSF) TX Partial Store and Forward Register Offset */ 1130 1131 #define GMAC_TPSF_TPB1ADR_Pos 0 /**< (GMAC_TPSF) Transmit Partial Store and Forward Address Position */ 1132 #define GMAC_TPSF_TPB1ADR_Msk (_U_(0xFFF) << GMAC_TPSF_TPB1ADR_Pos) /**< (GMAC_TPSF) Transmit Partial Store and Forward Address Mask */ 1133 #define GMAC_TPSF_TPB1ADR(value) (GMAC_TPSF_TPB1ADR_Msk & ((value) << GMAC_TPSF_TPB1ADR_Pos)) 1134 #define GMAC_TPSF_ENTXP_Pos 31 /**< (GMAC_TPSF) Enable TX Partial Store and Forward Operation Position */ 1135 #define GMAC_TPSF_ENTXP_Msk (_U_(0x1) << GMAC_TPSF_ENTXP_Pos) /**< (GMAC_TPSF) Enable TX Partial Store and Forward Operation Mask */ 1136 #define GMAC_TPSF_ENTXP GMAC_TPSF_ENTXP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_TPSF_ENTXP_Msk instead */ 1137 #define GMAC_TPSF_MASK _U_(0x80000FFF) /**< \deprecated (GMAC_TPSF) Register MASK (Use GMAC_TPSF_Msk instead) */ 1138 #define GMAC_TPSF_Msk _U_(0x80000FFF) /**< (GMAC_TPSF) Register Mask */ 1139 1140 1141 /* -------- GMAC_RPSF : (GMAC Offset: 0x44) (R/W 32) RX Partial Store and Forward Register -------- */ 1142 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1143 #if COMPONENT_TYPEDEF_STYLE == 'N' 1144 typedef union { 1145 struct { 1146 uint32_t RPB1ADR:12; /**< bit: 0..11 Receive Partial Store and Forward Address */ 1147 uint32_t :19; /**< bit: 12..30 Reserved */ 1148 uint32_t ENRXP:1; /**< bit: 31 Enable RX Partial Store and Forward Operation */ 1149 } bit; /**< Structure used for bit access */ 1150 uint32_t reg; /**< Type used for register access */ 1151 } GMAC_RPSF_Type; 1152 #endif 1153 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1154 1155 #define GMAC_RPSF_OFFSET (0x44) /**< (GMAC_RPSF) RX Partial Store and Forward Register Offset */ 1156 1157 #define GMAC_RPSF_RPB1ADR_Pos 0 /**< (GMAC_RPSF) Receive Partial Store and Forward Address Position */ 1158 #define GMAC_RPSF_RPB1ADR_Msk (_U_(0xFFF) << GMAC_RPSF_RPB1ADR_Pos) /**< (GMAC_RPSF) Receive Partial Store and Forward Address Mask */ 1159 #define GMAC_RPSF_RPB1ADR(value) (GMAC_RPSF_RPB1ADR_Msk & ((value) << GMAC_RPSF_RPB1ADR_Pos)) 1160 #define GMAC_RPSF_ENRXP_Pos 31 /**< (GMAC_RPSF) Enable RX Partial Store and Forward Operation Position */ 1161 #define GMAC_RPSF_ENRXP_Msk (_U_(0x1) << GMAC_RPSF_ENRXP_Pos) /**< (GMAC_RPSF) Enable RX Partial Store and Forward Operation Mask */ 1162 #define GMAC_RPSF_ENRXP GMAC_RPSF_ENRXP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_RPSF_ENRXP_Msk instead */ 1163 #define GMAC_RPSF_MASK _U_(0x80000FFF) /**< \deprecated (GMAC_RPSF) Register MASK (Use GMAC_RPSF_Msk instead) */ 1164 #define GMAC_RPSF_Msk _U_(0x80000FFF) /**< (GMAC_RPSF) Register Mask */ 1165 1166 1167 /* -------- GMAC_RJFML : (GMAC Offset: 0x48) (R/W 32) RX Jumbo Frame Max Length Register -------- */ 1168 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1169 #if COMPONENT_TYPEDEF_STYLE == 'N' 1170 typedef union { 1171 struct { 1172 uint32_t FML:14; /**< bit: 0..13 Frame Max Length */ 1173 uint32_t :18; /**< bit: 14..31 Reserved */ 1174 } bit; /**< Structure used for bit access */ 1175 uint32_t reg; /**< Type used for register access */ 1176 } GMAC_RJFML_Type; 1177 #endif 1178 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1179 1180 #define GMAC_RJFML_OFFSET (0x48) /**< (GMAC_RJFML) RX Jumbo Frame Max Length Register Offset */ 1181 1182 #define GMAC_RJFML_FML_Pos 0 /**< (GMAC_RJFML) Frame Max Length Position */ 1183 #define GMAC_RJFML_FML_Msk (_U_(0x3FFF) << GMAC_RJFML_FML_Pos) /**< (GMAC_RJFML) Frame Max Length Mask */ 1184 #define GMAC_RJFML_FML(value) (GMAC_RJFML_FML_Msk & ((value) << GMAC_RJFML_FML_Pos)) 1185 #define GMAC_RJFML_MASK _U_(0x3FFF) /**< \deprecated (GMAC_RJFML) Register MASK (Use GMAC_RJFML_Msk instead) */ 1186 #define GMAC_RJFML_Msk _U_(0x3FFF) /**< (GMAC_RJFML) Register Mask */ 1187 1188 1189 /* -------- GMAC_HRB : (GMAC Offset: 0x80) (R/W 32) Hash Register Bottom -------- */ 1190 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1191 #if COMPONENT_TYPEDEF_STYLE == 'N' 1192 typedef union { 1193 struct { 1194 uint32_t ADDR:32; /**< bit: 0..31 Hash Address */ 1195 } bit; /**< Structure used for bit access */ 1196 uint32_t reg; /**< Type used for register access */ 1197 } GMAC_HRB_Type; 1198 #endif 1199 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1200 1201 #define GMAC_HRB_OFFSET (0x80) /**< (GMAC_HRB) Hash Register Bottom Offset */ 1202 1203 #define GMAC_HRB_ADDR_Pos 0 /**< (GMAC_HRB) Hash Address Position */ 1204 #define GMAC_HRB_ADDR_Msk (_U_(0xFFFFFFFF) << GMAC_HRB_ADDR_Pos) /**< (GMAC_HRB) Hash Address Mask */ 1205 #define GMAC_HRB_ADDR(value) (GMAC_HRB_ADDR_Msk & ((value) << GMAC_HRB_ADDR_Pos)) 1206 #define GMAC_HRB_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_HRB) Register MASK (Use GMAC_HRB_Msk instead) */ 1207 #define GMAC_HRB_Msk _U_(0xFFFFFFFF) /**< (GMAC_HRB) Register Mask */ 1208 1209 1210 /* -------- GMAC_HRT : (GMAC Offset: 0x84) (R/W 32) Hash Register Top -------- */ 1211 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1212 #if COMPONENT_TYPEDEF_STYLE == 'N' 1213 typedef union { 1214 struct { 1215 uint32_t ADDR:32; /**< bit: 0..31 Hash Address */ 1216 } bit; /**< Structure used for bit access */ 1217 uint32_t reg; /**< Type used for register access */ 1218 } GMAC_HRT_Type; 1219 #endif 1220 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1221 1222 #define GMAC_HRT_OFFSET (0x84) /**< (GMAC_HRT) Hash Register Top Offset */ 1223 1224 #define GMAC_HRT_ADDR_Pos 0 /**< (GMAC_HRT) Hash Address Position */ 1225 #define GMAC_HRT_ADDR_Msk (_U_(0xFFFFFFFF) << GMAC_HRT_ADDR_Pos) /**< (GMAC_HRT) Hash Address Mask */ 1226 #define GMAC_HRT_ADDR(value) (GMAC_HRT_ADDR_Msk & ((value) << GMAC_HRT_ADDR_Pos)) 1227 #define GMAC_HRT_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_HRT) Register MASK (Use GMAC_HRT_Msk instead) */ 1228 #define GMAC_HRT_Msk _U_(0xFFFFFFFF) /**< (GMAC_HRT) Register Mask */ 1229 1230 1231 /* -------- GMAC_TIDM1 : (GMAC Offset: 0xa8) (R/W 32) Type ID Match 1 Register -------- */ 1232 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1233 #if COMPONENT_TYPEDEF_STYLE == 'N' 1234 typedef union { 1235 struct { 1236 uint32_t TID:16; /**< bit: 0..15 Type ID Match 1 */ 1237 uint32_t :15; /**< bit: 16..30 Reserved */ 1238 uint32_t ENID1:1; /**< bit: 31 Enable Copying of TID Matched Frames */ 1239 } bit; /**< Structure used for bit access */ 1240 struct { 1241 uint32_t :31; /**< bit: 0..30 Reserved */ 1242 uint32_t ENID:1; /**< bit: 31 Enable Copying of TID Matched Frames */ 1243 } vec; /**< Structure used for vec access */ 1244 uint32_t reg; /**< Type used for register access */ 1245 } GMAC_TIDM1_Type; 1246 #endif 1247 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1248 1249 #define GMAC_TIDM1_OFFSET (0xA8) /**< (GMAC_TIDM1) Type ID Match 1 Register Offset */ 1250 1251 #define GMAC_TIDM1_TID_Pos 0 /**< (GMAC_TIDM1) Type ID Match 1 Position */ 1252 #define GMAC_TIDM1_TID_Msk (_U_(0xFFFF) << GMAC_TIDM1_TID_Pos) /**< (GMAC_TIDM1) Type ID Match 1 Mask */ 1253 #define GMAC_TIDM1_TID(value) (GMAC_TIDM1_TID_Msk & ((value) << GMAC_TIDM1_TID_Pos)) 1254 #define GMAC_TIDM1_ENID1_Pos 31 /**< (GMAC_TIDM1) Enable Copying of TID Matched Frames Position */ 1255 #define GMAC_TIDM1_ENID1_Msk (_U_(0x1) << GMAC_TIDM1_ENID1_Pos) /**< (GMAC_TIDM1) Enable Copying of TID Matched Frames Mask */ 1256 #define GMAC_TIDM1_ENID1 GMAC_TIDM1_ENID1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_TIDM1_ENID1_Msk instead */ 1257 #define GMAC_TIDM1_MASK _U_(0x8000FFFF) /**< \deprecated (GMAC_TIDM1) Register MASK (Use GMAC_TIDM1_Msk instead) */ 1258 #define GMAC_TIDM1_Msk _U_(0x8000FFFF) /**< (GMAC_TIDM1) Register Mask */ 1259 1260 #define GMAC_TIDM1_ENID_Pos 31 /**< (GMAC_TIDM1 Position) Enable Copying of TID Matched Frames */ 1261 #define GMAC_TIDM1_ENID_Msk (_U_(0x1) << GMAC_TIDM1_ENID_Pos) /**< (GMAC_TIDM1 Mask) ENID */ 1262 #define GMAC_TIDM1_ENID(value) (GMAC_TIDM1_ENID_Msk & ((value) << GMAC_TIDM1_ENID_Pos)) 1263 1264 /* -------- GMAC_TIDM2 : (GMAC Offset: 0xac) (R/W 32) Type ID Match 2 Register -------- */ 1265 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1266 #if COMPONENT_TYPEDEF_STYLE == 'N' 1267 typedef union { 1268 struct { 1269 uint32_t TID:16; /**< bit: 0..15 Type ID Match 2 */ 1270 uint32_t :15; /**< bit: 16..30 Reserved */ 1271 uint32_t ENID2:1; /**< bit: 31 Enable Copying of TID Matched Frames */ 1272 } bit; /**< Structure used for bit access */ 1273 struct { 1274 uint32_t :31; /**< bit: 0..30 Reserved */ 1275 uint32_t ENID:1; /**< bit: 31 Enable Copying of TID Matched Frames */ 1276 } vec; /**< Structure used for vec access */ 1277 uint32_t reg; /**< Type used for register access */ 1278 } GMAC_TIDM2_Type; 1279 #endif 1280 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1281 1282 #define GMAC_TIDM2_OFFSET (0xAC) /**< (GMAC_TIDM2) Type ID Match 2 Register Offset */ 1283 1284 #define GMAC_TIDM2_TID_Pos 0 /**< (GMAC_TIDM2) Type ID Match 2 Position */ 1285 #define GMAC_TIDM2_TID_Msk (_U_(0xFFFF) << GMAC_TIDM2_TID_Pos) /**< (GMAC_TIDM2) Type ID Match 2 Mask */ 1286 #define GMAC_TIDM2_TID(value) (GMAC_TIDM2_TID_Msk & ((value) << GMAC_TIDM2_TID_Pos)) 1287 #define GMAC_TIDM2_ENID2_Pos 31 /**< (GMAC_TIDM2) Enable Copying of TID Matched Frames Position */ 1288 #define GMAC_TIDM2_ENID2_Msk (_U_(0x1) << GMAC_TIDM2_ENID2_Pos) /**< (GMAC_TIDM2) Enable Copying of TID Matched Frames Mask */ 1289 #define GMAC_TIDM2_ENID2 GMAC_TIDM2_ENID2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_TIDM2_ENID2_Msk instead */ 1290 #define GMAC_TIDM2_MASK _U_(0x8000FFFF) /**< \deprecated (GMAC_TIDM2) Register MASK (Use GMAC_TIDM2_Msk instead) */ 1291 #define GMAC_TIDM2_Msk _U_(0x8000FFFF) /**< (GMAC_TIDM2) Register Mask */ 1292 1293 #define GMAC_TIDM2_ENID_Pos 31 /**< (GMAC_TIDM2 Position) Enable Copying of TID Matched Frames */ 1294 #define GMAC_TIDM2_ENID_Msk (_U_(0x1) << GMAC_TIDM2_ENID_Pos) /**< (GMAC_TIDM2 Mask) ENID */ 1295 #define GMAC_TIDM2_ENID(value) (GMAC_TIDM2_ENID_Msk & ((value) << GMAC_TIDM2_ENID_Pos)) 1296 1297 /* -------- GMAC_TIDM3 : (GMAC Offset: 0xb0) (R/W 32) Type ID Match 3 Register -------- */ 1298 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1299 #if COMPONENT_TYPEDEF_STYLE == 'N' 1300 typedef union { 1301 struct { 1302 uint32_t TID:16; /**< bit: 0..15 Type ID Match 3 */ 1303 uint32_t :15; /**< bit: 16..30 Reserved */ 1304 uint32_t ENID3:1; /**< bit: 31 Enable Copying of TID Matched Frames */ 1305 } bit; /**< Structure used for bit access */ 1306 struct { 1307 uint32_t :31; /**< bit: 0..30 Reserved */ 1308 uint32_t ENID:1; /**< bit: 31 Enable Copying of TID Matched Frames */ 1309 } vec; /**< Structure used for vec access */ 1310 uint32_t reg; /**< Type used for register access */ 1311 } GMAC_TIDM3_Type; 1312 #endif 1313 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1314 1315 #define GMAC_TIDM3_OFFSET (0xB0) /**< (GMAC_TIDM3) Type ID Match 3 Register Offset */ 1316 1317 #define GMAC_TIDM3_TID_Pos 0 /**< (GMAC_TIDM3) Type ID Match 3 Position */ 1318 #define GMAC_TIDM3_TID_Msk (_U_(0xFFFF) << GMAC_TIDM3_TID_Pos) /**< (GMAC_TIDM3) Type ID Match 3 Mask */ 1319 #define GMAC_TIDM3_TID(value) (GMAC_TIDM3_TID_Msk & ((value) << GMAC_TIDM3_TID_Pos)) 1320 #define GMAC_TIDM3_ENID3_Pos 31 /**< (GMAC_TIDM3) Enable Copying of TID Matched Frames Position */ 1321 #define GMAC_TIDM3_ENID3_Msk (_U_(0x1) << GMAC_TIDM3_ENID3_Pos) /**< (GMAC_TIDM3) Enable Copying of TID Matched Frames Mask */ 1322 #define GMAC_TIDM3_ENID3 GMAC_TIDM3_ENID3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_TIDM3_ENID3_Msk instead */ 1323 #define GMAC_TIDM3_MASK _U_(0x8000FFFF) /**< \deprecated (GMAC_TIDM3) Register MASK (Use GMAC_TIDM3_Msk instead) */ 1324 #define GMAC_TIDM3_Msk _U_(0x8000FFFF) /**< (GMAC_TIDM3) Register Mask */ 1325 1326 #define GMAC_TIDM3_ENID_Pos 31 /**< (GMAC_TIDM3 Position) Enable Copying of TID Matched Frames */ 1327 #define GMAC_TIDM3_ENID_Msk (_U_(0x1) << GMAC_TIDM3_ENID_Pos) /**< (GMAC_TIDM3 Mask) ENID */ 1328 #define GMAC_TIDM3_ENID(value) (GMAC_TIDM3_ENID_Msk & ((value) << GMAC_TIDM3_ENID_Pos)) 1329 1330 /* -------- GMAC_TIDM4 : (GMAC Offset: 0xb4) (R/W 32) Type ID Match 4 Register -------- */ 1331 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1332 #if COMPONENT_TYPEDEF_STYLE == 'N' 1333 typedef union { 1334 struct { 1335 uint32_t TID:16; /**< bit: 0..15 Type ID Match 4 */ 1336 uint32_t :15; /**< bit: 16..30 Reserved */ 1337 uint32_t ENID4:1; /**< bit: 31 Enable Copying of TID Matched Frames */ 1338 } bit; /**< Structure used for bit access */ 1339 struct { 1340 uint32_t :31; /**< bit: 0..30 Reserved */ 1341 uint32_t ENID:1; /**< bit: 31 Enable Copying of TID Matched Frames */ 1342 } vec; /**< Structure used for vec access */ 1343 uint32_t reg; /**< Type used for register access */ 1344 } GMAC_TIDM4_Type; 1345 #endif 1346 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1347 1348 #define GMAC_TIDM4_OFFSET (0xB4) /**< (GMAC_TIDM4) Type ID Match 4 Register Offset */ 1349 1350 #define GMAC_TIDM4_TID_Pos 0 /**< (GMAC_TIDM4) Type ID Match 4 Position */ 1351 #define GMAC_TIDM4_TID_Msk (_U_(0xFFFF) << GMAC_TIDM4_TID_Pos) /**< (GMAC_TIDM4) Type ID Match 4 Mask */ 1352 #define GMAC_TIDM4_TID(value) (GMAC_TIDM4_TID_Msk & ((value) << GMAC_TIDM4_TID_Pos)) 1353 #define GMAC_TIDM4_ENID4_Pos 31 /**< (GMAC_TIDM4) Enable Copying of TID Matched Frames Position */ 1354 #define GMAC_TIDM4_ENID4_Msk (_U_(0x1) << GMAC_TIDM4_ENID4_Pos) /**< (GMAC_TIDM4) Enable Copying of TID Matched Frames Mask */ 1355 #define GMAC_TIDM4_ENID4 GMAC_TIDM4_ENID4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_TIDM4_ENID4_Msk instead */ 1356 #define GMAC_TIDM4_MASK _U_(0x8000FFFF) /**< \deprecated (GMAC_TIDM4) Register MASK (Use GMAC_TIDM4_Msk instead) */ 1357 #define GMAC_TIDM4_Msk _U_(0x8000FFFF) /**< (GMAC_TIDM4) Register Mask */ 1358 1359 #define GMAC_TIDM4_ENID_Pos 31 /**< (GMAC_TIDM4 Position) Enable Copying of TID Matched Frames */ 1360 #define GMAC_TIDM4_ENID_Msk (_U_(0x1) << GMAC_TIDM4_ENID_Pos) /**< (GMAC_TIDM4 Mask) ENID */ 1361 #define GMAC_TIDM4_ENID(value) (GMAC_TIDM4_ENID_Msk & ((value) << GMAC_TIDM4_ENID_Pos)) 1362 1363 /* -------- GMAC_WOL : (GMAC Offset: 0xb8) (R/W 32) Wake on LAN Register -------- */ 1364 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1365 #if COMPONENT_TYPEDEF_STYLE == 'N' 1366 typedef union { 1367 struct { 1368 uint32_t IP:16; /**< bit: 0..15 ARP Request IP Address */ 1369 uint32_t MAG:1; /**< bit: 16 Magic Packet Event Enable */ 1370 uint32_t ARP:1; /**< bit: 17 ARP Request IP Address */ 1371 uint32_t SA1:1; /**< bit: 18 Specific Address Register 1 Event Enable */ 1372 uint32_t MTI:1; /**< bit: 19 Multicast Hash Event Enable */ 1373 uint32_t :12; /**< bit: 20..31 Reserved */ 1374 } bit; /**< Structure used for bit access */ 1375 struct { 1376 uint32_t :18; /**< bit: 0..17 Reserved */ 1377 uint32_t SA:1; /**< bit: 18 Specific Address Register x Event Enable */ 1378 uint32_t :13; /**< bit: 19..31 Reserved */ 1379 } vec; /**< Structure used for vec access */ 1380 uint32_t reg; /**< Type used for register access */ 1381 } GMAC_WOL_Type; 1382 #endif 1383 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1384 1385 #define GMAC_WOL_OFFSET (0xB8) /**< (GMAC_WOL) Wake on LAN Register Offset */ 1386 1387 #define GMAC_WOL_IP_Pos 0 /**< (GMAC_WOL) ARP Request IP Address Position */ 1388 #define GMAC_WOL_IP_Msk (_U_(0xFFFF) << GMAC_WOL_IP_Pos) /**< (GMAC_WOL) ARP Request IP Address Mask */ 1389 #define GMAC_WOL_IP(value) (GMAC_WOL_IP_Msk & ((value) << GMAC_WOL_IP_Pos)) 1390 #define GMAC_WOL_MAG_Pos 16 /**< (GMAC_WOL) Magic Packet Event Enable Position */ 1391 #define GMAC_WOL_MAG_Msk (_U_(0x1) << GMAC_WOL_MAG_Pos) /**< (GMAC_WOL) Magic Packet Event Enable Mask */ 1392 #define GMAC_WOL_MAG GMAC_WOL_MAG_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_WOL_MAG_Msk instead */ 1393 #define GMAC_WOL_ARP_Pos 17 /**< (GMAC_WOL) ARP Request IP Address Position */ 1394 #define GMAC_WOL_ARP_Msk (_U_(0x1) << GMAC_WOL_ARP_Pos) /**< (GMAC_WOL) ARP Request IP Address Mask */ 1395 #define GMAC_WOL_ARP GMAC_WOL_ARP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_WOL_ARP_Msk instead */ 1396 #define GMAC_WOL_SA1_Pos 18 /**< (GMAC_WOL) Specific Address Register 1 Event Enable Position */ 1397 #define GMAC_WOL_SA1_Msk (_U_(0x1) << GMAC_WOL_SA1_Pos) /**< (GMAC_WOL) Specific Address Register 1 Event Enable Mask */ 1398 #define GMAC_WOL_SA1 GMAC_WOL_SA1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_WOL_SA1_Msk instead */ 1399 #define GMAC_WOL_MTI_Pos 19 /**< (GMAC_WOL) Multicast Hash Event Enable Position */ 1400 #define GMAC_WOL_MTI_Msk (_U_(0x1) << GMAC_WOL_MTI_Pos) /**< (GMAC_WOL) Multicast Hash Event Enable Mask */ 1401 #define GMAC_WOL_MTI GMAC_WOL_MTI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_WOL_MTI_Msk instead */ 1402 #define GMAC_WOL_MASK _U_(0xFFFFF) /**< \deprecated (GMAC_WOL) Register MASK (Use GMAC_WOL_Msk instead) */ 1403 #define GMAC_WOL_Msk _U_(0xFFFFF) /**< (GMAC_WOL) Register Mask */ 1404 1405 #define GMAC_WOL_SA_Pos 18 /**< (GMAC_WOL Position) Specific Address Register x Event Enable */ 1406 #define GMAC_WOL_SA_Msk (_U_(0x1) << GMAC_WOL_SA_Pos) /**< (GMAC_WOL Mask) SA */ 1407 #define GMAC_WOL_SA(value) (GMAC_WOL_SA_Msk & ((value) << GMAC_WOL_SA_Pos)) 1408 1409 /* -------- GMAC_IPGS : (GMAC Offset: 0xbc) (R/W 32) IPG Stretch Register -------- */ 1410 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1411 #if COMPONENT_TYPEDEF_STYLE == 'N' 1412 typedef union { 1413 struct { 1414 uint32_t FL:16; /**< bit: 0..15 Frame Length */ 1415 uint32_t :16; /**< bit: 16..31 Reserved */ 1416 } bit; /**< Structure used for bit access */ 1417 uint32_t reg; /**< Type used for register access */ 1418 } GMAC_IPGS_Type; 1419 #endif 1420 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1421 1422 #define GMAC_IPGS_OFFSET (0xBC) /**< (GMAC_IPGS) IPG Stretch Register Offset */ 1423 1424 #define GMAC_IPGS_FL_Pos 0 /**< (GMAC_IPGS) Frame Length Position */ 1425 #define GMAC_IPGS_FL_Msk (_U_(0xFFFF) << GMAC_IPGS_FL_Pos) /**< (GMAC_IPGS) Frame Length Mask */ 1426 #define GMAC_IPGS_FL(value) (GMAC_IPGS_FL_Msk & ((value) << GMAC_IPGS_FL_Pos)) 1427 #define GMAC_IPGS_MASK _U_(0xFFFF) /**< \deprecated (GMAC_IPGS) Register MASK (Use GMAC_IPGS_Msk instead) */ 1428 #define GMAC_IPGS_Msk _U_(0xFFFF) /**< (GMAC_IPGS) Register Mask */ 1429 1430 1431 /* -------- GMAC_SVLAN : (GMAC Offset: 0xc0) (R/W 32) Stacked VLAN Register -------- */ 1432 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1433 #if COMPONENT_TYPEDEF_STYLE == 'N' 1434 typedef union { 1435 struct { 1436 uint32_t VLAN_TYPE:16; /**< bit: 0..15 User Defined VLAN_TYPE Field */ 1437 uint32_t :15; /**< bit: 16..30 Reserved */ 1438 uint32_t ESVLAN:1; /**< bit: 31 Enable Stacked VLAN Processing Mode */ 1439 } bit; /**< Structure used for bit access */ 1440 uint32_t reg; /**< Type used for register access */ 1441 } GMAC_SVLAN_Type; 1442 #endif 1443 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1444 1445 #define GMAC_SVLAN_OFFSET (0xC0) /**< (GMAC_SVLAN) Stacked VLAN Register Offset */ 1446 1447 #define GMAC_SVLAN_VLAN_TYPE_Pos 0 /**< (GMAC_SVLAN) User Defined VLAN_TYPE Field Position */ 1448 #define GMAC_SVLAN_VLAN_TYPE_Msk (_U_(0xFFFF) << GMAC_SVLAN_VLAN_TYPE_Pos) /**< (GMAC_SVLAN) User Defined VLAN_TYPE Field Mask */ 1449 #define GMAC_SVLAN_VLAN_TYPE(value) (GMAC_SVLAN_VLAN_TYPE_Msk & ((value) << GMAC_SVLAN_VLAN_TYPE_Pos)) 1450 #define GMAC_SVLAN_ESVLAN_Pos 31 /**< (GMAC_SVLAN) Enable Stacked VLAN Processing Mode Position */ 1451 #define GMAC_SVLAN_ESVLAN_Msk (_U_(0x1) << GMAC_SVLAN_ESVLAN_Pos) /**< (GMAC_SVLAN) Enable Stacked VLAN Processing Mode Mask */ 1452 #define GMAC_SVLAN_ESVLAN GMAC_SVLAN_ESVLAN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_SVLAN_ESVLAN_Msk instead */ 1453 #define GMAC_SVLAN_MASK _U_(0x8000FFFF) /**< \deprecated (GMAC_SVLAN) Register MASK (Use GMAC_SVLAN_Msk instead) */ 1454 #define GMAC_SVLAN_Msk _U_(0x8000FFFF) /**< (GMAC_SVLAN) Register Mask */ 1455 1456 1457 /* -------- GMAC_TPFCP : (GMAC Offset: 0xc4) (R/W 32) Transmit PFC Pause Register -------- */ 1458 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1459 #if COMPONENT_TYPEDEF_STYLE == 'N' 1460 typedef union { 1461 struct { 1462 uint32_t PEV:8; /**< bit: 0..7 Priority Enable Vector */ 1463 uint32_t PQ:8; /**< bit: 8..15 Pause Quantum */ 1464 uint32_t :16; /**< bit: 16..31 Reserved */ 1465 } bit; /**< Structure used for bit access */ 1466 uint32_t reg; /**< Type used for register access */ 1467 } GMAC_TPFCP_Type; 1468 #endif 1469 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1470 1471 #define GMAC_TPFCP_OFFSET (0xC4) /**< (GMAC_TPFCP) Transmit PFC Pause Register Offset */ 1472 1473 #define GMAC_TPFCP_PEV_Pos 0 /**< (GMAC_TPFCP) Priority Enable Vector Position */ 1474 #define GMAC_TPFCP_PEV_Msk (_U_(0xFF) << GMAC_TPFCP_PEV_Pos) /**< (GMAC_TPFCP) Priority Enable Vector Mask */ 1475 #define GMAC_TPFCP_PEV(value) (GMAC_TPFCP_PEV_Msk & ((value) << GMAC_TPFCP_PEV_Pos)) 1476 #define GMAC_TPFCP_PQ_Pos 8 /**< (GMAC_TPFCP) Pause Quantum Position */ 1477 #define GMAC_TPFCP_PQ_Msk (_U_(0xFF) << GMAC_TPFCP_PQ_Pos) /**< (GMAC_TPFCP) Pause Quantum Mask */ 1478 #define GMAC_TPFCP_PQ(value) (GMAC_TPFCP_PQ_Msk & ((value) << GMAC_TPFCP_PQ_Pos)) 1479 #define GMAC_TPFCP_MASK _U_(0xFFFF) /**< \deprecated (GMAC_TPFCP) Register MASK (Use GMAC_TPFCP_Msk instead) */ 1480 #define GMAC_TPFCP_Msk _U_(0xFFFF) /**< (GMAC_TPFCP) Register Mask */ 1481 1482 1483 /* -------- GMAC_SAMB1 : (GMAC Offset: 0xc8) (R/W 32) Specific Address 1 Mask Bottom Register -------- */ 1484 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1485 #if COMPONENT_TYPEDEF_STYLE == 'N' 1486 typedef union { 1487 struct { 1488 uint32_t ADDR:32; /**< bit: 0..31 Specific Address 1 Mask */ 1489 } bit; /**< Structure used for bit access */ 1490 uint32_t reg; /**< Type used for register access */ 1491 } GMAC_SAMB1_Type; 1492 #endif 1493 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1494 1495 #define GMAC_SAMB1_OFFSET (0xC8) /**< (GMAC_SAMB1) Specific Address 1 Mask Bottom Register Offset */ 1496 1497 #define GMAC_SAMB1_ADDR_Pos 0 /**< (GMAC_SAMB1) Specific Address 1 Mask Position */ 1498 #define GMAC_SAMB1_ADDR_Msk (_U_(0xFFFFFFFF) << GMAC_SAMB1_ADDR_Pos) /**< (GMAC_SAMB1) Specific Address 1 Mask Mask */ 1499 #define GMAC_SAMB1_ADDR(value) (GMAC_SAMB1_ADDR_Msk & ((value) << GMAC_SAMB1_ADDR_Pos)) 1500 #define GMAC_SAMB1_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_SAMB1) Register MASK (Use GMAC_SAMB1_Msk instead) */ 1501 #define GMAC_SAMB1_Msk _U_(0xFFFFFFFF) /**< (GMAC_SAMB1) Register Mask */ 1502 1503 1504 /* -------- GMAC_SAMT1 : (GMAC Offset: 0xcc) (R/W 32) Specific Address 1 Mask Top Register -------- */ 1505 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1506 #if COMPONENT_TYPEDEF_STYLE == 'N' 1507 typedef union { 1508 struct { 1509 uint32_t ADDR:16; /**< bit: 0..15 Specific Address 1 Mask */ 1510 uint32_t :16; /**< bit: 16..31 Reserved */ 1511 } bit; /**< Structure used for bit access */ 1512 uint32_t reg; /**< Type used for register access */ 1513 } GMAC_SAMT1_Type; 1514 #endif 1515 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1516 1517 #define GMAC_SAMT1_OFFSET (0xCC) /**< (GMAC_SAMT1) Specific Address 1 Mask Top Register Offset */ 1518 1519 #define GMAC_SAMT1_ADDR_Pos 0 /**< (GMAC_SAMT1) Specific Address 1 Mask Position */ 1520 #define GMAC_SAMT1_ADDR_Msk (_U_(0xFFFF) << GMAC_SAMT1_ADDR_Pos) /**< (GMAC_SAMT1) Specific Address 1 Mask Mask */ 1521 #define GMAC_SAMT1_ADDR(value) (GMAC_SAMT1_ADDR_Msk & ((value) << GMAC_SAMT1_ADDR_Pos)) 1522 #define GMAC_SAMT1_MASK _U_(0xFFFF) /**< \deprecated (GMAC_SAMT1) Register MASK (Use GMAC_SAMT1_Msk instead) */ 1523 #define GMAC_SAMT1_Msk _U_(0xFFFF) /**< (GMAC_SAMT1) Register Mask */ 1524 1525 1526 /* -------- GMAC_NSC : (GMAC Offset: 0xdc) (R/W 32) 1588 Timer Nanosecond Comparison Register -------- */ 1527 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1528 #if COMPONENT_TYPEDEF_STYLE == 'N' 1529 typedef union { 1530 struct { 1531 uint32_t NANOSEC:22; /**< bit: 0..21 1588 Timer Nanosecond Comparison Value */ 1532 uint32_t :10; /**< bit: 22..31 Reserved */ 1533 } bit; /**< Structure used for bit access */ 1534 uint32_t reg; /**< Type used for register access */ 1535 } GMAC_NSC_Type; 1536 #endif 1537 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1538 1539 #define GMAC_NSC_OFFSET (0xDC) /**< (GMAC_NSC) 1588 Timer Nanosecond Comparison Register Offset */ 1540 1541 #define GMAC_NSC_NANOSEC_Pos 0 /**< (GMAC_NSC) 1588 Timer Nanosecond Comparison Value Position */ 1542 #define GMAC_NSC_NANOSEC_Msk (_U_(0x3FFFFF) << GMAC_NSC_NANOSEC_Pos) /**< (GMAC_NSC) 1588 Timer Nanosecond Comparison Value Mask */ 1543 #define GMAC_NSC_NANOSEC(value) (GMAC_NSC_NANOSEC_Msk & ((value) << GMAC_NSC_NANOSEC_Pos)) 1544 #define GMAC_NSC_MASK _U_(0x3FFFFF) /**< \deprecated (GMAC_NSC) Register MASK (Use GMAC_NSC_Msk instead) */ 1545 #define GMAC_NSC_Msk _U_(0x3FFFFF) /**< (GMAC_NSC) Register Mask */ 1546 1547 1548 /* -------- GMAC_SCL : (GMAC Offset: 0xe0) (R/W 32) 1588 Timer Second Comparison Low Register -------- */ 1549 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1550 #if COMPONENT_TYPEDEF_STYLE == 'N' 1551 typedef union { 1552 struct { 1553 uint32_t SEC:32; /**< bit: 0..31 1588 Timer Second Comparison Value */ 1554 } bit; /**< Structure used for bit access */ 1555 uint32_t reg; /**< Type used for register access */ 1556 } GMAC_SCL_Type; 1557 #endif 1558 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1559 1560 #define GMAC_SCL_OFFSET (0xE0) /**< (GMAC_SCL) 1588 Timer Second Comparison Low Register Offset */ 1561 1562 #define GMAC_SCL_SEC_Pos 0 /**< (GMAC_SCL) 1588 Timer Second Comparison Value Position */ 1563 #define GMAC_SCL_SEC_Msk (_U_(0xFFFFFFFF) << GMAC_SCL_SEC_Pos) /**< (GMAC_SCL) 1588 Timer Second Comparison Value Mask */ 1564 #define GMAC_SCL_SEC(value) (GMAC_SCL_SEC_Msk & ((value) << GMAC_SCL_SEC_Pos)) 1565 #define GMAC_SCL_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_SCL) Register MASK (Use GMAC_SCL_Msk instead) */ 1566 #define GMAC_SCL_Msk _U_(0xFFFFFFFF) /**< (GMAC_SCL) Register Mask */ 1567 1568 1569 /* -------- GMAC_SCH : (GMAC Offset: 0xe4) (R/W 32) 1588 Timer Second Comparison High Register -------- */ 1570 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1571 #if COMPONENT_TYPEDEF_STYLE == 'N' 1572 typedef union { 1573 struct { 1574 uint32_t SEC:16; /**< bit: 0..15 1588 Timer Second Comparison Value */ 1575 uint32_t :16; /**< bit: 16..31 Reserved */ 1576 } bit; /**< Structure used for bit access */ 1577 uint32_t reg; /**< Type used for register access */ 1578 } GMAC_SCH_Type; 1579 #endif 1580 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1581 1582 #define GMAC_SCH_OFFSET (0xE4) /**< (GMAC_SCH) 1588 Timer Second Comparison High Register Offset */ 1583 1584 #define GMAC_SCH_SEC_Pos 0 /**< (GMAC_SCH) 1588 Timer Second Comparison Value Position */ 1585 #define GMAC_SCH_SEC_Msk (_U_(0xFFFF) << GMAC_SCH_SEC_Pos) /**< (GMAC_SCH) 1588 Timer Second Comparison Value Mask */ 1586 #define GMAC_SCH_SEC(value) (GMAC_SCH_SEC_Msk & ((value) << GMAC_SCH_SEC_Pos)) 1587 #define GMAC_SCH_MASK _U_(0xFFFF) /**< \deprecated (GMAC_SCH) Register MASK (Use GMAC_SCH_Msk instead) */ 1588 #define GMAC_SCH_Msk _U_(0xFFFF) /**< (GMAC_SCH) Register Mask */ 1589 1590 1591 /* -------- GMAC_EFTSH : (GMAC Offset: 0xe8) (R/ 32) PTP Event Frame Transmitted Seconds High Register -------- */ 1592 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1593 #if COMPONENT_TYPEDEF_STYLE == 'N' 1594 typedef union { 1595 struct { 1596 uint32_t RUD:16; /**< bit: 0..15 Register Update */ 1597 uint32_t :16; /**< bit: 16..31 Reserved */ 1598 } bit; /**< Structure used for bit access */ 1599 uint32_t reg; /**< Type used for register access */ 1600 } GMAC_EFTSH_Type; 1601 #endif 1602 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1603 1604 #define GMAC_EFTSH_OFFSET (0xE8) /**< (GMAC_EFTSH) PTP Event Frame Transmitted Seconds High Register Offset */ 1605 1606 #define GMAC_EFTSH_RUD_Pos 0 /**< (GMAC_EFTSH) Register Update Position */ 1607 #define GMAC_EFTSH_RUD_Msk (_U_(0xFFFF) << GMAC_EFTSH_RUD_Pos) /**< (GMAC_EFTSH) Register Update Mask */ 1608 #define GMAC_EFTSH_RUD(value) (GMAC_EFTSH_RUD_Msk & ((value) << GMAC_EFTSH_RUD_Pos)) 1609 #define GMAC_EFTSH_MASK _U_(0xFFFF) /**< \deprecated (GMAC_EFTSH) Register MASK (Use GMAC_EFTSH_Msk instead) */ 1610 #define GMAC_EFTSH_Msk _U_(0xFFFF) /**< (GMAC_EFTSH) Register Mask */ 1611 1612 1613 /* -------- GMAC_EFRSH : (GMAC Offset: 0xec) (R/ 32) PTP Event Frame Received Seconds High Register -------- */ 1614 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1615 #if COMPONENT_TYPEDEF_STYLE == 'N' 1616 typedef union { 1617 struct { 1618 uint32_t RUD:16; /**< bit: 0..15 Register Update */ 1619 uint32_t :16; /**< bit: 16..31 Reserved */ 1620 } bit; /**< Structure used for bit access */ 1621 uint32_t reg; /**< Type used for register access */ 1622 } GMAC_EFRSH_Type; 1623 #endif 1624 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1625 1626 #define GMAC_EFRSH_OFFSET (0xEC) /**< (GMAC_EFRSH) PTP Event Frame Received Seconds High Register Offset */ 1627 1628 #define GMAC_EFRSH_RUD_Pos 0 /**< (GMAC_EFRSH) Register Update Position */ 1629 #define GMAC_EFRSH_RUD_Msk (_U_(0xFFFF) << GMAC_EFRSH_RUD_Pos) /**< (GMAC_EFRSH) Register Update Mask */ 1630 #define GMAC_EFRSH_RUD(value) (GMAC_EFRSH_RUD_Msk & ((value) << GMAC_EFRSH_RUD_Pos)) 1631 #define GMAC_EFRSH_MASK _U_(0xFFFF) /**< \deprecated (GMAC_EFRSH) Register MASK (Use GMAC_EFRSH_Msk instead) */ 1632 #define GMAC_EFRSH_Msk _U_(0xFFFF) /**< (GMAC_EFRSH) Register Mask */ 1633 1634 1635 /* -------- GMAC_PEFTSH : (GMAC Offset: 0xf0) (R/ 32) PTP Peer Event Frame Transmitted Seconds High Register -------- */ 1636 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1637 #if COMPONENT_TYPEDEF_STYLE == 'N' 1638 typedef union { 1639 struct { 1640 uint32_t RUD:16; /**< bit: 0..15 Register Update */ 1641 uint32_t :16; /**< bit: 16..31 Reserved */ 1642 } bit; /**< Structure used for bit access */ 1643 uint32_t reg; /**< Type used for register access */ 1644 } GMAC_PEFTSH_Type; 1645 #endif 1646 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1647 1648 #define GMAC_PEFTSH_OFFSET (0xF0) /**< (GMAC_PEFTSH) PTP Peer Event Frame Transmitted Seconds High Register Offset */ 1649 1650 #define GMAC_PEFTSH_RUD_Pos 0 /**< (GMAC_PEFTSH) Register Update Position */ 1651 #define GMAC_PEFTSH_RUD_Msk (_U_(0xFFFF) << GMAC_PEFTSH_RUD_Pos) /**< (GMAC_PEFTSH) Register Update Mask */ 1652 #define GMAC_PEFTSH_RUD(value) (GMAC_PEFTSH_RUD_Msk & ((value) << GMAC_PEFTSH_RUD_Pos)) 1653 #define GMAC_PEFTSH_MASK _U_(0xFFFF) /**< \deprecated (GMAC_PEFTSH) Register MASK (Use GMAC_PEFTSH_Msk instead) */ 1654 #define GMAC_PEFTSH_Msk _U_(0xFFFF) /**< (GMAC_PEFTSH) Register Mask */ 1655 1656 1657 /* -------- GMAC_PEFRSH : (GMAC Offset: 0xf4) (R/ 32) PTP Peer Event Frame Received Seconds High Register -------- */ 1658 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1659 #if COMPONENT_TYPEDEF_STYLE == 'N' 1660 typedef union { 1661 struct { 1662 uint32_t RUD:16; /**< bit: 0..15 Register Update */ 1663 uint32_t :16; /**< bit: 16..31 Reserved */ 1664 } bit; /**< Structure used for bit access */ 1665 uint32_t reg; /**< Type used for register access */ 1666 } GMAC_PEFRSH_Type; 1667 #endif 1668 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1669 1670 #define GMAC_PEFRSH_OFFSET (0xF4) /**< (GMAC_PEFRSH) PTP Peer Event Frame Received Seconds High Register Offset */ 1671 1672 #define GMAC_PEFRSH_RUD_Pos 0 /**< (GMAC_PEFRSH) Register Update Position */ 1673 #define GMAC_PEFRSH_RUD_Msk (_U_(0xFFFF) << GMAC_PEFRSH_RUD_Pos) /**< (GMAC_PEFRSH) Register Update Mask */ 1674 #define GMAC_PEFRSH_RUD(value) (GMAC_PEFRSH_RUD_Msk & ((value) << GMAC_PEFRSH_RUD_Pos)) 1675 #define GMAC_PEFRSH_MASK _U_(0xFFFF) /**< \deprecated (GMAC_PEFRSH) Register MASK (Use GMAC_PEFRSH_Msk instead) */ 1676 #define GMAC_PEFRSH_Msk _U_(0xFFFF) /**< (GMAC_PEFRSH) Register Mask */ 1677 1678 1679 /* -------- GMAC_MID : (GMAC Offset: 0xfc) (R/ 32) Module ID Register -------- */ 1680 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1681 #if COMPONENT_TYPEDEF_STYLE == 'N' 1682 typedef union { 1683 struct { 1684 uint32_t MREV:16; /**< bit: 0..15 Module Revision */ 1685 uint32_t MID:16; /**< bit: 16..31 Module Identification Number */ 1686 } bit; /**< Structure used for bit access */ 1687 uint32_t reg; /**< Type used for register access */ 1688 } GMAC_MID_Type; 1689 #endif 1690 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1691 1692 #define GMAC_MID_OFFSET (0xFC) /**< (GMAC_MID) Module ID Register Offset */ 1693 1694 #define GMAC_MID_MREV_Pos 0 /**< (GMAC_MID) Module Revision Position */ 1695 #define GMAC_MID_MREV_Msk (_U_(0xFFFF) << GMAC_MID_MREV_Pos) /**< (GMAC_MID) Module Revision Mask */ 1696 #define GMAC_MID_MREV(value) (GMAC_MID_MREV_Msk & ((value) << GMAC_MID_MREV_Pos)) 1697 #define GMAC_MID_MID_Pos 16 /**< (GMAC_MID) Module Identification Number Position */ 1698 #define GMAC_MID_MID_Msk (_U_(0xFFFF) << GMAC_MID_MID_Pos) /**< (GMAC_MID) Module Identification Number Mask */ 1699 #define GMAC_MID_MID(value) (GMAC_MID_MID_Msk & ((value) << GMAC_MID_MID_Pos)) 1700 #define GMAC_MID_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_MID) Register MASK (Use GMAC_MID_Msk instead) */ 1701 #define GMAC_MID_Msk _U_(0xFFFFFFFF) /**< (GMAC_MID) Register Mask */ 1702 1703 1704 /* -------- GMAC_OTLO : (GMAC Offset: 0x100) (R/ 32) Octets Transmitted Low Register -------- */ 1705 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1706 #if COMPONENT_TYPEDEF_STYLE == 'N' 1707 typedef union { 1708 struct { 1709 uint32_t TXO:32; /**< bit: 0..31 Transmitted Octets */ 1710 } bit; /**< Structure used for bit access */ 1711 uint32_t reg; /**< Type used for register access */ 1712 } GMAC_OTLO_Type; 1713 #endif 1714 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1715 1716 #define GMAC_OTLO_OFFSET (0x100) /**< (GMAC_OTLO) Octets Transmitted Low Register Offset */ 1717 1718 #define GMAC_OTLO_TXO_Pos 0 /**< (GMAC_OTLO) Transmitted Octets Position */ 1719 #define GMAC_OTLO_TXO_Msk (_U_(0xFFFFFFFF) << GMAC_OTLO_TXO_Pos) /**< (GMAC_OTLO) Transmitted Octets Mask */ 1720 #define GMAC_OTLO_TXO(value) (GMAC_OTLO_TXO_Msk & ((value) << GMAC_OTLO_TXO_Pos)) 1721 #define GMAC_OTLO_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_OTLO) Register MASK (Use GMAC_OTLO_Msk instead) */ 1722 #define GMAC_OTLO_Msk _U_(0xFFFFFFFF) /**< (GMAC_OTLO) Register Mask */ 1723 1724 1725 /* -------- GMAC_OTHI : (GMAC Offset: 0x104) (R/ 32) Octets Transmitted High Register -------- */ 1726 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1727 #if COMPONENT_TYPEDEF_STYLE == 'N' 1728 typedef union { 1729 struct { 1730 uint32_t TXO:16; /**< bit: 0..15 Transmitted Octets */ 1731 uint32_t :16; /**< bit: 16..31 Reserved */ 1732 } bit; /**< Structure used for bit access */ 1733 uint32_t reg; /**< Type used for register access */ 1734 } GMAC_OTHI_Type; 1735 #endif 1736 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1737 1738 #define GMAC_OTHI_OFFSET (0x104) /**< (GMAC_OTHI) Octets Transmitted High Register Offset */ 1739 1740 #define GMAC_OTHI_TXO_Pos 0 /**< (GMAC_OTHI) Transmitted Octets Position */ 1741 #define GMAC_OTHI_TXO_Msk (_U_(0xFFFF) << GMAC_OTHI_TXO_Pos) /**< (GMAC_OTHI) Transmitted Octets Mask */ 1742 #define GMAC_OTHI_TXO(value) (GMAC_OTHI_TXO_Msk & ((value) << GMAC_OTHI_TXO_Pos)) 1743 #define GMAC_OTHI_MASK _U_(0xFFFF) /**< \deprecated (GMAC_OTHI) Register MASK (Use GMAC_OTHI_Msk instead) */ 1744 #define GMAC_OTHI_Msk _U_(0xFFFF) /**< (GMAC_OTHI) Register Mask */ 1745 1746 1747 /* -------- GMAC_FT : (GMAC Offset: 0x108) (R/ 32) Frames Transmitted Register -------- */ 1748 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1749 #if COMPONENT_TYPEDEF_STYLE == 'N' 1750 typedef union { 1751 struct { 1752 uint32_t FTX:32; /**< bit: 0..31 Frames Transmitted without Error */ 1753 } bit; /**< Structure used for bit access */ 1754 uint32_t reg; /**< Type used for register access */ 1755 } GMAC_FT_Type; 1756 #endif 1757 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1758 1759 #define GMAC_FT_OFFSET (0x108) /**< (GMAC_FT) Frames Transmitted Register Offset */ 1760 1761 #define GMAC_FT_FTX_Pos 0 /**< (GMAC_FT) Frames Transmitted without Error Position */ 1762 #define GMAC_FT_FTX_Msk (_U_(0xFFFFFFFF) << GMAC_FT_FTX_Pos) /**< (GMAC_FT) Frames Transmitted without Error Mask */ 1763 #define GMAC_FT_FTX(value) (GMAC_FT_FTX_Msk & ((value) << GMAC_FT_FTX_Pos)) 1764 #define GMAC_FT_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_FT) Register MASK (Use GMAC_FT_Msk instead) */ 1765 #define GMAC_FT_Msk _U_(0xFFFFFFFF) /**< (GMAC_FT) Register Mask */ 1766 1767 1768 /* -------- GMAC_BCFT : (GMAC Offset: 0x10c) (R/ 32) Broadcast Frames Transmitted Register -------- */ 1769 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1770 #if COMPONENT_TYPEDEF_STYLE == 'N' 1771 typedef union { 1772 struct { 1773 uint32_t BFTX:32; /**< bit: 0..31 Broadcast Frames Transmitted without Error */ 1774 } bit; /**< Structure used for bit access */ 1775 uint32_t reg; /**< Type used for register access */ 1776 } GMAC_BCFT_Type; 1777 #endif 1778 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1779 1780 #define GMAC_BCFT_OFFSET (0x10C) /**< (GMAC_BCFT) Broadcast Frames Transmitted Register Offset */ 1781 1782 #define GMAC_BCFT_BFTX_Pos 0 /**< (GMAC_BCFT) Broadcast Frames Transmitted without Error Position */ 1783 #define GMAC_BCFT_BFTX_Msk (_U_(0xFFFFFFFF) << GMAC_BCFT_BFTX_Pos) /**< (GMAC_BCFT) Broadcast Frames Transmitted without Error Mask */ 1784 #define GMAC_BCFT_BFTX(value) (GMAC_BCFT_BFTX_Msk & ((value) << GMAC_BCFT_BFTX_Pos)) 1785 #define GMAC_BCFT_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_BCFT) Register MASK (Use GMAC_BCFT_Msk instead) */ 1786 #define GMAC_BCFT_Msk _U_(0xFFFFFFFF) /**< (GMAC_BCFT) Register Mask */ 1787 1788 1789 /* -------- GMAC_MFT : (GMAC Offset: 0x110) (R/ 32) Multicast Frames Transmitted Register -------- */ 1790 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1791 #if COMPONENT_TYPEDEF_STYLE == 'N' 1792 typedef union { 1793 struct { 1794 uint32_t MFTX:32; /**< bit: 0..31 Multicast Frames Transmitted without Error */ 1795 } bit; /**< Structure used for bit access */ 1796 uint32_t reg; /**< Type used for register access */ 1797 } GMAC_MFT_Type; 1798 #endif 1799 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1800 1801 #define GMAC_MFT_OFFSET (0x110) /**< (GMAC_MFT) Multicast Frames Transmitted Register Offset */ 1802 1803 #define GMAC_MFT_MFTX_Pos 0 /**< (GMAC_MFT) Multicast Frames Transmitted without Error Position */ 1804 #define GMAC_MFT_MFTX_Msk (_U_(0xFFFFFFFF) << GMAC_MFT_MFTX_Pos) /**< (GMAC_MFT) Multicast Frames Transmitted without Error Mask */ 1805 #define GMAC_MFT_MFTX(value) (GMAC_MFT_MFTX_Msk & ((value) << GMAC_MFT_MFTX_Pos)) 1806 #define GMAC_MFT_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_MFT) Register MASK (Use GMAC_MFT_Msk instead) */ 1807 #define GMAC_MFT_Msk _U_(0xFFFFFFFF) /**< (GMAC_MFT) Register Mask */ 1808 1809 1810 /* -------- GMAC_PFT : (GMAC Offset: 0x114) (R/ 32) Pause Frames Transmitted Register -------- */ 1811 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1812 #if COMPONENT_TYPEDEF_STYLE == 'N' 1813 typedef union { 1814 struct { 1815 uint32_t PFTX:16; /**< bit: 0..15 Pause Frames Transmitted Register */ 1816 uint32_t :16; /**< bit: 16..31 Reserved */ 1817 } bit; /**< Structure used for bit access */ 1818 uint32_t reg; /**< Type used for register access */ 1819 } GMAC_PFT_Type; 1820 #endif 1821 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1822 1823 #define GMAC_PFT_OFFSET (0x114) /**< (GMAC_PFT) Pause Frames Transmitted Register Offset */ 1824 1825 #define GMAC_PFT_PFTX_Pos 0 /**< (GMAC_PFT) Pause Frames Transmitted Register Position */ 1826 #define GMAC_PFT_PFTX_Msk (_U_(0xFFFF) << GMAC_PFT_PFTX_Pos) /**< (GMAC_PFT) Pause Frames Transmitted Register Mask */ 1827 #define GMAC_PFT_PFTX(value) (GMAC_PFT_PFTX_Msk & ((value) << GMAC_PFT_PFTX_Pos)) 1828 #define GMAC_PFT_MASK _U_(0xFFFF) /**< \deprecated (GMAC_PFT) Register MASK (Use GMAC_PFT_Msk instead) */ 1829 #define GMAC_PFT_Msk _U_(0xFFFF) /**< (GMAC_PFT) Register Mask */ 1830 1831 1832 /* -------- GMAC_BFT64 : (GMAC Offset: 0x118) (R/ 32) 64 Byte Frames Transmitted Register -------- */ 1833 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1834 #if COMPONENT_TYPEDEF_STYLE == 'N' 1835 typedef union { 1836 struct { 1837 uint32_t NFTX:32; /**< bit: 0..31 64 Byte Frames Transmitted without Error */ 1838 } bit; /**< Structure used for bit access */ 1839 uint32_t reg; /**< Type used for register access */ 1840 } GMAC_BFT64_Type; 1841 #endif 1842 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1843 1844 #define GMAC_BFT64_OFFSET (0x118) /**< (GMAC_BFT64) 64 Byte Frames Transmitted Register Offset */ 1845 1846 #define GMAC_BFT64_NFTX_Pos 0 /**< (GMAC_BFT64) 64 Byte Frames Transmitted without Error Position */ 1847 #define GMAC_BFT64_NFTX_Msk (_U_(0xFFFFFFFF) << GMAC_BFT64_NFTX_Pos) /**< (GMAC_BFT64) 64 Byte Frames Transmitted without Error Mask */ 1848 #define GMAC_BFT64_NFTX(value) (GMAC_BFT64_NFTX_Msk & ((value) << GMAC_BFT64_NFTX_Pos)) 1849 #define GMAC_BFT64_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_BFT64) Register MASK (Use GMAC_BFT64_Msk instead) */ 1850 #define GMAC_BFT64_Msk _U_(0xFFFFFFFF) /**< (GMAC_BFT64) Register Mask */ 1851 1852 1853 /* -------- GMAC_TBFT127 : (GMAC Offset: 0x11c) (R/ 32) 65 to 127 Byte Frames Transmitted Register -------- */ 1854 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1855 #if COMPONENT_TYPEDEF_STYLE == 'N' 1856 typedef union { 1857 struct { 1858 uint32_t NFTX:32; /**< bit: 0..31 65 to 127 Byte Frames Transmitted without Error */ 1859 } bit; /**< Structure used for bit access */ 1860 uint32_t reg; /**< Type used for register access */ 1861 } GMAC_TBFT127_Type; 1862 #endif 1863 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1864 1865 #define GMAC_TBFT127_OFFSET (0x11C) /**< (GMAC_TBFT127) 65 to 127 Byte Frames Transmitted Register Offset */ 1866 1867 #define GMAC_TBFT127_NFTX_Pos 0 /**< (GMAC_TBFT127) 65 to 127 Byte Frames Transmitted without Error Position */ 1868 #define GMAC_TBFT127_NFTX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFT127_NFTX_Pos) /**< (GMAC_TBFT127) 65 to 127 Byte Frames Transmitted without Error Mask */ 1869 #define GMAC_TBFT127_NFTX(value) (GMAC_TBFT127_NFTX_Msk & ((value) << GMAC_TBFT127_NFTX_Pos)) 1870 #define GMAC_TBFT127_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_TBFT127) Register MASK (Use GMAC_TBFT127_Msk instead) */ 1871 #define GMAC_TBFT127_Msk _U_(0xFFFFFFFF) /**< (GMAC_TBFT127) Register Mask */ 1872 1873 1874 /* -------- GMAC_TBFT255 : (GMAC Offset: 0x120) (R/ 32) 128 to 255 Byte Frames Transmitted Register -------- */ 1875 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1876 #if COMPONENT_TYPEDEF_STYLE == 'N' 1877 typedef union { 1878 struct { 1879 uint32_t NFTX:32; /**< bit: 0..31 128 to 255 Byte Frames Transmitted without Error */ 1880 } bit; /**< Structure used for bit access */ 1881 uint32_t reg; /**< Type used for register access */ 1882 } GMAC_TBFT255_Type; 1883 #endif 1884 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1885 1886 #define GMAC_TBFT255_OFFSET (0x120) /**< (GMAC_TBFT255) 128 to 255 Byte Frames Transmitted Register Offset */ 1887 1888 #define GMAC_TBFT255_NFTX_Pos 0 /**< (GMAC_TBFT255) 128 to 255 Byte Frames Transmitted without Error Position */ 1889 #define GMAC_TBFT255_NFTX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFT255_NFTX_Pos) /**< (GMAC_TBFT255) 128 to 255 Byte Frames Transmitted without Error Mask */ 1890 #define GMAC_TBFT255_NFTX(value) (GMAC_TBFT255_NFTX_Msk & ((value) << GMAC_TBFT255_NFTX_Pos)) 1891 #define GMAC_TBFT255_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_TBFT255) Register MASK (Use GMAC_TBFT255_Msk instead) */ 1892 #define GMAC_TBFT255_Msk _U_(0xFFFFFFFF) /**< (GMAC_TBFT255) Register Mask */ 1893 1894 1895 /* -------- GMAC_TBFT511 : (GMAC Offset: 0x124) (R/ 32) 256 to 511 Byte Frames Transmitted Register -------- */ 1896 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1897 #if COMPONENT_TYPEDEF_STYLE == 'N' 1898 typedef union { 1899 struct { 1900 uint32_t NFTX:32; /**< bit: 0..31 256 to 511 Byte Frames Transmitted without Error */ 1901 } bit; /**< Structure used for bit access */ 1902 uint32_t reg; /**< Type used for register access */ 1903 } GMAC_TBFT511_Type; 1904 #endif 1905 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1906 1907 #define GMAC_TBFT511_OFFSET (0x124) /**< (GMAC_TBFT511) 256 to 511 Byte Frames Transmitted Register Offset */ 1908 1909 #define GMAC_TBFT511_NFTX_Pos 0 /**< (GMAC_TBFT511) 256 to 511 Byte Frames Transmitted without Error Position */ 1910 #define GMAC_TBFT511_NFTX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFT511_NFTX_Pos) /**< (GMAC_TBFT511) 256 to 511 Byte Frames Transmitted without Error Mask */ 1911 #define GMAC_TBFT511_NFTX(value) (GMAC_TBFT511_NFTX_Msk & ((value) << GMAC_TBFT511_NFTX_Pos)) 1912 #define GMAC_TBFT511_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_TBFT511) Register MASK (Use GMAC_TBFT511_Msk instead) */ 1913 #define GMAC_TBFT511_Msk _U_(0xFFFFFFFF) /**< (GMAC_TBFT511) Register Mask */ 1914 1915 1916 /* -------- GMAC_TBFT1023 : (GMAC Offset: 0x128) (R/ 32) 512 to 1023 Byte Frames Transmitted Register -------- */ 1917 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1918 #if COMPONENT_TYPEDEF_STYLE == 'N' 1919 typedef union { 1920 struct { 1921 uint32_t NFTX:32; /**< bit: 0..31 512 to 1023 Byte Frames Transmitted without Error */ 1922 } bit; /**< Structure used for bit access */ 1923 uint32_t reg; /**< Type used for register access */ 1924 } GMAC_TBFT1023_Type; 1925 #endif 1926 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1927 1928 #define GMAC_TBFT1023_OFFSET (0x128) /**< (GMAC_TBFT1023) 512 to 1023 Byte Frames Transmitted Register Offset */ 1929 1930 #define GMAC_TBFT1023_NFTX_Pos 0 /**< (GMAC_TBFT1023) 512 to 1023 Byte Frames Transmitted without Error Position */ 1931 #define GMAC_TBFT1023_NFTX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFT1023_NFTX_Pos) /**< (GMAC_TBFT1023) 512 to 1023 Byte Frames Transmitted without Error Mask */ 1932 #define GMAC_TBFT1023_NFTX(value) (GMAC_TBFT1023_NFTX_Msk & ((value) << GMAC_TBFT1023_NFTX_Pos)) 1933 #define GMAC_TBFT1023_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_TBFT1023) Register MASK (Use GMAC_TBFT1023_Msk instead) */ 1934 #define GMAC_TBFT1023_Msk _U_(0xFFFFFFFF) /**< (GMAC_TBFT1023) Register Mask */ 1935 1936 1937 /* -------- GMAC_TBFT1518 : (GMAC Offset: 0x12c) (R/ 32) 1024 to 1518 Byte Frames Transmitted Register -------- */ 1938 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1939 #if COMPONENT_TYPEDEF_STYLE == 'N' 1940 typedef union { 1941 struct { 1942 uint32_t NFTX:32; /**< bit: 0..31 1024 to 1518 Byte Frames Transmitted without Error */ 1943 } bit; /**< Structure used for bit access */ 1944 uint32_t reg; /**< Type used for register access */ 1945 } GMAC_TBFT1518_Type; 1946 #endif 1947 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1948 1949 #define GMAC_TBFT1518_OFFSET (0x12C) /**< (GMAC_TBFT1518) 1024 to 1518 Byte Frames Transmitted Register Offset */ 1950 1951 #define GMAC_TBFT1518_NFTX_Pos 0 /**< (GMAC_TBFT1518) 1024 to 1518 Byte Frames Transmitted without Error Position */ 1952 #define GMAC_TBFT1518_NFTX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFT1518_NFTX_Pos) /**< (GMAC_TBFT1518) 1024 to 1518 Byte Frames Transmitted without Error Mask */ 1953 #define GMAC_TBFT1518_NFTX(value) (GMAC_TBFT1518_NFTX_Msk & ((value) << GMAC_TBFT1518_NFTX_Pos)) 1954 #define GMAC_TBFT1518_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_TBFT1518) Register MASK (Use GMAC_TBFT1518_Msk instead) */ 1955 #define GMAC_TBFT1518_Msk _U_(0xFFFFFFFF) /**< (GMAC_TBFT1518) Register Mask */ 1956 1957 1958 /* -------- GMAC_GTBFT1518 : (GMAC Offset: 0x130) (R/ 32) Greater Than 1518 Byte Frames Transmitted Register -------- */ 1959 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1960 #if COMPONENT_TYPEDEF_STYLE == 'N' 1961 typedef union { 1962 struct { 1963 uint32_t NFTX:32; /**< bit: 0..31 Greater than 1518 Byte Frames Transmitted without Error */ 1964 } bit; /**< Structure used for bit access */ 1965 uint32_t reg; /**< Type used for register access */ 1966 } GMAC_GTBFT1518_Type; 1967 #endif 1968 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1969 1970 #define GMAC_GTBFT1518_OFFSET (0x130) /**< (GMAC_GTBFT1518) Greater Than 1518 Byte Frames Transmitted Register Offset */ 1971 1972 #define GMAC_GTBFT1518_NFTX_Pos 0 /**< (GMAC_GTBFT1518) Greater than 1518 Byte Frames Transmitted without Error Position */ 1973 #define GMAC_GTBFT1518_NFTX_Msk (_U_(0xFFFFFFFF) << GMAC_GTBFT1518_NFTX_Pos) /**< (GMAC_GTBFT1518) Greater than 1518 Byte Frames Transmitted without Error Mask */ 1974 #define GMAC_GTBFT1518_NFTX(value) (GMAC_GTBFT1518_NFTX_Msk & ((value) << GMAC_GTBFT1518_NFTX_Pos)) 1975 #define GMAC_GTBFT1518_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_GTBFT1518) Register MASK (Use GMAC_GTBFT1518_Msk instead) */ 1976 #define GMAC_GTBFT1518_Msk _U_(0xFFFFFFFF) /**< (GMAC_GTBFT1518) Register Mask */ 1977 1978 1979 /* -------- GMAC_TUR : (GMAC Offset: 0x134) (R/ 32) Transmit Underruns Register -------- */ 1980 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1981 #if COMPONENT_TYPEDEF_STYLE == 'N' 1982 typedef union { 1983 struct { 1984 uint32_t TXUNR:10; /**< bit: 0..9 Transmit Underruns */ 1985 uint32_t :22; /**< bit: 10..31 Reserved */ 1986 } bit; /**< Structure used for bit access */ 1987 uint32_t reg; /**< Type used for register access */ 1988 } GMAC_TUR_Type; 1989 #endif 1990 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1991 1992 #define GMAC_TUR_OFFSET (0x134) /**< (GMAC_TUR) Transmit Underruns Register Offset */ 1993 1994 #define GMAC_TUR_TXUNR_Pos 0 /**< (GMAC_TUR) Transmit Underruns Position */ 1995 #define GMAC_TUR_TXUNR_Msk (_U_(0x3FF) << GMAC_TUR_TXUNR_Pos) /**< (GMAC_TUR) Transmit Underruns Mask */ 1996 #define GMAC_TUR_TXUNR(value) (GMAC_TUR_TXUNR_Msk & ((value) << GMAC_TUR_TXUNR_Pos)) 1997 #define GMAC_TUR_MASK _U_(0x3FF) /**< \deprecated (GMAC_TUR) Register MASK (Use GMAC_TUR_Msk instead) */ 1998 #define GMAC_TUR_Msk _U_(0x3FF) /**< (GMAC_TUR) Register Mask */ 1999 2000 2001 /* -------- GMAC_SCF : (GMAC Offset: 0x138) (R/ 32) Single Collision Frames Register -------- */ 2002 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2003 #if COMPONENT_TYPEDEF_STYLE == 'N' 2004 typedef union { 2005 struct { 2006 uint32_t SCOL:18; /**< bit: 0..17 Single Collision */ 2007 uint32_t :14; /**< bit: 18..31 Reserved */ 2008 } bit; /**< Structure used for bit access */ 2009 uint32_t reg; /**< Type used for register access */ 2010 } GMAC_SCF_Type; 2011 #endif 2012 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2013 2014 #define GMAC_SCF_OFFSET (0x138) /**< (GMAC_SCF) Single Collision Frames Register Offset */ 2015 2016 #define GMAC_SCF_SCOL_Pos 0 /**< (GMAC_SCF) Single Collision Position */ 2017 #define GMAC_SCF_SCOL_Msk (_U_(0x3FFFF) << GMAC_SCF_SCOL_Pos) /**< (GMAC_SCF) Single Collision Mask */ 2018 #define GMAC_SCF_SCOL(value) (GMAC_SCF_SCOL_Msk & ((value) << GMAC_SCF_SCOL_Pos)) 2019 #define GMAC_SCF_MASK _U_(0x3FFFF) /**< \deprecated (GMAC_SCF) Register MASK (Use GMAC_SCF_Msk instead) */ 2020 #define GMAC_SCF_Msk _U_(0x3FFFF) /**< (GMAC_SCF) Register Mask */ 2021 2022 2023 /* -------- GMAC_MCF : (GMAC Offset: 0x13c) (R/ 32) Multiple Collision Frames Register -------- */ 2024 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2025 #if COMPONENT_TYPEDEF_STYLE == 'N' 2026 typedef union { 2027 struct { 2028 uint32_t MCOL:18; /**< bit: 0..17 Multiple Collision */ 2029 uint32_t :14; /**< bit: 18..31 Reserved */ 2030 } bit; /**< Structure used for bit access */ 2031 uint32_t reg; /**< Type used for register access */ 2032 } GMAC_MCF_Type; 2033 #endif 2034 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2035 2036 #define GMAC_MCF_OFFSET (0x13C) /**< (GMAC_MCF) Multiple Collision Frames Register Offset */ 2037 2038 #define GMAC_MCF_MCOL_Pos 0 /**< (GMAC_MCF) Multiple Collision Position */ 2039 #define GMAC_MCF_MCOL_Msk (_U_(0x3FFFF) << GMAC_MCF_MCOL_Pos) /**< (GMAC_MCF) Multiple Collision Mask */ 2040 #define GMAC_MCF_MCOL(value) (GMAC_MCF_MCOL_Msk & ((value) << GMAC_MCF_MCOL_Pos)) 2041 #define GMAC_MCF_MASK _U_(0x3FFFF) /**< \deprecated (GMAC_MCF) Register MASK (Use GMAC_MCF_Msk instead) */ 2042 #define GMAC_MCF_Msk _U_(0x3FFFF) /**< (GMAC_MCF) Register Mask */ 2043 2044 2045 /* -------- GMAC_EC : (GMAC Offset: 0x140) (R/ 32) Excessive Collisions Register -------- */ 2046 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2047 #if COMPONENT_TYPEDEF_STYLE == 'N' 2048 typedef union { 2049 struct { 2050 uint32_t XCOL:10; /**< bit: 0..9 Excessive Collisions */ 2051 uint32_t :22; /**< bit: 10..31 Reserved */ 2052 } bit; /**< Structure used for bit access */ 2053 uint32_t reg; /**< Type used for register access */ 2054 } GMAC_EC_Type; 2055 #endif 2056 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2057 2058 #define GMAC_EC_OFFSET (0x140) /**< (GMAC_EC) Excessive Collisions Register Offset */ 2059 2060 #define GMAC_EC_XCOL_Pos 0 /**< (GMAC_EC) Excessive Collisions Position */ 2061 #define GMAC_EC_XCOL_Msk (_U_(0x3FF) << GMAC_EC_XCOL_Pos) /**< (GMAC_EC) Excessive Collisions Mask */ 2062 #define GMAC_EC_XCOL(value) (GMAC_EC_XCOL_Msk & ((value) << GMAC_EC_XCOL_Pos)) 2063 #define GMAC_EC_MASK _U_(0x3FF) /**< \deprecated (GMAC_EC) Register MASK (Use GMAC_EC_Msk instead) */ 2064 #define GMAC_EC_Msk _U_(0x3FF) /**< (GMAC_EC) Register Mask */ 2065 2066 2067 /* -------- GMAC_LC : (GMAC Offset: 0x144) (R/ 32) Late Collisions Register -------- */ 2068 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2069 #if COMPONENT_TYPEDEF_STYLE == 'N' 2070 typedef union { 2071 struct { 2072 uint32_t LCOL:10; /**< bit: 0..9 Late Collisions */ 2073 uint32_t :22; /**< bit: 10..31 Reserved */ 2074 } bit; /**< Structure used for bit access */ 2075 uint32_t reg; /**< Type used for register access */ 2076 } GMAC_LC_Type; 2077 #endif 2078 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2079 2080 #define GMAC_LC_OFFSET (0x144) /**< (GMAC_LC) Late Collisions Register Offset */ 2081 2082 #define GMAC_LC_LCOL_Pos 0 /**< (GMAC_LC) Late Collisions Position */ 2083 #define GMAC_LC_LCOL_Msk (_U_(0x3FF) << GMAC_LC_LCOL_Pos) /**< (GMAC_LC) Late Collisions Mask */ 2084 #define GMAC_LC_LCOL(value) (GMAC_LC_LCOL_Msk & ((value) << GMAC_LC_LCOL_Pos)) 2085 #define GMAC_LC_MASK _U_(0x3FF) /**< \deprecated (GMAC_LC) Register MASK (Use GMAC_LC_Msk instead) */ 2086 #define GMAC_LC_Msk _U_(0x3FF) /**< (GMAC_LC) Register Mask */ 2087 2088 2089 /* -------- GMAC_DTF : (GMAC Offset: 0x148) (R/ 32) Deferred Transmission Frames Register -------- */ 2090 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2091 #if COMPONENT_TYPEDEF_STYLE == 'N' 2092 typedef union { 2093 struct { 2094 uint32_t DEFT:18; /**< bit: 0..17 Deferred Transmission */ 2095 uint32_t :14; /**< bit: 18..31 Reserved */ 2096 } bit; /**< Structure used for bit access */ 2097 uint32_t reg; /**< Type used for register access */ 2098 } GMAC_DTF_Type; 2099 #endif 2100 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2101 2102 #define GMAC_DTF_OFFSET (0x148) /**< (GMAC_DTF) Deferred Transmission Frames Register Offset */ 2103 2104 #define GMAC_DTF_DEFT_Pos 0 /**< (GMAC_DTF) Deferred Transmission Position */ 2105 #define GMAC_DTF_DEFT_Msk (_U_(0x3FFFF) << GMAC_DTF_DEFT_Pos) /**< (GMAC_DTF) Deferred Transmission Mask */ 2106 #define GMAC_DTF_DEFT(value) (GMAC_DTF_DEFT_Msk & ((value) << GMAC_DTF_DEFT_Pos)) 2107 #define GMAC_DTF_MASK _U_(0x3FFFF) /**< \deprecated (GMAC_DTF) Register MASK (Use GMAC_DTF_Msk instead) */ 2108 #define GMAC_DTF_Msk _U_(0x3FFFF) /**< (GMAC_DTF) Register Mask */ 2109 2110 2111 /* -------- GMAC_CSE : (GMAC Offset: 0x14c) (R/ 32) Carrier Sense Errors Register -------- */ 2112 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2113 #if COMPONENT_TYPEDEF_STYLE == 'N' 2114 typedef union { 2115 struct { 2116 uint32_t CSR:10; /**< bit: 0..9 Carrier Sense Error */ 2117 uint32_t :22; /**< bit: 10..31 Reserved */ 2118 } bit; /**< Structure used for bit access */ 2119 uint32_t reg; /**< Type used for register access */ 2120 } GMAC_CSE_Type; 2121 #endif 2122 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2123 2124 #define GMAC_CSE_OFFSET (0x14C) /**< (GMAC_CSE) Carrier Sense Errors Register Offset */ 2125 2126 #define GMAC_CSE_CSR_Pos 0 /**< (GMAC_CSE) Carrier Sense Error Position */ 2127 #define GMAC_CSE_CSR_Msk (_U_(0x3FF) << GMAC_CSE_CSR_Pos) /**< (GMAC_CSE) Carrier Sense Error Mask */ 2128 #define GMAC_CSE_CSR(value) (GMAC_CSE_CSR_Msk & ((value) << GMAC_CSE_CSR_Pos)) 2129 #define GMAC_CSE_MASK _U_(0x3FF) /**< \deprecated (GMAC_CSE) Register MASK (Use GMAC_CSE_Msk instead) */ 2130 #define GMAC_CSE_Msk _U_(0x3FF) /**< (GMAC_CSE) Register Mask */ 2131 2132 2133 /* -------- GMAC_ORLO : (GMAC Offset: 0x150) (R/ 32) Octets Received Low Received Register -------- */ 2134 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2135 #if COMPONENT_TYPEDEF_STYLE == 'N' 2136 typedef union { 2137 struct { 2138 uint32_t RXO:32; /**< bit: 0..31 Received Octets */ 2139 } bit; /**< Structure used for bit access */ 2140 uint32_t reg; /**< Type used for register access */ 2141 } GMAC_ORLO_Type; 2142 #endif 2143 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2144 2145 #define GMAC_ORLO_OFFSET (0x150) /**< (GMAC_ORLO) Octets Received Low Received Register Offset */ 2146 2147 #define GMAC_ORLO_RXO_Pos 0 /**< (GMAC_ORLO) Received Octets Position */ 2148 #define GMAC_ORLO_RXO_Msk (_U_(0xFFFFFFFF) << GMAC_ORLO_RXO_Pos) /**< (GMAC_ORLO) Received Octets Mask */ 2149 #define GMAC_ORLO_RXO(value) (GMAC_ORLO_RXO_Msk & ((value) << GMAC_ORLO_RXO_Pos)) 2150 #define GMAC_ORLO_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_ORLO) Register MASK (Use GMAC_ORLO_Msk instead) */ 2151 #define GMAC_ORLO_Msk _U_(0xFFFFFFFF) /**< (GMAC_ORLO) Register Mask */ 2152 2153 2154 /* -------- GMAC_ORHI : (GMAC Offset: 0x154) (R/ 32) Octets Received High Received Register -------- */ 2155 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2156 #if COMPONENT_TYPEDEF_STYLE == 'N' 2157 typedef union { 2158 struct { 2159 uint32_t RXO:16; /**< bit: 0..15 Received Octets */ 2160 uint32_t :16; /**< bit: 16..31 Reserved */ 2161 } bit; /**< Structure used for bit access */ 2162 uint32_t reg; /**< Type used for register access */ 2163 } GMAC_ORHI_Type; 2164 #endif 2165 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2166 2167 #define GMAC_ORHI_OFFSET (0x154) /**< (GMAC_ORHI) Octets Received High Received Register Offset */ 2168 2169 #define GMAC_ORHI_RXO_Pos 0 /**< (GMAC_ORHI) Received Octets Position */ 2170 #define GMAC_ORHI_RXO_Msk (_U_(0xFFFF) << GMAC_ORHI_RXO_Pos) /**< (GMAC_ORHI) Received Octets Mask */ 2171 #define GMAC_ORHI_RXO(value) (GMAC_ORHI_RXO_Msk & ((value) << GMAC_ORHI_RXO_Pos)) 2172 #define GMAC_ORHI_MASK _U_(0xFFFF) /**< \deprecated (GMAC_ORHI) Register MASK (Use GMAC_ORHI_Msk instead) */ 2173 #define GMAC_ORHI_Msk _U_(0xFFFF) /**< (GMAC_ORHI) Register Mask */ 2174 2175 2176 /* -------- GMAC_FR : (GMAC Offset: 0x158) (R/ 32) Frames Received Register -------- */ 2177 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2178 #if COMPONENT_TYPEDEF_STYLE == 'N' 2179 typedef union { 2180 struct { 2181 uint32_t FRX:32; /**< bit: 0..31 Frames Received without Error */ 2182 } bit; /**< Structure used for bit access */ 2183 uint32_t reg; /**< Type used for register access */ 2184 } GMAC_FR_Type; 2185 #endif 2186 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2187 2188 #define GMAC_FR_OFFSET (0x158) /**< (GMAC_FR) Frames Received Register Offset */ 2189 2190 #define GMAC_FR_FRX_Pos 0 /**< (GMAC_FR) Frames Received without Error Position */ 2191 #define GMAC_FR_FRX_Msk (_U_(0xFFFFFFFF) << GMAC_FR_FRX_Pos) /**< (GMAC_FR) Frames Received without Error Mask */ 2192 #define GMAC_FR_FRX(value) (GMAC_FR_FRX_Msk & ((value) << GMAC_FR_FRX_Pos)) 2193 #define GMAC_FR_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_FR) Register MASK (Use GMAC_FR_Msk instead) */ 2194 #define GMAC_FR_Msk _U_(0xFFFFFFFF) /**< (GMAC_FR) Register Mask */ 2195 2196 2197 /* -------- GMAC_BCFR : (GMAC Offset: 0x15c) (R/ 32) Broadcast Frames Received Register -------- */ 2198 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2199 #if COMPONENT_TYPEDEF_STYLE == 'N' 2200 typedef union { 2201 struct { 2202 uint32_t BFRX:32; /**< bit: 0..31 Broadcast Frames Received without Error */ 2203 } bit; /**< Structure used for bit access */ 2204 uint32_t reg; /**< Type used for register access */ 2205 } GMAC_BCFR_Type; 2206 #endif 2207 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2208 2209 #define GMAC_BCFR_OFFSET (0x15C) /**< (GMAC_BCFR) Broadcast Frames Received Register Offset */ 2210 2211 #define GMAC_BCFR_BFRX_Pos 0 /**< (GMAC_BCFR) Broadcast Frames Received without Error Position */ 2212 #define GMAC_BCFR_BFRX_Msk (_U_(0xFFFFFFFF) << GMAC_BCFR_BFRX_Pos) /**< (GMAC_BCFR) Broadcast Frames Received without Error Mask */ 2213 #define GMAC_BCFR_BFRX(value) (GMAC_BCFR_BFRX_Msk & ((value) << GMAC_BCFR_BFRX_Pos)) 2214 #define GMAC_BCFR_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_BCFR) Register MASK (Use GMAC_BCFR_Msk instead) */ 2215 #define GMAC_BCFR_Msk _U_(0xFFFFFFFF) /**< (GMAC_BCFR) Register Mask */ 2216 2217 2218 /* -------- GMAC_MFR : (GMAC Offset: 0x160) (R/ 32) Multicast Frames Received Register -------- */ 2219 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2220 #if COMPONENT_TYPEDEF_STYLE == 'N' 2221 typedef union { 2222 struct { 2223 uint32_t MFRX:32; /**< bit: 0..31 Multicast Frames Received without Error */ 2224 } bit; /**< Structure used for bit access */ 2225 uint32_t reg; /**< Type used for register access */ 2226 } GMAC_MFR_Type; 2227 #endif 2228 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2229 2230 #define GMAC_MFR_OFFSET (0x160) /**< (GMAC_MFR) Multicast Frames Received Register Offset */ 2231 2232 #define GMAC_MFR_MFRX_Pos 0 /**< (GMAC_MFR) Multicast Frames Received without Error Position */ 2233 #define GMAC_MFR_MFRX_Msk (_U_(0xFFFFFFFF) << GMAC_MFR_MFRX_Pos) /**< (GMAC_MFR) Multicast Frames Received without Error Mask */ 2234 #define GMAC_MFR_MFRX(value) (GMAC_MFR_MFRX_Msk & ((value) << GMAC_MFR_MFRX_Pos)) 2235 #define GMAC_MFR_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_MFR) Register MASK (Use GMAC_MFR_Msk instead) */ 2236 #define GMAC_MFR_Msk _U_(0xFFFFFFFF) /**< (GMAC_MFR) Register Mask */ 2237 2238 2239 /* -------- GMAC_PFR : (GMAC Offset: 0x164) (R/ 32) Pause Frames Received Register -------- */ 2240 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2241 #if COMPONENT_TYPEDEF_STYLE == 'N' 2242 typedef union { 2243 struct { 2244 uint32_t PFRX:16; /**< bit: 0..15 Pause Frames Received Register */ 2245 uint32_t :16; /**< bit: 16..31 Reserved */ 2246 } bit; /**< Structure used for bit access */ 2247 uint32_t reg; /**< Type used for register access */ 2248 } GMAC_PFR_Type; 2249 #endif 2250 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2251 2252 #define GMAC_PFR_OFFSET (0x164) /**< (GMAC_PFR) Pause Frames Received Register Offset */ 2253 2254 #define GMAC_PFR_PFRX_Pos 0 /**< (GMAC_PFR) Pause Frames Received Register Position */ 2255 #define GMAC_PFR_PFRX_Msk (_U_(0xFFFF) << GMAC_PFR_PFRX_Pos) /**< (GMAC_PFR) Pause Frames Received Register Mask */ 2256 #define GMAC_PFR_PFRX(value) (GMAC_PFR_PFRX_Msk & ((value) << GMAC_PFR_PFRX_Pos)) 2257 #define GMAC_PFR_MASK _U_(0xFFFF) /**< \deprecated (GMAC_PFR) Register MASK (Use GMAC_PFR_Msk instead) */ 2258 #define GMAC_PFR_Msk _U_(0xFFFF) /**< (GMAC_PFR) Register Mask */ 2259 2260 2261 /* -------- GMAC_BFR64 : (GMAC Offset: 0x168) (R/ 32) 64 Byte Frames Received Register -------- */ 2262 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2263 #if COMPONENT_TYPEDEF_STYLE == 'N' 2264 typedef union { 2265 struct { 2266 uint32_t NFRX:32; /**< bit: 0..31 64 Byte Frames Received without Error */ 2267 } bit; /**< Structure used for bit access */ 2268 uint32_t reg; /**< Type used for register access */ 2269 } GMAC_BFR64_Type; 2270 #endif 2271 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2272 2273 #define GMAC_BFR64_OFFSET (0x168) /**< (GMAC_BFR64) 64 Byte Frames Received Register Offset */ 2274 2275 #define GMAC_BFR64_NFRX_Pos 0 /**< (GMAC_BFR64) 64 Byte Frames Received without Error Position */ 2276 #define GMAC_BFR64_NFRX_Msk (_U_(0xFFFFFFFF) << GMAC_BFR64_NFRX_Pos) /**< (GMAC_BFR64) 64 Byte Frames Received without Error Mask */ 2277 #define GMAC_BFR64_NFRX(value) (GMAC_BFR64_NFRX_Msk & ((value) << GMAC_BFR64_NFRX_Pos)) 2278 #define GMAC_BFR64_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_BFR64) Register MASK (Use GMAC_BFR64_Msk instead) */ 2279 #define GMAC_BFR64_Msk _U_(0xFFFFFFFF) /**< (GMAC_BFR64) Register Mask */ 2280 2281 2282 /* -------- GMAC_TBFR127 : (GMAC Offset: 0x16c) (R/ 32) 65 to 127 Byte Frames Received Register -------- */ 2283 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2284 #if COMPONENT_TYPEDEF_STYLE == 'N' 2285 typedef union { 2286 struct { 2287 uint32_t NFRX:32; /**< bit: 0..31 65 to 127 Byte Frames Received without Error */ 2288 } bit; /**< Structure used for bit access */ 2289 uint32_t reg; /**< Type used for register access */ 2290 } GMAC_TBFR127_Type; 2291 #endif 2292 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2293 2294 #define GMAC_TBFR127_OFFSET (0x16C) /**< (GMAC_TBFR127) 65 to 127 Byte Frames Received Register Offset */ 2295 2296 #define GMAC_TBFR127_NFRX_Pos 0 /**< (GMAC_TBFR127) 65 to 127 Byte Frames Received without Error Position */ 2297 #define GMAC_TBFR127_NFRX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFR127_NFRX_Pos) /**< (GMAC_TBFR127) 65 to 127 Byte Frames Received without Error Mask */ 2298 #define GMAC_TBFR127_NFRX(value) (GMAC_TBFR127_NFRX_Msk & ((value) << GMAC_TBFR127_NFRX_Pos)) 2299 #define GMAC_TBFR127_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_TBFR127) Register MASK (Use GMAC_TBFR127_Msk instead) */ 2300 #define GMAC_TBFR127_Msk _U_(0xFFFFFFFF) /**< (GMAC_TBFR127) Register Mask */ 2301 2302 2303 /* -------- GMAC_TBFR255 : (GMAC Offset: 0x170) (R/ 32) 128 to 255 Byte Frames Received Register -------- */ 2304 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2305 #if COMPONENT_TYPEDEF_STYLE == 'N' 2306 typedef union { 2307 struct { 2308 uint32_t NFRX:32; /**< bit: 0..31 128 to 255 Byte Frames Received without Error */ 2309 } bit; /**< Structure used for bit access */ 2310 uint32_t reg; /**< Type used for register access */ 2311 } GMAC_TBFR255_Type; 2312 #endif 2313 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2314 2315 #define GMAC_TBFR255_OFFSET (0x170) /**< (GMAC_TBFR255) 128 to 255 Byte Frames Received Register Offset */ 2316 2317 #define GMAC_TBFR255_NFRX_Pos 0 /**< (GMAC_TBFR255) 128 to 255 Byte Frames Received without Error Position */ 2318 #define GMAC_TBFR255_NFRX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFR255_NFRX_Pos) /**< (GMAC_TBFR255) 128 to 255 Byte Frames Received without Error Mask */ 2319 #define GMAC_TBFR255_NFRX(value) (GMAC_TBFR255_NFRX_Msk & ((value) << GMAC_TBFR255_NFRX_Pos)) 2320 #define GMAC_TBFR255_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_TBFR255) Register MASK (Use GMAC_TBFR255_Msk instead) */ 2321 #define GMAC_TBFR255_Msk _U_(0xFFFFFFFF) /**< (GMAC_TBFR255) Register Mask */ 2322 2323 2324 /* -------- GMAC_TBFR511 : (GMAC Offset: 0x174) (R/ 32) 256 to 511 Byte Frames Received Register -------- */ 2325 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2326 #if COMPONENT_TYPEDEF_STYLE == 'N' 2327 typedef union { 2328 struct { 2329 uint32_t NFRX:32; /**< bit: 0..31 256 to 511 Byte Frames Received without Error */ 2330 } bit; /**< Structure used for bit access */ 2331 uint32_t reg; /**< Type used for register access */ 2332 } GMAC_TBFR511_Type; 2333 #endif 2334 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2335 2336 #define GMAC_TBFR511_OFFSET (0x174) /**< (GMAC_TBFR511) 256 to 511 Byte Frames Received Register Offset */ 2337 2338 #define GMAC_TBFR511_NFRX_Pos 0 /**< (GMAC_TBFR511) 256 to 511 Byte Frames Received without Error Position */ 2339 #define GMAC_TBFR511_NFRX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFR511_NFRX_Pos) /**< (GMAC_TBFR511) 256 to 511 Byte Frames Received without Error Mask */ 2340 #define GMAC_TBFR511_NFRX(value) (GMAC_TBFR511_NFRX_Msk & ((value) << GMAC_TBFR511_NFRX_Pos)) 2341 #define GMAC_TBFR511_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_TBFR511) Register MASK (Use GMAC_TBFR511_Msk instead) */ 2342 #define GMAC_TBFR511_Msk _U_(0xFFFFFFFF) /**< (GMAC_TBFR511) Register Mask */ 2343 2344 2345 /* -------- GMAC_TBFR1023 : (GMAC Offset: 0x178) (R/ 32) 512 to 1023 Byte Frames Received Register -------- */ 2346 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2347 #if COMPONENT_TYPEDEF_STYLE == 'N' 2348 typedef union { 2349 struct { 2350 uint32_t NFRX:32; /**< bit: 0..31 512 to 1023 Byte Frames Received without Error */ 2351 } bit; /**< Structure used for bit access */ 2352 uint32_t reg; /**< Type used for register access */ 2353 } GMAC_TBFR1023_Type; 2354 #endif 2355 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2356 2357 #define GMAC_TBFR1023_OFFSET (0x178) /**< (GMAC_TBFR1023) 512 to 1023 Byte Frames Received Register Offset */ 2358 2359 #define GMAC_TBFR1023_NFRX_Pos 0 /**< (GMAC_TBFR1023) 512 to 1023 Byte Frames Received without Error Position */ 2360 #define GMAC_TBFR1023_NFRX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFR1023_NFRX_Pos) /**< (GMAC_TBFR1023) 512 to 1023 Byte Frames Received without Error Mask */ 2361 #define GMAC_TBFR1023_NFRX(value) (GMAC_TBFR1023_NFRX_Msk & ((value) << GMAC_TBFR1023_NFRX_Pos)) 2362 #define GMAC_TBFR1023_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_TBFR1023) Register MASK (Use GMAC_TBFR1023_Msk instead) */ 2363 #define GMAC_TBFR1023_Msk _U_(0xFFFFFFFF) /**< (GMAC_TBFR1023) Register Mask */ 2364 2365 2366 /* -------- GMAC_TBFR1518 : (GMAC Offset: 0x17c) (R/ 32) 1024 to 1518 Byte Frames Received Register -------- */ 2367 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2368 #if COMPONENT_TYPEDEF_STYLE == 'N' 2369 typedef union { 2370 struct { 2371 uint32_t NFRX:32; /**< bit: 0..31 1024 to 1518 Byte Frames Received without Error */ 2372 } bit; /**< Structure used for bit access */ 2373 uint32_t reg; /**< Type used for register access */ 2374 } GMAC_TBFR1518_Type; 2375 #endif 2376 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2377 2378 #define GMAC_TBFR1518_OFFSET (0x17C) /**< (GMAC_TBFR1518) 1024 to 1518 Byte Frames Received Register Offset */ 2379 2380 #define GMAC_TBFR1518_NFRX_Pos 0 /**< (GMAC_TBFR1518) 1024 to 1518 Byte Frames Received without Error Position */ 2381 #define GMAC_TBFR1518_NFRX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFR1518_NFRX_Pos) /**< (GMAC_TBFR1518) 1024 to 1518 Byte Frames Received without Error Mask */ 2382 #define GMAC_TBFR1518_NFRX(value) (GMAC_TBFR1518_NFRX_Msk & ((value) << GMAC_TBFR1518_NFRX_Pos)) 2383 #define GMAC_TBFR1518_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_TBFR1518) Register MASK (Use GMAC_TBFR1518_Msk instead) */ 2384 #define GMAC_TBFR1518_Msk _U_(0xFFFFFFFF) /**< (GMAC_TBFR1518) Register Mask */ 2385 2386 2387 /* -------- GMAC_TMXBFR : (GMAC Offset: 0x180) (R/ 32) 1519 to Maximum Byte Frames Received Register -------- */ 2388 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2389 #if COMPONENT_TYPEDEF_STYLE == 'N' 2390 typedef union { 2391 struct { 2392 uint32_t NFRX:32; /**< bit: 0..31 1519 to Maximum Byte Frames Received without Error */ 2393 } bit; /**< Structure used for bit access */ 2394 uint32_t reg; /**< Type used for register access */ 2395 } GMAC_TMXBFR_Type; 2396 #endif 2397 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2398 2399 #define GMAC_TMXBFR_OFFSET (0x180) /**< (GMAC_TMXBFR) 1519 to Maximum Byte Frames Received Register Offset */ 2400 2401 #define GMAC_TMXBFR_NFRX_Pos 0 /**< (GMAC_TMXBFR) 1519 to Maximum Byte Frames Received without Error Position */ 2402 #define GMAC_TMXBFR_NFRX_Msk (_U_(0xFFFFFFFF) << GMAC_TMXBFR_NFRX_Pos) /**< (GMAC_TMXBFR) 1519 to Maximum Byte Frames Received without Error Mask */ 2403 #define GMAC_TMXBFR_NFRX(value) (GMAC_TMXBFR_NFRX_Msk & ((value) << GMAC_TMXBFR_NFRX_Pos)) 2404 #define GMAC_TMXBFR_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_TMXBFR) Register MASK (Use GMAC_TMXBFR_Msk instead) */ 2405 #define GMAC_TMXBFR_Msk _U_(0xFFFFFFFF) /**< (GMAC_TMXBFR) Register Mask */ 2406 2407 2408 /* -------- GMAC_UFR : (GMAC Offset: 0x184) (R/ 32) Undersize Frames Received Register -------- */ 2409 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2410 #if COMPONENT_TYPEDEF_STYLE == 'N' 2411 typedef union { 2412 struct { 2413 uint32_t UFRX:10; /**< bit: 0..9 Undersize Frames Received */ 2414 uint32_t :22; /**< bit: 10..31 Reserved */ 2415 } bit; /**< Structure used for bit access */ 2416 uint32_t reg; /**< Type used for register access */ 2417 } GMAC_UFR_Type; 2418 #endif 2419 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2420 2421 #define GMAC_UFR_OFFSET (0x184) /**< (GMAC_UFR) Undersize Frames Received Register Offset */ 2422 2423 #define GMAC_UFR_UFRX_Pos 0 /**< (GMAC_UFR) Undersize Frames Received Position */ 2424 #define GMAC_UFR_UFRX_Msk (_U_(0x3FF) << GMAC_UFR_UFRX_Pos) /**< (GMAC_UFR) Undersize Frames Received Mask */ 2425 #define GMAC_UFR_UFRX(value) (GMAC_UFR_UFRX_Msk & ((value) << GMAC_UFR_UFRX_Pos)) 2426 #define GMAC_UFR_MASK _U_(0x3FF) /**< \deprecated (GMAC_UFR) Register MASK (Use GMAC_UFR_Msk instead) */ 2427 #define GMAC_UFR_Msk _U_(0x3FF) /**< (GMAC_UFR) Register Mask */ 2428 2429 2430 /* -------- GMAC_OFR : (GMAC Offset: 0x188) (R/ 32) Oversize Frames Received Register -------- */ 2431 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2432 #if COMPONENT_TYPEDEF_STYLE == 'N' 2433 typedef union { 2434 struct { 2435 uint32_t OFRX:10; /**< bit: 0..9 Oversized Frames Received */ 2436 uint32_t :22; /**< bit: 10..31 Reserved */ 2437 } bit; /**< Structure used for bit access */ 2438 uint32_t reg; /**< Type used for register access */ 2439 } GMAC_OFR_Type; 2440 #endif 2441 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2442 2443 #define GMAC_OFR_OFFSET (0x188) /**< (GMAC_OFR) Oversize Frames Received Register Offset */ 2444 2445 #define GMAC_OFR_OFRX_Pos 0 /**< (GMAC_OFR) Oversized Frames Received Position */ 2446 #define GMAC_OFR_OFRX_Msk (_U_(0x3FF) << GMAC_OFR_OFRX_Pos) /**< (GMAC_OFR) Oversized Frames Received Mask */ 2447 #define GMAC_OFR_OFRX(value) (GMAC_OFR_OFRX_Msk & ((value) << GMAC_OFR_OFRX_Pos)) 2448 #define GMAC_OFR_MASK _U_(0x3FF) /**< \deprecated (GMAC_OFR) Register MASK (Use GMAC_OFR_Msk instead) */ 2449 #define GMAC_OFR_Msk _U_(0x3FF) /**< (GMAC_OFR) Register Mask */ 2450 2451 2452 /* -------- GMAC_JR : (GMAC Offset: 0x18c) (R/ 32) Jabbers Received Register -------- */ 2453 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2454 #if COMPONENT_TYPEDEF_STYLE == 'N' 2455 typedef union { 2456 struct { 2457 uint32_t JRX:10; /**< bit: 0..9 Jabbers Received */ 2458 uint32_t :22; /**< bit: 10..31 Reserved */ 2459 } bit; /**< Structure used for bit access */ 2460 uint32_t reg; /**< Type used for register access */ 2461 } GMAC_JR_Type; 2462 #endif 2463 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2464 2465 #define GMAC_JR_OFFSET (0x18C) /**< (GMAC_JR) Jabbers Received Register Offset */ 2466 2467 #define GMAC_JR_JRX_Pos 0 /**< (GMAC_JR) Jabbers Received Position */ 2468 #define GMAC_JR_JRX_Msk (_U_(0x3FF) << GMAC_JR_JRX_Pos) /**< (GMAC_JR) Jabbers Received Mask */ 2469 #define GMAC_JR_JRX(value) (GMAC_JR_JRX_Msk & ((value) << GMAC_JR_JRX_Pos)) 2470 #define GMAC_JR_MASK _U_(0x3FF) /**< \deprecated (GMAC_JR) Register MASK (Use GMAC_JR_Msk instead) */ 2471 #define GMAC_JR_Msk _U_(0x3FF) /**< (GMAC_JR) Register Mask */ 2472 2473 2474 /* -------- GMAC_FCSE : (GMAC Offset: 0x190) (R/ 32) Frame Check Sequence Errors Register -------- */ 2475 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2476 #if COMPONENT_TYPEDEF_STYLE == 'N' 2477 typedef union { 2478 struct { 2479 uint32_t FCKR:10; /**< bit: 0..9 Frame Check Sequence Errors */ 2480 uint32_t :22; /**< bit: 10..31 Reserved */ 2481 } bit; /**< Structure used for bit access */ 2482 uint32_t reg; /**< Type used for register access */ 2483 } GMAC_FCSE_Type; 2484 #endif 2485 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2486 2487 #define GMAC_FCSE_OFFSET (0x190) /**< (GMAC_FCSE) Frame Check Sequence Errors Register Offset */ 2488 2489 #define GMAC_FCSE_FCKR_Pos 0 /**< (GMAC_FCSE) Frame Check Sequence Errors Position */ 2490 #define GMAC_FCSE_FCKR_Msk (_U_(0x3FF) << GMAC_FCSE_FCKR_Pos) /**< (GMAC_FCSE) Frame Check Sequence Errors Mask */ 2491 #define GMAC_FCSE_FCKR(value) (GMAC_FCSE_FCKR_Msk & ((value) << GMAC_FCSE_FCKR_Pos)) 2492 #define GMAC_FCSE_MASK _U_(0x3FF) /**< \deprecated (GMAC_FCSE) Register MASK (Use GMAC_FCSE_Msk instead) */ 2493 #define GMAC_FCSE_Msk _U_(0x3FF) /**< (GMAC_FCSE) Register Mask */ 2494 2495 2496 /* -------- GMAC_LFFE : (GMAC Offset: 0x194) (R/ 32) Length Field Frame Errors Register -------- */ 2497 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2498 #if COMPONENT_TYPEDEF_STYLE == 'N' 2499 typedef union { 2500 struct { 2501 uint32_t LFER:10; /**< bit: 0..9 Length Field Frame Errors */ 2502 uint32_t :22; /**< bit: 10..31 Reserved */ 2503 } bit; /**< Structure used for bit access */ 2504 uint32_t reg; /**< Type used for register access */ 2505 } GMAC_LFFE_Type; 2506 #endif 2507 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2508 2509 #define GMAC_LFFE_OFFSET (0x194) /**< (GMAC_LFFE) Length Field Frame Errors Register Offset */ 2510 2511 #define GMAC_LFFE_LFER_Pos 0 /**< (GMAC_LFFE) Length Field Frame Errors Position */ 2512 #define GMAC_LFFE_LFER_Msk (_U_(0x3FF) << GMAC_LFFE_LFER_Pos) /**< (GMAC_LFFE) Length Field Frame Errors Mask */ 2513 #define GMAC_LFFE_LFER(value) (GMAC_LFFE_LFER_Msk & ((value) << GMAC_LFFE_LFER_Pos)) 2514 #define GMAC_LFFE_MASK _U_(0x3FF) /**< \deprecated (GMAC_LFFE) Register MASK (Use GMAC_LFFE_Msk instead) */ 2515 #define GMAC_LFFE_Msk _U_(0x3FF) /**< (GMAC_LFFE) Register Mask */ 2516 2517 2518 /* -------- GMAC_RSE : (GMAC Offset: 0x198) (R/ 32) Receive Symbol Errors Register -------- */ 2519 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2520 #if COMPONENT_TYPEDEF_STYLE == 'N' 2521 typedef union { 2522 struct { 2523 uint32_t RXSE:10; /**< bit: 0..9 Receive Symbol Errors */ 2524 uint32_t :22; /**< bit: 10..31 Reserved */ 2525 } bit; /**< Structure used for bit access */ 2526 uint32_t reg; /**< Type used for register access */ 2527 } GMAC_RSE_Type; 2528 #endif 2529 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2530 2531 #define GMAC_RSE_OFFSET (0x198) /**< (GMAC_RSE) Receive Symbol Errors Register Offset */ 2532 2533 #define GMAC_RSE_RXSE_Pos 0 /**< (GMAC_RSE) Receive Symbol Errors Position */ 2534 #define GMAC_RSE_RXSE_Msk (_U_(0x3FF) << GMAC_RSE_RXSE_Pos) /**< (GMAC_RSE) Receive Symbol Errors Mask */ 2535 #define GMAC_RSE_RXSE(value) (GMAC_RSE_RXSE_Msk & ((value) << GMAC_RSE_RXSE_Pos)) 2536 #define GMAC_RSE_MASK _U_(0x3FF) /**< \deprecated (GMAC_RSE) Register MASK (Use GMAC_RSE_Msk instead) */ 2537 #define GMAC_RSE_Msk _U_(0x3FF) /**< (GMAC_RSE) Register Mask */ 2538 2539 2540 /* -------- GMAC_AE : (GMAC Offset: 0x19c) (R/ 32) Alignment Errors Register -------- */ 2541 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2542 #if COMPONENT_TYPEDEF_STYLE == 'N' 2543 typedef union { 2544 struct { 2545 uint32_t AER:10; /**< bit: 0..9 Alignment Errors */ 2546 uint32_t :22; /**< bit: 10..31 Reserved */ 2547 } bit; /**< Structure used for bit access */ 2548 uint32_t reg; /**< Type used for register access */ 2549 } GMAC_AE_Type; 2550 #endif 2551 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2552 2553 #define GMAC_AE_OFFSET (0x19C) /**< (GMAC_AE) Alignment Errors Register Offset */ 2554 2555 #define GMAC_AE_AER_Pos 0 /**< (GMAC_AE) Alignment Errors Position */ 2556 #define GMAC_AE_AER_Msk (_U_(0x3FF) << GMAC_AE_AER_Pos) /**< (GMAC_AE) Alignment Errors Mask */ 2557 #define GMAC_AE_AER(value) (GMAC_AE_AER_Msk & ((value) << GMAC_AE_AER_Pos)) 2558 #define GMAC_AE_MASK _U_(0x3FF) /**< \deprecated (GMAC_AE) Register MASK (Use GMAC_AE_Msk instead) */ 2559 #define GMAC_AE_Msk _U_(0x3FF) /**< (GMAC_AE) Register Mask */ 2560 2561 2562 /* -------- GMAC_RRE : (GMAC Offset: 0x1a0) (R/ 32) Receive Resource Errors Register -------- */ 2563 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2564 #if COMPONENT_TYPEDEF_STYLE == 'N' 2565 typedef union { 2566 struct { 2567 uint32_t RXRER:18; /**< bit: 0..17 Receive Resource Errors */ 2568 uint32_t :14; /**< bit: 18..31 Reserved */ 2569 } bit; /**< Structure used for bit access */ 2570 uint32_t reg; /**< Type used for register access */ 2571 } GMAC_RRE_Type; 2572 #endif 2573 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2574 2575 #define GMAC_RRE_OFFSET (0x1A0) /**< (GMAC_RRE) Receive Resource Errors Register Offset */ 2576 2577 #define GMAC_RRE_RXRER_Pos 0 /**< (GMAC_RRE) Receive Resource Errors Position */ 2578 #define GMAC_RRE_RXRER_Msk (_U_(0x3FFFF) << GMAC_RRE_RXRER_Pos) /**< (GMAC_RRE) Receive Resource Errors Mask */ 2579 #define GMAC_RRE_RXRER(value) (GMAC_RRE_RXRER_Msk & ((value) << GMAC_RRE_RXRER_Pos)) 2580 #define GMAC_RRE_MASK _U_(0x3FFFF) /**< \deprecated (GMAC_RRE) Register MASK (Use GMAC_RRE_Msk instead) */ 2581 #define GMAC_RRE_Msk _U_(0x3FFFF) /**< (GMAC_RRE) Register Mask */ 2582 2583 2584 /* -------- GMAC_ROE : (GMAC Offset: 0x1a4) (R/ 32) Receive Overrun Register -------- */ 2585 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2586 #if COMPONENT_TYPEDEF_STYLE == 'N' 2587 typedef union { 2588 struct { 2589 uint32_t RXOVR:10; /**< bit: 0..9 Receive Overruns */ 2590 uint32_t :22; /**< bit: 10..31 Reserved */ 2591 } bit; /**< Structure used for bit access */ 2592 uint32_t reg; /**< Type used for register access */ 2593 } GMAC_ROE_Type; 2594 #endif 2595 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2596 2597 #define GMAC_ROE_OFFSET (0x1A4) /**< (GMAC_ROE) Receive Overrun Register Offset */ 2598 2599 #define GMAC_ROE_RXOVR_Pos 0 /**< (GMAC_ROE) Receive Overruns Position */ 2600 #define GMAC_ROE_RXOVR_Msk (_U_(0x3FF) << GMAC_ROE_RXOVR_Pos) /**< (GMAC_ROE) Receive Overruns Mask */ 2601 #define GMAC_ROE_RXOVR(value) (GMAC_ROE_RXOVR_Msk & ((value) << GMAC_ROE_RXOVR_Pos)) 2602 #define GMAC_ROE_MASK _U_(0x3FF) /**< \deprecated (GMAC_ROE) Register MASK (Use GMAC_ROE_Msk instead) */ 2603 #define GMAC_ROE_Msk _U_(0x3FF) /**< (GMAC_ROE) Register Mask */ 2604 2605 2606 /* -------- GMAC_IHCE : (GMAC Offset: 0x1a8) (R/ 32) IP Header Checksum Errors Register -------- */ 2607 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2608 #if COMPONENT_TYPEDEF_STYLE == 'N' 2609 typedef union { 2610 struct { 2611 uint32_t HCKER:8; /**< bit: 0..7 IP Header Checksum Errors */ 2612 uint32_t :24; /**< bit: 8..31 Reserved */ 2613 } bit; /**< Structure used for bit access */ 2614 uint32_t reg; /**< Type used for register access */ 2615 } GMAC_IHCE_Type; 2616 #endif 2617 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2618 2619 #define GMAC_IHCE_OFFSET (0x1A8) /**< (GMAC_IHCE) IP Header Checksum Errors Register Offset */ 2620 2621 #define GMAC_IHCE_HCKER_Pos 0 /**< (GMAC_IHCE) IP Header Checksum Errors Position */ 2622 #define GMAC_IHCE_HCKER_Msk (_U_(0xFF) << GMAC_IHCE_HCKER_Pos) /**< (GMAC_IHCE) IP Header Checksum Errors Mask */ 2623 #define GMAC_IHCE_HCKER(value) (GMAC_IHCE_HCKER_Msk & ((value) << GMAC_IHCE_HCKER_Pos)) 2624 #define GMAC_IHCE_MASK _U_(0xFF) /**< \deprecated (GMAC_IHCE) Register MASK (Use GMAC_IHCE_Msk instead) */ 2625 #define GMAC_IHCE_Msk _U_(0xFF) /**< (GMAC_IHCE) Register Mask */ 2626 2627 2628 /* -------- GMAC_TCE : (GMAC Offset: 0x1ac) (R/ 32) TCP Checksum Errors Register -------- */ 2629 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2630 #if COMPONENT_TYPEDEF_STYLE == 'N' 2631 typedef union { 2632 struct { 2633 uint32_t TCKER:8; /**< bit: 0..7 TCP Checksum Errors */ 2634 uint32_t :24; /**< bit: 8..31 Reserved */ 2635 } bit; /**< Structure used for bit access */ 2636 uint32_t reg; /**< Type used for register access */ 2637 } GMAC_TCE_Type; 2638 #endif 2639 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2640 2641 #define GMAC_TCE_OFFSET (0x1AC) /**< (GMAC_TCE) TCP Checksum Errors Register Offset */ 2642 2643 #define GMAC_TCE_TCKER_Pos 0 /**< (GMAC_TCE) TCP Checksum Errors Position */ 2644 #define GMAC_TCE_TCKER_Msk (_U_(0xFF) << GMAC_TCE_TCKER_Pos) /**< (GMAC_TCE) TCP Checksum Errors Mask */ 2645 #define GMAC_TCE_TCKER(value) (GMAC_TCE_TCKER_Msk & ((value) << GMAC_TCE_TCKER_Pos)) 2646 #define GMAC_TCE_MASK _U_(0xFF) /**< \deprecated (GMAC_TCE) Register MASK (Use GMAC_TCE_Msk instead) */ 2647 #define GMAC_TCE_Msk _U_(0xFF) /**< (GMAC_TCE) Register Mask */ 2648 2649 2650 /* -------- GMAC_UCE : (GMAC Offset: 0x1b0) (R/ 32) UDP Checksum Errors Register -------- */ 2651 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2652 #if COMPONENT_TYPEDEF_STYLE == 'N' 2653 typedef union { 2654 struct { 2655 uint32_t UCKER:8; /**< bit: 0..7 UDP Checksum Errors */ 2656 uint32_t :24; /**< bit: 8..31 Reserved */ 2657 } bit; /**< Structure used for bit access */ 2658 uint32_t reg; /**< Type used for register access */ 2659 } GMAC_UCE_Type; 2660 #endif 2661 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2662 2663 #define GMAC_UCE_OFFSET (0x1B0) /**< (GMAC_UCE) UDP Checksum Errors Register Offset */ 2664 2665 #define GMAC_UCE_UCKER_Pos 0 /**< (GMAC_UCE) UDP Checksum Errors Position */ 2666 #define GMAC_UCE_UCKER_Msk (_U_(0xFF) << GMAC_UCE_UCKER_Pos) /**< (GMAC_UCE) UDP Checksum Errors Mask */ 2667 #define GMAC_UCE_UCKER(value) (GMAC_UCE_UCKER_Msk & ((value) << GMAC_UCE_UCKER_Pos)) 2668 #define GMAC_UCE_MASK _U_(0xFF) /**< \deprecated (GMAC_UCE) Register MASK (Use GMAC_UCE_Msk instead) */ 2669 #define GMAC_UCE_Msk _U_(0xFF) /**< (GMAC_UCE) Register Mask */ 2670 2671 2672 /* -------- GMAC_TISUBN : (GMAC Offset: 0x1bc) (R/W 32) 1588 Timer Increment Sub-nanoseconds Register -------- */ 2673 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2674 #if COMPONENT_TYPEDEF_STYLE == 'N' 2675 typedef union { 2676 struct { 2677 uint32_t LSBTIR:16; /**< bit: 0..15 Lower Significant Bits of Timer Increment Register */ 2678 uint32_t :16; /**< bit: 16..31 Reserved */ 2679 } bit; /**< Structure used for bit access */ 2680 uint32_t reg; /**< Type used for register access */ 2681 } GMAC_TISUBN_Type; 2682 #endif 2683 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2684 2685 #define GMAC_TISUBN_OFFSET (0x1BC) /**< (GMAC_TISUBN) 1588 Timer Increment Sub-nanoseconds Register Offset */ 2686 2687 #define GMAC_TISUBN_LSBTIR_Pos 0 /**< (GMAC_TISUBN) Lower Significant Bits of Timer Increment Register Position */ 2688 #define GMAC_TISUBN_LSBTIR_Msk (_U_(0xFFFF) << GMAC_TISUBN_LSBTIR_Pos) /**< (GMAC_TISUBN) Lower Significant Bits of Timer Increment Register Mask */ 2689 #define GMAC_TISUBN_LSBTIR(value) (GMAC_TISUBN_LSBTIR_Msk & ((value) << GMAC_TISUBN_LSBTIR_Pos)) 2690 #define GMAC_TISUBN_MASK _U_(0xFFFF) /**< \deprecated (GMAC_TISUBN) Register MASK (Use GMAC_TISUBN_Msk instead) */ 2691 #define GMAC_TISUBN_Msk _U_(0xFFFF) /**< (GMAC_TISUBN) Register Mask */ 2692 2693 2694 /* -------- GMAC_TSH : (GMAC Offset: 0x1c0) (R/W 32) 1588 Timer Seconds High Register -------- */ 2695 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2696 #if COMPONENT_TYPEDEF_STYLE == 'N' 2697 typedef union { 2698 struct { 2699 uint32_t TCS:16; /**< bit: 0..15 Timer Count in Seconds */ 2700 uint32_t :16; /**< bit: 16..31 Reserved */ 2701 } bit; /**< Structure used for bit access */ 2702 uint32_t reg; /**< Type used for register access */ 2703 } GMAC_TSH_Type; 2704 #endif 2705 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2706 2707 #define GMAC_TSH_OFFSET (0x1C0) /**< (GMAC_TSH) 1588 Timer Seconds High Register Offset */ 2708 2709 #define GMAC_TSH_TCS_Pos 0 /**< (GMAC_TSH) Timer Count in Seconds Position */ 2710 #define GMAC_TSH_TCS_Msk (_U_(0xFFFF) << GMAC_TSH_TCS_Pos) /**< (GMAC_TSH) Timer Count in Seconds Mask */ 2711 #define GMAC_TSH_TCS(value) (GMAC_TSH_TCS_Msk & ((value) << GMAC_TSH_TCS_Pos)) 2712 #define GMAC_TSH_MASK _U_(0xFFFF) /**< \deprecated (GMAC_TSH) Register MASK (Use GMAC_TSH_Msk instead) */ 2713 #define GMAC_TSH_Msk _U_(0xFFFF) /**< (GMAC_TSH) Register Mask */ 2714 2715 2716 /* -------- GMAC_TSL : (GMAC Offset: 0x1d0) (R/W 32) 1588 Timer Seconds Low Register -------- */ 2717 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2718 #if COMPONENT_TYPEDEF_STYLE == 'N' 2719 typedef union { 2720 struct { 2721 uint32_t TCS:32; /**< bit: 0..31 Timer Count in Seconds */ 2722 } bit; /**< Structure used for bit access */ 2723 uint32_t reg; /**< Type used for register access */ 2724 } GMAC_TSL_Type; 2725 #endif 2726 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2727 2728 #define GMAC_TSL_OFFSET (0x1D0) /**< (GMAC_TSL) 1588 Timer Seconds Low Register Offset */ 2729 2730 #define GMAC_TSL_TCS_Pos 0 /**< (GMAC_TSL) Timer Count in Seconds Position */ 2731 #define GMAC_TSL_TCS_Msk (_U_(0xFFFFFFFF) << GMAC_TSL_TCS_Pos) /**< (GMAC_TSL) Timer Count in Seconds Mask */ 2732 #define GMAC_TSL_TCS(value) (GMAC_TSL_TCS_Msk & ((value) << GMAC_TSL_TCS_Pos)) 2733 #define GMAC_TSL_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_TSL) Register MASK (Use GMAC_TSL_Msk instead) */ 2734 #define GMAC_TSL_Msk _U_(0xFFFFFFFF) /**< (GMAC_TSL) Register Mask */ 2735 2736 2737 /* -------- GMAC_TN : (GMAC Offset: 0x1d4) (R/W 32) 1588 Timer Nanoseconds Register -------- */ 2738 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2739 #if COMPONENT_TYPEDEF_STYLE == 'N' 2740 typedef union { 2741 struct { 2742 uint32_t TNS:30; /**< bit: 0..29 Timer Count in Nanoseconds */ 2743 uint32_t :2; /**< bit: 30..31 Reserved */ 2744 } bit; /**< Structure used for bit access */ 2745 uint32_t reg; /**< Type used for register access */ 2746 } GMAC_TN_Type; 2747 #endif 2748 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2749 2750 #define GMAC_TN_OFFSET (0x1D4) /**< (GMAC_TN) 1588 Timer Nanoseconds Register Offset */ 2751 2752 #define GMAC_TN_TNS_Pos 0 /**< (GMAC_TN) Timer Count in Nanoseconds Position */ 2753 #define GMAC_TN_TNS_Msk (_U_(0x3FFFFFFF) << GMAC_TN_TNS_Pos) /**< (GMAC_TN) Timer Count in Nanoseconds Mask */ 2754 #define GMAC_TN_TNS(value) (GMAC_TN_TNS_Msk & ((value) << GMAC_TN_TNS_Pos)) 2755 #define GMAC_TN_MASK _U_(0x3FFFFFFF) /**< \deprecated (GMAC_TN) Register MASK (Use GMAC_TN_Msk instead) */ 2756 #define GMAC_TN_Msk _U_(0x3FFFFFFF) /**< (GMAC_TN) Register Mask */ 2757 2758 2759 /* -------- GMAC_TA : (GMAC Offset: 0x1d8) (/W 32) 1588 Timer Adjust Register -------- */ 2760 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2761 #if COMPONENT_TYPEDEF_STYLE == 'N' 2762 typedef union { 2763 struct { 2764 uint32_t ITDT:30; /**< bit: 0..29 Increment/Decrement */ 2765 uint32_t :1; /**< bit: 30 Reserved */ 2766 uint32_t ADJ:1; /**< bit: 31 Adjust 1588 Timer */ 2767 } bit; /**< Structure used for bit access */ 2768 uint32_t reg; /**< Type used for register access */ 2769 } GMAC_TA_Type; 2770 #endif 2771 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2772 2773 #define GMAC_TA_OFFSET (0x1D8) /**< (GMAC_TA) 1588 Timer Adjust Register Offset */ 2774 2775 #define GMAC_TA_ITDT_Pos 0 /**< (GMAC_TA) Increment/Decrement Position */ 2776 #define GMAC_TA_ITDT_Msk (_U_(0x3FFFFFFF) << GMAC_TA_ITDT_Pos) /**< (GMAC_TA) Increment/Decrement Mask */ 2777 #define GMAC_TA_ITDT(value) (GMAC_TA_ITDT_Msk & ((value) << GMAC_TA_ITDT_Pos)) 2778 #define GMAC_TA_ADJ_Pos 31 /**< (GMAC_TA) Adjust 1588 Timer Position */ 2779 #define GMAC_TA_ADJ_Msk (_U_(0x1) << GMAC_TA_ADJ_Pos) /**< (GMAC_TA) Adjust 1588 Timer Mask */ 2780 #define GMAC_TA_ADJ GMAC_TA_ADJ_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_TA_ADJ_Msk instead */ 2781 #define GMAC_TA_MASK _U_(0xBFFFFFFF) /**< \deprecated (GMAC_TA) Register MASK (Use GMAC_TA_Msk instead) */ 2782 #define GMAC_TA_Msk _U_(0xBFFFFFFF) /**< (GMAC_TA) Register Mask */ 2783 2784 2785 /* -------- GMAC_TI : (GMAC Offset: 0x1dc) (R/W 32) 1588 Timer Increment Register -------- */ 2786 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2787 #if COMPONENT_TYPEDEF_STYLE == 'N' 2788 typedef union { 2789 struct { 2790 uint32_t CNS:8; /**< bit: 0..7 Count Nanoseconds */ 2791 uint32_t ACNS:8; /**< bit: 8..15 Alternative Count Nanoseconds */ 2792 uint32_t NIT:8; /**< bit: 16..23 Number of Increments */ 2793 uint32_t :8; /**< bit: 24..31 Reserved */ 2794 } bit; /**< Structure used for bit access */ 2795 uint32_t reg; /**< Type used for register access */ 2796 } GMAC_TI_Type; 2797 #endif 2798 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2799 2800 #define GMAC_TI_OFFSET (0x1DC) /**< (GMAC_TI) 1588 Timer Increment Register Offset */ 2801 2802 #define GMAC_TI_CNS_Pos 0 /**< (GMAC_TI) Count Nanoseconds Position */ 2803 #define GMAC_TI_CNS_Msk (_U_(0xFF) << GMAC_TI_CNS_Pos) /**< (GMAC_TI) Count Nanoseconds Mask */ 2804 #define GMAC_TI_CNS(value) (GMAC_TI_CNS_Msk & ((value) << GMAC_TI_CNS_Pos)) 2805 #define GMAC_TI_ACNS_Pos 8 /**< (GMAC_TI) Alternative Count Nanoseconds Position */ 2806 #define GMAC_TI_ACNS_Msk (_U_(0xFF) << GMAC_TI_ACNS_Pos) /**< (GMAC_TI) Alternative Count Nanoseconds Mask */ 2807 #define GMAC_TI_ACNS(value) (GMAC_TI_ACNS_Msk & ((value) << GMAC_TI_ACNS_Pos)) 2808 #define GMAC_TI_NIT_Pos 16 /**< (GMAC_TI) Number of Increments Position */ 2809 #define GMAC_TI_NIT_Msk (_U_(0xFF) << GMAC_TI_NIT_Pos) /**< (GMAC_TI) Number of Increments Mask */ 2810 #define GMAC_TI_NIT(value) (GMAC_TI_NIT_Msk & ((value) << GMAC_TI_NIT_Pos)) 2811 #define GMAC_TI_MASK _U_(0xFFFFFF) /**< \deprecated (GMAC_TI) Register MASK (Use GMAC_TI_Msk instead) */ 2812 #define GMAC_TI_Msk _U_(0xFFFFFF) /**< (GMAC_TI) Register Mask */ 2813 2814 2815 /* -------- GMAC_EFTSL : (GMAC Offset: 0x1e0) (R/ 32) PTP Event Frame Transmitted Seconds Low Register -------- */ 2816 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2817 #if COMPONENT_TYPEDEF_STYLE == 'N' 2818 typedef union { 2819 struct { 2820 uint32_t RUD:32; /**< bit: 0..31 Register Update */ 2821 } bit; /**< Structure used for bit access */ 2822 uint32_t reg; /**< Type used for register access */ 2823 } GMAC_EFTSL_Type; 2824 #endif 2825 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2826 2827 #define GMAC_EFTSL_OFFSET (0x1E0) /**< (GMAC_EFTSL) PTP Event Frame Transmitted Seconds Low Register Offset */ 2828 2829 #define GMAC_EFTSL_RUD_Pos 0 /**< (GMAC_EFTSL) Register Update Position */ 2830 #define GMAC_EFTSL_RUD_Msk (_U_(0xFFFFFFFF) << GMAC_EFTSL_RUD_Pos) /**< (GMAC_EFTSL) Register Update Mask */ 2831 #define GMAC_EFTSL_RUD(value) (GMAC_EFTSL_RUD_Msk & ((value) << GMAC_EFTSL_RUD_Pos)) 2832 #define GMAC_EFTSL_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_EFTSL) Register MASK (Use GMAC_EFTSL_Msk instead) */ 2833 #define GMAC_EFTSL_Msk _U_(0xFFFFFFFF) /**< (GMAC_EFTSL) Register Mask */ 2834 2835 2836 /* -------- GMAC_EFTN : (GMAC Offset: 0x1e4) (R/ 32) PTP Event Frame Transmitted Nanoseconds Register -------- */ 2837 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2838 #if COMPONENT_TYPEDEF_STYLE == 'N' 2839 typedef union { 2840 struct { 2841 uint32_t RUD:30; /**< bit: 0..29 Register Update */ 2842 uint32_t :2; /**< bit: 30..31 Reserved */ 2843 } bit; /**< Structure used for bit access */ 2844 uint32_t reg; /**< Type used for register access */ 2845 } GMAC_EFTN_Type; 2846 #endif 2847 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2848 2849 #define GMAC_EFTN_OFFSET (0x1E4) /**< (GMAC_EFTN) PTP Event Frame Transmitted Nanoseconds Register Offset */ 2850 2851 #define GMAC_EFTN_RUD_Pos 0 /**< (GMAC_EFTN) Register Update Position */ 2852 #define GMAC_EFTN_RUD_Msk (_U_(0x3FFFFFFF) << GMAC_EFTN_RUD_Pos) /**< (GMAC_EFTN) Register Update Mask */ 2853 #define GMAC_EFTN_RUD(value) (GMAC_EFTN_RUD_Msk & ((value) << GMAC_EFTN_RUD_Pos)) 2854 #define GMAC_EFTN_MASK _U_(0x3FFFFFFF) /**< \deprecated (GMAC_EFTN) Register MASK (Use GMAC_EFTN_Msk instead) */ 2855 #define GMAC_EFTN_Msk _U_(0x3FFFFFFF) /**< (GMAC_EFTN) Register Mask */ 2856 2857 2858 /* -------- GMAC_EFRSL : (GMAC Offset: 0x1e8) (R/ 32) PTP Event Frame Received Seconds Low Register -------- */ 2859 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2860 #if COMPONENT_TYPEDEF_STYLE == 'N' 2861 typedef union { 2862 struct { 2863 uint32_t RUD:32; /**< bit: 0..31 Register Update */ 2864 } bit; /**< Structure used for bit access */ 2865 uint32_t reg; /**< Type used for register access */ 2866 } GMAC_EFRSL_Type; 2867 #endif 2868 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2869 2870 #define GMAC_EFRSL_OFFSET (0x1E8) /**< (GMAC_EFRSL) PTP Event Frame Received Seconds Low Register Offset */ 2871 2872 #define GMAC_EFRSL_RUD_Pos 0 /**< (GMAC_EFRSL) Register Update Position */ 2873 #define GMAC_EFRSL_RUD_Msk (_U_(0xFFFFFFFF) << GMAC_EFRSL_RUD_Pos) /**< (GMAC_EFRSL) Register Update Mask */ 2874 #define GMAC_EFRSL_RUD(value) (GMAC_EFRSL_RUD_Msk & ((value) << GMAC_EFRSL_RUD_Pos)) 2875 #define GMAC_EFRSL_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_EFRSL) Register MASK (Use GMAC_EFRSL_Msk instead) */ 2876 #define GMAC_EFRSL_Msk _U_(0xFFFFFFFF) /**< (GMAC_EFRSL) Register Mask */ 2877 2878 2879 /* -------- GMAC_EFRN : (GMAC Offset: 0x1ec) (R/ 32) PTP Event Frame Received Nanoseconds Register -------- */ 2880 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2881 #if COMPONENT_TYPEDEF_STYLE == 'N' 2882 typedef union { 2883 struct { 2884 uint32_t RUD:30; /**< bit: 0..29 Register Update */ 2885 uint32_t :2; /**< bit: 30..31 Reserved */ 2886 } bit; /**< Structure used for bit access */ 2887 uint32_t reg; /**< Type used for register access */ 2888 } GMAC_EFRN_Type; 2889 #endif 2890 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2891 2892 #define GMAC_EFRN_OFFSET (0x1EC) /**< (GMAC_EFRN) PTP Event Frame Received Nanoseconds Register Offset */ 2893 2894 #define GMAC_EFRN_RUD_Pos 0 /**< (GMAC_EFRN) Register Update Position */ 2895 #define GMAC_EFRN_RUD_Msk (_U_(0x3FFFFFFF) << GMAC_EFRN_RUD_Pos) /**< (GMAC_EFRN) Register Update Mask */ 2896 #define GMAC_EFRN_RUD(value) (GMAC_EFRN_RUD_Msk & ((value) << GMAC_EFRN_RUD_Pos)) 2897 #define GMAC_EFRN_MASK _U_(0x3FFFFFFF) /**< \deprecated (GMAC_EFRN) Register MASK (Use GMAC_EFRN_Msk instead) */ 2898 #define GMAC_EFRN_Msk _U_(0x3FFFFFFF) /**< (GMAC_EFRN) Register Mask */ 2899 2900 2901 /* -------- GMAC_PEFTSL : (GMAC Offset: 0x1f0) (R/ 32) PTP Peer Event Frame Transmitted Seconds Low Register -------- */ 2902 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2903 #if COMPONENT_TYPEDEF_STYLE == 'N' 2904 typedef union { 2905 struct { 2906 uint32_t RUD:32; /**< bit: 0..31 Register Update */ 2907 } bit; /**< Structure used for bit access */ 2908 uint32_t reg; /**< Type used for register access */ 2909 } GMAC_PEFTSL_Type; 2910 #endif 2911 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2912 2913 #define GMAC_PEFTSL_OFFSET (0x1F0) /**< (GMAC_PEFTSL) PTP Peer Event Frame Transmitted Seconds Low Register Offset */ 2914 2915 #define GMAC_PEFTSL_RUD_Pos 0 /**< (GMAC_PEFTSL) Register Update Position */ 2916 #define GMAC_PEFTSL_RUD_Msk (_U_(0xFFFFFFFF) << GMAC_PEFTSL_RUD_Pos) /**< (GMAC_PEFTSL) Register Update Mask */ 2917 #define GMAC_PEFTSL_RUD(value) (GMAC_PEFTSL_RUD_Msk & ((value) << GMAC_PEFTSL_RUD_Pos)) 2918 #define GMAC_PEFTSL_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_PEFTSL) Register MASK (Use GMAC_PEFTSL_Msk instead) */ 2919 #define GMAC_PEFTSL_Msk _U_(0xFFFFFFFF) /**< (GMAC_PEFTSL) Register Mask */ 2920 2921 2922 /* -------- GMAC_PEFTN : (GMAC Offset: 0x1f4) (R/ 32) PTP Peer Event Frame Transmitted Nanoseconds Register -------- */ 2923 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2924 #if COMPONENT_TYPEDEF_STYLE == 'N' 2925 typedef union { 2926 struct { 2927 uint32_t RUD:30; /**< bit: 0..29 Register Update */ 2928 uint32_t :2; /**< bit: 30..31 Reserved */ 2929 } bit; /**< Structure used for bit access */ 2930 uint32_t reg; /**< Type used for register access */ 2931 } GMAC_PEFTN_Type; 2932 #endif 2933 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2934 2935 #define GMAC_PEFTN_OFFSET (0x1F4) /**< (GMAC_PEFTN) PTP Peer Event Frame Transmitted Nanoseconds Register Offset */ 2936 2937 #define GMAC_PEFTN_RUD_Pos 0 /**< (GMAC_PEFTN) Register Update Position */ 2938 #define GMAC_PEFTN_RUD_Msk (_U_(0x3FFFFFFF) << GMAC_PEFTN_RUD_Pos) /**< (GMAC_PEFTN) Register Update Mask */ 2939 #define GMAC_PEFTN_RUD(value) (GMAC_PEFTN_RUD_Msk & ((value) << GMAC_PEFTN_RUD_Pos)) 2940 #define GMAC_PEFTN_MASK _U_(0x3FFFFFFF) /**< \deprecated (GMAC_PEFTN) Register MASK (Use GMAC_PEFTN_Msk instead) */ 2941 #define GMAC_PEFTN_Msk _U_(0x3FFFFFFF) /**< (GMAC_PEFTN) Register Mask */ 2942 2943 2944 /* -------- GMAC_PEFRSL : (GMAC Offset: 0x1f8) (R/ 32) PTP Peer Event Frame Received Seconds Low Register -------- */ 2945 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2946 #if COMPONENT_TYPEDEF_STYLE == 'N' 2947 typedef union { 2948 struct { 2949 uint32_t RUD:32; /**< bit: 0..31 Register Update */ 2950 } bit; /**< Structure used for bit access */ 2951 uint32_t reg; /**< Type used for register access */ 2952 } GMAC_PEFRSL_Type; 2953 #endif 2954 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2955 2956 #define GMAC_PEFRSL_OFFSET (0x1F8) /**< (GMAC_PEFRSL) PTP Peer Event Frame Received Seconds Low Register Offset */ 2957 2958 #define GMAC_PEFRSL_RUD_Pos 0 /**< (GMAC_PEFRSL) Register Update Position */ 2959 #define GMAC_PEFRSL_RUD_Msk (_U_(0xFFFFFFFF) << GMAC_PEFRSL_RUD_Pos) /**< (GMAC_PEFRSL) Register Update Mask */ 2960 #define GMAC_PEFRSL_RUD(value) (GMAC_PEFRSL_RUD_Msk & ((value) << GMAC_PEFRSL_RUD_Pos)) 2961 #define GMAC_PEFRSL_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_PEFRSL) Register MASK (Use GMAC_PEFRSL_Msk instead) */ 2962 #define GMAC_PEFRSL_Msk _U_(0xFFFFFFFF) /**< (GMAC_PEFRSL) Register Mask */ 2963 2964 2965 /* -------- GMAC_PEFRN : (GMAC Offset: 0x1fc) (R/ 32) PTP Peer Event Frame Received Nanoseconds Register -------- */ 2966 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2967 #if COMPONENT_TYPEDEF_STYLE == 'N' 2968 typedef union { 2969 struct { 2970 uint32_t RUD:30; /**< bit: 0..29 Register Update */ 2971 uint32_t :2; /**< bit: 30..31 Reserved */ 2972 } bit; /**< Structure used for bit access */ 2973 uint32_t reg; /**< Type used for register access */ 2974 } GMAC_PEFRN_Type; 2975 #endif 2976 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2977 2978 #define GMAC_PEFRN_OFFSET (0x1FC) /**< (GMAC_PEFRN) PTP Peer Event Frame Received Nanoseconds Register Offset */ 2979 2980 #define GMAC_PEFRN_RUD_Pos 0 /**< (GMAC_PEFRN) Register Update Position */ 2981 #define GMAC_PEFRN_RUD_Msk (_U_(0x3FFFFFFF) << GMAC_PEFRN_RUD_Pos) /**< (GMAC_PEFRN) Register Update Mask */ 2982 #define GMAC_PEFRN_RUD(value) (GMAC_PEFRN_RUD_Msk & ((value) << GMAC_PEFRN_RUD_Pos)) 2983 #define GMAC_PEFRN_MASK _U_(0x3FFFFFFF) /**< \deprecated (GMAC_PEFRN) Register MASK (Use GMAC_PEFRN_Msk instead) */ 2984 #define GMAC_PEFRN_Msk _U_(0x3FFFFFFF) /**< (GMAC_PEFRN) Register Mask */ 2985 2986 2987 /* -------- GMAC_ISRPQ : (GMAC Offset: 0x400) (R/ 32) Interrupt Status Register Priority Queue (index = 1) 0 -------- */ 2988 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2989 #if COMPONENT_TYPEDEF_STYLE == 'N' 2990 typedef union { 2991 struct { 2992 uint32_t :1; /**< bit: 0 Reserved */ 2993 uint32_t RCOMP:1; /**< bit: 1 Receive Complete */ 2994 uint32_t RXUBR:1; /**< bit: 2 RX Used Bit Read */ 2995 uint32_t :2; /**< bit: 3..4 Reserved */ 2996 uint32_t RLEX:1; /**< bit: 5 Retry Limit Exceeded or Late Collision */ 2997 uint32_t TFC:1; /**< bit: 6 Transmit Frame Corruption Due to AHB Error */ 2998 uint32_t TCOMP:1; /**< bit: 7 Transmit Complete */ 2999 uint32_t :2; /**< bit: 8..9 Reserved */ 3000 uint32_t ROVR:1; /**< bit: 10 Receive Overrun */ 3001 uint32_t HRESP:1; /**< bit: 11 HRESP Not OK */ 3002 uint32_t :20; /**< bit: 12..31 Reserved */ 3003 } bit; /**< Structure used for bit access */ 3004 uint32_t reg; /**< Type used for register access */ 3005 } GMAC_ISRPQ_Type; 3006 #endif 3007 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 3008 3009 #define GMAC_ISRPQ_OFFSET (0x400) /**< (GMAC_ISRPQ) Interrupt Status Register Priority Queue (index = 1) 0 Offset */ 3010 3011 #define GMAC_ISRPQ_RCOMP_Pos 1 /**< (GMAC_ISRPQ) Receive Complete Position */ 3012 #define GMAC_ISRPQ_RCOMP_Msk (_U_(0x1) << GMAC_ISRPQ_RCOMP_Pos) /**< (GMAC_ISRPQ) Receive Complete Mask */ 3013 #define GMAC_ISRPQ_RCOMP GMAC_ISRPQ_RCOMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISRPQ_RCOMP_Msk instead */ 3014 #define GMAC_ISRPQ_RXUBR_Pos 2 /**< (GMAC_ISRPQ) RX Used Bit Read Position */ 3015 #define GMAC_ISRPQ_RXUBR_Msk (_U_(0x1) << GMAC_ISRPQ_RXUBR_Pos) /**< (GMAC_ISRPQ) RX Used Bit Read Mask */ 3016 #define GMAC_ISRPQ_RXUBR GMAC_ISRPQ_RXUBR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISRPQ_RXUBR_Msk instead */ 3017 #define GMAC_ISRPQ_RLEX_Pos 5 /**< (GMAC_ISRPQ) Retry Limit Exceeded or Late Collision Position */ 3018 #define GMAC_ISRPQ_RLEX_Msk (_U_(0x1) << GMAC_ISRPQ_RLEX_Pos) /**< (GMAC_ISRPQ) Retry Limit Exceeded or Late Collision Mask */ 3019 #define GMAC_ISRPQ_RLEX GMAC_ISRPQ_RLEX_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISRPQ_RLEX_Msk instead */ 3020 #define GMAC_ISRPQ_TFC_Pos 6 /**< (GMAC_ISRPQ) Transmit Frame Corruption Due to AHB Error Position */ 3021 #define GMAC_ISRPQ_TFC_Msk (_U_(0x1) << GMAC_ISRPQ_TFC_Pos) /**< (GMAC_ISRPQ) Transmit Frame Corruption Due to AHB Error Mask */ 3022 #define GMAC_ISRPQ_TFC GMAC_ISRPQ_TFC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISRPQ_TFC_Msk instead */ 3023 #define GMAC_ISRPQ_TCOMP_Pos 7 /**< (GMAC_ISRPQ) Transmit Complete Position */ 3024 #define GMAC_ISRPQ_TCOMP_Msk (_U_(0x1) << GMAC_ISRPQ_TCOMP_Pos) /**< (GMAC_ISRPQ) Transmit Complete Mask */ 3025 #define GMAC_ISRPQ_TCOMP GMAC_ISRPQ_TCOMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISRPQ_TCOMP_Msk instead */ 3026 #define GMAC_ISRPQ_ROVR_Pos 10 /**< (GMAC_ISRPQ) Receive Overrun Position */ 3027 #define GMAC_ISRPQ_ROVR_Msk (_U_(0x1) << GMAC_ISRPQ_ROVR_Pos) /**< (GMAC_ISRPQ) Receive Overrun Mask */ 3028 #define GMAC_ISRPQ_ROVR GMAC_ISRPQ_ROVR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISRPQ_ROVR_Msk instead */ 3029 #define GMAC_ISRPQ_HRESP_Pos 11 /**< (GMAC_ISRPQ) HRESP Not OK Position */ 3030 #define GMAC_ISRPQ_HRESP_Msk (_U_(0x1) << GMAC_ISRPQ_HRESP_Pos) /**< (GMAC_ISRPQ) HRESP Not OK Mask */ 3031 #define GMAC_ISRPQ_HRESP GMAC_ISRPQ_HRESP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISRPQ_HRESP_Msk instead */ 3032 #define GMAC_ISRPQ_MASK _U_(0xCE6) /**< \deprecated (GMAC_ISRPQ) Register MASK (Use GMAC_ISRPQ_Msk instead) */ 3033 #define GMAC_ISRPQ_Msk _U_(0xCE6) /**< (GMAC_ISRPQ) Register Mask */ 3034 3035 3036 /* -------- GMAC_TBQBAPQ : (GMAC Offset: 0x440) (R/W 32) Transmit Buffer Queue Base Address Register Priority Queue (index = 1) 0 -------- */ 3037 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 3038 #if COMPONENT_TYPEDEF_STYLE == 'N' 3039 typedef union { 3040 struct { 3041 uint32_t :2; /**< bit: 0..1 Reserved */ 3042 uint32_t TXBQBA:30; /**< bit: 2..31 Transmit Buffer Queue Base Address */ 3043 } bit; /**< Structure used for bit access */ 3044 uint32_t reg; /**< Type used for register access */ 3045 } GMAC_TBQBAPQ_Type; 3046 #endif 3047 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 3048 3049 #define GMAC_TBQBAPQ_OFFSET (0x440) /**< (GMAC_TBQBAPQ) Transmit Buffer Queue Base Address Register Priority Queue (index = 1) 0 Offset */ 3050 3051 #define GMAC_TBQBAPQ_TXBQBA_Pos 2 /**< (GMAC_TBQBAPQ) Transmit Buffer Queue Base Address Position */ 3052 #define GMAC_TBQBAPQ_TXBQBA_Msk (_U_(0x3FFFFFFF) << GMAC_TBQBAPQ_TXBQBA_Pos) /**< (GMAC_TBQBAPQ) Transmit Buffer Queue Base Address Mask */ 3053 #define GMAC_TBQBAPQ_TXBQBA(value) (GMAC_TBQBAPQ_TXBQBA_Msk & ((value) << GMAC_TBQBAPQ_TXBQBA_Pos)) 3054 #define GMAC_TBQBAPQ_MASK _U_(0xFFFFFFFC) /**< \deprecated (GMAC_TBQBAPQ) Register MASK (Use GMAC_TBQBAPQ_Msk instead) */ 3055 #define GMAC_TBQBAPQ_Msk _U_(0xFFFFFFFC) /**< (GMAC_TBQBAPQ) Register Mask */ 3056 3057 3058 /* -------- GMAC_RBQBAPQ : (GMAC Offset: 0x480) (R/W 32) Receive Buffer Queue Base Address Register Priority Queue (index = 1) 0 -------- */ 3059 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 3060 #if COMPONENT_TYPEDEF_STYLE == 'N' 3061 typedef union { 3062 struct { 3063 uint32_t :2; /**< bit: 0..1 Reserved */ 3064 uint32_t RXBQBA:30; /**< bit: 2..31 Receive Buffer Queue Base Address */ 3065 } bit; /**< Structure used for bit access */ 3066 uint32_t reg; /**< Type used for register access */ 3067 } GMAC_RBQBAPQ_Type; 3068 #endif 3069 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 3070 3071 #define GMAC_RBQBAPQ_OFFSET (0x480) /**< (GMAC_RBQBAPQ) Receive Buffer Queue Base Address Register Priority Queue (index = 1) 0 Offset */ 3072 3073 #define GMAC_RBQBAPQ_RXBQBA_Pos 2 /**< (GMAC_RBQBAPQ) Receive Buffer Queue Base Address Position */ 3074 #define GMAC_RBQBAPQ_RXBQBA_Msk (_U_(0x3FFFFFFF) << GMAC_RBQBAPQ_RXBQBA_Pos) /**< (GMAC_RBQBAPQ) Receive Buffer Queue Base Address Mask */ 3075 #define GMAC_RBQBAPQ_RXBQBA(value) (GMAC_RBQBAPQ_RXBQBA_Msk & ((value) << GMAC_RBQBAPQ_RXBQBA_Pos)) 3076 #define GMAC_RBQBAPQ_MASK _U_(0xFFFFFFFC) /**< \deprecated (GMAC_RBQBAPQ) Register MASK (Use GMAC_RBQBAPQ_Msk instead) */ 3077 #define GMAC_RBQBAPQ_Msk _U_(0xFFFFFFFC) /**< (GMAC_RBQBAPQ) Register Mask */ 3078 3079 3080 /* -------- GMAC_RBSRPQ : (GMAC Offset: 0x4a0) (R/W 32) Receive Buffer Size Register Priority Queue (index = 1) 0 -------- */ 3081 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 3082 #if COMPONENT_TYPEDEF_STYLE == 'N' 3083 typedef union { 3084 struct { 3085 uint32_t RBS:16; /**< bit: 0..15 Receive Buffer Size */ 3086 uint32_t :16; /**< bit: 16..31 Reserved */ 3087 } bit; /**< Structure used for bit access */ 3088 uint32_t reg; /**< Type used for register access */ 3089 } GMAC_RBSRPQ_Type; 3090 #endif 3091 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 3092 3093 #define GMAC_RBSRPQ_OFFSET (0x4A0) /**< (GMAC_RBSRPQ) Receive Buffer Size Register Priority Queue (index = 1) 0 Offset */ 3094 3095 #define GMAC_RBSRPQ_RBS_Pos 0 /**< (GMAC_RBSRPQ) Receive Buffer Size Position */ 3096 #define GMAC_RBSRPQ_RBS_Msk (_U_(0xFFFF) << GMAC_RBSRPQ_RBS_Pos) /**< (GMAC_RBSRPQ) Receive Buffer Size Mask */ 3097 #define GMAC_RBSRPQ_RBS(value) (GMAC_RBSRPQ_RBS_Msk & ((value) << GMAC_RBSRPQ_RBS_Pos)) 3098 #define GMAC_RBSRPQ_MASK _U_(0xFFFF) /**< \deprecated (GMAC_RBSRPQ) Register MASK (Use GMAC_RBSRPQ_Msk instead) */ 3099 #define GMAC_RBSRPQ_Msk _U_(0xFFFF) /**< (GMAC_RBSRPQ) Register Mask */ 3100 3101 3102 /* -------- GMAC_CBSCR : (GMAC Offset: 0x4bc) (R/W 32) Credit-Based Shaping Control Register -------- */ 3103 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 3104 #if COMPONENT_TYPEDEF_STYLE == 'N' 3105 typedef union { 3106 struct { 3107 uint32_t QBE:1; /**< bit: 0 Queue B CBS Enable */ 3108 uint32_t QAE:1; /**< bit: 1 Queue A CBS Enable */ 3109 uint32_t :30; /**< bit: 2..31 Reserved */ 3110 } bit; /**< Structure used for bit access */ 3111 uint32_t reg; /**< Type used for register access */ 3112 } GMAC_CBSCR_Type; 3113 #endif 3114 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 3115 3116 #define GMAC_CBSCR_OFFSET (0x4BC) /**< (GMAC_CBSCR) Credit-Based Shaping Control Register Offset */ 3117 3118 #define GMAC_CBSCR_QBE_Pos 0 /**< (GMAC_CBSCR) Queue B CBS Enable Position */ 3119 #define GMAC_CBSCR_QBE_Msk (_U_(0x1) << GMAC_CBSCR_QBE_Pos) /**< (GMAC_CBSCR) Queue B CBS Enable Mask */ 3120 #define GMAC_CBSCR_QBE GMAC_CBSCR_QBE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_CBSCR_QBE_Msk instead */ 3121 #define GMAC_CBSCR_QAE_Pos 1 /**< (GMAC_CBSCR) Queue A CBS Enable Position */ 3122 #define GMAC_CBSCR_QAE_Msk (_U_(0x1) << GMAC_CBSCR_QAE_Pos) /**< (GMAC_CBSCR) Queue A CBS Enable Mask */ 3123 #define GMAC_CBSCR_QAE GMAC_CBSCR_QAE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_CBSCR_QAE_Msk instead */ 3124 #define GMAC_CBSCR_MASK _U_(0x03) /**< \deprecated (GMAC_CBSCR) Register MASK (Use GMAC_CBSCR_Msk instead) */ 3125 #define GMAC_CBSCR_Msk _U_(0x03) /**< (GMAC_CBSCR) Register Mask */ 3126 3127 3128 /* -------- GMAC_CBSISQA : (GMAC Offset: 0x4c0) (R/W 32) Credit-Based Shaping IdleSlope Register for Queue A -------- */ 3129 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 3130 #if COMPONENT_TYPEDEF_STYLE == 'N' 3131 typedef union { 3132 struct { 3133 uint32_t IS:32; /**< bit: 0..31 IdleSlope */ 3134 } bit; /**< Structure used for bit access */ 3135 uint32_t reg; /**< Type used for register access */ 3136 } GMAC_CBSISQA_Type; 3137 #endif 3138 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 3139 3140 #define GMAC_CBSISQA_OFFSET (0x4C0) /**< (GMAC_CBSISQA) Credit-Based Shaping IdleSlope Register for Queue A Offset */ 3141 3142 #define GMAC_CBSISQA_IS_Pos 0 /**< (GMAC_CBSISQA) IdleSlope Position */ 3143 #define GMAC_CBSISQA_IS_Msk (_U_(0xFFFFFFFF) << GMAC_CBSISQA_IS_Pos) /**< (GMAC_CBSISQA) IdleSlope Mask */ 3144 #define GMAC_CBSISQA_IS(value) (GMAC_CBSISQA_IS_Msk & ((value) << GMAC_CBSISQA_IS_Pos)) 3145 #define GMAC_CBSISQA_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_CBSISQA) Register MASK (Use GMAC_CBSISQA_Msk instead) */ 3146 #define GMAC_CBSISQA_Msk _U_(0xFFFFFFFF) /**< (GMAC_CBSISQA) Register Mask */ 3147 3148 3149 /* -------- GMAC_CBSISQB : (GMAC Offset: 0x4c4) (R/W 32) Credit-Based Shaping IdleSlope Register for Queue B -------- */ 3150 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 3151 #if COMPONENT_TYPEDEF_STYLE == 'N' 3152 typedef union { 3153 struct { 3154 uint32_t IS:32; /**< bit: 0..31 IdleSlope */ 3155 } bit; /**< Structure used for bit access */ 3156 uint32_t reg; /**< Type used for register access */ 3157 } GMAC_CBSISQB_Type; 3158 #endif 3159 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 3160 3161 #define GMAC_CBSISQB_OFFSET (0x4C4) /**< (GMAC_CBSISQB) Credit-Based Shaping IdleSlope Register for Queue B Offset */ 3162 3163 #define GMAC_CBSISQB_IS_Pos 0 /**< (GMAC_CBSISQB) IdleSlope Position */ 3164 #define GMAC_CBSISQB_IS_Msk (_U_(0xFFFFFFFF) << GMAC_CBSISQB_IS_Pos) /**< (GMAC_CBSISQB) IdleSlope Mask */ 3165 #define GMAC_CBSISQB_IS(value) (GMAC_CBSISQB_IS_Msk & ((value) << GMAC_CBSISQB_IS_Pos)) 3166 #define GMAC_CBSISQB_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_CBSISQB) Register MASK (Use GMAC_CBSISQB_Msk instead) */ 3167 #define GMAC_CBSISQB_Msk _U_(0xFFFFFFFF) /**< (GMAC_CBSISQB) Register Mask */ 3168 3169 3170 /* -------- GMAC_ST1RPQ : (GMAC Offset: 0x500) (R/W 32) Screening Type 1 Register Priority Queue (index = 0) 0 -------- */ 3171 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 3172 #if COMPONENT_TYPEDEF_STYLE == 'N' 3173 typedef union { 3174 struct { 3175 uint32_t QNB:3; /**< bit: 0..2 Queue Number (0-2) */ 3176 uint32_t :1; /**< bit: 3 Reserved */ 3177 uint32_t DSTCM:8; /**< bit: 4..11 Differentiated Services or Traffic Class Match */ 3178 uint32_t UDPM:16; /**< bit: 12..27 UDP Port Match */ 3179 uint32_t DSTCE:1; /**< bit: 28 Differentiated Services or Traffic Class Match Enable */ 3180 uint32_t UDPE:1; /**< bit: 29 UDP Port Match Enable */ 3181 uint32_t :2; /**< bit: 30..31 Reserved */ 3182 } bit; /**< Structure used for bit access */ 3183 uint32_t reg; /**< Type used for register access */ 3184 } GMAC_ST1RPQ_Type; 3185 #endif 3186 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 3187 3188 #define GMAC_ST1RPQ_OFFSET (0x500) /**< (GMAC_ST1RPQ) Screening Type 1 Register Priority Queue (index = 0) 0 Offset */ 3189 3190 #define GMAC_ST1RPQ_QNB_Pos 0 /**< (GMAC_ST1RPQ) Queue Number (0-2) Position */ 3191 #define GMAC_ST1RPQ_QNB_Msk (_U_(0x7) << GMAC_ST1RPQ_QNB_Pos) /**< (GMAC_ST1RPQ) Queue Number (0-2) Mask */ 3192 #define GMAC_ST1RPQ_QNB(value) (GMAC_ST1RPQ_QNB_Msk & ((value) << GMAC_ST1RPQ_QNB_Pos)) 3193 #define GMAC_ST1RPQ_DSTCM_Pos 4 /**< (GMAC_ST1RPQ) Differentiated Services or Traffic Class Match Position */ 3194 #define GMAC_ST1RPQ_DSTCM_Msk (_U_(0xFF) << GMAC_ST1RPQ_DSTCM_Pos) /**< (GMAC_ST1RPQ) Differentiated Services or Traffic Class Match Mask */ 3195 #define GMAC_ST1RPQ_DSTCM(value) (GMAC_ST1RPQ_DSTCM_Msk & ((value) << GMAC_ST1RPQ_DSTCM_Pos)) 3196 #define GMAC_ST1RPQ_UDPM_Pos 12 /**< (GMAC_ST1RPQ) UDP Port Match Position */ 3197 #define GMAC_ST1RPQ_UDPM_Msk (_U_(0xFFFF) << GMAC_ST1RPQ_UDPM_Pos) /**< (GMAC_ST1RPQ) UDP Port Match Mask */ 3198 #define GMAC_ST1RPQ_UDPM(value) (GMAC_ST1RPQ_UDPM_Msk & ((value) << GMAC_ST1RPQ_UDPM_Pos)) 3199 #define GMAC_ST1RPQ_DSTCE_Pos 28 /**< (GMAC_ST1RPQ) Differentiated Services or Traffic Class Match Enable Position */ 3200 #define GMAC_ST1RPQ_DSTCE_Msk (_U_(0x1) << GMAC_ST1RPQ_DSTCE_Pos) /**< (GMAC_ST1RPQ) Differentiated Services or Traffic Class Match Enable Mask */ 3201 #define GMAC_ST1RPQ_DSTCE GMAC_ST1RPQ_DSTCE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ST1RPQ_DSTCE_Msk instead */ 3202 #define GMAC_ST1RPQ_UDPE_Pos 29 /**< (GMAC_ST1RPQ) UDP Port Match Enable Position */ 3203 #define GMAC_ST1RPQ_UDPE_Msk (_U_(0x1) << GMAC_ST1RPQ_UDPE_Pos) /**< (GMAC_ST1RPQ) UDP Port Match Enable Mask */ 3204 #define GMAC_ST1RPQ_UDPE GMAC_ST1RPQ_UDPE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ST1RPQ_UDPE_Msk instead */ 3205 #define GMAC_ST1RPQ_MASK _U_(0x3FFFFFF7) /**< \deprecated (GMAC_ST1RPQ) Register MASK (Use GMAC_ST1RPQ_Msk instead) */ 3206 #define GMAC_ST1RPQ_Msk _U_(0x3FFFFFF7) /**< (GMAC_ST1RPQ) Register Mask */ 3207 3208 3209 /* -------- GMAC_ST2RPQ : (GMAC Offset: 0x540) (R/W 32) Screening Type 2 Register Priority Queue (index = 0) 0 -------- */ 3210 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 3211 #if COMPONENT_TYPEDEF_STYLE == 'N' 3212 typedef union { 3213 struct { 3214 uint32_t QNB:3; /**< bit: 0..2 Queue Number (0-2) */ 3215 uint32_t :1; /**< bit: 3 Reserved */ 3216 uint32_t VLANP:3; /**< bit: 4..6 VLAN Priority */ 3217 uint32_t :1; /**< bit: 7 Reserved */ 3218 uint32_t VLANE:1; /**< bit: 8 VLAN Enable */ 3219 uint32_t I2ETH:3; /**< bit: 9..11 Index of Screening Type 2 EtherType register x */ 3220 uint32_t ETHE:1; /**< bit: 12 EtherType Enable */ 3221 uint32_t COMPA:5; /**< bit: 13..17 Index of Screening Type 2 Compare Word 0/Word 1 register x */ 3222 uint32_t COMPAE:1; /**< bit: 18 Compare A Enable */ 3223 uint32_t COMPB:5; /**< bit: 19..23 Index of Screening Type 2 Compare Word 0/Word 1 register x */ 3224 uint32_t COMPBE:1; /**< bit: 24 Compare B Enable */ 3225 uint32_t COMPC:5; /**< bit: 25..29 Index of Screening Type 2 Compare Word 0/Word 1 register x */ 3226 uint32_t COMPCE:1; /**< bit: 30 Compare C Enable */ 3227 uint32_t :1; /**< bit: 31 Reserved */ 3228 } bit; /**< Structure used for bit access */ 3229 uint32_t reg; /**< Type used for register access */ 3230 } GMAC_ST2RPQ_Type; 3231 #endif 3232 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 3233 3234 #define GMAC_ST2RPQ_OFFSET (0x540) /**< (GMAC_ST2RPQ) Screening Type 2 Register Priority Queue (index = 0) 0 Offset */ 3235 3236 #define GMAC_ST2RPQ_QNB_Pos 0 /**< (GMAC_ST2RPQ) Queue Number (0-2) Position */ 3237 #define GMAC_ST2RPQ_QNB_Msk (_U_(0x7) << GMAC_ST2RPQ_QNB_Pos) /**< (GMAC_ST2RPQ) Queue Number (0-2) Mask */ 3238 #define GMAC_ST2RPQ_QNB(value) (GMAC_ST2RPQ_QNB_Msk & ((value) << GMAC_ST2RPQ_QNB_Pos)) 3239 #define GMAC_ST2RPQ_VLANP_Pos 4 /**< (GMAC_ST2RPQ) VLAN Priority Position */ 3240 #define GMAC_ST2RPQ_VLANP_Msk (_U_(0x7) << GMAC_ST2RPQ_VLANP_Pos) /**< (GMAC_ST2RPQ) VLAN Priority Mask */ 3241 #define GMAC_ST2RPQ_VLANP(value) (GMAC_ST2RPQ_VLANP_Msk & ((value) << GMAC_ST2RPQ_VLANP_Pos)) 3242 #define GMAC_ST2RPQ_VLANE_Pos 8 /**< (GMAC_ST2RPQ) VLAN Enable Position */ 3243 #define GMAC_ST2RPQ_VLANE_Msk (_U_(0x1) << GMAC_ST2RPQ_VLANE_Pos) /**< (GMAC_ST2RPQ) VLAN Enable Mask */ 3244 #define GMAC_ST2RPQ_VLANE GMAC_ST2RPQ_VLANE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ST2RPQ_VLANE_Msk instead */ 3245 #define GMAC_ST2RPQ_I2ETH_Pos 9 /**< (GMAC_ST2RPQ) Index of Screening Type 2 EtherType register x Position */ 3246 #define GMAC_ST2RPQ_I2ETH_Msk (_U_(0x7) << GMAC_ST2RPQ_I2ETH_Pos) /**< (GMAC_ST2RPQ) Index of Screening Type 2 EtherType register x Mask */ 3247 #define GMAC_ST2RPQ_I2ETH(value) (GMAC_ST2RPQ_I2ETH_Msk & ((value) << GMAC_ST2RPQ_I2ETH_Pos)) 3248 #define GMAC_ST2RPQ_ETHE_Pos 12 /**< (GMAC_ST2RPQ) EtherType Enable Position */ 3249 #define GMAC_ST2RPQ_ETHE_Msk (_U_(0x1) << GMAC_ST2RPQ_ETHE_Pos) /**< (GMAC_ST2RPQ) EtherType Enable Mask */ 3250 #define GMAC_ST2RPQ_ETHE GMAC_ST2RPQ_ETHE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ST2RPQ_ETHE_Msk instead */ 3251 #define GMAC_ST2RPQ_COMPA_Pos 13 /**< (GMAC_ST2RPQ) Index of Screening Type 2 Compare Word 0/Word 1 register x Position */ 3252 #define GMAC_ST2RPQ_COMPA_Msk (_U_(0x1F) << GMAC_ST2RPQ_COMPA_Pos) /**< (GMAC_ST2RPQ) Index of Screening Type 2 Compare Word 0/Word 1 register x Mask */ 3253 #define GMAC_ST2RPQ_COMPA(value) (GMAC_ST2RPQ_COMPA_Msk & ((value) << GMAC_ST2RPQ_COMPA_Pos)) 3254 #define GMAC_ST2RPQ_COMPAE_Pos 18 /**< (GMAC_ST2RPQ) Compare A Enable Position */ 3255 #define GMAC_ST2RPQ_COMPAE_Msk (_U_(0x1) << GMAC_ST2RPQ_COMPAE_Pos) /**< (GMAC_ST2RPQ) Compare A Enable Mask */ 3256 #define GMAC_ST2RPQ_COMPAE GMAC_ST2RPQ_COMPAE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ST2RPQ_COMPAE_Msk instead */ 3257 #define GMAC_ST2RPQ_COMPB_Pos 19 /**< (GMAC_ST2RPQ) Index of Screening Type 2 Compare Word 0/Word 1 register x Position */ 3258 #define GMAC_ST2RPQ_COMPB_Msk (_U_(0x1F) << GMAC_ST2RPQ_COMPB_Pos) /**< (GMAC_ST2RPQ) Index of Screening Type 2 Compare Word 0/Word 1 register x Mask */ 3259 #define GMAC_ST2RPQ_COMPB(value) (GMAC_ST2RPQ_COMPB_Msk & ((value) << GMAC_ST2RPQ_COMPB_Pos)) 3260 #define GMAC_ST2RPQ_COMPBE_Pos 24 /**< (GMAC_ST2RPQ) Compare B Enable Position */ 3261 #define GMAC_ST2RPQ_COMPBE_Msk (_U_(0x1) << GMAC_ST2RPQ_COMPBE_Pos) /**< (GMAC_ST2RPQ) Compare B Enable Mask */ 3262 #define GMAC_ST2RPQ_COMPBE GMAC_ST2RPQ_COMPBE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ST2RPQ_COMPBE_Msk instead */ 3263 #define GMAC_ST2RPQ_COMPC_Pos 25 /**< (GMAC_ST2RPQ) Index of Screening Type 2 Compare Word 0/Word 1 register x Position */ 3264 #define GMAC_ST2RPQ_COMPC_Msk (_U_(0x1F) << GMAC_ST2RPQ_COMPC_Pos) /**< (GMAC_ST2RPQ) Index of Screening Type 2 Compare Word 0/Word 1 register x Mask */ 3265 #define GMAC_ST2RPQ_COMPC(value) (GMAC_ST2RPQ_COMPC_Msk & ((value) << GMAC_ST2RPQ_COMPC_Pos)) 3266 #define GMAC_ST2RPQ_COMPCE_Pos 30 /**< (GMAC_ST2RPQ) Compare C Enable Position */ 3267 #define GMAC_ST2RPQ_COMPCE_Msk (_U_(0x1) << GMAC_ST2RPQ_COMPCE_Pos) /**< (GMAC_ST2RPQ) Compare C Enable Mask */ 3268 #define GMAC_ST2RPQ_COMPCE GMAC_ST2RPQ_COMPCE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ST2RPQ_COMPCE_Msk instead */ 3269 #define GMAC_ST2RPQ_MASK _U_(0x7FFFFF77) /**< \deprecated (GMAC_ST2RPQ) Register MASK (Use GMAC_ST2RPQ_Msk instead) */ 3270 #define GMAC_ST2RPQ_Msk _U_(0x7FFFFF77) /**< (GMAC_ST2RPQ) Register Mask */ 3271 3272 3273 /* -------- GMAC_IERPQ : (GMAC Offset: 0x600) (/W 32) Interrupt Enable Register Priority Queue (index = 1) 0 -------- */ 3274 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 3275 #if COMPONENT_TYPEDEF_STYLE == 'N' 3276 typedef union { 3277 struct { 3278 uint32_t :1; /**< bit: 0 Reserved */ 3279 uint32_t RCOMP:1; /**< bit: 1 Receive Complete */ 3280 uint32_t RXUBR:1; /**< bit: 2 RX Used Bit Read */ 3281 uint32_t :2; /**< bit: 3..4 Reserved */ 3282 uint32_t RLEX:1; /**< bit: 5 Retry Limit Exceeded or Late Collision */ 3283 uint32_t TFC:1; /**< bit: 6 Transmit Frame Corruption Due to AHB Error */ 3284 uint32_t TCOMP:1; /**< bit: 7 Transmit Complete */ 3285 uint32_t :2; /**< bit: 8..9 Reserved */ 3286 uint32_t ROVR:1; /**< bit: 10 Receive Overrun */ 3287 uint32_t HRESP:1; /**< bit: 11 HRESP Not OK */ 3288 uint32_t :20; /**< bit: 12..31 Reserved */ 3289 } bit; /**< Structure used for bit access */ 3290 uint32_t reg; /**< Type used for register access */ 3291 } GMAC_IERPQ_Type; 3292 #endif 3293 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 3294 3295 #define GMAC_IERPQ_OFFSET (0x600) /**< (GMAC_IERPQ) Interrupt Enable Register Priority Queue (index = 1) 0 Offset */ 3296 3297 #define GMAC_IERPQ_RCOMP_Pos 1 /**< (GMAC_IERPQ) Receive Complete Position */ 3298 #define GMAC_IERPQ_RCOMP_Msk (_U_(0x1) << GMAC_IERPQ_RCOMP_Pos) /**< (GMAC_IERPQ) Receive Complete Mask */ 3299 #define GMAC_IERPQ_RCOMP GMAC_IERPQ_RCOMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IERPQ_RCOMP_Msk instead */ 3300 #define GMAC_IERPQ_RXUBR_Pos 2 /**< (GMAC_IERPQ) RX Used Bit Read Position */ 3301 #define GMAC_IERPQ_RXUBR_Msk (_U_(0x1) << GMAC_IERPQ_RXUBR_Pos) /**< (GMAC_IERPQ) RX Used Bit Read Mask */ 3302 #define GMAC_IERPQ_RXUBR GMAC_IERPQ_RXUBR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IERPQ_RXUBR_Msk instead */ 3303 #define GMAC_IERPQ_RLEX_Pos 5 /**< (GMAC_IERPQ) Retry Limit Exceeded or Late Collision Position */ 3304 #define GMAC_IERPQ_RLEX_Msk (_U_(0x1) << GMAC_IERPQ_RLEX_Pos) /**< (GMAC_IERPQ) Retry Limit Exceeded or Late Collision Mask */ 3305 #define GMAC_IERPQ_RLEX GMAC_IERPQ_RLEX_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IERPQ_RLEX_Msk instead */ 3306 #define GMAC_IERPQ_TFC_Pos 6 /**< (GMAC_IERPQ) Transmit Frame Corruption Due to AHB Error Position */ 3307 #define GMAC_IERPQ_TFC_Msk (_U_(0x1) << GMAC_IERPQ_TFC_Pos) /**< (GMAC_IERPQ) Transmit Frame Corruption Due to AHB Error Mask */ 3308 #define GMAC_IERPQ_TFC GMAC_IERPQ_TFC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IERPQ_TFC_Msk instead */ 3309 #define GMAC_IERPQ_TCOMP_Pos 7 /**< (GMAC_IERPQ) Transmit Complete Position */ 3310 #define GMAC_IERPQ_TCOMP_Msk (_U_(0x1) << GMAC_IERPQ_TCOMP_Pos) /**< (GMAC_IERPQ) Transmit Complete Mask */ 3311 #define GMAC_IERPQ_TCOMP GMAC_IERPQ_TCOMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IERPQ_TCOMP_Msk instead */ 3312 #define GMAC_IERPQ_ROVR_Pos 10 /**< (GMAC_IERPQ) Receive Overrun Position */ 3313 #define GMAC_IERPQ_ROVR_Msk (_U_(0x1) << GMAC_IERPQ_ROVR_Pos) /**< (GMAC_IERPQ) Receive Overrun Mask */ 3314 #define GMAC_IERPQ_ROVR GMAC_IERPQ_ROVR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IERPQ_ROVR_Msk instead */ 3315 #define GMAC_IERPQ_HRESP_Pos 11 /**< (GMAC_IERPQ) HRESP Not OK Position */ 3316 #define GMAC_IERPQ_HRESP_Msk (_U_(0x1) << GMAC_IERPQ_HRESP_Pos) /**< (GMAC_IERPQ) HRESP Not OK Mask */ 3317 #define GMAC_IERPQ_HRESP GMAC_IERPQ_HRESP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IERPQ_HRESP_Msk instead */ 3318 #define GMAC_IERPQ_MASK _U_(0xCE6) /**< \deprecated (GMAC_IERPQ) Register MASK (Use GMAC_IERPQ_Msk instead) */ 3319 #define GMAC_IERPQ_Msk _U_(0xCE6) /**< (GMAC_IERPQ) Register Mask */ 3320 3321 3322 /* -------- GMAC_IDRPQ : (GMAC Offset: 0x620) (/W 32) Interrupt Disable Register Priority Queue (index = 1) 0 -------- */ 3323 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 3324 #if COMPONENT_TYPEDEF_STYLE == 'N' 3325 typedef union { 3326 struct { 3327 uint32_t :1; /**< bit: 0 Reserved */ 3328 uint32_t RCOMP:1; /**< bit: 1 Receive Complete */ 3329 uint32_t RXUBR:1; /**< bit: 2 RX Used Bit Read */ 3330 uint32_t :2; /**< bit: 3..4 Reserved */ 3331 uint32_t RLEX:1; /**< bit: 5 Retry Limit Exceeded or Late Collision */ 3332 uint32_t TFC:1; /**< bit: 6 Transmit Frame Corruption Due to AHB Error */ 3333 uint32_t TCOMP:1; /**< bit: 7 Transmit Complete */ 3334 uint32_t :2; /**< bit: 8..9 Reserved */ 3335 uint32_t ROVR:1; /**< bit: 10 Receive Overrun */ 3336 uint32_t HRESP:1; /**< bit: 11 HRESP Not OK */ 3337 uint32_t :20; /**< bit: 12..31 Reserved */ 3338 } bit; /**< Structure used for bit access */ 3339 uint32_t reg; /**< Type used for register access */ 3340 } GMAC_IDRPQ_Type; 3341 #endif 3342 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 3343 3344 #define GMAC_IDRPQ_OFFSET (0x620) /**< (GMAC_IDRPQ) Interrupt Disable Register Priority Queue (index = 1) 0 Offset */ 3345 3346 #define GMAC_IDRPQ_RCOMP_Pos 1 /**< (GMAC_IDRPQ) Receive Complete Position */ 3347 #define GMAC_IDRPQ_RCOMP_Msk (_U_(0x1) << GMAC_IDRPQ_RCOMP_Pos) /**< (GMAC_IDRPQ) Receive Complete Mask */ 3348 #define GMAC_IDRPQ_RCOMP GMAC_IDRPQ_RCOMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDRPQ_RCOMP_Msk instead */ 3349 #define GMAC_IDRPQ_RXUBR_Pos 2 /**< (GMAC_IDRPQ) RX Used Bit Read Position */ 3350 #define GMAC_IDRPQ_RXUBR_Msk (_U_(0x1) << GMAC_IDRPQ_RXUBR_Pos) /**< (GMAC_IDRPQ) RX Used Bit Read Mask */ 3351 #define GMAC_IDRPQ_RXUBR GMAC_IDRPQ_RXUBR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDRPQ_RXUBR_Msk instead */ 3352 #define GMAC_IDRPQ_RLEX_Pos 5 /**< (GMAC_IDRPQ) Retry Limit Exceeded or Late Collision Position */ 3353 #define GMAC_IDRPQ_RLEX_Msk (_U_(0x1) << GMAC_IDRPQ_RLEX_Pos) /**< (GMAC_IDRPQ) Retry Limit Exceeded or Late Collision Mask */ 3354 #define GMAC_IDRPQ_RLEX GMAC_IDRPQ_RLEX_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDRPQ_RLEX_Msk instead */ 3355 #define GMAC_IDRPQ_TFC_Pos 6 /**< (GMAC_IDRPQ) Transmit Frame Corruption Due to AHB Error Position */ 3356 #define GMAC_IDRPQ_TFC_Msk (_U_(0x1) << GMAC_IDRPQ_TFC_Pos) /**< (GMAC_IDRPQ) Transmit Frame Corruption Due to AHB Error Mask */ 3357 #define GMAC_IDRPQ_TFC GMAC_IDRPQ_TFC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDRPQ_TFC_Msk instead */ 3358 #define GMAC_IDRPQ_TCOMP_Pos 7 /**< (GMAC_IDRPQ) Transmit Complete Position */ 3359 #define GMAC_IDRPQ_TCOMP_Msk (_U_(0x1) << GMAC_IDRPQ_TCOMP_Pos) /**< (GMAC_IDRPQ) Transmit Complete Mask */ 3360 #define GMAC_IDRPQ_TCOMP GMAC_IDRPQ_TCOMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDRPQ_TCOMP_Msk instead */ 3361 #define GMAC_IDRPQ_ROVR_Pos 10 /**< (GMAC_IDRPQ) Receive Overrun Position */ 3362 #define GMAC_IDRPQ_ROVR_Msk (_U_(0x1) << GMAC_IDRPQ_ROVR_Pos) /**< (GMAC_IDRPQ) Receive Overrun Mask */ 3363 #define GMAC_IDRPQ_ROVR GMAC_IDRPQ_ROVR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDRPQ_ROVR_Msk instead */ 3364 #define GMAC_IDRPQ_HRESP_Pos 11 /**< (GMAC_IDRPQ) HRESP Not OK Position */ 3365 #define GMAC_IDRPQ_HRESP_Msk (_U_(0x1) << GMAC_IDRPQ_HRESP_Pos) /**< (GMAC_IDRPQ) HRESP Not OK Mask */ 3366 #define GMAC_IDRPQ_HRESP GMAC_IDRPQ_HRESP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDRPQ_HRESP_Msk instead */ 3367 #define GMAC_IDRPQ_MASK _U_(0xCE6) /**< \deprecated (GMAC_IDRPQ) Register MASK (Use GMAC_IDRPQ_Msk instead) */ 3368 #define GMAC_IDRPQ_Msk _U_(0xCE6) /**< (GMAC_IDRPQ) Register Mask */ 3369 3370 3371 /* -------- GMAC_IMRPQ : (GMAC Offset: 0x640) (R/W 32) Interrupt Mask Register Priority Queue (index = 1) 0 -------- */ 3372 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 3373 #if COMPONENT_TYPEDEF_STYLE == 'N' 3374 typedef union { 3375 struct { 3376 uint32_t :1; /**< bit: 0 Reserved */ 3377 uint32_t RCOMP:1; /**< bit: 1 Receive Complete */ 3378 uint32_t RXUBR:1; /**< bit: 2 RX Used Bit Read */ 3379 uint32_t :2; /**< bit: 3..4 Reserved */ 3380 uint32_t RLEX:1; /**< bit: 5 Retry Limit Exceeded or Late Collision */ 3381 uint32_t AHB:1; /**< bit: 6 AHB Error */ 3382 uint32_t TCOMP:1; /**< bit: 7 Transmit Complete */ 3383 uint32_t :2; /**< bit: 8..9 Reserved */ 3384 uint32_t ROVR:1; /**< bit: 10 Receive Overrun */ 3385 uint32_t HRESP:1; /**< bit: 11 HRESP Not OK */ 3386 uint32_t :20; /**< bit: 12..31 Reserved */ 3387 } bit; /**< Structure used for bit access */ 3388 uint32_t reg; /**< Type used for register access */ 3389 } GMAC_IMRPQ_Type; 3390 #endif 3391 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 3392 3393 #define GMAC_IMRPQ_OFFSET (0x640) /**< (GMAC_IMRPQ) Interrupt Mask Register Priority Queue (index = 1) 0 Offset */ 3394 3395 #define GMAC_IMRPQ_RCOMP_Pos 1 /**< (GMAC_IMRPQ) Receive Complete Position */ 3396 #define GMAC_IMRPQ_RCOMP_Msk (_U_(0x1) << GMAC_IMRPQ_RCOMP_Pos) /**< (GMAC_IMRPQ) Receive Complete Mask */ 3397 #define GMAC_IMRPQ_RCOMP GMAC_IMRPQ_RCOMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMRPQ_RCOMP_Msk instead */ 3398 #define GMAC_IMRPQ_RXUBR_Pos 2 /**< (GMAC_IMRPQ) RX Used Bit Read Position */ 3399 #define GMAC_IMRPQ_RXUBR_Msk (_U_(0x1) << GMAC_IMRPQ_RXUBR_Pos) /**< (GMAC_IMRPQ) RX Used Bit Read Mask */ 3400 #define GMAC_IMRPQ_RXUBR GMAC_IMRPQ_RXUBR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMRPQ_RXUBR_Msk instead */ 3401 #define GMAC_IMRPQ_RLEX_Pos 5 /**< (GMAC_IMRPQ) Retry Limit Exceeded or Late Collision Position */ 3402 #define GMAC_IMRPQ_RLEX_Msk (_U_(0x1) << GMAC_IMRPQ_RLEX_Pos) /**< (GMAC_IMRPQ) Retry Limit Exceeded or Late Collision Mask */ 3403 #define GMAC_IMRPQ_RLEX GMAC_IMRPQ_RLEX_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMRPQ_RLEX_Msk instead */ 3404 #define GMAC_IMRPQ_AHB_Pos 6 /**< (GMAC_IMRPQ) AHB Error Position */ 3405 #define GMAC_IMRPQ_AHB_Msk (_U_(0x1) << GMAC_IMRPQ_AHB_Pos) /**< (GMAC_IMRPQ) AHB Error Mask */ 3406 #define GMAC_IMRPQ_AHB GMAC_IMRPQ_AHB_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMRPQ_AHB_Msk instead */ 3407 #define GMAC_IMRPQ_TCOMP_Pos 7 /**< (GMAC_IMRPQ) Transmit Complete Position */ 3408 #define GMAC_IMRPQ_TCOMP_Msk (_U_(0x1) << GMAC_IMRPQ_TCOMP_Pos) /**< (GMAC_IMRPQ) Transmit Complete Mask */ 3409 #define GMAC_IMRPQ_TCOMP GMAC_IMRPQ_TCOMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMRPQ_TCOMP_Msk instead */ 3410 #define GMAC_IMRPQ_ROVR_Pos 10 /**< (GMAC_IMRPQ) Receive Overrun Position */ 3411 #define GMAC_IMRPQ_ROVR_Msk (_U_(0x1) << GMAC_IMRPQ_ROVR_Pos) /**< (GMAC_IMRPQ) Receive Overrun Mask */ 3412 #define GMAC_IMRPQ_ROVR GMAC_IMRPQ_ROVR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMRPQ_ROVR_Msk instead */ 3413 #define GMAC_IMRPQ_HRESP_Pos 11 /**< (GMAC_IMRPQ) HRESP Not OK Position */ 3414 #define GMAC_IMRPQ_HRESP_Msk (_U_(0x1) << GMAC_IMRPQ_HRESP_Pos) /**< (GMAC_IMRPQ) HRESP Not OK Mask */ 3415 #define GMAC_IMRPQ_HRESP GMAC_IMRPQ_HRESP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMRPQ_HRESP_Msk instead */ 3416 #define GMAC_IMRPQ_MASK _U_(0xCE6) /**< \deprecated (GMAC_IMRPQ) Register MASK (Use GMAC_IMRPQ_Msk instead) */ 3417 #define GMAC_IMRPQ_Msk _U_(0xCE6) /**< (GMAC_IMRPQ) Register Mask */ 3418 3419 3420 /* -------- GMAC_ST2ER : (GMAC Offset: 0x6e0) (R/W 32) Screening Type 2 Ethertype Register (index = 0) 0 -------- */ 3421 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 3422 #if COMPONENT_TYPEDEF_STYLE == 'N' 3423 typedef union { 3424 struct { 3425 uint32_t COMPVAL:16; /**< bit: 0..15 Ethertype Compare Value */ 3426 uint32_t :16; /**< bit: 16..31 Reserved */ 3427 } bit; /**< Structure used for bit access */ 3428 uint32_t reg; /**< Type used for register access */ 3429 } GMAC_ST2ER_Type; 3430 #endif 3431 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 3432 3433 #define GMAC_ST2ER_OFFSET (0x6E0) /**< (GMAC_ST2ER) Screening Type 2 Ethertype Register (index = 0) 0 Offset */ 3434 3435 #define GMAC_ST2ER_COMPVAL_Pos 0 /**< (GMAC_ST2ER) Ethertype Compare Value Position */ 3436 #define GMAC_ST2ER_COMPVAL_Msk (_U_(0xFFFF) << GMAC_ST2ER_COMPVAL_Pos) /**< (GMAC_ST2ER) Ethertype Compare Value Mask */ 3437 #define GMAC_ST2ER_COMPVAL(value) (GMAC_ST2ER_COMPVAL_Msk & ((value) << GMAC_ST2ER_COMPVAL_Pos)) 3438 #define GMAC_ST2ER_MASK _U_(0xFFFF) /**< \deprecated (GMAC_ST2ER) Register MASK (Use GMAC_ST2ER_Msk instead) */ 3439 #define GMAC_ST2ER_Msk _U_(0xFFFF) /**< (GMAC_ST2ER) Register Mask */ 3440 3441 3442 /* -------- GMAC_ST2CW00 : (GMAC Offset: 0x700) (R/W 32) Screening Type 2 Compare Word 0 Register (index = 0) -------- */ 3443 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 3444 #if COMPONENT_TYPEDEF_STYLE == 'N' 3445 typedef union { 3446 struct { 3447 uint32_t MASKVAL:16; /**< bit: 0..15 Mask Value */ 3448 uint32_t COMPVAL:16; /**< bit: 16..31 Compare Value */ 3449 } bit; /**< Structure used for bit access */ 3450 uint32_t reg; /**< Type used for register access */ 3451 } GMAC_ST2CW00_Type; 3452 #endif 3453 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 3454 3455 #define GMAC_ST2CW00_OFFSET (0x700) /**< (GMAC_ST2CW00) Screening Type 2 Compare Word 0 Register (index = 0) Offset */ 3456 3457 #define GMAC_ST2CW00_MASKVAL_Pos 0 /**< (GMAC_ST2CW00) Mask Value Position */ 3458 #define GMAC_ST2CW00_MASKVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW00_MASKVAL_Pos) /**< (GMAC_ST2CW00) Mask Value Mask */ 3459 #define GMAC_ST2CW00_MASKVAL(value) (GMAC_ST2CW00_MASKVAL_Msk & ((value) << GMAC_ST2CW00_MASKVAL_Pos)) 3460 #define GMAC_ST2CW00_COMPVAL_Pos 16 /**< (GMAC_ST2CW00) Compare Value Position */ 3461 #define GMAC_ST2CW00_COMPVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW00_COMPVAL_Pos) /**< (GMAC_ST2CW00) Compare Value Mask */ 3462 #define GMAC_ST2CW00_COMPVAL(value) (GMAC_ST2CW00_COMPVAL_Msk & ((value) << GMAC_ST2CW00_COMPVAL_Pos)) 3463 #define GMAC_ST2CW00_Msk _U_(0xFFFFFFFF) /**< (GMAC_ST2CW00) Register Mask */ 3464 3465 3466 /* -------- GMAC_ST2CW10 : (GMAC Offset: 0x704) (R/W 32) Screening Type 2 Compare Word 1 Register (index = 0) -------- */ 3467 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 3468 #if COMPONENT_TYPEDEF_STYLE == 'N' 3469 typedef union { 3470 struct { 3471 uint32_t OFFSVAL:7; /**< bit: 0..6 Offset Value in Bytes */ 3472 uint32_t OFFSSTRT:2; /**< bit: 7..8 Ethernet Frame Offset Start */ 3473 uint32_t :23; /**< bit: 9..31 Reserved */ 3474 } bit; /**< Structure used for bit access */ 3475 uint32_t reg; /**< Type used for register access */ 3476 } GMAC_ST2CW10_Type; 3477 #endif 3478 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 3479 3480 #define GMAC_ST2CW10_OFFSET (0x704) /**< (GMAC_ST2CW10) Screening Type 2 Compare Word 1 Register (index = 0) Offset */ 3481 3482 #define GMAC_ST2CW10_OFFSVAL_Pos 0 /**< (GMAC_ST2CW10) Offset Value in Bytes Position */ 3483 #define GMAC_ST2CW10_OFFSVAL_Msk (_U_(0x7F) << GMAC_ST2CW10_OFFSVAL_Pos) /**< (GMAC_ST2CW10) Offset Value in Bytes Mask */ 3484 #define GMAC_ST2CW10_OFFSVAL(value) (GMAC_ST2CW10_OFFSVAL_Msk & ((value) << GMAC_ST2CW10_OFFSVAL_Pos)) 3485 #define GMAC_ST2CW10_OFFSSTRT_Pos 7 /**< (GMAC_ST2CW10) Ethernet Frame Offset Start Position */ 3486 #define GMAC_ST2CW10_OFFSSTRT_Msk (_U_(0x3) << GMAC_ST2CW10_OFFSSTRT_Pos) /**< (GMAC_ST2CW10) Ethernet Frame Offset Start Mask */ 3487 #define GMAC_ST2CW10_OFFSSTRT(value) (GMAC_ST2CW10_OFFSSTRT_Msk & ((value) << GMAC_ST2CW10_OFFSSTRT_Pos)) 3488 #define GMAC_ST2CW10_OFFSSTRT_FRAMESTART_Val _U_(0x0) /**< (GMAC_ST2CW10) Offset from the start of the frame */ 3489 #define GMAC_ST2CW10_OFFSSTRT_ETHERTYPE_Val _U_(0x1) /**< (GMAC_ST2CW10) Offset from the byte after the EtherType field */ 3490 #define GMAC_ST2CW10_OFFSSTRT_IP_Val _U_(0x2) /**< (GMAC_ST2CW10) Offset from the byte after the IP header field */ 3491 #define GMAC_ST2CW10_OFFSSTRT_TCP_UDP_Val _U_(0x3) /**< (GMAC_ST2CW10) Offset from the byte after the TCP/UDP header field */ 3492 #define GMAC_ST2CW10_OFFSSTRT_FRAMESTART (GMAC_ST2CW10_OFFSSTRT_FRAMESTART_Val << GMAC_ST2CW10_OFFSSTRT_Pos) /**< (GMAC_ST2CW10) Offset from the start of the frame Position */ 3493 #define GMAC_ST2CW10_OFFSSTRT_ETHERTYPE (GMAC_ST2CW10_OFFSSTRT_ETHERTYPE_Val << GMAC_ST2CW10_OFFSSTRT_Pos) /**< (GMAC_ST2CW10) Offset from the byte after the EtherType field Position */ 3494 #define GMAC_ST2CW10_OFFSSTRT_IP (GMAC_ST2CW10_OFFSSTRT_IP_Val << GMAC_ST2CW10_OFFSSTRT_Pos) /**< (GMAC_ST2CW10) Offset from the byte after the IP header field Position */ 3495 #define GMAC_ST2CW10_OFFSSTRT_TCP_UDP (GMAC_ST2CW10_OFFSSTRT_TCP_UDP_Val << GMAC_ST2CW10_OFFSSTRT_Pos) /**< (GMAC_ST2CW10) Offset from the byte after the TCP/UDP header field Position */ 3496 #define GMAC_ST2CW10_MASK _U_(0x1FF) /**< \deprecated (GMAC_ST2CW10) Register MASK (Use GMAC_ST2CW10_Msk instead) */ 3497 #define GMAC_ST2CW10_Msk _U_(0x1FF) /**< (GMAC_ST2CW10) Register Mask */ 3498 3499 3500 /* -------- GMAC_ST2CW01 : (GMAC Offset: 0x708) (R/W 32) Screening Type 2 Compare Word 0 Register (index = 1) -------- */ 3501 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 3502 #if COMPONENT_TYPEDEF_STYLE == 'N' 3503 typedef union { 3504 struct { 3505 uint32_t MASKVAL:16; /**< bit: 0..15 Mask Value */ 3506 uint32_t COMPVAL:16; /**< bit: 16..31 Compare Value */ 3507 } bit; /**< Structure used for bit access */ 3508 uint32_t reg; /**< Type used for register access */ 3509 } GMAC_ST2CW01_Type; 3510 #endif 3511 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 3512 3513 #define GMAC_ST2CW01_OFFSET (0x708) /**< (GMAC_ST2CW01) Screening Type 2 Compare Word 0 Register (index = 1) Offset */ 3514 3515 #define GMAC_ST2CW01_MASKVAL_Pos 0 /**< (GMAC_ST2CW01) Mask Value Position */ 3516 #define GMAC_ST2CW01_MASKVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW01_MASKVAL_Pos) /**< (GMAC_ST2CW01) Mask Value Mask */ 3517 #define GMAC_ST2CW01_MASKVAL(value) (GMAC_ST2CW01_MASKVAL_Msk & ((value) << GMAC_ST2CW01_MASKVAL_Pos)) 3518 #define GMAC_ST2CW01_COMPVAL_Pos 16 /**< (GMAC_ST2CW01) Compare Value Position */ 3519 #define GMAC_ST2CW01_COMPVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW01_COMPVAL_Pos) /**< (GMAC_ST2CW01) Compare Value Mask */ 3520 #define GMAC_ST2CW01_COMPVAL(value) (GMAC_ST2CW01_COMPVAL_Msk & ((value) << GMAC_ST2CW01_COMPVAL_Pos)) 3521 #define GMAC_ST2CW01_Msk _U_(0xFFFFFFFF) /**< (GMAC_ST2CW01) Register Mask */ 3522 3523 3524 /* -------- GMAC_ST2CW11 : (GMAC Offset: 0x70c) (R/W 32) Screening Type 2 Compare Word 1 Register (index = 1) -------- */ 3525 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 3526 #if COMPONENT_TYPEDEF_STYLE == 'N' 3527 typedef union { 3528 struct { 3529 uint32_t OFFSVAL:7; /**< bit: 0..6 Offset Value in Bytes */ 3530 uint32_t OFFSSTRT:2; /**< bit: 7..8 Ethernet Frame Offset Start */ 3531 uint32_t :23; /**< bit: 9..31 Reserved */ 3532 } bit; /**< Structure used for bit access */ 3533 uint32_t reg; /**< Type used for register access */ 3534 } GMAC_ST2CW11_Type; 3535 #endif 3536 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 3537 3538 #define GMAC_ST2CW11_OFFSET (0x70C) /**< (GMAC_ST2CW11) Screening Type 2 Compare Word 1 Register (index = 1) Offset */ 3539 3540 #define GMAC_ST2CW11_OFFSVAL_Pos 0 /**< (GMAC_ST2CW11) Offset Value in Bytes Position */ 3541 #define GMAC_ST2CW11_OFFSVAL_Msk (_U_(0x7F) << GMAC_ST2CW11_OFFSVAL_Pos) /**< (GMAC_ST2CW11) Offset Value in Bytes Mask */ 3542 #define GMAC_ST2CW11_OFFSVAL(value) (GMAC_ST2CW11_OFFSVAL_Msk & ((value) << GMAC_ST2CW11_OFFSVAL_Pos)) 3543 #define GMAC_ST2CW11_OFFSSTRT_Pos 7 /**< (GMAC_ST2CW11) Ethernet Frame Offset Start Position */ 3544 #define GMAC_ST2CW11_OFFSSTRT_Msk (_U_(0x3) << GMAC_ST2CW11_OFFSSTRT_Pos) /**< (GMAC_ST2CW11) Ethernet Frame Offset Start Mask */ 3545 #define GMAC_ST2CW11_OFFSSTRT(value) (GMAC_ST2CW11_OFFSSTRT_Msk & ((value) << GMAC_ST2CW11_OFFSSTRT_Pos)) 3546 #define GMAC_ST2CW11_OFFSSTRT_FRAMESTART_Val _U_(0x0) /**< (GMAC_ST2CW11) Offset from the start of the frame */ 3547 #define GMAC_ST2CW11_OFFSSTRT_ETHERTYPE_Val _U_(0x1) /**< (GMAC_ST2CW11) Offset from the byte after the EtherType field */ 3548 #define GMAC_ST2CW11_OFFSSTRT_IP_Val _U_(0x2) /**< (GMAC_ST2CW11) Offset from the byte after the IP header field */ 3549 #define GMAC_ST2CW11_OFFSSTRT_TCP_UDP_Val _U_(0x3) /**< (GMAC_ST2CW11) Offset from the byte after the TCP/UDP header field */ 3550 #define GMAC_ST2CW11_OFFSSTRT_FRAMESTART (GMAC_ST2CW11_OFFSSTRT_FRAMESTART_Val << GMAC_ST2CW11_OFFSSTRT_Pos) /**< (GMAC_ST2CW11) Offset from the start of the frame Position */ 3551 #define GMAC_ST2CW11_OFFSSTRT_ETHERTYPE (GMAC_ST2CW11_OFFSSTRT_ETHERTYPE_Val << GMAC_ST2CW11_OFFSSTRT_Pos) /**< (GMAC_ST2CW11) Offset from the byte after the EtherType field Position */ 3552 #define GMAC_ST2CW11_OFFSSTRT_IP (GMAC_ST2CW11_OFFSSTRT_IP_Val << GMAC_ST2CW11_OFFSSTRT_Pos) /**< (GMAC_ST2CW11) Offset from the byte after the IP header field Position */ 3553 #define GMAC_ST2CW11_OFFSSTRT_TCP_UDP (GMAC_ST2CW11_OFFSSTRT_TCP_UDP_Val << GMAC_ST2CW11_OFFSSTRT_Pos) /**< (GMAC_ST2CW11) Offset from the byte after the TCP/UDP header field Position */ 3554 #define GMAC_ST2CW11_MASK _U_(0x1FF) /**< \deprecated (GMAC_ST2CW11) Register MASK (Use GMAC_ST2CW11_Msk instead) */ 3555 #define GMAC_ST2CW11_Msk _U_(0x1FF) /**< (GMAC_ST2CW11) Register Mask */ 3556 3557 3558 /* -------- GMAC_ST2CW02 : (GMAC Offset: 0x710) (R/W 32) Screening Type 2 Compare Word 0 Register (index = 2) -------- */ 3559 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 3560 #if COMPONENT_TYPEDEF_STYLE == 'N' 3561 typedef union { 3562 struct { 3563 uint32_t MASKVAL:16; /**< bit: 0..15 Mask Value */ 3564 uint32_t COMPVAL:16; /**< bit: 16..31 Compare Value */ 3565 } bit; /**< Structure used for bit access */ 3566 uint32_t reg; /**< Type used for register access */ 3567 } GMAC_ST2CW02_Type; 3568 #endif 3569 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 3570 3571 #define GMAC_ST2CW02_OFFSET (0x710) /**< (GMAC_ST2CW02) Screening Type 2 Compare Word 0 Register (index = 2) Offset */ 3572 3573 #define GMAC_ST2CW02_MASKVAL_Pos 0 /**< (GMAC_ST2CW02) Mask Value Position */ 3574 #define GMAC_ST2CW02_MASKVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW02_MASKVAL_Pos) /**< (GMAC_ST2CW02) Mask Value Mask */ 3575 #define GMAC_ST2CW02_MASKVAL(value) (GMAC_ST2CW02_MASKVAL_Msk & ((value) << GMAC_ST2CW02_MASKVAL_Pos)) 3576 #define GMAC_ST2CW02_COMPVAL_Pos 16 /**< (GMAC_ST2CW02) Compare Value Position */ 3577 #define GMAC_ST2CW02_COMPVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW02_COMPVAL_Pos) /**< (GMAC_ST2CW02) Compare Value Mask */ 3578 #define GMAC_ST2CW02_COMPVAL(value) (GMAC_ST2CW02_COMPVAL_Msk & ((value) << GMAC_ST2CW02_COMPVAL_Pos)) 3579 #define GMAC_ST2CW02_Msk _U_(0xFFFFFFFF) /**< (GMAC_ST2CW02) Register Mask */ 3580 3581 3582 /* -------- GMAC_ST2CW12 : (GMAC Offset: 0x714) (R/W 32) Screening Type 2 Compare Word 1 Register (index = 2) -------- */ 3583 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 3584 #if COMPONENT_TYPEDEF_STYLE == 'N' 3585 typedef union { 3586 struct { 3587 uint32_t OFFSVAL:7; /**< bit: 0..6 Offset Value in Bytes */ 3588 uint32_t OFFSSTRT:2; /**< bit: 7..8 Ethernet Frame Offset Start */ 3589 uint32_t :23; /**< bit: 9..31 Reserved */ 3590 } bit; /**< Structure used for bit access */ 3591 uint32_t reg; /**< Type used for register access */ 3592 } GMAC_ST2CW12_Type; 3593 #endif 3594 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 3595 3596 #define GMAC_ST2CW12_OFFSET (0x714) /**< (GMAC_ST2CW12) Screening Type 2 Compare Word 1 Register (index = 2) Offset */ 3597 3598 #define GMAC_ST2CW12_OFFSVAL_Pos 0 /**< (GMAC_ST2CW12) Offset Value in Bytes Position */ 3599 #define GMAC_ST2CW12_OFFSVAL_Msk (_U_(0x7F) << GMAC_ST2CW12_OFFSVAL_Pos) /**< (GMAC_ST2CW12) Offset Value in Bytes Mask */ 3600 #define GMAC_ST2CW12_OFFSVAL(value) (GMAC_ST2CW12_OFFSVAL_Msk & ((value) << GMAC_ST2CW12_OFFSVAL_Pos)) 3601 #define GMAC_ST2CW12_OFFSSTRT_Pos 7 /**< (GMAC_ST2CW12) Ethernet Frame Offset Start Position */ 3602 #define GMAC_ST2CW12_OFFSSTRT_Msk (_U_(0x3) << GMAC_ST2CW12_OFFSSTRT_Pos) /**< (GMAC_ST2CW12) Ethernet Frame Offset Start Mask */ 3603 #define GMAC_ST2CW12_OFFSSTRT(value) (GMAC_ST2CW12_OFFSSTRT_Msk & ((value) << GMAC_ST2CW12_OFFSSTRT_Pos)) 3604 #define GMAC_ST2CW12_OFFSSTRT_FRAMESTART_Val _U_(0x0) /**< (GMAC_ST2CW12) Offset from the start of the frame */ 3605 #define GMAC_ST2CW12_OFFSSTRT_ETHERTYPE_Val _U_(0x1) /**< (GMAC_ST2CW12) Offset from the byte after the EtherType field */ 3606 #define GMAC_ST2CW12_OFFSSTRT_IP_Val _U_(0x2) /**< (GMAC_ST2CW12) Offset from the byte after the IP header field */ 3607 #define GMAC_ST2CW12_OFFSSTRT_TCP_UDP_Val _U_(0x3) /**< (GMAC_ST2CW12) Offset from the byte after the TCP/UDP header field */ 3608 #define GMAC_ST2CW12_OFFSSTRT_FRAMESTART (GMAC_ST2CW12_OFFSSTRT_FRAMESTART_Val << GMAC_ST2CW12_OFFSSTRT_Pos) /**< (GMAC_ST2CW12) Offset from the start of the frame Position */ 3609 #define GMAC_ST2CW12_OFFSSTRT_ETHERTYPE (GMAC_ST2CW12_OFFSSTRT_ETHERTYPE_Val << GMAC_ST2CW12_OFFSSTRT_Pos) /**< (GMAC_ST2CW12) Offset from the byte after the EtherType field Position */ 3610 #define GMAC_ST2CW12_OFFSSTRT_IP (GMAC_ST2CW12_OFFSSTRT_IP_Val << GMAC_ST2CW12_OFFSSTRT_Pos) /**< (GMAC_ST2CW12) Offset from the byte after the IP header field Position */ 3611 #define GMAC_ST2CW12_OFFSSTRT_TCP_UDP (GMAC_ST2CW12_OFFSSTRT_TCP_UDP_Val << GMAC_ST2CW12_OFFSSTRT_Pos) /**< (GMAC_ST2CW12) Offset from the byte after the TCP/UDP header field Position */ 3612 #define GMAC_ST2CW12_MASK _U_(0x1FF) /**< \deprecated (GMAC_ST2CW12) Register MASK (Use GMAC_ST2CW12_Msk instead) */ 3613 #define GMAC_ST2CW12_Msk _U_(0x1FF) /**< (GMAC_ST2CW12) Register Mask */ 3614 3615 3616 /* -------- GMAC_ST2CW03 : (GMAC Offset: 0x718) (R/W 32) Screening Type 2 Compare Word 0 Register (index = 3) -------- */ 3617 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 3618 #if COMPONENT_TYPEDEF_STYLE == 'N' 3619 typedef union { 3620 struct { 3621 uint32_t MASKVAL:16; /**< bit: 0..15 Mask Value */ 3622 uint32_t COMPVAL:16; /**< bit: 16..31 Compare Value */ 3623 } bit; /**< Structure used for bit access */ 3624 uint32_t reg; /**< Type used for register access */ 3625 } GMAC_ST2CW03_Type; 3626 #endif 3627 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 3628 3629 #define GMAC_ST2CW03_OFFSET (0x718) /**< (GMAC_ST2CW03) Screening Type 2 Compare Word 0 Register (index = 3) Offset */ 3630 3631 #define GMAC_ST2CW03_MASKVAL_Pos 0 /**< (GMAC_ST2CW03) Mask Value Position */ 3632 #define GMAC_ST2CW03_MASKVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW03_MASKVAL_Pos) /**< (GMAC_ST2CW03) Mask Value Mask */ 3633 #define GMAC_ST2CW03_MASKVAL(value) (GMAC_ST2CW03_MASKVAL_Msk & ((value) << GMAC_ST2CW03_MASKVAL_Pos)) 3634 #define GMAC_ST2CW03_COMPVAL_Pos 16 /**< (GMAC_ST2CW03) Compare Value Position */ 3635 #define GMAC_ST2CW03_COMPVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW03_COMPVAL_Pos) /**< (GMAC_ST2CW03) Compare Value Mask */ 3636 #define GMAC_ST2CW03_COMPVAL(value) (GMAC_ST2CW03_COMPVAL_Msk & ((value) << GMAC_ST2CW03_COMPVAL_Pos)) 3637 #define GMAC_ST2CW03_Msk _U_(0xFFFFFFFF) /**< (GMAC_ST2CW03) Register Mask */ 3638 3639 3640 /* -------- GMAC_ST2CW13 : (GMAC Offset: 0x71c) (R/W 32) Screening Type 2 Compare Word 1 Register (index = 3) -------- */ 3641 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 3642 #if COMPONENT_TYPEDEF_STYLE == 'N' 3643 typedef union { 3644 struct { 3645 uint32_t OFFSVAL:7; /**< bit: 0..6 Offset Value in Bytes */ 3646 uint32_t OFFSSTRT:2; /**< bit: 7..8 Ethernet Frame Offset Start */ 3647 uint32_t :23; /**< bit: 9..31 Reserved */ 3648 } bit; /**< Structure used for bit access */ 3649 uint32_t reg; /**< Type used for register access */ 3650 } GMAC_ST2CW13_Type; 3651 #endif 3652 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 3653 3654 #define GMAC_ST2CW13_OFFSET (0x71C) /**< (GMAC_ST2CW13) Screening Type 2 Compare Word 1 Register (index = 3) Offset */ 3655 3656 #define GMAC_ST2CW13_OFFSVAL_Pos 0 /**< (GMAC_ST2CW13) Offset Value in Bytes Position */ 3657 #define GMAC_ST2CW13_OFFSVAL_Msk (_U_(0x7F) << GMAC_ST2CW13_OFFSVAL_Pos) /**< (GMAC_ST2CW13) Offset Value in Bytes Mask */ 3658 #define GMAC_ST2CW13_OFFSVAL(value) (GMAC_ST2CW13_OFFSVAL_Msk & ((value) << GMAC_ST2CW13_OFFSVAL_Pos)) 3659 #define GMAC_ST2CW13_OFFSSTRT_Pos 7 /**< (GMAC_ST2CW13) Ethernet Frame Offset Start Position */ 3660 #define GMAC_ST2CW13_OFFSSTRT_Msk (_U_(0x3) << GMAC_ST2CW13_OFFSSTRT_Pos) /**< (GMAC_ST2CW13) Ethernet Frame Offset Start Mask */ 3661 #define GMAC_ST2CW13_OFFSSTRT(value) (GMAC_ST2CW13_OFFSSTRT_Msk & ((value) << GMAC_ST2CW13_OFFSSTRT_Pos)) 3662 #define GMAC_ST2CW13_OFFSSTRT_FRAMESTART_Val _U_(0x0) /**< (GMAC_ST2CW13) Offset from the start of the frame */ 3663 #define GMAC_ST2CW13_OFFSSTRT_ETHERTYPE_Val _U_(0x1) /**< (GMAC_ST2CW13) Offset from the byte after the EtherType field */ 3664 #define GMAC_ST2CW13_OFFSSTRT_IP_Val _U_(0x2) /**< (GMAC_ST2CW13) Offset from the byte after the IP header field */ 3665 #define GMAC_ST2CW13_OFFSSTRT_TCP_UDP_Val _U_(0x3) /**< (GMAC_ST2CW13) Offset from the byte after the TCP/UDP header field */ 3666 #define GMAC_ST2CW13_OFFSSTRT_FRAMESTART (GMAC_ST2CW13_OFFSSTRT_FRAMESTART_Val << GMAC_ST2CW13_OFFSSTRT_Pos) /**< (GMAC_ST2CW13) Offset from the start of the frame Position */ 3667 #define GMAC_ST2CW13_OFFSSTRT_ETHERTYPE (GMAC_ST2CW13_OFFSSTRT_ETHERTYPE_Val << GMAC_ST2CW13_OFFSSTRT_Pos) /**< (GMAC_ST2CW13) Offset from the byte after the EtherType field Position */ 3668 #define GMAC_ST2CW13_OFFSSTRT_IP (GMAC_ST2CW13_OFFSSTRT_IP_Val << GMAC_ST2CW13_OFFSSTRT_Pos) /**< (GMAC_ST2CW13) Offset from the byte after the IP header field Position */ 3669 #define GMAC_ST2CW13_OFFSSTRT_TCP_UDP (GMAC_ST2CW13_OFFSSTRT_TCP_UDP_Val << GMAC_ST2CW13_OFFSSTRT_Pos) /**< (GMAC_ST2CW13) Offset from the byte after the TCP/UDP header field Position */ 3670 #define GMAC_ST2CW13_MASK _U_(0x1FF) /**< \deprecated (GMAC_ST2CW13) Register MASK (Use GMAC_ST2CW13_Msk instead) */ 3671 #define GMAC_ST2CW13_Msk _U_(0x1FF) /**< (GMAC_ST2CW13) Register Mask */ 3672 3673 3674 /* -------- GMAC_ST2CW04 : (GMAC Offset: 0x720) (R/W 32) Screening Type 2 Compare Word 0 Register (index = 4) -------- */ 3675 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 3676 #if COMPONENT_TYPEDEF_STYLE == 'N' 3677 typedef union { 3678 struct { 3679 uint32_t MASKVAL:16; /**< bit: 0..15 Mask Value */ 3680 uint32_t COMPVAL:16; /**< bit: 16..31 Compare Value */ 3681 } bit; /**< Structure used for bit access */ 3682 uint32_t reg; /**< Type used for register access */ 3683 } GMAC_ST2CW04_Type; 3684 #endif 3685 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 3686 3687 #define GMAC_ST2CW04_OFFSET (0x720) /**< (GMAC_ST2CW04) Screening Type 2 Compare Word 0 Register (index = 4) Offset */ 3688 3689 #define GMAC_ST2CW04_MASKVAL_Pos 0 /**< (GMAC_ST2CW04) Mask Value Position */ 3690 #define GMAC_ST2CW04_MASKVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW04_MASKVAL_Pos) /**< (GMAC_ST2CW04) Mask Value Mask */ 3691 #define GMAC_ST2CW04_MASKVAL(value) (GMAC_ST2CW04_MASKVAL_Msk & ((value) << GMAC_ST2CW04_MASKVAL_Pos)) 3692 #define GMAC_ST2CW04_COMPVAL_Pos 16 /**< (GMAC_ST2CW04) Compare Value Position */ 3693 #define GMAC_ST2CW04_COMPVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW04_COMPVAL_Pos) /**< (GMAC_ST2CW04) Compare Value Mask */ 3694 #define GMAC_ST2CW04_COMPVAL(value) (GMAC_ST2CW04_COMPVAL_Msk & ((value) << GMAC_ST2CW04_COMPVAL_Pos)) 3695 #define GMAC_ST2CW04_Msk _U_(0xFFFFFFFF) /**< (GMAC_ST2CW04) Register Mask */ 3696 3697 3698 /* -------- GMAC_ST2CW14 : (GMAC Offset: 0x724) (R/W 32) Screening Type 2 Compare Word 1 Register (index = 4) -------- */ 3699 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 3700 #if COMPONENT_TYPEDEF_STYLE == 'N' 3701 typedef union { 3702 struct { 3703 uint32_t OFFSVAL:7; /**< bit: 0..6 Offset Value in Bytes */ 3704 uint32_t OFFSSTRT:2; /**< bit: 7..8 Ethernet Frame Offset Start */ 3705 uint32_t :23; /**< bit: 9..31 Reserved */ 3706 } bit; /**< Structure used for bit access */ 3707 uint32_t reg; /**< Type used for register access */ 3708 } GMAC_ST2CW14_Type; 3709 #endif 3710 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 3711 3712 #define GMAC_ST2CW14_OFFSET (0x724) /**< (GMAC_ST2CW14) Screening Type 2 Compare Word 1 Register (index = 4) Offset */ 3713 3714 #define GMAC_ST2CW14_OFFSVAL_Pos 0 /**< (GMAC_ST2CW14) Offset Value in Bytes Position */ 3715 #define GMAC_ST2CW14_OFFSVAL_Msk (_U_(0x7F) << GMAC_ST2CW14_OFFSVAL_Pos) /**< (GMAC_ST2CW14) Offset Value in Bytes Mask */ 3716 #define GMAC_ST2CW14_OFFSVAL(value) (GMAC_ST2CW14_OFFSVAL_Msk & ((value) << GMAC_ST2CW14_OFFSVAL_Pos)) 3717 #define GMAC_ST2CW14_OFFSSTRT_Pos 7 /**< (GMAC_ST2CW14) Ethernet Frame Offset Start Position */ 3718 #define GMAC_ST2CW14_OFFSSTRT_Msk (_U_(0x3) << GMAC_ST2CW14_OFFSSTRT_Pos) /**< (GMAC_ST2CW14) Ethernet Frame Offset Start Mask */ 3719 #define GMAC_ST2CW14_OFFSSTRT(value) (GMAC_ST2CW14_OFFSSTRT_Msk & ((value) << GMAC_ST2CW14_OFFSSTRT_Pos)) 3720 #define GMAC_ST2CW14_OFFSSTRT_FRAMESTART_Val _U_(0x0) /**< (GMAC_ST2CW14) Offset from the start of the frame */ 3721 #define GMAC_ST2CW14_OFFSSTRT_ETHERTYPE_Val _U_(0x1) /**< (GMAC_ST2CW14) Offset from the byte after the EtherType field */ 3722 #define GMAC_ST2CW14_OFFSSTRT_IP_Val _U_(0x2) /**< (GMAC_ST2CW14) Offset from the byte after the IP header field */ 3723 #define GMAC_ST2CW14_OFFSSTRT_TCP_UDP_Val _U_(0x3) /**< (GMAC_ST2CW14) Offset from the byte after the TCP/UDP header field */ 3724 #define GMAC_ST2CW14_OFFSSTRT_FRAMESTART (GMAC_ST2CW14_OFFSSTRT_FRAMESTART_Val << GMAC_ST2CW14_OFFSSTRT_Pos) /**< (GMAC_ST2CW14) Offset from the start of the frame Position */ 3725 #define GMAC_ST2CW14_OFFSSTRT_ETHERTYPE (GMAC_ST2CW14_OFFSSTRT_ETHERTYPE_Val << GMAC_ST2CW14_OFFSSTRT_Pos) /**< (GMAC_ST2CW14) Offset from the byte after the EtherType field Position */ 3726 #define GMAC_ST2CW14_OFFSSTRT_IP (GMAC_ST2CW14_OFFSSTRT_IP_Val << GMAC_ST2CW14_OFFSSTRT_Pos) /**< (GMAC_ST2CW14) Offset from the byte after the IP header field Position */ 3727 #define GMAC_ST2CW14_OFFSSTRT_TCP_UDP (GMAC_ST2CW14_OFFSSTRT_TCP_UDP_Val << GMAC_ST2CW14_OFFSSTRT_Pos) /**< (GMAC_ST2CW14) Offset from the byte after the TCP/UDP header field Position */ 3728 #define GMAC_ST2CW14_MASK _U_(0x1FF) /**< \deprecated (GMAC_ST2CW14) Register MASK (Use GMAC_ST2CW14_Msk instead) */ 3729 #define GMAC_ST2CW14_Msk _U_(0x1FF) /**< (GMAC_ST2CW14) Register Mask */ 3730 3731 3732 /* -------- GMAC_ST2CW05 : (GMAC Offset: 0x728) (R/W 32) Screening Type 2 Compare Word 0 Register (index = 5) -------- */ 3733 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 3734 #if COMPONENT_TYPEDEF_STYLE == 'N' 3735 typedef union { 3736 struct { 3737 uint32_t MASKVAL:16; /**< bit: 0..15 Mask Value */ 3738 uint32_t COMPVAL:16; /**< bit: 16..31 Compare Value */ 3739 } bit; /**< Structure used for bit access */ 3740 uint32_t reg; /**< Type used for register access */ 3741 } GMAC_ST2CW05_Type; 3742 #endif 3743 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 3744 3745 #define GMAC_ST2CW05_OFFSET (0x728) /**< (GMAC_ST2CW05) Screening Type 2 Compare Word 0 Register (index = 5) Offset */ 3746 3747 #define GMAC_ST2CW05_MASKVAL_Pos 0 /**< (GMAC_ST2CW05) Mask Value Position */ 3748 #define GMAC_ST2CW05_MASKVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW05_MASKVAL_Pos) /**< (GMAC_ST2CW05) Mask Value Mask */ 3749 #define GMAC_ST2CW05_MASKVAL(value) (GMAC_ST2CW05_MASKVAL_Msk & ((value) << GMAC_ST2CW05_MASKVAL_Pos)) 3750 #define GMAC_ST2CW05_COMPVAL_Pos 16 /**< (GMAC_ST2CW05) Compare Value Position */ 3751 #define GMAC_ST2CW05_COMPVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW05_COMPVAL_Pos) /**< (GMAC_ST2CW05) Compare Value Mask */ 3752 #define GMAC_ST2CW05_COMPVAL(value) (GMAC_ST2CW05_COMPVAL_Msk & ((value) << GMAC_ST2CW05_COMPVAL_Pos)) 3753 #define GMAC_ST2CW05_Msk _U_(0xFFFFFFFF) /**< (GMAC_ST2CW05) Register Mask */ 3754 3755 3756 /* -------- GMAC_ST2CW15 : (GMAC Offset: 0x72c) (R/W 32) Screening Type 2 Compare Word 1 Register (index = 5) -------- */ 3757 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 3758 #if COMPONENT_TYPEDEF_STYLE == 'N' 3759 typedef union { 3760 struct { 3761 uint32_t OFFSVAL:7; /**< bit: 0..6 Offset Value in Bytes */ 3762 uint32_t OFFSSTRT:2; /**< bit: 7..8 Ethernet Frame Offset Start */ 3763 uint32_t :23; /**< bit: 9..31 Reserved */ 3764 } bit; /**< Structure used for bit access */ 3765 uint32_t reg; /**< Type used for register access */ 3766 } GMAC_ST2CW15_Type; 3767 #endif 3768 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 3769 3770 #define GMAC_ST2CW15_OFFSET (0x72C) /**< (GMAC_ST2CW15) Screening Type 2 Compare Word 1 Register (index = 5) Offset */ 3771 3772 #define GMAC_ST2CW15_OFFSVAL_Pos 0 /**< (GMAC_ST2CW15) Offset Value in Bytes Position */ 3773 #define GMAC_ST2CW15_OFFSVAL_Msk (_U_(0x7F) << GMAC_ST2CW15_OFFSVAL_Pos) /**< (GMAC_ST2CW15) Offset Value in Bytes Mask */ 3774 #define GMAC_ST2CW15_OFFSVAL(value) (GMAC_ST2CW15_OFFSVAL_Msk & ((value) << GMAC_ST2CW15_OFFSVAL_Pos)) 3775 #define GMAC_ST2CW15_OFFSSTRT_Pos 7 /**< (GMAC_ST2CW15) Ethernet Frame Offset Start Position */ 3776 #define GMAC_ST2CW15_OFFSSTRT_Msk (_U_(0x3) << GMAC_ST2CW15_OFFSSTRT_Pos) /**< (GMAC_ST2CW15) Ethernet Frame Offset Start Mask */ 3777 #define GMAC_ST2CW15_OFFSSTRT(value) (GMAC_ST2CW15_OFFSSTRT_Msk & ((value) << GMAC_ST2CW15_OFFSSTRT_Pos)) 3778 #define GMAC_ST2CW15_OFFSSTRT_FRAMESTART_Val _U_(0x0) /**< (GMAC_ST2CW15) Offset from the start of the frame */ 3779 #define GMAC_ST2CW15_OFFSSTRT_ETHERTYPE_Val _U_(0x1) /**< (GMAC_ST2CW15) Offset from the byte after the EtherType field */ 3780 #define GMAC_ST2CW15_OFFSSTRT_IP_Val _U_(0x2) /**< (GMAC_ST2CW15) Offset from the byte after the IP header field */ 3781 #define GMAC_ST2CW15_OFFSSTRT_TCP_UDP_Val _U_(0x3) /**< (GMAC_ST2CW15) Offset from the byte after the TCP/UDP header field */ 3782 #define GMAC_ST2CW15_OFFSSTRT_FRAMESTART (GMAC_ST2CW15_OFFSSTRT_FRAMESTART_Val << GMAC_ST2CW15_OFFSSTRT_Pos) /**< (GMAC_ST2CW15) Offset from the start of the frame Position */ 3783 #define GMAC_ST2CW15_OFFSSTRT_ETHERTYPE (GMAC_ST2CW15_OFFSSTRT_ETHERTYPE_Val << GMAC_ST2CW15_OFFSSTRT_Pos) /**< (GMAC_ST2CW15) Offset from the byte after the EtherType field Position */ 3784 #define GMAC_ST2CW15_OFFSSTRT_IP (GMAC_ST2CW15_OFFSSTRT_IP_Val << GMAC_ST2CW15_OFFSSTRT_Pos) /**< (GMAC_ST2CW15) Offset from the byte after the IP header field Position */ 3785 #define GMAC_ST2CW15_OFFSSTRT_TCP_UDP (GMAC_ST2CW15_OFFSSTRT_TCP_UDP_Val << GMAC_ST2CW15_OFFSSTRT_Pos) /**< (GMAC_ST2CW15) Offset from the byte after the TCP/UDP header field Position */ 3786 #define GMAC_ST2CW15_MASK _U_(0x1FF) /**< \deprecated (GMAC_ST2CW15) Register MASK (Use GMAC_ST2CW15_Msk instead) */ 3787 #define GMAC_ST2CW15_Msk _U_(0x1FF) /**< (GMAC_ST2CW15) Register Mask */ 3788 3789 3790 /* -------- GMAC_ST2CW06 : (GMAC Offset: 0x730) (R/W 32) Screening Type 2 Compare Word 0 Register (index = 6) -------- */ 3791 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 3792 #if COMPONENT_TYPEDEF_STYLE == 'N' 3793 typedef union { 3794 struct { 3795 uint32_t MASKVAL:16; /**< bit: 0..15 Mask Value */ 3796 uint32_t COMPVAL:16; /**< bit: 16..31 Compare Value */ 3797 } bit; /**< Structure used for bit access */ 3798 uint32_t reg; /**< Type used for register access */ 3799 } GMAC_ST2CW06_Type; 3800 #endif 3801 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 3802 3803 #define GMAC_ST2CW06_OFFSET (0x730) /**< (GMAC_ST2CW06) Screening Type 2 Compare Word 0 Register (index = 6) Offset */ 3804 3805 #define GMAC_ST2CW06_MASKVAL_Pos 0 /**< (GMAC_ST2CW06) Mask Value Position */ 3806 #define GMAC_ST2CW06_MASKVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW06_MASKVAL_Pos) /**< (GMAC_ST2CW06) Mask Value Mask */ 3807 #define GMAC_ST2CW06_MASKVAL(value) (GMAC_ST2CW06_MASKVAL_Msk & ((value) << GMAC_ST2CW06_MASKVAL_Pos)) 3808 #define GMAC_ST2CW06_COMPVAL_Pos 16 /**< (GMAC_ST2CW06) Compare Value Position */ 3809 #define GMAC_ST2CW06_COMPVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW06_COMPVAL_Pos) /**< (GMAC_ST2CW06) Compare Value Mask */ 3810 #define GMAC_ST2CW06_COMPVAL(value) (GMAC_ST2CW06_COMPVAL_Msk & ((value) << GMAC_ST2CW06_COMPVAL_Pos)) 3811 #define GMAC_ST2CW06_Msk _U_(0xFFFFFFFF) /**< (GMAC_ST2CW06) Register Mask */ 3812 3813 3814 /* -------- GMAC_ST2CW16 : (GMAC Offset: 0x734) (R/W 32) Screening Type 2 Compare Word 1 Register (index = 6) -------- */ 3815 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 3816 #if COMPONENT_TYPEDEF_STYLE == 'N' 3817 typedef union { 3818 struct { 3819 uint32_t OFFSVAL:7; /**< bit: 0..6 Offset Value in Bytes */ 3820 uint32_t OFFSSTRT:2; /**< bit: 7..8 Ethernet Frame Offset Start */ 3821 uint32_t :23; /**< bit: 9..31 Reserved */ 3822 } bit; /**< Structure used for bit access */ 3823 uint32_t reg; /**< Type used for register access */ 3824 } GMAC_ST2CW16_Type; 3825 #endif 3826 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 3827 3828 #define GMAC_ST2CW16_OFFSET (0x734) /**< (GMAC_ST2CW16) Screening Type 2 Compare Word 1 Register (index = 6) Offset */ 3829 3830 #define GMAC_ST2CW16_OFFSVAL_Pos 0 /**< (GMAC_ST2CW16) Offset Value in Bytes Position */ 3831 #define GMAC_ST2CW16_OFFSVAL_Msk (_U_(0x7F) << GMAC_ST2CW16_OFFSVAL_Pos) /**< (GMAC_ST2CW16) Offset Value in Bytes Mask */ 3832 #define GMAC_ST2CW16_OFFSVAL(value) (GMAC_ST2CW16_OFFSVAL_Msk & ((value) << GMAC_ST2CW16_OFFSVAL_Pos)) 3833 #define GMAC_ST2CW16_OFFSSTRT_Pos 7 /**< (GMAC_ST2CW16) Ethernet Frame Offset Start Position */ 3834 #define GMAC_ST2CW16_OFFSSTRT_Msk (_U_(0x3) << GMAC_ST2CW16_OFFSSTRT_Pos) /**< (GMAC_ST2CW16) Ethernet Frame Offset Start Mask */ 3835 #define GMAC_ST2CW16_OFFSSTRT(value) (GMAC_ST2CW16_OFFSSTRT_Msk & ((value) << GMAC_ST2CW16_OFFSSTRT_Pos)) 3836 #define GMAC_ST2CW16_OFFSSTRT_FRAMESTART_Val _U_(0x0) /**< (GMAC_ST2CW16) Offset from the start of the frame */ 3837 #define GMAC_ST2CW16_OFFSSTRT_ETHERTYPE_Val _U_(0x1) /**< (GMAC_ST2CW16) Offset from the byte after the EtherType field */ 3838 #define GMAC_ST2CW16_OFFSSTRT_IP_Val _U_(0x2) /**< (GMAC_ST2CW16) Offset from the byte after the IP header field */ 3839 #define GMAC_ST2CW16_OFFSSTRT_TCP_UDP_Val _U_(0x3) /**< (GMAC_ST2CW16) Offset from the byte after the TCP/UDP header field */ 3840 #define GMAC_ST2CW16_OFFSSTRT_FRAMESTART (GMAC_ST2CW16_OFFSSTRT_FRAMESTART_Val << GMAC_ST2CW16_OFFSSTRT_Pos) /**< (GMAC_ST2CW16) Offset from the start of the frame Position */ 3841 #define GMAC_ST2CW16_OFFSSTRT_ETHERTYPE (GMAC_ST2CW16_OFFSSTRT_ETHERTYPE_Val << GMAC_ST2CW16_OFFSSTRT_Pos) /**< (GMAC_ST2CW16) Offset from the byte after the EtherType field Position */ 3842 #define GMAC_ST2CW16_OFFSSTRT_IP (GMAC_ST2CW16_OFFSSTRT_IP_Val << GMAC_ST2CW16_OFFSSTRT_Pos) /**< (GMAC_ST2CW16) Offset from the byte after the IP header field Position */ 3843 #define GMAC_ST2CW16_OFFSSTRT_TCP_UDP (GMAC_ST2CW16_OFFSSTRT_TCP_UDP_Val << GMAC_ST2CW16_OFFSSTRT_Pos) /**< (GMAC_ST2CW16) Offset from the byte after the TCP/UDP header field Position */ 3844 #define GMAC_ST2CW16_MASK _U_(0x1FF) /**< \deprecated (GMAC_ST2CW16) Register MASK (Use GMAC_ST2CW16_Msk instead) */ 3845 #define GMAC_ST2CW16_Msk _U_(0x1FF) /**< (GMAC_ST2CW16) Register Mask */ 3846 3847 3848 /* -------- GMAC_ST2CW07 : (GMAC Offset: 0x738) (R/W 32) Screening Type 2 Compare Word 0 Register (index = 7) -------- */ 3849 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 3850 #if COMPONENT_TYPEDEF_STYLE == 'N' 3851 typedef union { 3852 struct { 3853 uint32_t MASKVAL:16; /**< bit: 0..15 Mask Value */ 3854 uint32_t COMPVAL:16; /**< bit: 16..31 Compare Value */ 3855 } bit; /**< Structure used for bit access */ 3856 uint32_t reg; /**< Type used for register access */ 3857 } GMAC_ST2CW07_Type; 3858 #endif 3859 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 3860 3861 #define GMAC_ST2CW07_OFFSET (0x738) /**< (GMAC_ST2CW07) Screening Type 2 Compare Word 0 Register (index = 7) Offset */ 3862 3863 #define GMAC_ST2CW07_MASKVAL_Pos 0 /**< (GMAC_ST2CW07) Mask Value Position */ 3864 #define GMAC_ST2CW07_MASKVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW07_MASKVAL_Pos) /**< (GMAC_ST2CW07) Mask Value Mask */ 3865 #define GMAC_ST2CW07_MASKVAL(value) (GMAC_ST2CW07_MASKVAL_Msk & ((value) << GMAC_ST2CW07_MASKVAL_Pos)) 3866 #define GMAC_ST2CW07_COMPVAL_Pos 16 /**< (GMAC_ST2CW07) Compare Value Position */ 3867 #define GMAC_ST2CW07_COMPVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW07_COMPVAL_Pos) /**< (GMAC_ST2CW07) Compare Value Mask */ 3868 #define GMAC_ST2CW07_COMPVAL(value) (GMAC_ST2CW07_COMPVAL_Msk & ((value) << GMAC_ST2CW07_COMPVAL_Pos)) 3869 #define GMAC_ST2CW07_Msk _U_(0xFFFFFFFF) /**< (GMAC_ST2CW07) Register Mask */ 3870 3871 3872 /* -------- GMAC_ST2CW17 : (GMAC Offset: 0x73c) (R/W 32) Screening Type 2 Compare Word 1 Register (index = 7) -------- */ 3873 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 3874 #if COMPONENT_TYPEDEF_STYLE == 'N' 3875 typedef union { 3876 struct { 3877 uint32_t OFFSVAL:7; /**< bit: 0..6 Offset Value in Bytes */ 3878 uint32_t OFFSSTRT:2; /**< bit: 7..8 Ethernet Frame Offset Start */ 3879 uint32_t :23; /**< bit: 9..31 Reserved */ 3880 } bit; /**< Structure used for bit access */ 3881 uint32_t reg; /**< Type used for register access */ 3882 } GMAC_ST2CW17_Type; 3883 #endif 3884 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 3885 3886 #define GMAC_ST2CW17_OFFSET (0x73C) /**< (GMAC_ST2CW17) Screening Type 2 Compare Word 1 Register (index = 7) Offset */ 3887 3888 #define GMAC_ST2CW17_OFFSVAL_Pos 0 /**< (GMAC_ST2CW17) Offset Value in Bytes Position */ 3889 #define GMAC_ST2CW17_OFFSVAL_Msk (_U_(0x7F) << GMAC_ST2CW17_OFFSVAL_Pos) /**< (GMAC_ST2CW17) Offset Value in Bytes Mask */ 3890 #define GMAC_ST2CW17_OFFSVAL(value) (GMAC_ST2CW17_OFFSVAL_Msk & ((value) << GMAC_ST2CW17_OFFSVAL_Pos)) 3891 #define GMAC_ST2CW17_OFFSSTRT_Pos 7 /**< (GMAC_ST2CW17) Ethernet Frame Offset Start Position */ 3892 #define GMAC_ST2CW17_OFFSSTRT_Msk (_U_(0x3) << GMAC_ST2CW17_OFFSSTRT_Pos) /**< (GMAC_ST2CW17) Ethernet Frame Offset Start Mask */ 3893 #define GMAC_ST2CW17_OFFSSTRT(value) (GMAC_ST2CW17_OFFSSTRT_Msk & ((value) << GMAC_ST2CW17_OFFSSTRT_Pos)) 3894 #define GMAC_ST2CW17_OFFSSTRT_FRAMESTART_Val _U_(0x0) /**< (GMAC_ST2CW17) Offset from the start of the frame */ 3895 #define GMAC_ST2CW17_OFFSSTRT_ETHERTYPE_Val _U_(0x1) /**< (GMAC_ST2CW17) Offset from the byte after the EtherType field */ 3896 #define GMAC_ST2CW17_OFFSSTRT_IP_Val _U_(0x2) /**< (GMAC_ST2CW17) Offset from the byte after the IP header field */ 3897 #define GMAC_ST2CW17_OFFSSTRT_TCP_UDP_Val _U_(0x3) /**< (GMAC_ST2CW17) Offset from the byte after the TCP/UDP header field */ 3898 #define GMAC_ST2CW17_OFFSSTRT_FRAMESTART (GMAC_ST2CW17_OFFSSTRT_FRAMESTART_Val << GMAC_ST2CW17_OFFSSTRT_Pos) /**< (GMAC_ST2CW17) Offset from the start of the frame Position */ 3899 #define GMAC_ST2CW17_OFFSSTRT_ETHERTYPE (GMAC_ST2CW17_OFFSSTRT_ETHERTYPE_Val << GMAC_ST2CW17_OFFSSTRT_Pos) /**< (GMAC_ST2CW17) Offset from the byte after the EtherType field Position */ 3900 #define GMAC_ST2CW17_OFFSSTRT_IP (GMAC_ST2CW17_OFFSSTRT_IP_Val << GMAC_ST2CW17_OFFSSTRT_Pos) /**< (GMAC_ST2CW17) Offset from the byte after the IP header field Position */ 3901 #define GMAC_ST2CW17_OFFSSTRT_TCP_UDP (GMAC_ST2CW17_OFFSSTRT_TCP_UDP_Val << GMAC_ST2CW17_OFFSSTRT_Pos) /**< (GMAC_ST2CW17) Offset from the byte after the TCP/UDP header field Position */ 3902 #define GMAC_ST2CW17_MASK _U_(0x1FF) /**< \deprecated (GMAC_ST2CW17) Register MASK (Use GMAC_ST2CW17_Msk instead) */ 3903 #define GMAC_ST2CW17_Msk _U_(0x1FF) /**< (GMAC_ST2CW17) Register Mask */ 3904 3905 3906 /* -------- GMAC_ST2CW08 : (GMAC Offset: 0x740) (R/W 32) Screening Type 2 Compare Word 0 Register (index = 8) -------- */ 3907 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 3908 #if COMPONENT_TYPEDEF_STYLE == 'N' 3909 typedef union { 3910 struct { 3911 uint32_t MASKVAL:16; /**< bit: 0..15 Mask Value */ 3912 uint32_t COMPVAL:16; /**< bit: 16..31 Compare Value */ 3913 } bit; /**< Structure used for bit access */ 3914 uint32_t reg; /**< Type used for register access */ 3915 } GMAC_ST2CW08_Type; 3916 #endif 3917 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 3918 3919 #define GMAC_ST2CW08_OFFSET (0x740) /**< (GMAC_ST2CW08) Screening Type 2 Compare Word 0 Register (index = 8) Offset */ 3920 3921 #define GMAC_ST2CW08_MASKVAL_Pos 0 /**< (GMAC_ST2CW08) Mask Value Position */ 3922 #define GMAC_ST2CW08_MASKVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW08_MASKVAL_Pos) /**< (GMAC_ST2CW08) Mask Value Mask */ 3923 #define GMAC_ST2CW08_MASKVAL(value) (GMAC_ST2CW08_MASKVAL_Msk & ((value) << GMAC_ST2CW08_MASKVAL_Pos)) 3924 #define GMAC_ST2CW08_COMPVAL_Pos 16 /**< (GMAC_ST2CW08) Compare Value Position */ 3925 #define GMAC_ST2CW08_COMPVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW08_COMPVAL_Pos) /**< (GMAC_ST2CW08) Compare Value Mask */ 3926 #define GMAC_ST2CW08_COMPVAL(value) (GMAC_ST2CW08_COMPVAL_Msk & ((value) << GMAC_ST2CW08_COMPVAL_Pos)) 3927 #define GMAC_ST2CW08_Msk _U_(0xFFFFFFFF) /**< (GMAC_ST2CW08) Register Mask */ 3928 3929 3930 /* -------- GMAC_ST2CW18 : (GMAC Offset: 0x744) (R/W 32) Screening Type 2 Compare Word 1 Register (index = 8) -------- */ 3931 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 3932 #if COMPONENT_TYPEDEF_STYLE == 'N' 3933 typedef union { 3934 struct { 3935 uint32_t OFFSVAL:7; /**< bit: 0..6 Offset Value in Bytes */ 3936 uint32_t OFFSSTRT:2; /**< bit: 7..8 Ethernet Frame Offset Start */ 3937 uint32_t :23; /**< bit: 9..31 Reserved */ 3938 } bit; /**< Structure used for bit access */ 3939 uint32_t reg; /**< Type used for register access */ 3940 } GMAC_ST2CW18_Type; 3941 #endif 3942 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 3943 3944 #define GMAC_ST2CW18_OFFSET (0x744) /**< (GMAC_ST2CW18) Screening Type 2 Compare Word 1 Register (index = 8) Offset */ 3945 3946 #define GMAC_ST2CW18_OFFSVAL_Pos 0 /**< (GMAC_ST2CW18) Offset Value in Bytes Position */ 3947 #define GMAC_ST2CW18_OFFSVAL_Msk (_U_(0x7F) << GMAC_ST2CW18_OFFSVAL_Pos) /**< (GMAC_ST2CW18) Offset Value in Bytes Mask */ 3948 #define GMAC_ST2CW18_OFFSVAL(value) (GMAC_ST2CW18_OFFSVAL_Msk & ((value) << GMAC_ST2CW18_OFFSVAL_Pos)) 3949 #define GMAC_ST2CW18_OFFSSTRT_Pos 7 /**< (GMAC_ST2CW18) Ethernet Frame Offset Start Position */ 3950 #define GMAC_ST2CW18_OFFSSTRT_Msk (_U_(0x3) << GMAC_ST2CW18_OFFSSTRT_Pos) /**< (GMAC_ST2CW18) Ethernet Frame Offset Start Mask */ 3951 #define GMAC_ST2CW18_OFFSSTRT(value) (GMAC_ST2CW18_OFFSSTRT_Msk & ((value) << GMAC_ST2CW18_OFFSSTRT_Pos)) 3952 #define GMAC_ST2CW18_OFFSSTRT_FRAMESTART_Val _U_(0x0) /**< (GMAC_ST2CW18) Offset from the start of the frame */ 3953 #define GMAC_ST2CW18_OFFSSTRT_ETHERTYPE_Val _U_(0x1) /**< (GMAC_ST2CW18) Offset from the byte after the EtherType field */ 3954 #define GMAC_ST2CW18_OFFSSTRT_IP_Val _U_(0x2) /**< (GMAC_ST2CW18) Offset from the byte after the IP header field */ 3955 #define GMAC_ST2CW18_OFFSSTRT_TCP_UDP_Val _U_(0x3) /**< (GMAC_ST2CW18) Offset from the byte after the TCP/UDP header field */ 3956 #define GMAC_ST2CW18_OFFSSTRT_FRAMESTART (GMAC_ST2CW18_OFFSSTRT_FRAMESTART_Val << GMAC_ST2CW18_OFFSSTRT_Pos) /**< (GMAC_ST2CW18) Offset from the start of the frame Position */ 3957 #define GMAC_ST2CW18_OFFSSTRT_ETHERTYPE (GMAC_ST2CW18_OFFSSTRT_ETHERTYPE_Val << GMAC_ST2CW18_OFFSSTRT_Pos) /**< (GMAC_ST2CW18) Offset from the byte after the EtherType field Position */ 3958 #define GMAC_ST2CW18_OFFSSTRT_IP (GMAC_ST2CW18_OFFSSTRT_IP_Val << GMAC_ST2CW18_OFFSSTRT_Pos) /**< (GMAC_ST2CW18) Offset from the byte after the IP header field Position */ 3959 #define GMAC_ST2CW18_OFFSSTRT_TCP_UDP (GMAC_ST2CW18_OFFSSTRT_TCP_UDP_Val << GMAC_ST2CW18_OFFSSTRT_Pos) /**< (GMAC_ST2CW18) Offset from the byte after the TCP/UDP header field Position */ 3960 #define GMAC_ST2CW18_MASK _U_(0x1FF) /**< \deprecated (GMAC_ST2CW18) Register MASK (Use GMAC_ST2CW18_Msk instead) */ 3961 #define GMAC_ST2CW18_Msk _U_(0x1FF) /**< (GMAC_ST2CW18) Register Mask */ 3962 3963 3964 /* -------- GMAC_ST2CW09 : (GMAC Offset: 0x748) (R/W 32) Screening Type 2 Compare Word 0 Register (index = 9) -------- */ 3965 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 3966 #if COMPONENT_TYPEDEF_STYLE == 'N' 3967 typedef union { 3968 struct { 3969 uint32_t MASKVAL:16; /**< bit: 0..15 Mask Value */ 3970 uint32_t COMPVAL:16; /**< bit: 16..31 Compare Value */ 3971 } bit; /**< Structure used for bit access */ 3972 uint32_t reg; /**< Type used for register access */ 3973 } GMAC_ST2CW09_Type; 3974 #endif 3975 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 3976 3977 #define GMAC_ST2CW09_OFFSET (0x748) /**< (GMAC_ST2CW09) Screening Type 2 Compare Word 0 Register (index = 9) Offset */ 3978 3979 #define GMAC_ST2CW09_MASKVAL_Pos 0 /**< (GMAC_ST2CW09) Mask Value Position */ 3980 #define GMAC_ST2CW09_MASKVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW09_MASKVAL_Pos) /**< (GMAC_ST2CW09) Mask Value Mask */ 3981 #define GMAC_ST2CW09_MASKVAL(value) (GMAC_ST2CW09_MASKVAL_Msk & ((value) << GMAC_ST2CW09_MASKVAL_Pos)) 3982 #define GMAC_ST2CW09_COMPVAL_Pos 16 /**< (GMAC_ST2CW09) Compare Value Position */ 3983 #define GMAC_ST2CW09_COMPVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW09_COMPVAL_Pos) /**< (GMAC_ST2CW09) Compare Value Mask */ 3984 #define GMAC_ST2CW09_COMPVAL(value) (GMAC_ST2CW09_COMPVAL_Msk & ((value) << GMAC_ST2CW09_COMPVAL_Pos)) 3985 #define GMAC_ST2CW09_Msk _U_(0xFFFFFFFF) /**< (GMAC_ST2CW09) Register Mask */ 3986 3987 3988 /* -------- GMAC_ST2CW19 : (GMAC Offset: 0x74c) (R/W 32) Screening Type 2 Compare Word 1 Register (index = 9) -------- */ 3989 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 3990 #if COMPONENT_TYPEDEF_STYLE == 'N' 3991 typedef union { 3992 struct { 3993 uint32_t OFFSVAL:7; /**< bit: 0..6 Offset Value in Bytes */ 3994 uint32_t OFFSSTRT:2; /**< bit: 7..8 Ethernet Frame Offset Start */ 3995 uint32_t :23; /**< bit: 9..31 Reserved */ 3996 } bit; /**< Structure used for bit access */ 3997 uint32_t reg; /**< Type used for register access */ 3998 } GMAC_ST2CW19_Type; 3999 #endif 4000 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 4001 4002 #define GMAC_ST2CW19_OFFSET (0x74C) /**< (GMAC_ST2CW19) Screening Type 2 Compare Word 1 Register (index = 9) Offset */ 4003 4004 #define GMAC_ST2CW19_OFFSVAL_Pos 0 /**< (GMAC_ST2CW19) Offset Value in Bytes Position */ 4005 #define GMAC_ST2CW19_OFFSVAL_Msk (_U_(0x7F) << GMAC_ST2CW19_OFFSVAL_Pos) /**< (GMAC_ST2CW19) Offset Value in Bytes Mask */ 4006 #define GMAC_ST2CW19_OFFSVAL(value) (GMAC_ST2CW19_OFFSVAL_Msk & ((value) << GMAC_ST2CW19_OFFSVAL_Pos)) 4007 #define GMAC_ST2CW19_OFFSSTRT_Pos 7 /**< (GMAC_ST2CW19) Ethernet Frame Offset Start Position */ 4008 #define GMAC_ST2CW19_OFFSSTRT_Msk (_U_(0x3) << GMAC_ST2CW19_OFFSSTRT_Pos) /**< (GMAC_ST2CW19) Ethernet Frame Offset Start Mask */ 4009 #define GMAC_ST2CW19_OFFSSTRT(value) (GMAC_ST2CW19_OFFSSTRT_Msk & ((value) << GMAC_ST2CW19_OFFSSTRT_Pos)) 4010 #define GMAC_ST2CW19_OFFSSTRT_FRAMESTART_Val _U_(0x0) /**< (GMAC_ST2CW19) Offset from the start of the frame */ 4011 #define GMAC_ST2CW19_OFFSSTRT_ETHERTYPE_Val _U_(0x1) /**< (GMAC_ST2CW19) Offset from the byte after the EtherType field */ 4012 #define GMAC_ST2CW19_OFFSSTRT_IP_Val _U_(0x2) /**< (GMAC_ST2CW19) Offset from the byte after the IP header field */ 4013 #define GMAC_ST2CW19_OFFSSTRT_TCP_UDP_Val _U_(0x3) /**< (GMAC_ST2CW19) Offset from the byte after the TCP/UDP header field */ 4014 #define GMAC_ST2CW19_OFFSSTRT_FRAMESTART (GMAC_ST2CW19_OFFSSTRT_FRAMESTART_Val << GMAC_ST2CW19_OFFSSTRT_Pos) /**< (GMAC_ST2CW19) Offset from the start of the frame Position */ 4015 #define GMAC_ST2CW19_OFFSSTRT_ETHERTYPE (GMAC_ST2CW19_OFFSSTRT_ETHERTYPE_Val << GMAC_ST2CW19_OFFSSTRT_Pos) /**< (GMAC_ST2CW19) Offset from the byte after the EtherType field Position */ 4016 #define GMAC_ST2CW19_OFFSSTRT_IP (GMAC_ST2CW19_OFFSSTRT_IP_Val << GMAC_ST2CW19_OFFSSTRT_Pos) /**< (GMAC_ST2CW19) Offset from the byte after the IP header field Position */ 4017 #define GMAC_ST2CW19_OFFSSTRT_TCP_UDP (GMAC_ST2CW19_OFFSSTRT_TCP_UDP_Val << GMAC_ST2CW19_OFFSSTRT_Pos) /**< (GMAC_ST2CW19) Offset from the byte after the TCP/UDP header field Position */ 4018 #define GMAC_ST2CW19_MASK _U_(0x1FF) /**< \deprecated (GMAC_ST2CW19) Register MASK (Use GMAC_ST2CW19_Msk instead) */ 4019 #define GMAC_ST2CW19_Msk _U_(0x1FF) /**< (GMAC_ST2CW19) Register Mask */ 4020 4021 4022 /* -------- GMAC_ST2CW010 : (GMAC Offset: 0x750) (R/W 32) Screening Type 2 Compare Word 0 Register (index = 10) -------- */ 4023 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 4024 #if COMPONENT_TYPEDEF_STYLE == 'N' 4025 typedef union { 4026 struct { 4027 uint32_t MASKVAL:16; /**< bit: 0..15 Mask Value */ 4028 uint32_t COMPVAL:16; /**< bit: 16..31 Compare Value */ 4029 } bit; /**< Structure used for bit access */ 4030 uint32_t reg; /**< Type used for register access */ 4031 } GMAC_ST2CW010_Type; 4032 #endif 4033 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 4034 4035 #define GMAC_ST2CW010_OFFSET (0x750) /**< (GMAC_ST2CW010) Screening Type 2 Compare Word 0 Register (index = 10) Offset */ 4036 4037 #define GMAC_ST2CW010_MASKVAL_Pos 0 /**< (GMAC_ST2CW010) Mask Value Position */ 4038 #define GMAC_ST2CW010_MASKVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW010_MASKVAL_Pos) /**< (GMAC_ST2CW010) Mask Value Mask */ 4039 #define GMAC_ST2CW010_MASKVAL(value) (GMAC_ST2CW010_MASKVAL_Msk & ((value) << GMAC_ST2CW010_MASKVAL_Pos)) 4040 #define GMAC_ST2CW010_COMPVAL_Pos 16 /**< (GMAC_ST2CW010) Compare Value Position */ 4041 #define GMAC_ST2CW010_COMPVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW010_COMPVAL_Pos) /**< (GMAC_ST2CW010) Compare Value Mask */ 4042 #define GMAC_ST2CW010_COMPVAL(value) (GMAC_ST2CW010_COMPVAL_Msk & ((value) << GMAC_ST2CW010_COMPVAL_Pos)) 4043 #define GMAC_ST2CW010_Msk _U_(0xFFFFFFFF) /**< (GMAC_ST2CW010) Register Mask */ 4044 4045 4046 /* -------- GMAC_ST2CW110 : (GMAC Offset: 0x754) (R/W 32) Screening Type 2 Compare Word 1 Register (index = 10) -------- */ 4047 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 4048 #if COMPONENT_TYPEDEF_STYLE == 'N' 4049 typedef union { 4050 struct { 4051 uint32_t OFFSVAL:7; /**< bit: 0..6 Offset Value in Bytes */ 4052 uint32_t OFFSSTRT:2; /**< bit: 7..8 Ethernet Frame Offset Start */ 4053 uint32_t :23; /**< bit: 9..31 Reserved */ 4054 } bit; /**< Structure used for bit access */ 4055 uint32_t reg; /**< Type used for register access */ 4056 } GMAC_ST2CW110_Type; 4057 #endif 4058 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 4059 4060 #define GMAC_ST2CW110_OFFSET (0x754) /**< (GMAC_ST2CW110) Screening Type 2 Compare Word 1 Register (index = 10) Offset */ 4061 4062 #define GMAC_ST2CW110_OFFSVAL_Pos 0 /**< (GMAC_ST2CW110) Offset Value in Bytes Position */ 4063 #define GMAC_ST2CW110_OFFSVAL_Msk (_U_(0x7F) << GMAC_ST2CW110_OFFSVAL_Pos) /**< (GMAC_ST2CW110) Offset Value in Bytes Mask */ 4064 #define GMAC_ST2CW110_OFFSVAL(value) (GMAC_ST2CW110_OFFSVAL_Msk & ((value) << GMAC_ST2CW110_OFFSVAL_Pos)) 4065 #define GMAC_ST2CW110_OFFSSTRT_Pos 7 /**< (GMAC_ST2CW110) Ethernet Frame Offset Start Position */ 4066 #define GMAC_ST2CW110_OFFSSTRT_Msk (_U_(0x3) << GMAC_ST2CW110_OFFSSTRT_Pos) /**< (GMAC_ST2CW110) Ethernet Frame Offset Start Mask */ 4067 #define GMAC_ST2CW110_OFFSSTRT(value) (GMAC_ST2CW110_OFFSSTRT_Msk & ((value) << GMAC_ST2CW110_OFFSSTRT_Pos)) 4068 #define GMAC_ST2CW110_OFFSSTRT_FRAMESTART_Val _U_(0x0) /**< (GMAC_ST2CW110) Offset from the start of the frame */ 4069 #define GMAC_ST2CW110_OFFSSTRT_ETHERTYPE_Val _U_(0x1) /**< (GMAC_ST2CW110) Offset from the byte after the EtherType field */ 4070 #define GMAC_ST2CW110_OFFSSTRT_IP_Val _U_(0x2) /**< (GMAC_ST2CW110) Offset from the byte after the IP header field */ 4071 #define GMAC_ST2CW110_OFFSSTRT_TCP_UDP_Val _U_(0x3) /**< (GMAC_ST2CW110) Offset from the byte after the TCP/UDP header field */ 4072 #define GMAC_ST2CW110_OFFSSTRT_FRAMESTART (GMAC_ST2CW110_OFFSSTRT_FRAMESTART_Val << GMAC_ST2CW110_OFFSSTRT_Pos) /**< (GMAC_ST2CW110) Offset from the start of the frame Position */ 4073 #define GMAC_ST2CW110_OFFSSTRT_ETHERTYPE (GMAC_ST2CW110_OFFSSTRT_ETHERTYPE_Val << GMAC_ST2CW110_OFFSSTRT_Pos) /**< (GMAC_ST2CW110) Offset from the byte after the EtherType field Position */ 4074 #define GMAC_ST2CW110_OFFSSTRT_IP (GMAC_ST2CW110_OFFSSTRT_IP_Val << GMAC_ST2CW110_OFFSSTRT_Pos) /**< (GMAC_ST2CW110) Offset from the byte after the IP header field Position */ 4075 #define GMAC_ST2CW110_OFFSSTRT_TCP_UDP (GMAC_ST2CW110_OFFSSTRT_TCP_UDP_Val << GMAC_ST2CW110_OFFSSTRT_Pos) /**< (GMAC_ST2CW110) Offset from the byte after the TCP/UDP header field Position */ 4076 #define GMAC_ST2CW110_MASK _U_(0x1FF) /**< \deprecated (GMAC_ST2CW110) Register MASK (Use GMAC_ST2CW110_Msk instead) */ 4077 #define GMAC_ST2CW110_Msk _U_(0x1FF) /**< (GMAC_ST2CW110) Register Mask */ 4078 4079 4080 /* -------- GMAC_ST2CW011 : (GMAC Offset: 0x758) (R/W 32) Screening Type 2 Compare Word 0 Register (index = 11) -------- */ 4081 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 4082 #if COMPONENT_TYPEDEF_STYLE == 'N' 4083 typedef union { 4084 struct { 4085 uint32_t MASKVAL:16; /**< bit: 0..15 Mask Value */ 4086 uint32_t COMPVAL:16; /**< bit: 16..31 Compare Value */ 4087 } bit; /**< Structure used for bit access */ 4088 uint32_t reg; /**< Type used for register access */ 4089 } GMAC_ST2CW011_Type; 4090 #endif 4091 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 4092 4093 #define GMAC_ST2CW011_OFFSET (0x758) /**< (GMAC_ST2CW011) Screening Type 2 Compare Word 0 Register (index = 11) Offset */ 4094 4095 #define GMAC_ST2CW011_MASKVAL_Pos 0 /**< (GMAC_ST2CW011) Mask Value Position */ 4096 #define GMAC_ST2CW011_MASKVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW011_MASKVAL_Pos) /**< (GMAC_ST2CW011) Mask Value Mask */ 4097 #define GMAC_ST2CW011_MASKVAL(value) (GMAC_ST2CW011_MASKVAL_Msk & ((value) << GMAC_ST2CW011_MASKVAL_Pos)) 4098 #define GMAC_ST2CW011_COMPVAL_Pos 16 /**< (GMAC_ST2CW011) Compare Value Position */ 4099 #define GMAC_ST2CW011_COMPVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW011_COMPVAL_Pos) /**< (GMAC_ST2CW011) Compare Value Mask */ 4100 #define GMAC_ST2CW011_COMPVAL(value) (GMAC_ST2CW011_COMPVAL_Msk & ((value) << GMAC_ST2CW011_COMPVAL_Pos)) 4101 #define GMAC_ST2CW011_Msk _U_(0xFFFFFFFF) /**< (GMAC_ST2CW011) Register Mask */ 4102 4103 4104 /* -------- GMAC_ST2CW111 : (GMAC Offset: 0x75c) (R/W 32) Screening Type 2 Compare Word 1 Register (index = 11) -------- */ 4105 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 4106 #if COMPONENT_TYPEDEF_STYLE == 'N' 4107 typedef union { 4108 struct { 4109 uint32_t OFFSVAL:7; /**< bit: 0..6 Offset Value in Bytes */ 4110 uint32_t OFFSSTRT:2; /**< bit: 7..8 Ethernet Frame Offset Start */ 4111 uint32_t :23; /**< bit: 9..31 Reserved */ 4112 } bit; /**< Structure used for bit access */ 4113 uint32_t reg; /**< Type used for register access */ 4114 } GMAC_ST2CW111_Type; 4115 #endif 4116 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 4117 4118 #define GMAC_ST2CW111_OFFSET (0x75C) /**< (GMAC_ST2CW111) Screening Type 2 Compare Word 1 Register (index = 11) Offset */ 4119 4120 #define GMAC_ST2CW111_OFFSVAL_Pos 0 /**< (GMAC_ST2CW111) Offset Value in Bytes Position */ 4121 #define GMAC_ST2CW111_OFFSVAL_Msk (_U_(0x7F) << GMAC_ST2CW111_OFFSVAL_Pos) /**< (GMAC_ST2CW111) Offset Value in Bytes Mask */ 4122 #define GMAC_ST2CW111_OFFSVAL(value) (GMAC_ST2CW111_OFFSVAL_Msk & ((value) << GMAC_ST2CW111_OFFSVAL_Pos)) 4123 #define GMAC_ST2CW111_OFFSSTRT_Pos 7 /**< (GMAC_ST2CW111) Ethernet Frame Offset Start Position */ 4124 #define GMAC_ST2CW111_OFFSSTRT_Msk (_U_(0x3) << GMAC_ST2CW111_OFFSSTRT_Pos) /**< (GMAC_ST2CW111) Ethernet Frame Offset Start Mask */ 4125 #define GMAC_ST2CW111_OFFSSTRT(value) (GMAC_ST2CW111_OFFSSTRT_Msk & ((value) << GMAC_ST2CW111_OFFSSTRT_Pos)) 4126 #define GMAC_ST2CW111_OFFSSTRT_FRAMESTART_Val _U_(0x0) /**< (GMAC_ST2CW111) Offset from the start of the frame */ 4127 #define GMAC_ST2CW111_OFFSSTRT_ETHERTYPE_Val _U_(0x1) /**< (GMAC_ST2CW111) Offset from the byte after the EtherType field */ 4128 #define GMAC_ST2CW111_OFFSSTRT_IP_Val _U_(0x2) /**< (GMAC_ST2CW111) Offset from the byte after the IP header field */ 4129 #define GMAC_ST2CW111_OFFSSTRT_TCP_UDP_Val _U_(0x3) /**< (GMAC_ST2CW111) Offset from the byte after the TCP/UDP header field */ 4130 #define GMAC_ST2CW111_OFFSSTRT_FRAMESTART (GMAC_ST2CW111_OFFSSTRT_FRAMESTART_Val << GMAC_ST2CW111_OFFSSTRT_Pos) /**< (GMAC_ST2CW111) Offset from the start of the frame Position */ 4131 #define GMAC_ST2CW111_OFFSSTRT_ETHERTYPE (GMAC_ST2CW111_OFFSSTRT_ETHERTYPE_Val << GMAC_ST2CW111_OFFSSTRT_Pos) /**< (GMAC_ST2CW111) Offset from the byte after the EtherType field Position */ 4132 #define GMAC_ST2CW111_OFFSSTRT_IP (GMAC_ST2CW111_OFFSSTRT_IP_Val << GMAC_ST2CW111_OFFSSTRT_Pos) /**< (GMAC_ST2CW111) Offset from the byte after the IP header field Position */ 4133 #define GMAC_ST2CW111_OFFSSTRT_TCP_UDP (GMAC_ST2CW111_OFFSSTRT_TCP_UDP_Val << GMAC_ST2CW111_OFFSSTRT_Pos) /**< (GMAC_ST2CW111) Offset from the byte after the TCP/UDP header field Position */ 4134 #define GMAC_ST2CW111_MASK _U_(0x1FF) /**< \deprecated (GMAC_ST2CW111) Register MASK (Use GMAC_ST2CW111_Msk instead) */ 4135 #define GMAC_ST2CW111_Msk _U_(0x1FF) /**< (GMAC_ST2CW111) Register Mask */ 4136 4137 4138 /* -------- GMAC_ST2CW012 : (GMAC Offset: 0x760) (R/W 32) Screening Type 2 Compare Word 0 Register (index = 12) -------- */ 4139 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 4140 #if COMPONENT_TYPEDEF_STYLE == 'N' 4141 typedef union { 4142 struct { 4143 uint32_t MASKVAL:16; /**< bit: 0..15 Mask Value */ 4144 uint32_t COMPVAL:16; /**< bit: 16..31 Compare Value */ 4145 } bit; /**< Structure used for bit access */ 4146 uint32_t reg; /**< Type used for register access */ 4147 } GMAC_ST2CW012_Type; 4148 #endif 4149 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 4150 4151 #define GMAC_ST2CW012_OFFSET (0x760) /**< (GMAC_ST2CW012) Screening Type 2 Compare Word 0 Register (index = 12) Offset */ 4152 4153 #define GMAC_ST2CW012_MASKVAL_Pos 0 /**< (GMAC_ST2CW012) Mask Value Position */ 4154 #define GMAC_ST2CW012_MASKVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW012_MASKVAL_Pos) /**< (GMAC_ST2CW012) Mask Value Mask */ 4155 #define GMAC_ST2CW012_MASKVAL(value) (GMAC_ST2CW012_MASKVAL_Msk & ((value) << GMAC_ST2CW012_MASKVAL_Pos)) 4156 #define GMAC_ST2CW012_COMPVAL_Pos 16 /**< (GMAC_ST2CW012) Compare Value Position */ 4157 #define GMAC_ST2CW012_COMPVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW012_COMPVAL_Pos) /**< (GMAC_ST2CW012) Compare Value Mask */ 4158 #define GMAC_ST2CW012_COMPVAL(value) (GMAC_ST2CW012_COMPVAL_Msk & ((value) << GMAC_ST2CW012_COMPVAL_Pos)) 4159 #define GMAC_ST2CW012_Msk _U_(0xFFFFFFFF) /**< (GMAC_ST2CW012) Register Mask */ 4160 4161 4162 /* -------- GMAC_ST2CW112 : (GMAC Offset: 0x764) (R/W 32) Screening Type 2 Compare Word 1 Register (index = 12) -------- */ 4163 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 4164 #if COMPONENT_TYPEDEF_STYLE == 'N' 4165 typedef union { 4166 struct { 4167 uint32_t OFFSVAL:7; /**< bit: 0..6 Offset Value in Bytes */ 4168 uint32_t OFFSSTRT:2; /**< bit: 7..8 Ethernet Frame Offset Start */ 4169 uint32_t :23; /**< bit: 9..31 Reserved */ 4170 } bit; /**< Structure used for bit access */ 4171 uint32_t reg; /**< Type used for register access */ 4172 } GMAC_ST2CW112_Type; 4173 #endif 4174 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 4175 4176 #define GMAC_ST2CW112_OFFSET (0x764) /**< (GMAC_ST2CW112) Screening Type 2 Compare Word 1 Register (index = 12) Offset */ 4177 4178 #define GMAC_ST2CW112_OFFSVAL_Pos 0 /**< (GMAC_ST2CW112) Offset Value in Bytes Position */ 4179 #define GMAC_ST2CW112_OFFSVAL_Msk (_U_(0x7F) << GMAC_ST2CW112_OFFSVAL_Pos) /**< (GMAC_ST2CW112) Offset Value in Bytes Mask */ 4180 #define GMAC_ST2CW112_OFFSVAL(value) (GMAC_ST2CW112_OFFSVAL_Msk & ((value) << GMAC_ST2CW112_OFFSVAL_Pos)) 4181 #define GMAC_ST2CW112_OFFSSTRT_Pos 7 /**< (GMAC_ST2CW112) Ethernet Frame Offset Start Position */ 4182 #define GMAC_ST2CW112_OFFSSTRT_Msk (_U_(0x3) << GMAC_ST2CW112_OFFSSTRT_Pos) /**< (GMAC_ST2CW112) Ethernet Frame Offset Start Mask */ 4183 #define GMAC_ST2CW112_OFFSSTRT(value) (GMAC_ST2CW112_OFFSSTRT_Msk & ((value) << GMAC_ST2CW112_OFFSSTRT_Pos)) 4184 #define GMAC_ST2CW112_OFFSSTRT_FRAMESTART_Val _U_(0x0) /**< (GMAC_ST2CW112) Offset from the start of the frame */ 4185 #define GMAC_ST2CW112_OFFSSTRT_ETHERTYPE_Val _U_(0x1) /**< (GMAC_ST2CW112) Offset from the byte after the EtherType field */ 4186 #define GMAC_ST2CW112_OFFSSTRT_IP_Val _U_(0x2) /**< (GMAC_ST2CW112) Offset from the byte after the IP header field */ 4187 #define GMAC_ST2CW112_OFFSSTRT_TCP_UDP_Val _U_(0x3) /**< (GMAC_ST2CW112) Offset from the byte after the TCP/UDP header field */ 4188 #define GMAC_ST2CW112_OFFSSTRT_FRAMESTART (GMAC_ST2CW112_OFFSSTRT_FRAMESTART_Val << GMAC_ST2CW112_OFFSSTRT_Pos) /**< (GMAC_ST2CW112) Offset from the start of the frame Position */ 4189 #define GMAC_ST2CW112_OFFSSTRT_ETHERTYPE (GMAC_ST2CW112_OFFSSTRT_ETHERTYPE_Val << GMAC_ST2CW112_OFFSSTRT_Pos) /**< (GMAC_ST2CW112) Offset from the byte after the EtherType field Position */ 4190 #define GMAC_ST2CW112_OFFSSTRT_IP (GMAC_ST2CW112_OFFSSTRT_IP_Val << GMAC_ST2CW112_OFFSSTRT_Pos) /**< (GMAC_ST2CW112) Offset from the byte after the IP header field Position */ 4191 #define GMAC_ST2CW112_OFFSSTRT_TCP_UDP (GMAC_ST2CW112_OFFSSTRT_TCP_UDP_Val << GMAC_ST2CW112_OFFSSTRT_Pos) /**< (GMAC_ST2CW112) Offset from the byte after the TCP/UDP header field Position */ 4192 #define GMAC_ST2CW112_MASK _U_(0x1FF) /**< \deprecated (GMAC_ST2CW112) Register MASK (Use GMAC_ST2CW112_Msk instead) */ 4193 #define GMAC_ST2CW112_Msk _U_(0x1FF) /**< (GMAC_ST2CW112) Register Mask */ 4194 4195 4196 /* -------- GMAC_ST2CW013 : (GMAC Offset: 0x768) (R/W 32) Screening Type 2 Compare Word 0 Register (index = 13) -------- */ 4197 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 4198 #if COMPONENT_TYPEDEF_STYLE == 'N' 4199 typedef union { 4200 struct { 4201 uint32_t MASKVAL:16; /**< bit: 0..15 Mask Value */ 4202 uint32_t COMPVAL:16; /**< bit: 16..31 Compare Value */ 4203 } bit; /**< Structure used for bit access */ 4204 uint32_t reg; /**< Type used for register access */ 4205 } GMAC_ST2CW013_Type; 4206 #endif 4207 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 4208 4209 #define GMAC_ST2CW013_OFFSET (0x768) /**< (GMAC_ST2CW013) Screening Type 2 Compare Word 0 Register (index = 13) Offset */ 4210 4211 #define GMAC_ST2CW013_MASKVAL_Pos 0 /**< (GMAC_ST2CW013) Mask Value Position */ 4212 #define GMAC_ST2CW013_MASKVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW013_MASKVAL_Pos) /**< (GMAC_ST2CW013) Mask Value Mask */ 4213 #define GMAC_ST2CW013_MASKVAL(value) (GMAC_ST2CW013_MASKVAL_Msk & ((value) << GMAC_ST2CW013_MASKVAL_Pos)) 4214 #define GMAC_ST2CW013_COMPVAL_Pos 16 /**< (GMAC_ST2CW013) Compare Value Position */ 4215 #define GMAC_ST2CW013_COMPVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW013_COMPVAL_Pos) /**< (GMAC_ST2CW013) Compare Value Mask */ 4216 #define GMAC_ST2CW013_COMPVAL(value) (GMAC_ST2CW013_COMPVAL_Msk & ((value) << GMAC_ST2CW013_COMPVAL_Pos)) 4217 #define GMAC_ST2CW013_Msk _U_(0xFFFFFFFF) /**< (GMAC_ST2CW013) Register Mask */ 4218 4219 4220 /* -------- GMAC_ST2CW113 : (GMAC Offset: 0x76c) (R/W 32) Screening Type 2 Compare Word 1 Register (index = 13) -------- */ 4221 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 4222 #if COMPONENT_TYPEDEF_STYLE == 'N' 4223 typedef union { 4224 struct { 4225 uint32_t OFFSVAL:7; /**< bit: 0..6 Offset Value in Bytes */ 4226 uint32_t OFFSSTRT:2; /**< bit: 7..8 Ethernet Frame Offset Start */ 4227 uint32_t :23; /**< bit: 9..31 Reserved */ 4228 } bit; /**< Structure used for bit access */ 4229 uint32_t reg; /**< Type used for register access */ 4230 } GMAC_ST2CW113_Type; 4231 #endif 4232 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 4233 4234 #define GMAC_ST2CW113_OFFSET (0x76C) /**< (GMAC_ST2CW113) Screening Type 2 Compare Word 1 Register (index = 13) Offset */ 4235 4236 #define GMAC_ST2CW113_OFFSVAL_Pos 0 /**< (GMAC_ST2CW113) Offset Value in Bytes Position */ 4237 #define GMAC_ST2CW113_OFFSVAL_Msk (_U_(0x7F) << GMAC_ST2CW113_OFFSVAL_Pos) /**< (GMAC_ST2CW113) Offset Value in Bytes Mask */ 4238 #define GMAC_ST2CW113_OFFSVAL(value) (GMAC_ST2CW113_OFFSVAL_Msk & ((value) << GMAC_ST2CW113_OFFSVAL_Pos)) 4239 #define GMAC_ST2CW113_OFFSSTRT_Pos 7 /**< (GMAC_ST2CW113) Ethernet Frame Offset Start Position */ 4240 #define GMAC_ST2CW113_OFFSSTRT_Msk (_U_(0x3) << GMAC_ST2CW113_OFFSSTRT_Pos) /**< (GMAC_ST2CW113) Ethernet Frame Offset Start Mask */ 4241 #define GMAC_ST2CW113_OFFSSTRT(value) (GMAC_ST2CW113_OFFSSTRT_Msk & ((value) << GMAC_ST2CW113_OFFSSTRT_Pos)) 4242 #define GMAC_ST2CW113_OFFSSTRT_FRAMESTART_Val _U_(0x0) /**< (GMAC_ST2CW113) Offset from the start of the frame */ 4243 #define GMAC_ST2CW113_OFFSSTRT_ETHERTYPE_Val _U_(0x1) /**< (GMAC_ST2CW113) Offset from the byte after the EtherType field */ 4244 #define GMAC_ST2CW113_OFFSSTRT_IP_Val _U_(0x2) /**< (GMAC_ST2CW113) Offset from the byte after the IP header field */ 4245 #define GMAC_ST2CW113_OFFSSTRT_TCP_UDP_Val _U_(0x3) /**< (GMAC_ST2CW113) Offset from the byte after the TCP/UDP header field */ 4246 #define GMAC_ST2CW113_OFFSSTRT_FRAMESTART (GMAC_ST2CW113_OFFSSTRT_FRAMESTART_Val << GMAC_ST2CW113_OFFSSTRT_Pos) /**< (GMAC_ST2CW113) Offset from the start of the frame Position */ 4247 #define GMAC_ST2CW113_OFFSSTRT_ETHERTYPE (GMAC_ST2CW113_OFFSSTRT_ETHERTYPE_Val << GMAC_ST2CW113_OFFSSTRT_Pos) /**< (GMAC_ST2CW113) Offset from the byte after the EtherType field Position */ 4248 #define GMAC_ST2CW113_OFFSSTRT_IP (GMAC_ST2CW113_OFFSSTRT_IP_Val << GMAC_ST2CW113_OFFSSTRT_Pos) /**< (GMAC_ST2CW113) Offset from the byte after the IP header field Position */ 4249 #define GMAC_ST2CW113_OFFSSTRT_TCP_UDP (GMAC_ST2CW113_OFFSSTRT_TCP_UDP_Val << GMAC_ST2CW113_OFFSSTRT_Pos) /**< (GMAC_ST2CW113) Offset from the byte after the TCP/UDP header field Position */ 4250 #define GMAC_ST2CW113_MASK _U_(0x1FF) /**< \deprecated (GMAC_ST2CW113) Register MASK (Use GMAC_ST2CW113_Msk instead) */ 4251 #define GMAC_ST2CW113_Msk _U_(0x1FF) /**< (GMAC_ST2CW113) Register Mask */ 4252 4253 4254 /* -------- GMAC_ST2CW014 : (GMAC Offset: 0x770) (R/W 32) Screening Type 2 Compare Word 0 Register (index = 14) -------- */ 4255 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 4256 #if COMPONENT_TYPEDEF_STYLE == 'N' 4257 typedef union { 4258 struct { 4259 uint32_t MASKVAL:16; /**< bit: 0..15 Mask Value */ 4260 uint32_t COMPVAL:16; /**< bit: 16..31 Compare Value */ 4261 } bit; /**< Structure used for bit access */ 4262 uint32_t reg; /**< Type used for register access */ 4263 } GMAC_ST2CW014_Type; 4264 #endif 4265 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 4266 4267 #define GMAC_ST2CW014_OFFSET (0x770) /**< (GMAC_ST2CW014) Screening Type 2 Compare Word 0 Register (index = 14) Offset */ 4268 4269 #define GMAC_ST2CW014_MASKVAL_Pos 0 /**< (GMAC_ST2CW014) Mask Value Position */ 4270 #define GMAC_ST2CW014_MASKVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW014_MASKVAL_Pos) /**< (GMAC_ST2CW014) Mask Value Mask */ 4271 #define GMAC_ST2CW014_MASKVAL(value) (GMAC_ST2CW014_MASKVAL_Msk & ((value) << GMAC_ST2CW014_MASKVAL_Pos)) 4272 #define GMAC_ST2CW014_COMPVAL_Pos 16 /**< (GMAC_ST2CW014) Compare Value Position */ 4273 #define GMAC_ST2CW014_COMPVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW014_COMPVAL_Pos) /**< (GMAC_ST2CW014) Compare Value Mask */ 4274 #define GMAC_ST2CW014_COMPVAL(value) (GMAC_ST2CW014_COMPVAL_Msk & ((value) << GMAC_ST2CW014_COMPVAL_Pos)) 4275 #define GMAC_ST2CW014_Msk _U_(0xFFFFFFFF) /**< (GMAC_ST2CW014) Register Mask */ 4276 4277 4278 /* -------- GMAC_ST2CW114 : (GMAC Offset: 0x774) (R/W 32) Screening Type 2 Compare Word 1 Register (index = 14) -------- */ 4279 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 4280 #if COMPONENT_TYPEDEF_STYLE == 'N' 4281 typedef union { 4282 struct { 4283 uint32_t OFFSVAL:7; /**< bit: 0..6 Offset Value in Bytes */ 4284 uint32_t OFFSSTRT:2; /**< bit: 7..8 Ethernet Frame Offset Start */ 4285 uint32_t :23; /**< bit: 9..31 Reserved */ 4286 } bit; /**< Structure used for bit access */ 4287 uint32_t reg; /**< Type used for register access */ 4288 } GMAC_ST2CW114_Type; 4289 #endif 4290 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 4291 4292 #define GMAC_ST2CW114_OFFSET (0x774) /**< (GMAC_ST2CW114) Screening Type 2 Compare Word 1 Register (index = 14) Offset */ 4293 4294 #define GMAC_ST2CW114_OFFSVAL_Pos 0 /**< (GMAC_ST2CW114) Offset Value in Bytes Position */ 4295 #define GMAC_ST2CW114_OFFSVAL_Msk (_U_(0x7F) << GMAC_ST2CW114_OFFSVAL_Pos) /**< (GMAC_ST2CW114) Offset Value in Bytes Mask */ 4296 #define GMAC_ST2CW114_OFFSVAL(value) (GMAC_ST2CW114_OFFSVAL_Msk & ((value) << GMAC_ST2CW114_OFFSVAL_Pos)) 4297 #define GMAC_ST2CW114_OFFSSTRT_Pos 7 /**< (GMAC_ST2CW114) Ethernet Frame Offset Start Position */ 4298 #define GMAC_ST2CW114_OFFSSTRT_Msk (_U_(0x3) << GMAC_ST2CW114_OFFSSTRT_Pos) /**< (GMAC_ST2CW114) Ethernet Frame Offset Start Mask */ 4299 #define GMAC_ST2CW114_OFFSSTRT(value) (GMAC_ST2CW114_OFFSSTRT_Msk & ((value) << GMAC_ST2CW114_OFFSSTRT_Pos)) 4300 #define GMAC_ST2CW114_OFFSSTRT_FRAMESTART_Val _U_(0x0) /**< (GMAC_ST2CW114) Offset from the start of the frame */ 4301 #define GMAC_ST2CW114_OFFSSTRT_ETHERTYPE_Val _U_(0x1) /**< (GMAC_ST2CW114) Offset from the byte after the EtherType field */ 4302 #define GMAC_ST2CW114_OFFSSTRT_IP_Val _U_(0x2) /**< (GMAC_ST2CW114) Offset from the byte after the IP header field */ 4303 #define GMAC_ST2CW114_OFFSSTRT_TCP_UDP_Val _U_(0x3) /**< (GMAC_ST2CW114) Offset from the byte after the TCP/UDP header field */ 4304 #define GMAC_ST2CW114_OFFSSTRT_FRAMESTART (GMAC_ST2CW114_OFFSSTRT_FRAMESTART_Val << GMAC_ST2CW114_OFFSSTRT_Pos) /**< (GMAC_ST2CW114) Offset from the start of the frame Position */ 4305 #define GMAC_ST2CW114_OFFSSTRT_ETHERTYPE (GMAC_ST2CW114_OFFSSTRT_ETHERTYPE_Val << GMAC_ST2CW114_OFFSSTRT_Pos) /**< (GMAC_ST2CW114) Offset from the byte after the EtherType field Position */ 4306 #define GMAC_ST2CW114_OFFSSTRT_IP (GMAC_ST2CW114_OFFSSTRT_IP_Val << GMAC_ST2CW114_OFFSSTRT_Pos) /**< (GMAC_ST2CW114) Offset from the byte after the IP header field Position */ 4307 #define GMAC_ST2CW114_OFFSSTRT_TCP_UDP (GMAC_ST2CW114_OFFSSTRT_TCP_UDP_Val << GMAC_ST2CW114_OFFSSTRT_Pos) /**< (GMAC_ST2CW114) Offset from the byte after the TCP/UDP header field Position */ 4308 #define GMAC_ST2CW114_MASK _U_(0x1FF) /**< \deprecated (GMAC_ST2CW114) Register MASK (Use GMAC_ST2CW114_Msk instead) */ 4309 #define GMAC_ST2CW114_Msk _U_(0x1FF) /**< (GMAC_ST2CW114) Register Mask */ 4310 4311 4312 /* -------- GMAC_ST2CW015 : (GMAC Offset: 0x778) (R/W 32) Screening Type 2 Compare Word 0 Register (index = 15) -------- */ 4313 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 4314 #if COMPONENT_TYPEDEF_STYLE == 'N' 4315 typedef union { 4316 struct { 4317 uint32_t MASKVAL:16; /**< bit: 0..15 Mask Value */ 4318 uint32_t COMPVAL:16; /**< bit: 16..31 Compare Value */ 4319 } bit; /**< Structure used for bit access */ 4320 uint32_t reg; /**< Type used for register access */ 4321 } GMAC_ST2CW015_Type; 4322 #endif 4323 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 4324 4325 #define GMAC_ST2CW015_OFFSET (0x778) /**< (GMAC_ST2CW015) Screening Type 2 Compare Word 0 Register (index = 15) Offset */ 4326 4327 #define GMAC_ST2CW015_MASKVAL_Pos 0 /**< (GMAC_ST2CW015) Mask Value Position */ 4328 #define GMAC_ST2CW015_MASKVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW015_MASKVAL_Pos) /**< (GMAC_ST2CW015) Mask Value Mask */ 4329 #define GMAC_ST2CW015_MASKVAL(value) (GMAC_ST2CW015_MASKVAL_Msk & ((value) << GMAC_ST2CW015_MASKVAL_Pos)) 4330 #define GMAC_ST2CW015_COMPVAL_Pos 16 /**< (GMAC_ST2CW015) Compare Value Position */ 4331 #define GMAC_ST2CW015_COMPVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW015_COMPVAL_Pos) /**< (GMAC_ST2CW015) Compare Value Mask */ 4332 #define GMAC_ST2CW015_COMPVAL(value) (GMAC_ST2CW015_COMPVAL_Msk & ((value) << GMAC_ST2CW015_COMPVAL_Pos)) 4333 #define GMAC_ST2CW015_Msk _U_(0xFFFFFFFF) /**< (GMAC_ST2CW015) Register Mask */ 4334 4335 4336 /* -------- GMAC_ST2CW115 : (GMAC Offset: 0x77c) (R/W 32) Screening Type 2 Compare Word 1 Register (index = 15) -------- */ 4337 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 4338 #if COMPONENT_TYPEDEF_STYLE == 'N' 4339 typedef union { 4340 struct { 4341 uint32_t OFFSVAL:7; /**< bit: 0..6 Offset Value in Bytes */ 4342 uint32_t OFFSSTRT:2; /**< bit: 7..8 Ethernet Frame Offset Start */ 4343 uint32_t :23; /**< bit: 9..31 Reserved */ 4344 } bit; /**< Structure used for bit access */ 4345 uint32_t reg; /**< Type used for register access */ 4346 } GMAC_ST2CW115_Type; 4347 #endif 4348 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 4349 4350 #define GMAC_ST2CW115_OFFSET (0x77C) /**< (GMAC_ST2CW115) Screening Type 2 Compare Word 1 Register (index = 15) Offset */ 4351 4352 #define GMAC_ST2CW115_OFFSVAL_Pos 0 /**< (GMAC_ST2CW115) Offset Value in Bytes Position */ 4353 #define GMAC_ST2CW115_OFFSVAL_Msk (_U_(0x7F) << GMAC_ST2CW115_OFFSVAL_Pos) /**< (GMAC_ST2CW115) Offset Value in Bytes Mask */ 4354 #define GMAC_ST2CW115_OFFSVAL(value) (GMAC_ST2CW115_OFFSVAL_Msk & ((value) << GMAC_ST2CW115_OFFSVAL_Pos)) 4355 #define GMAC_ST2CW115_OFFSSTRT_Pos 7 /**< (GMAC_ST2CW115) Ethernet Frame Offset Start Position */ 4356 #define GMAC_ST2CW115_OFFSSTRT_Msk (_U_(0x3) << GMAC_ST2CW115_OFFSSTRT_Pos) /**< (GMAC_ST2CW115) Ethernet Frame Offset Start Mask */ 4357 #define GMAC_ST2CW115_OFFSSTRT(value) (GMAC_ST2CW115_OFFSSTRT_Msk & ((value) << GMAC_ST2CW115_OFFSSTRT_Pos)) 4358 #define GMAC_ST2CW115_OFFSSTRT_FRAMESTART_Val _U_(0x0) /**< (GMAC_ST2CW115) Offset from the start of the frame */ 4359 #define GMAC_ST2CW115_OFFSSTRT_ETHERTYPE_Val _U_(0x1) /**< (GMAC_ST2CW115) Offset from the byte after the EtherType field */ 4360 #define GMAC_ST2CW115_OFFSSTRT_IP_Val _U_(0x2) /**< (GMAC_ST2CW115) Offset from the byte after the IP header field */ 4361 #define GMAC_ST2CW115_OFFSSTRT_TCP_UDP_Val _U_(0x3) /**< (GMAC_ST2CW115) Offset from the byte after the TCP/UDP header field */ 4362 #define GMAC_ST2CW115_OFFSSTRT_FRAMESTART (GMAC_ST2CW115_OFFSSTRT_FRAMESTART_Val << GMAC_ST2CW115_OFFSSTRT_Pos) /**< (GMAC_ST2CW115) Offset from the start of the frame Position */ 4363 #define GMAC_ST2CW115_OFFSSTRT_ETHERTYPE (GMAC_ST2CW115_OFFSSTRT_ETHERTYPE_Val << GMAC_ST2CW115_OFFSSTRT_Pos) /**< (GMAC_ST2CW115) Offset from the byte after the EtherType field Position */ 4364 #define GMAC_ST2CW115_OFFSSTRT_IP (GMAC_ST2CW115_OFFSSTRT_IP_Val << GMAC_ST2CW115_OFFSSTRT_Pos) /**< (GMAC_ST2CW115) Offset from the byte after the IP header field Position */ 4365 #define GMAC_ST2CW115_OFFSSTRT_TCP_UDP (GMAC_ST2CW115_OFFSSTRT_TCP_UDP_Val << GMAC_ST2CW115_OFFSSTRT_Pos) /**< (GMAC_ST2CW115) Offset from the byte after the TCP/UDP header field Position */ 4366 #define GMAC_ST2CW115_MASK _U_(0x1FF) /**< \deprecated (GMAC_ST2CW115) Register MASK (Use GMAC_ST2CW115_Msk instead) */ 4367 #define GMAC_ST2CW115_Msk _U_(0x1FF) /**< (GMAC_ST2CW115) Register Mask */ 4368 4369 4370 /* -------- GMAC_ST2CW016 : (GMAC Offset: 0x780) (R/W 32) Screening Type 2 Compare Word 0 Register (index = 16) -------- */ 4371 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 4372 #if COMPONENT_TYPEDEF_STYLE == 'N' 4373 typedef union { 4374 struct { 4375 uint32_t MASKVAL:16; /**< bit: 0..15 Mask Value */ 4376 uint32_t COMPVAL:16; /**< bit: 16..31 Compare Value */ 4377 } bit; /**< Structure used for bit access */ 4378 uint32_t reg; /**< Type used for register access */ 4379 } GMAC_ST2CW016_Type; 4380 #endif 4381 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 4382 4383 #define GMAC_ST2CW016_OFFSET (0x780) /**< (GMAC_ST2CW016) Screening Type 2 Compare Word 0 Register (index = 16) Offset */ 4384 4385 #define GMAC_ST2CW016_MASKVAL_Pos 0 /**< (GMAC_ST2CW016) Mask Value Position */ 4386 #define GMAC_ST2CW016_MASKVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW016_MASKVAL_Pos) /**< (GMAC_ST2CW016) Mask Value Mask */ 4387 #define GMAC_ST2CW016_MASKVAL(value) (GMAC_ST2CW016_MASKVAL_Msk & ((value) << GMAC_ST2CW016_MASKVAL_Pos)) 4388 #define GMAC_ST2CW016_COMPVAL_Pos 16 /**< (GMAC_ST2CW016) Compare Value Position */ 4389 #define GMAC_ST2CW016_COMPVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW016_COMPVAL_Pos) /**< (GMAC_ST2CW016) Compare Value Mask */ 4390 #define GMAC_ST2CW016_COMPVAL(value) (GMAC_ST2CW016_COMPVAL_Msk & ((value) << GMAC_ST2CW016_COMPVAL_Pos)) 4391 #define GMAC_ST2CW016_Msk _U_(0xFFFFFFFF) /**< (GMAC_ST2CW016) Register Mask */ 4392 4393 4394 /* -------- GMAC_ST2CW116 : (GMAC Offset: 0x784) (R/W 32) Screening Type 2 Compare Word 1 Register (index = 16) -------- */ 4395 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 4396 #if COMPONENT_TYPEDEF_STYLE == 'N' 4397 typedef union { 4398 struct { 4399 uint32_t OFFSVAL:7; /**< bit: 0..6 Offset Value in Bytes */ 4400 uint32_t OFFSSTRT:2; /**< bit: 7..8 Ethernet Frame Offset Start */ 4401 uint32_t :23; /**< bit: 9..31 Reserved */ 4402 } bit; /**< Structure used for bit access */ 4403 uint32_t reg; /**< Type used for register access */ 4404 } GMAC_ST2CW116_Type; 4405 #endif 4406 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 4407 4408 #define GMAC_ST2CW116_OFFSET (0x784) /**< (GMAC_ST2CW116) Screening Type 2 Compare Word 1 Register (index = 16) Offset */ 4409 4410 #define GMAC_ST2CW116_OFFSVAL_Pos 0 /**< (GMAC_ST2CW116) Offset Value in Bytes Position */ 4411 #define GMAC_ST2CW116_OFFSVAL_Msk (_U_(0x7F) << GMAC_ST2CW116_OFFSVAL_Pos) /**< (GMAC_ST2CW116) Offset Value in Bytes Mask */ 4412 #define GMAC_ST2CW116_OFFSVAL(value) (GMAC_ST2CW116_OFFSVAL_Msk & ((value) << GMAC_ST2CW116_OFFSVAL_Pos)) 4413 #define GMAC_ST2CW116_OFFSSTRT_Pos 7 /**< (GMAC_ST2CW116) Ethernet Frame Offset Start Position */ 4414 #define GMAC_ST2CW116_OFFSSTRT_Msk (_U_(0x3) << GMAC_ST2CW116_OFFSSTRT_Pos) /**< (GMAC_ST2CW116) Ethernet Frame Offset Start Mask */ 4415 #define GMAC_ST2CW116_OFFSSTRT(value) (GMAC_ST2CW116_OFFSSTRT_Msk & ((value) << GMAC_ST2CW116_OFFSSTRT_Pos)) 4416 #define GMAC_ST2CW116_OFFSSTRT_FRAMESTART_Val _U_(0x0) /**< (GMAC_ST2CW116) Offset from the start of the frame */ 4417 #define GMAC_ST2CW116_OFFSSTRT_ETHERTYPE_Val _U_(0x1) /**< (GMAC_ST2CW116) Offset from the byte after the EtherType field */ 4418 #define GMAC_ST2CW116_OFFSSTRT_IP_Val _U_(0x2) /**< (GMAC_ST2CW116) Offset from the byte after the IP header field */ 4419 #define GMAC_ST2CW116_OFFSSTRT_TCP_UDP_Val _U_(0x3) /**< (GMAC_ST2CW116) Offset from the byte after the TCP/UDP header field */ 4420 #define GMAC_ST2CW116_OFFSSTRT_FRAMESTART (GMAC_ST2CW116_OFFSSTRT_FRAMESTART_Val << GMAC_ST2CW116_OFFSSTRT_Pos) /**< (GMAC_ST2CW116) Offset from the start of the frame Position */ 4421 #define GMAC_ST2CW116_OFFSSTRT_ETHERTYPE (GMAC_ST2CW116_OFFSSTRT_ETHERTYPE_Val << GMAC_ST2CW116_OFFSSTRT_Pos) /**< (GMAC_ST2CW116) Offset from the byte after the EtherType field Position */ 4422 #define GMAC_ST2CW116_OFFSSTRT_IP (GMAC_ST2CW116_OFFSSTRT_IP_Val << GMAC_ST2CW116_OFFSSTRT_Pos) /**< (GMAC_ST2CW116) Offset from the byte after the IP header field Position */ 4423 #define GMAC_ST2CW116_OFFSSTRT_TCP_UDP (GMAC_ST2CW116_OFFSSTRT_TCP_UDP_Val << GMAC_ST2CW116_OFFSSTRT_Pos) /**< (GMAC_ST2CW116) Offset from the byte after the TCP/UDP header field Position */ 4424 #define GMAC_ST2CW116_MASK _U_(0x1FF) /**< \deprecated (GMAC_ST2CW116) Register MASK (Use GMAC_ST2CW116_Msk instead) */ 4425 #define GMAC_ST2CW116_Msk _U_(0x1FF) /**< (GMAC_ST2CW116) Register Mask */ 4426 4427 4428 /* -------- GMAC_ST2CW017 : (GMAC Offset: 0x788) (R/W 32) Screening Type 2 Compare Word 0 Register (index = 17) -------- */ 4429 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 4430 #if COMPONENT_TYPEDEF_STYLE == 'N' 4431 typedef union { 4432 struct { 4433 uint32_t MASKVAL:16; /**< bit: 0..15 Mask Value */ 4434 uint32_t COMPVAL:16; /**< bit: 16..31 Compare Value */ 4435 } bit; /**< Structure used for bit access */ 4436 uint32_t reg; /**< Type used for register access */ 4437 } GMAC_ST2CW017_Type; 4438 #endif 4439 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 4440 4441 #define GMAC_ST2CW017_OFFSET (0x788) /**< (GMAC_ST2CW017) Screening Type 2 Compare Word 0 Register (index = 17) Offset */ 4442 4443 #define GMAC_ST2CW017_MASKVAL_Pos 0 /**< (GMAC_ST2CW017) Mask Value Position */ 4444 #define GMAC_ST2CW017_MASKVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW017_MASKVAL_Pos) /**< (GMAC_ST2CW017) Mask Value Mask */ 4445 #define GMAC_ST2CW017_MASKVAL(value) (GMAC_ST2CW017_MASKVAL_Msk & ((value) << GMAC_ST2CW017_MASKVAL_Pos)) 4446 #define GMAC_ST2CW017_COMPVAL_Pos 16 /**< (GMAC_ST2CW017) Compare Value Position */ 4447 #define GMAC_ST2CW017_COMPVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW017_COMPVAL_Pos) /**< (GMAC_ST2CW017) Compare Value Mask */ 4448 #define GMAC_ST2CW017_COMPVAL(value) (GMAC_ST2CW017_COMPVAL_Msk & ((value) << GMAC_ST2CW017_COMPVAL_Pos)) 4449 #define GMAC_ST2CW017_Msk _U_(0xFFFFFFFF) /**< (GMAC_ST2CW017) Register Mask */ 4450 4451 4452 /* -------- GMAC_ST2CW117 : (GMAC Offset: 0x78c) (R/W 32) Screening Type 2 Compare Word 1 Register (index = 17) -------- */ 4453 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 4454 #if COMPONENT_TYPEDEF_STYLE == 'N' 4455 typedef union { 4456 struct { 4457 uint32_t OFFSVAL:7; /**< bit: 0..6 Offset Value in Bytes */ 4458 uint32_t OFFSSTRT:2; /**< bit: 7..8 Ethernet Frame Offset Start */ 4459 uint32_t :23; /**< bit: 9..31 Reserved */ 4460 } bit; /**< Structure used for bit access */ 4461 uint32_t reg; /**< Type used for register access */ 4462 } GMAC_ST2CW117_Type; 4463 #endif 4464 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 4465 4466 #define GMAC_ST2CW117_OFFSET (0x78C) /**< (GMAC_ST2CW117) Screening Type 2 Compare Word 1 Register (index = 17) Offset */ 4467 4468 #define GMAC_ST2CW117_OFFSVAL_Pos 0 /**< (GMAC_ST2CW117) Offset Value in Bytes Position */ 4469 #define GMAC_ST2CW117_OFFSVAL_Msk (_U_(0x7F) << GMAC_ST2CW117_OFFSVAL_Pos) /**< (GMAC_ST2CW117) Offset Value in Bytes Mask */ 4470 #define GMAC_ST2CW117_OFFSVAL(value) (GMAC_ST2CW117_OFFSVAL_Msk & ((value) << GMAC_ST2CW117_OFFSVAL_Pos)) 4471 #define GMAC_ST2CW117_OFFSSTRT_Pos 7 /**< (GMAC_ST2CW117) Ethernet Frame Offset Start Position */ 4472 #define GMAC_ST2CW117_OFFSSTRT_Msk (_U_(0x3) << GMAC_ST2CW117_OFFSSTRT_Pos) /**< (GMAC_ST2CW117) Ethernet Frame Offset Start Mask */ 4473 #define GMAC_ST2CW117_OFFSSTRT(value) (GMAC_ST2CW117_OFFSSTRT_Msk & ((value) << GMAC_ST2CW117_OFFSSTRT_Pos)) 4474 #define GMAC_ST2CW117_OFFSSTRT_FRAMESTART_Val _U_(0x0) /**< (GMAC_ST2CW117) Offset from the start of the frame */ 4475 #define GMAC_ST2CW117_OFFSSTRT_ETHERTYPE_Val _U_(0x1) /**< (GMAC_ST2CW117) Offset from the byte after the EtherType field */ 4476 #define GMAC_ST2CW117_OFFSSTRT_IP_Val _U_(0x2) /**< (GMAC_ST2CW117) Offset from the byte after the IP header field */ 4477 #define GMAC_ST2CW117_OFFSSTRT_TCP_UDP_Val _U_(0x3) /**< (GMAC_ST2CW117) Offset from the byte after the TCP/UDP header field */ 4478 #define GMAC_ST2CW117_OFFSSTRT_FRAMESTART (GMAC_ST2CW117_OFFSSTRT_FRAMESTART_Val << GMAC_ST2CW117_OFFSSTRT_Pos) /**< (GMAC_ST2CW117) Offset from the start of the frame Position */ 4479 #define GMAC_ST2CW117_OFFSSTRT_ETHERTYPE (GMAC_ST2CW117_OFFSSTRT_ETHERTYPE_Val << GMAC_ST2CW117_OFFSSTRT_Pos) /**< (GMAC_ST2CW117) Offset from the byte after the EtherType field Position */ 4480 #define GMAC_ST2CW117_OFFSSTRT_IP (GMAC_ST2CW117_OFFSSTRT_IP_Val << GMAC_ST2CW117_OFFSSTRT_Pos) /**< (GMAC_ST2CW117) Offset from the byte after the IP header field Position */ 4481 #define GMAC_ST2CW117_OFFSSTRT_TCP_UDP (GMAC_ST2CW117_OFFSSTRT_TCP_UDP_Val << GMAC_ST2CW117_OFFSSTRT_Pos) /**< (GMAC_ST2CW117) Offset from the byte after the TCP/UDP header field Position */ 4482 #define GMAC_ST2CW117_MASK _U_(0x1FF) /**< \deprecated (GMAC_ST2CW117) Register MASK (Use GMAC_ST2CW117_Msk instead) */ 4483 #define GMAC_ST2CW117_Msk _U_(0x1FF) /**< (GMAC_ST2CW117) Register Mask */ 4484 4485 4486 /* -------- GMAC_ST2CW018 : (GMAC Offset: 0x790) (R/W 32) Screening Type 2 Compare Word 0 Register (index = 18) -------- */ 4487 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 4488 #if COMPONENT_TYPEDEF_STYLE == 'N' 4489 typedef union { 4490 struct { 4491 uint32_t MASKVAL:16; /**< bit: 0..15 Mask Value */ 4492 uint32_t COMPVAL:16; /**< bit: 16..31 Compare Value */ 4493 } bit; /**< Structure used for bit access */ 4494 uint32_t reg; /**< Type used for register access */ 4495 } GMAC_ST2CW018_Type; 4496 #endif 4497 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 4498 4499 #define GMAC_ST2CW018_OFFSET (0x790) /**< (GMAC_ST2CW018) Screening Type 2 Compare Word 0 Register (index = 18) Offset */ 4500 4501 #define GMAC_ST2CW018_MASKVAL_Pos 0 /**< (GMAC_ST2CW018) Mask Value Position */ 4502 #define GMAC_ST2CW018_MASKVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW018_MASKVAL_Pos) /**< (GMAC_ST2CW018) Mask Value Mask */ 4503 #define GMAC_ST2CW018_MASKVAL(value) (GMAC_ST2CW018_MASKVAL_Msk & ((value) << GMAC_ST2CW018_MASKVAL_Pos)) 4504 #define GMAC_ST2CW018_COMPVAL_Pos 16 /**< (GMAC_ST2CW018) Compare Value Position */ 4505 #define GMAC_ST2CW018_COMPVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW018_COMPVAL_Pos) /**< (GMAC_ST2CW018) Compare Value Mask */ 4506 #define GMAC_ST2CW018_COMPVAL(value) (GMAC_ST2CW018_COMPVAL_Msk & ((value) << GMAC_ST2CW018_COMPVAL_Pos)) 4507 #define GMAC_ST2CW018_Msk _U_(0xFFFFFFFF) /**< (GMAC_ST2CW018) Register Mask */ 4508 4509 4510 /* -------- GMAC_ST2CW118 : (GMAC Offset: 0x794) (R/W 32) Screening Type 2 Compare Word 1 Register (index = 18) -------- */ 4511 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 4512 #if COMPONENT_TYPEDEF_STYLE == 'N' 4513 typedef union { 4514 struct { 4515 uint32_t OFFSVAL:7; /**< bit: 0..6 Offset Value in Bytes */ 4516 uint32_t OFFSSTRT:2; /**< bit: 7..8 Ethernet Frame Offset Start */ 4517 uint32_t :23; /**< bit: 9..31 Reserved */ 4518 } bit; /**< Structure used for bit access */ 4519 uint32_t reg; /**< Type used for register access */ 4520 } GMAC_ST2CW118_Type; 4521 #endif 4522 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 4523 4524 #define GMAC_ST2CW118_OFFSET (0x794) /**< (GMAC_ST2CW118) Screening Type 2 Compare Word 1 Register (index = 18) Offset */ 4525 4526 #define GMAC_ST2CW118_OFFSVAL_Pos 0 /**< (GMAC_ST2CW118) Offset Value in Bytes Position */ 4527 #define GMAC_ST2CW118_OFFSVAL_Msk (_U_(0x7F) << GMAC_ST2CW118_OFFSVAL_Pos) /**< (GMAC_ST2CW118) Offset Value in Bytes Mask */ 4528 #define GMAC_ST2CW118_OFFSVAL(value) (GMAC_ST2CW118_OFFSVAL_Msk & ((value) << GMAC_ST2CW118_OFFSVAL_Pos)) 4529 #define GMAC_ST2CW118_OFFSSTRT_Pos 7 /**< (GMAC_ST2CW118) Ethernet Frame Offset Start Position */ 4530 #define GMAC_ST2CW118_OFFSSTRT_Msk (_U_(0x3) << GMAC_ST2CW118_OFFSSTRT_Pos) /**< (GMAC_ST2CW118) Ethernet Frame Offset Start Mask */ 4531 #define GMAC_ST2CW118_OFFSSTRT(value) (GMAC_ST2CW118_OFFSSTRT_Msk & ((value) << GMAC_ST2CW118_OFFSSTRT_Pos)) 4532 #define GMAC_ST2CW118_OFFSSTRT_FRAMESTART_Val _U_(0x0) /**< (GMAC_ST2CW118) Offset from the start of the frame */ 4533 #define GMAC_ST2CW118_OFFSSTRT_ETHERTYPE_Val _U_(0x1) /**< (GMAC_ST2CW118) Offset from the byte after the EtherType field */ 4534 #define GMAC_ST2CW118_OFFSSTRT_IP_Val _U_(0x2) /**< (GMAC_ST2CW118) Offset from the byte after the IP header field */ 4535 #define GMAC_ST2CW118_OFFSSTRT_TCP_UDP_Val _U_(0x3) /**< (GMAC_ST2CW118) Offset from the byte after the TCP/UDP header field */ 4536 #define GMAC_ST2CW118_OFFSSTRT_FRAMESTART (GMAC_ST2CW118_OFFSSTRT_FRAMESTART_Val << GMAC_ST2CW118_OFFSSTRT_Pos) /**< (GMAC_ST2CW118) Offset from the start of the frame Position */ 4537 #define GMAC_ST2CW118_OFFSSTRT_ETHERTYPE (GMAC_ST2CW118_OFFSSTRT_ETHERTYPE_Val << GMAC_ST2CW118_OFFSSTRT_Pos) /**< (GMAC_ST2CW118) Offset from the byte after the EtherType field Position */ 4538 #define GMAC_ST2CW118_OFFSSTRT_IP (GMAC_ST2CW118_OFFSSTRT_IP_Val << GMAC_ST2CW118_OFFSSTRT_Pos) /**< (GMAC_ST2CW118) Offset from the byte after the IP header field Position */ 4539 #define GMAC_ST2CW118_OFFSSTRT_TCP_UDP (GMAC_ST2CW118_OFFSSTRT_TCP_UDP_Val << GMAC_ST2CW118_OFFSSTRT_Pos) /**< (GMAC_ST2CW118) Offset from the byte after the TCP/UDP header field Position */ 4540 #define GMAC_ST2CW118_MASK _U_(0x1FF) /**< \deprecated (GMAC_ST2CW118) Register MASK (Use GMAC_ST2CW118_Msk instead) */ 4541 #define GMAC_ST2CW118_Msk _U_(0x1FF) /**< (GMAC_ST2CW118) Register Mask */ 4542 4543 4544 /* -------- GMAC_ST2CW019 : (GMAC Offset: 0x798) (R/W 32) Screening Type 2 Compare Word 0 Register (index = 19) -------- */ 4545 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 4546 #if COMPONENT_TYPEDEF_STYLE == 'N' 4547 typedef union { 4548 struct { 4549 uint32_t MASKVAL:16; /**< bit: 0..15 Mask Value */ 4550 uint32_t COMPVAL:16; /**< bit: 16..31 Compare Value */ 4551 } bit; /**< Structure used for bit access */ 4552 uint32_t reg; /**< Type used for register access */ 4553 } GMAC_ST2CW019_Type; 4554 #endif 4555 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 4556 4557 #define GMAC_ST2CW019_OFFSET (0x798) /**< (GMAC_ST2CW019) Screening Type 2 Compare Word 0 Register (index = 19) Offset */ 4558 4559 #define GMAC_ST2CW019_MASKVAL_Pos 0 /**< (GMAC_ST2CW019) Mask Value Position */ 4560 #define GMAC_ST2CW019_MASKVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW019_MASKVAL_Pos) /**< (GMAC_ST2CW019) Mask Value Mask */ 4561 #define GMAC_ST2CW019_MASKVAL(value) (GMAC_ST2CW019_MASKVAL_Msk & ((value) << GMAC_ST2CW019_MASKVAL_Pos)) 4562 #define GMAC_ST2CW019_COMPVAL_Pos 16 /**< (GMAC_ST2CW019) Compare Value Position */ 4563 #define GMAC_ST2CW019_COMPVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW019_COMPVAL_Pos) /**< (GMAC_ST2CW019) Compare Value Mask */ 4564 #define GMAC_ST2CW019_COMPVAL(value) (GMAC_ST2CW019_COMPVAL_Msk & ((value) << GMAC_ST2CW019_COMPVAL_Pos)) 4565 #define GMAC_ST2CW019_Msk _U_(0xFFFFFFFF) /**< (GMAC_ST2CW019) Register Mask */ 4566 4567 4568 /* -------- GMAC_ST2CW119 : (GMAC Offset: 0x79c) (R/W 32) Screening Type 2 Compare Word 1 Register (index = 19) -------- */ 4569 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 4570 #if COMPONENT_TYPEDEF_STYLE == 'N' 4571 typedef union { 4572 struct { 4573 uint32_t OFFSVAL:7; /**< bit: 0..6 Offset Value in Bytes */ 4574 uint32_t OFFSSTRT:2; /**< bit: 7..8 Ethernet Frame Offset Start */ 4575 uint32_t :23; /**< bit: 9..31 Reserved */ 4576 } bit; /**< Structure used for bit access */ 4577 uint32_t reg; /**< Type used for register access */ 4578 } GMAC_ST2CW119_Type; 4579 #endif 4580 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 4581 4582 #define GMAC_ST2CW119_OFFSET (0x79C) /**< (GMAC_ST2CW119) Screening Type 2 Compare Word 1 Register (index = 19) Offset */ 4583 4584 #define GMAC_ST2CW119_OFFSVAL_Pos 0 /**< (GMAC_ST2CW119) Offset Value in Bytes Position */ 4585 #define GMAC_ST2CW119_OFFSVAL_Msk (_U_(0x7F) << GMAC_ST2CW119_OFFSVAL_Pos) /**< (GMAC_ST2CW119) Offset Value in Bytes Mask */ 4586 #define GMAC_ST2CW119_OFFSVAL(value) (GMAC_ST2CW119_OFFSVAL_Msk & ((value) << GMAC_ST2CW119_OFFSVAL_Pos)) 4587 #define GMAC_ST2CW119_OFFSSTRT_Pos 7 /**< (GMAC_ST2CW119) Ethernet Frame Offset Start Position */ 4588 #define GMAC_ST2CW119_OFFSSTRT_Msk (_U_(0x3) << GMAC_ST2CW119_OFFSSTRT_Pos) /**< (GMAC_ST2CW119) Ethernet Frame Offset Start Mask */ 4589 #define GMAC_ST2CW119_OFFSSTRT(value) (GMAC_ST2CW119_OFFSSTRT_Msk & ((value) << GMAC_ST2CW119_OFFSSTRT_Pos)) 4590 #define GMAC_ST2CW119_OFFSSTRT_FRAMESTART_Val _U_(0x0) /**< (GMAC_ST2CW119) Offset from the start of the frame */ 4591 #define GMAC_ST2CW119_OFFSSTRT_ETHERTYPE_Val _U_(0x1) /**< (GMAC_ST2CW119) Offset from the byte after the EtherType field */ 4592 #define GMAC_ST2CW119_OFFSSTRT_IP_Val _U_(0x2) /**< (GMAC_ST2CW119) Offset from the byte after the IP header field */ 4593 #define GMAC_ST2CW119_OFFSSTRT_TCP_UDP_Val _U_(0x3) /**< (GMAC_ST2CW119) Offset from the byte after the TCP/UDP header field */ 4594 #define GMAC_ST2CW119_OFFSSTRT_FRAMESTART (GMAC_ST2CW119_OFFSSTRT_FRAMESTART_Val << GMAC_ST2CW119_OFFSSTRT_Pos) /**< (GMAC_ST2CW119) Offset from the start of the frame Position */ 4595 #define GMAC_ST2CW119_OFFSSTRT_ETHERTYPE (GMAC_ST2CW119_OFFSSTRT_ETHERTYPE_Val << GMAC_ST2CW119_OFFSSTRT_Pos) /**< (GMAC_ST2CW119) Offset from the byte after the EtherType field Position */ 4596 #define GMAC_ST2CW119_OFFSSTRT_IP (GMAC_ST2CW119_OFFSSTRT_IP_Val << GMAC_ST2CW119_OFFSSTRT_Pos) /**< (GMAC_ST2CW119) Offset from the byte after the IP header field Position */ 4597 #define GMAC_ST2CW119_OFFSSTRT_TCP_UDP (GMAC_ST2CW119_OFFSSTRT_TCP_UDP_Val << GMAC_ST2CW119_OFFSSTRT_Pos) /**< (GMAC_ST2CW119) Offset from the byte after the TCP/UDP header field Position */ 4598 #define GMAC_ST2CW119_MASK _U_(0x1FF) /**< \deprecated (GMAC_ST2CW119) Register MASK (Use GMAC_ST2CW119_Msk instead) */ 4599 #define GMAC_ST2CW119_Msk _U_(0x1FF) /**< (GMAC_ST2CW119) Register Mask */ 4600 4601 4602 /* -------- GMAC_ST2CW020 : (GMAC Offset: 0x7a0) (R/W 32) Screening Type 2 Compare Word 0 Register (index = 20) -------- */ 4603 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 4604 #if COMPONENT_TYPEDEF_STYLE == 'N' 4605 typedef union { 4606 struct { 4607 uint32_t MASKVAL:16; /**< bit: 0..15 Mask Value */ 4608 uint32_t COMPVAL:16; /**< bit: 16..31 Compare Value */ 4609 } bit; /**< Structure used for bit access */ 4610 uint32_t reg; /**< Type used for register access */ 4611 } GMAC_ST2CW020_Type; 4612 #endif 4613 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 4614 4615 #define GMAC_ST2CW020_OFFSET (0x7A0) /**< (GMAC_ST2CW020) Screening Type 2 Compare Word 0 Register (index = 20) Offset */ 4616 4617 #define GMAC_ST2CW020_MASKVAL_Pos 0 /**< (GMAC_ST2CW020) Mask Value Position */ 4618 #define GMAC_ST2CW020_MASKVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW020_MASKVAL_Pos) /**< (GMAC_ST2CW020) Mask Value Mask */ 4619 #define GMAC_ST2CW020_MASKVAL(value) (GMAC_ST2CW020_MASKVAL_Msk & ((value) << GMAC_ST2CW020_MASKVAL_Pos)) 4620 #define GMAC_ST2CW020_COMPVAL_Pos 16 /**< (GMAC_ST2CW020) Compare Value Position */ 4621 #define GMAC_ST2CW020_COMPVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW020_COMPVAL_Pos) /**< (GMAC_ST2CW020) Compare Value Mask */ 4622 #define GMAC_ST2CW020_COMPVAL(value) (GMAC_ST2CW020_COMPVAL_Msk & ((value) << GMAC_ST2CW020_COMPVAL_Pos)) 4623 #define GMAC_ST2CW020_Msk _U_(0xFFFFFFFF) /**< (GMAC_ST2CW020) Register Mask */ 4624 4625 4626 /* -------- GMAC_ST2CW120 : (GMAC Offset: 0x7a4) (R/W 32) Screening Type 2 Compare Word 1 Register (index = 20) -------- */ 4627 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 4628 #if COMPONENT_TYPEDEF_STYLE == 'N' 4629 typedef union { 4630 struct { 4631 uint32_t OFFSVAL:7; /**< bit: 0..6 Offset Value in Bytes */ 4632 uint32_t OFFSSTRT:2; /**< bit: 7..8 Ethernet Frame Offset Start */ 4633 uint32_t :23; /**< bit: 9..31 Reserved */ 4634 } bit; /**< Structure used for bit access */ 4635 uint32_t reg; /**< Type used for register access */ 4636 } GMAC_ST2CW120_Type; 4637 #endif 4638 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 4639 4640 #define GMAC_ST2CW120_OFFSET (0x7A4) /**< (GMAC_ST2CW120) Screening Type 2 Compare Word 1 Register (index = 20) Offset */ 4641 4642 #define GMAC_ST2CW120_OFFSVAL_Pos 0 /**< (GMAC_ST2CW120) Offset Value in Bytes Position */ 4643 #define GMAC_ST2CW120_OFFSVAL_Msk (_U_(0x7F) << GMAC_ST2CW120_OFFSVAL_Pos) /**< (GMAC_ST2CW120) Offset Value in Bytes Mask */ 4644 #define GMAC_ST2CW120_OFFSVAL(value) (GMAC_ST2CW120_OFFSVAL_Msk & ((value) << GMAC_ST2CW120_OFFSVAL_Pos)) 4645 #define GMAC_ST2CW120_OFFSSTRT_Pos 7 /**< (GMAC_ST2CW120) Ethernet Frame Offset Start Position */ 4646 #define GMAC_ST2CW120_OFFSSTRT_Msk (_U_(0x3) << GMAC_ST2CW120_OFFSSTRT_Pos) /**< (GMAC_ST2CW120) Ethernet Frame Offset Start Mask */ 4647 #define GMAC_ST2CW120_OFFSSTRT(value) (GMAC_ST2CW120_OFFSSTRT_Msk & ((value) << GMAC_ST2CW120_OFFSSTRT_Pos)) 4648 #define GMAC_ST2CW120_OFFSSTRT_FRAMESTART_Val _U_(0x0) /**< (GMAC_ST2CW120) Offset from the start of the frame */ 4649 #define GMAC_ST2CW120_OFFSSTRT_ETHERTYPE_Val _U_(0x1) /**< (GMAC_ST2CW120) Offset from the byte after the EtherType field */ 4650 #define GMAC_ST2CW120_OFFSSTRT_IP_Val _U_(0x2) /**< (GMAC_ST2CW120) Offset from the byte after the IP header field */ 4651 #define GMAC_ST2CW120_OFFSSTRT_TCP_UDP_Val _U_(0x3) /**< (GMAC_ST2CW120) Offset from the byte after the TCP/UDP header field */ 4652 #define GMAC_ST2CW120_OFFSSTRT_FRAMESTART (GMAC_ST2CW120_OFFSSTRT_FRAMESTART_Val << GMAC_ST2CW120_OFFSSTRT_Pos) /**< (GMAC_ST2CW120) Offset from the start of the frame Position */ 4653 #define GMAC_ST2CW120_OFFSSTRT_ETHERTYPE (GMAC_ST2CW120_OFFSSTRT_ETHERTYPE_Val << GMAC_ST2CW120_OFFSSTRT_Pos) /**< (GMAC_ST2CW120) Offset from the byte after the EtherType field Position */ 4654 #define GMAC_ST2CW120_OFFSSTRT_IP (GMAC_ST2CW120_OFFSSTRT_IP_Val << GMAC_ST2CW120_OFFSSTRT_Pos) /**< (GMAC_ST2CW120) Offset from the byte after the IP header field Position */ 4655 #define GMAC_ST2CW120_OFFSSTRT_TCP_UDP (GMAC_ST2CW120_OFFSSTRT_TCP_UDP_Val << GMAC_ST2CW120_OFFSSTRT_Pos) /**< (GMAC_ST2CW120) Offset from the byte after the TCP/UDP header field Position */ 4656 #define GMAC_ST2CW120_MASK _U_(0x1FF) /**< \deprecated (GMAC_ST2CW120) Register MASK (Use GMAC_ST2CW120_Msk instead) */ 4657 #define GMAC_ST2CW120_Msk _U_(0x1FF) /**< (GMAC_ST2CW120) Register Mask */ 4658 4659 4660 /* -------- GMAC_ST2CW021 : (GMAC Offset: 0x7a8) (R/W 32) Screening Type 2 Compare Word 0 Register (index = 21) -------- */ 4661 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 4662 #if COMPONENT_TYPEDEF_STYLE == 'N' 4663 typedef union { 4664 struct { 4665 uint32_t MASKVAL:16; /**< bit: 0..15 Mask Value */ 4666 uint32_t COMPVAL:16; /**< bit: 16..31 Compare Value */ 4667 } bit; /**< Structure used for bit access */ 4668 uint32_t reg; /**< Type used for register access */ 4669 } GMAC_ST2CW021_Type; 4670 #endif 4671 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 4672 4673 #define GMAC_ST2CW021_OFFSET (0x7A8) /**< (GMAC_ST2CW021) Screening Type 2 Compare Word 0 Register (index = 21) Offset */ 4674 4675 #define GMAC_ST2CW021_MASKVAL_Pos 0 /**< (GMAC_ST2CW021) Mask Value Position */ 4676 #define GMAC_ST2CW021_MASKVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW021_MASKVAL_Pos) /**< (GMAC_ST2CW021) Mask Value Mask */ 4677 #define GMAC_ST2CW021_MASKVAL(value) (GMAC_ST2CW021_MASKVAL_Msk & ((value) << GMAC_ST2CW021_MASKVAL_Pos)) 4678 #define GMAC_ST2CW021_COMPVAL_Pos 16 /**< (GMAC_ST2CW021) Compare Value Position */ 4679 #define GMAC_ST2CW021_COMPVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW021_COMPVAL_Pos) /**< (GMAC_ST2CW021) Compare Value Mask */ 4680 #define GMAC_ST2CW021_COMPVAL(value) (GMAC_ST2CW021_COMPVAL_Msk & ((value) << GMAC_ST2CW021_COMPVAL_Pos)) 4681 #define GMAC_ST2CW021_Msk _U_(0xFFFFFFFF) /**< (GMAC_ST2CW021) Register Mask */ 4682 4683 4684 /* -------- GMAC_ST2CW121 : (GMAC Offset: 0x7ac) (R/W 32) Screening Type 2 Compare Word 1 Register (index = 21) -------- */ 4685 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 4686 #if COMPONENT_TYPEDEF_STYLE == 'N' 4687 typedef union { 4688 struct { 4689 uint32_t OFFSVAL:7; /**< bit: 0..6 Offset Value in Bytes */ 4690 uint32_t OFFSSTRT:2; /**< bit: 7..8 Ethernet Frame Offset Start */ 4691 uint32_t :23; /**< bit: 9..31 Reserved */ 4692 } bit; /**< Structure used for bit access */ 4693 uint32_t reg; /**< Type used for register access */ 4694 } GMAC_ST2CW121_Type; 4695 #endif 4696 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 4697 4698 #define GMAC_ST2CW121_OFFSET (0x7AC) /**< (GMAC_ST2CW121) Screening Type 2 Compare Word 1 Register (index = 21) Offset */ 4699 4700 #define GMAC_ST2CW121_OFFSVAL_Pos 0 /**< (GMAC_ST2CW121) Offset Value in Bytes Position */ 4701 #define GMAC_ST2CW121_OFFSVAL_Msk (_U_(0x7F) << GMAC_ST2CW121_OFFSVAL_Pos) /**< (GMAC_ST2CW121) Offset Value in Bytes Mask */ 4702 #define GMAC_ST2CW121_OFFSVAL(value) (GMAC_ST2CW121_OFFSVAL_Msk & ((value) << GMAC_ST2CW121_OFFSVAL_Pos)) 4703 #define GMAC_ST2CW121_OFFSSTRT_Pos 7 /**< (GMAC_ST2CW121) Ethernet Frame Offset Start Position */ 4704 #define GMAC_ST2CW121_OFFSSTRT_Msk (_U_(0x3) << GMAC_ST2CW121_OFFSSTRT_Pos) /**< (GMAC_ST2CW121) Ethernet Frame Offset Start Mask */ 4705 #define GMAC_ST2CW121_OFFSSTRT(value) (GMAC_ST2CW121_OFFSSTRT_Msk & ((value) << GMAC_ST2CW121_OFFSSTRT_Pos)) 4706 #define GMAC_ST2CW121_OFFSSTRT_FRAMESTART_Val _U_(0x0) /**< (GMAC_ST2CW121) Offset from the start of the frame */ 4707 #define GMAC_ST2CW121_OFFSSTRT_ETHERTYPE_Val _U_(0x1) /**< (GMAC_ST2CW121) Offset from the byte after the EtherType field */ 4708 #define GMAC_ST2CW121_OFFSSTRT_IP_Val _U_(0x2) /**< (GMAC_ST2CW121) Offset from the byte after the IP header field */ 4709 #define GMAC_ST2CW121_OFFSSTRT_TCP_UDP_Val _U_(0x3) /**< (GMAC_ST2CW121) Offset from the byte after the TCP/UDP header field */ 4710 #define GMAC_ST2CW121_OFFSSTRT_FRAMESTART (GMAC_ST2CW121_OFFSSTRT_FRAMESTART_Val << GMAC_ST2CW121_OFFSSTRT_Pos) /**< (GMAC_ST2CW121) Offset from the start of the frame Position */ 4711 #define GMAC_ST2CW121_OFFSSTRT_ETHERTYPE (GMAC_ST2CW121_OFFSSTRT_ETHERTYPE_Val << GMAC_ST2CW121_OFFSSTRT_Pos) /**< (GMAC_ST2CW121) Offset from the byte after the EtherType field Position */ 4712 #define GMAC_ST2CW121_OFFSSTRT_IP (GMAC_ST2CW121_OFFSSTRT_IP_Val << GMAC_ST2CW121_OFFSSTRT_Pos) /**< (GMAC_ST2CW121) Offset from the byte after the IP header field Position */ 4713 #define GMAC_ST2CW121_OFFSSTRT_TCP_UDP (GMAC_ST2CW121_OFFSSTRT_TCP_UDP_Val << GMAC_ST2CW121_OFFSSTRT_Pos) /**< (GMAC_ST2CW121) Offset from the byte after the TCP/UDP header field Position */ 4714 #define GMAC_ST2CW121_MASK _U_(0x1FF) /**< \deprecated (GMAC_ST2CW121) Register MASK (Use GMAC_ST2CW121_Msk instead) */ 4715 #define GMAC_ST2CW121_Msk _U_(0x1FF) /**< (GMAC_ST2CW121) Register Mask */ 4716 4717 4718 /* -------- GMAC_ST2CW022 : (GMAC Offset: 0x7b0) (R/W 32) Screening Type 2 Compare Word 0 Register (index = 22) -------- */ 4719 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 4720 #if COMPONENT_TYPEDEF_STYLE == 'N' 4721 typedef union { 4722 struct { 4723 uint32_t MASKVAL:16; /**< bit: 0..15 Mask Value */ 4724 uint32_t COMPVAL:16; /**< bit: 16..31 Compare Value */ 4725 } bit; /**< Structure used for bit access */ 4726 uint32_t reg; /**< Type used for register access */ 4727 } GMAC_ST2CW022_Type; 4728 #endif 4729 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 4730 4731 #define GMAC_ST2CW022_OFFSET (0x7B0) /**< (GMAC_ST2CW022) Screening Type 2 Compare Word 0 Register (index = 22) Offset */ 4732 4733 #define GMAC_ST2CW022_MASKVAL_Pos 0 /**< (GMAC_ST2CW022) Mask Value Position */ 4734 #define GMAC_ST2CW022_MASKVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW022_MASKVAL_Pos) /**< (GMAC_ST2CW022) Mask Value Mask */ 4735 #define GMAC_ST2CW022_MASKVAL(value) (GMAC_ST2CW022_MASKVAL_Msk & ((value) << GMAC_ST2CW022_MASKVAL_Pos)) 4736 #define GMAC_ST2CW022_COMPVAL_Pos 16 /**< (GMAC_ST2CW022) Compare Value Position */ 4737 #define GMAC_ST2CW022_COMPVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW022_COMPVAL_Pos) /**< (GMAC_ST2CW022) Compare Value Mask */ 4738 #define GMAC_ST2CW022_COMPVAL(value) (GMAC_ST2CW022_COMPVAL_Msk & ((value) << GMAC_ST2CW022_COMPVAL_Pos)) 4739 #define GMAC_ST2CW022_Msk _U_(0xFFFFFFFF) /**< (GMAC_ST2CW022) Register Mask */ 4740 4741 4742 /* -------- GMAC_ST2CW122 : (GMAC Offset: 0x7b4) (R/W 32) Screening Type 2 Compare Word 1 Register (index = 22) -------- */ 4743 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 4744 #if COMPONENT_TYPEDEF_STYLE == 'N' 4745 typedef union { 4746 struct { 4747 uint32_t OFFSVAL:7; /**< bit: 0..6 Offset Value in Bytes */ 4748 uint32_t OFFSSTRT:2; /**< bit: 7..8 Ethernet Frame Offset Start */ 4749 uint32_t :23; /**< bit: 9..31 Reserved */ 4750 } bit; /**< Structure used for bit access */ 4751 uint32_t reg; /**< Type used for register access */ 4752 } GMAC_ST2CW122_Type; 4753 #endif 4754 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 4755 4756 #define GMAC_ST2CW122_OFFSET (0x7B4) /**< (GMAC_ST2CW122) Screening Type 2 Compare Word 1 Register (index = 22) Offset */ 4757 4758 #define GMAC_ST2CW122_OFFSVAL_Pos 0 /**< (GMAC_ST2CW122) Offset Value in Bytes Position */ 4759 #define GMAC_ST2CW122_OFFSVAL_Msk (_U_(0x7F) << GMAC_ST2CW122_OFFSVAL_Pos) /**< (GMAC_ST2CW122) Offset Value in Bytes Mask */ 4760 #define GMAC_ST2CW122_OFFSVAL(value) (GMAC_ST2CW122_OFFSVAL_Msk & ((value) << GMAC_ST2CW122_OFFSVAL_Pos)) 4761 #define GMAC_ST2CW122_OFFSSTRT_Pos 7 /**< (GMAC_ST2CW122) Ethernet Frame Offset Start Position */ 4762 #define GMAC_ST2CW122_OFFSSTRT_Msk (_U_(0x3) << GMAC_ST2CW122_OFFSSTRT_Pos) /**< (GMAC_ST2CW122) Ethernet Frame Offset Start Mask */ 4763 #define GMAC_ST2CW122_OFFSSTRT(value) (GMAC_ST2CW122_OFFSSTRT_Msk & ((value) << GMAC_ST2CW122_OFFSSTRT_Pos)) 4764 #define GMAC_ST2CW122_OFFSSTRT_FRAMESTART_Val _U_(0x0) /**< (GMAC_ST2CW122) Offset from the start of the frame */ 4765 #define GMAC_ST2CW122_OFFSSTRT_ETHERTYPE_Val _U_(0x1) /**< (GMAC_ST2CW122) Offset from the byte after the EtherType field */ 4766 #define GMAC_ST2CW122_OFFSSTRT_IP_Val _U_(0x2) /**< (GMAC_ST2CW122) Offset from the byte after the IP header field */ 4767 #define GMAC_ST2CW122_OFFSSTRT_TCP_UDP_Val _U_(0x3) /**< (GMAC_ST2CW122) Offset from the byte after the TCP/UDP header field */ 4768 #define GMAC_ST2CW122_OFFSSTRT_FRAMESTART (GMAC_ST2CW122_OFFSSTRT_FRAMESTART_Val << GMAC_ST2CW122_OFFSSTRT_Pos) /**< (GMAC_ST2CW122) Offset from the start of the frame Position */ 4769 #define GMAC_ST2CW122_OFFSSTRT_ETHERTYPE (GMAC_ST2CW122_OFFSSTRT_ETHERTYPE_Val << GMAC_ST2CW122_OFFSSTRT_Pos) /**< (GMAC_ST2CW122) Offset from the byte after the EtherType field Position */ 4770 #define GMAC_ST2CW122_OFFSSTRT_IP (GMAC_ST2CW122_OFFSSTRT_IP_Val << GMAC_ST2CW122_OFFSSTRT_Pos) /**< (GMAC_ST2CW122) Offset from the byte after the IP header field Position */ 4771 #define GMAC_ST2CW122_OFFSSTRT_TCP_UDP (GMAC_ST2CW122_OFFSSTRT_TCP_UDP_Val << GMAC_ST2CW122_OFFSSTRT_Pos) /**< (GMAC_ST2CW122) Offset from the byte after the TCP/UDP header field Position */ 4772 #define GMAC_ST2CW122_MASK _U_(0x1FF) /**< \deprecated (GMAC_ST2CW122) Register MASK (Use GMAC_ST2CW122_Msk instead) */ 4773 #define GMAC_ST2CW122_Msk _U_(0x1FF) /**< (GMAC_ST2CW122) Register Mask */ 4774 4775 4776 /* -------- GMAC_ST2CW023 : (GMAC Offset: 0x7b8) (R/W 32) Screening Type 2 Compare Word 0 Register (index = 23) -------- */ 4777 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 4778 #if COMPONENT_TYPEDEF_STYLE == 'N' 4779 typedef union { 4780 struct { 4781 uint32_t MASKVAL:16; /**< bit: 0..15 Mask Value */ 4782 uint32_t COMPVAL:16; /**< bit: 16..31 Compare Value */ 4783 } bit; /**< Structure used for bit access */ 4784 uint32_t reg; /**< Type used for register access */ 4785 } GMAC_ST2CW023_Type; 4786 #endif 4787 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 4788 4789 #define GMAC_ST2CW023_OFFSET (0x7B8) /**< (GMAC_ST2CW023) Screening Type 2 Compare Word 0 Register (index = 23) Offset */ 4790 4791 #define GMAC_ST2CW023_MASKVAL_Pos 0 /**< (GMAC_ST2CW023) Mask Value Position */ 4792 #define GMAC_ST2CW023_MASKVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW023_MASKVAL_Pos) /**< (GMAC_ST2CW023) Mask Value Mask */ 4793 #define GMAC_ST2CW023_MASKVAL(value) (GMAC_ST2CW023_MASKVAL_Msk & ((value) << GMAC_ST2CW023_MASKVAL_Pos)) 4794 #define GMAC_ST2CW023_COMPVAL_Pos 16 /**< (GMAC_ST2CW023) Compare Value Position */ 4795 #define GMAC_ST2CW023_COMPVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW023_COMPVAL_Pos) /**< (GMAC_ST2CW023) Compare Value Mask */ 4796 #define GMAC_ST2CW023_COMPVAL(value) (GMAC_ST2CW023_COMPVAL_Msk & ((value) << GMAC_ST2CW023_COMPVAL_Pos)) 4797 #define GMAC_ST2CW023_Msk _U_(0xFFFFFFFF) /**< (GMAC_ST2CW023) Register Mask */ 4798 4799 4800 /* -------- GMAC_ST2CW123 : (GMAC Offset: 0x7bc) (R/W 32) Screening Type 2 Compare Word 1 Register (index = 23) -------- */ 4801 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 4802 #if COMPONENT_TYPEDEF_STYLE == 'N' 4803 typedef union { 4804 struct { 4805 uint32_t OFFSVAL:7; /**< bit: 0..6 Offset Value in Bytes */ 4806 uint32_t OFFSSTRT:2; /**< bit: 7..8 Ethernet Frame Offset Start */ 4807 uint32_t :23; /**< bit: 9..31 Reserved */ 4808 } bit; /**< Structure used for bit access */ 4809 uint32_t reg; /**< Type used for register access */ 4810 } GMAC_ST2CW123_Type; 4811 #endif 4812 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 4813 4814 #define GMAC_ST2CW123_OFFSET (0x7BC) /**< (GMAC_ST2CW123) Screening Type 2 Compare Word 1 Register (index = 23) Offset */ 4815 4816 #define GMAC_ST2CW123_OFFSVAL_Pos 0 /**< (GMAC_ST2CW123) Offset Value in Bytes Position */ 4817 #define GMAC_ST2CW123_OFFSVAL_Msk (_U_(0x7F) << GMAC_ST2CW123_OFFSVAL_Pos) /**< (GMAC_ST2CW123) Offset Value in Bytes Mask */ 4818 #define GMAC_ST2CW123_OFFSVAL(value) (GMAC_ST2CW123_OFFSVAL_Msk & ((value) << GMAC_ST2CW123_OFFSVAL_Pos)) 4819 #define GMAC_ST2CW123_OFFSSTRT_Pos 7 /**< (GMAC_ST2CW123) Ethernet Frame Offset Start Position */ 4820 #define GMAC_ST2CW123_OFFSSTRT_Msk (_U_(0x3) << GMAC_ST2CW123_OFFSSTRT_Pos) /**< (GMAC_ST2CW123) Ethernet Frame Offset Start Mask */ 4821 #define GMAC_ST2CW123_OFFSSTRT(value) (GMAC_ST2CW123_OFFSSTRT_Msk & ((value) << GMAC_ST2CW123_OFFSSTRT_Pos)) 4822 #define GMAC_ST2CW123_OFFSSTRT_FRAMESTART_Val _U_(0x0) /**< (GMAC_ST2CW123) Offset from the start of the frame */ 4823 #define GMAC_ST2CW123_OFFSSTRT_ETHERTYPE_Val _U_(0x1) /**< (GMAC_ST2CW123) Offset from the byte after the EtherType field */ 4824 #define GMAC_ST2CW123_OFFSSTRT_IP_Val _U_(0x2) /**< (GMAC_ST2CW123) Offset from the byte after the IP header field */ 4825 #define GMAC_ST2CW123_OFFSSTRT_TCP_UDP_Val _U_(0x3) /**< (GMAC_ST2CW123) Offset from the byte after the TCP/UDP header field */ 4826 #define GMAC_ST2CW123_OFFSSTRT_FRAMESTART (GMAC_ST2CW123_OFFSSTRT_FRAMESTART_Val << GMAC_ST2CW123_OFFSSTRT_Pos) /**< (GMAC_ST2CW123) Offset from the start of the frame Position */ 4827 #define GMAC_ST2CW123_OFFSSTRT_ETHERTYPE (GMAC_ST2CW123_OFFSSTRT_ETHERTYPE_Val << GMAC_ST2CW123_OFFSSTRT_Pos) /**< (GMAC_ST2CW123) Offset from the byte after the EtherType field Position */ 4828 #define GMAC_ST2CW123_OFFSSTRT_IP (GMAC_ST2CW123_OFFSSTRT_IP_Val << GMAC_ST2CW123_OFFSSTRT_Pos) /**< (GMAC_ST2CW123) Offset from the byte after the IP header field Position */ 4829 #define GMAC_ST2CW123_OFFSSTRT_TCP_UDP (GMAC_ST2CW123_OFFSSTRT_TCP_UDP_Val << GMAC_ST2CW123_OFFSSTRT_Pos) /**< (GMAC_ST2CW123) Offset from the byte after the TCP/UDP header field Position */ 4830 #define GMAC_ST2CW123_MASK _U_(0x1FF) /**< \deprecated (GMAC_ST2CW123) Register MASK (Use GMAC_ST2CW123_Msk instead) */ 4831 #define GMAC_ST2CW123_Msk _U_(0x1FF) /**< (GMAC_ST2CW123) Register Mask */ 4832 4833 4834 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 4835 #if COMPONENT_TYPEDEF_STYLE == 'R' 4836 /** \brief GMAC_SA hardware registers */ 4837 typedef struct { 4838 __IO uint32_t GMAC_SAB; /**< (GMAC_SA Offset: 0x00) Specific Address 1 Bottom Register */ 4839 __IO uint32_t GMAC_SAT; /**< (GMAC_SA Offset: 0x04) Specific Address 1 Top Register */ 4840 } GmacSa; 4841 4842 #define GMACSA_NUMBER 4 4843 /** \brief GMAC hardware registers */ 4844 typedef struct { 4845 __IO uint32_t GMAC_NCR; /**< (GMAC Offset: 0x00) Network Control Register */ 4846 __IO uint32_t GMAC_NCFGR; /**< (GMAC Offset: 0x04) Network Configuration Register */ 4847 __I uint32_t GMAC_NSR; /**< (GMAC Offset: 0x08) Network Status Register */ 4848 __IO uint32_t GMAC_UR; /**< (GMAC Offset: 0x0C) User Register */ 4849 __IO uint32_t GMAC_DCFGR; /**< (GMAC Offset: 0x10) DMA Configuration Register */ 4850 __IO uint32_t GMAC_TSR; /**< (GMAC Offset: 0x14) Transmit Status Register */ 4851 __IO uint32_t GMAC_RBQB; /**< (GMAC Offset: 0x18) Receive Buffer Queue Base Address Register */ 4852 __IO uint32_t GMAC_TBQB; /**< (GMAC Offset: 0x1C) Transmit Buffer Queue Base Address Register */ 4853 __IO uint32_t GMAC_RSR; /**< (GMAC Offset: 0x20) Receive Status Register */ 4854 __I uint32_t GMAC_ISR; /**< (GMAC Offset: 0x24) Interrupt Status Register */ 4855 __O uint32_t GMAC_IER; /**< (GMAC Offset: 0x28) Interrupt Enable Register */ 4856 __O uint32_t GMAC_IDR; /**< (GMAC Offset: 0x2C) Interrupt Disable Register */ 4857 __IO uint32_t GMAC_IMR; /**< (GMAC Offset: 0x30) Interrupt Mask Register */ 4858 __IO uint32_t GMAC_MAN; /**< (GMAC Offset: 0x34) PHY Maintenance Register */ 4859 __I uint32_t GMAC_RPQ; /**< (GMAC Offset: 0x38) Received Pause Quantum Register */ 4860 __IO uint32_t GMAC_TPQ; /**< (GMAC Offset: 0x3C) Transmit Pause Quantum Register */ 4861 __IO uint32_t GMAC_TPSF; /**< (GMAC Offset: 0x40) TX Partial Store and Forward Register */ 4862 __IO uint32_t GMAC_RPSF; /**< (GMAC Offset: 0x44) RX Partial Store and Forward Register */ 4863 __IO uint32_t GMAC_RJFML; /**< (GMAC Offset: 0x48) RX Jumbo Frame Max Length Register */ 4864 __I uint8_t Reserved1[52]; 4865 __IO uint32_t GMAC_HRB; /**< (GMAC Offset: 0x80) Hash Register Bottom */ 4866 __IO uint32_t GMAC_HRT; /**< (GMAC Offset: 0x84) Hash Register Top */ 4867 GmacSa GMAC_SA[GMACSA_NUMBER]; /**< Offset: 0x88 Specific Address 1 Bottom Register */ 4868 __IO uint32_t GMAC_TIDM1; /**< (GMAC Offset: 0xA8) Type ID Match 1 Register */ 4869 __IO uint32_t GMAC_TIDM2; /**< (GMAC Offset: 0xAC) Type ID Match 2 Register */ 4870 __IO uint32_t GMAC_TIDM3; /**< (GMAC Offset: 0xB0) Type ID Match 3 Register */ 4871 __IO uint32_t GMAC_TIDM4; /**< (GMAC Offset: 0xB4) Type ID Match 4 Register */ 4872 __IO uint32_t GMAC_WOL; /**< (GMAC Offset: 0xB8) Wake on LAN Register */ 4873 __IO uint32_t GMAC_IPGS; /**< (GMAC Offset: 0xBC) IPG Stretch Register */ 4874 __IO uint32_t GMAC_SVLAN; /**< (GMAC Offset: 0xC0) Stacked VLAN Register */ 4875 __IO uint32_t GMAC_TPFCP; /**< (GMAC Offset: 0xC4) Transmit PFC Pause Register */ 4876 __IO uint32_t GMAC_SAMB1; /**< (GMAC Offset: 0xC8) Specific Address 1 Mask Bottom Register */ 4877 __IO uint32_t GMAC_SAMT1; /**< (GMAC Offset: 0xCC) Specific Address 1 Mask Top Register */ 4878 __I uint8_t Reserved2[12]; 4879 __IO uint32_t GMAC_NSC; /**< (GMAC Offset: 0xDC) 1588 Timer Nanosecond Comparison Register */ 4880 __IO uint32_t GMAC_SCL; /**< (GMAC Offset: 0xE0) 1588 Timer Second Comparison Low Register */ 4881 __IO uint32_t GMAC_SCH; /**< (GMAC Offset: 0xE4) 1588 Timer Second Comparison High Register */ 4882 __I uint32_t GMAC_EFTSH; /**< (GMAC Offset: 0xE8) PTP Event Frame Transmitted Seconds High Register */ 4883 __I uint32_t GMAC_EFRSH; /**< (GMAC Offset: 0xEC) PTP Event Frame Received Seconds High Register */ 4884 __I uint32_t GMAC_PEFTSH; /**< (GMAC Offset: 0xF0) PTP Peer Event Frame Transmitted Seconds High Register */ 4885 __I uint32_t GMAC_PEFRSH; /**< (GMAC Offset: 0xF4) PTP Peer Event Frame Received Seconds High Register */ 4886 __I uint8_t Reserved3[4]; 4887 __I uint32_t GMAC_MID; /**< (GMAC Offset: 0xFC) Module ID Register */ 4888 __I uint32_t GMAC_OTLO; /**< (GMAC Offset: 0x100) Octets Transmitted Low Register */ 4889 __I uint32_t GMAC_OTHI; /**< (GMAC Offset: 0x104) Octets Transmitted High Register */ 4890 __I uint32_t GMAC_FT; /**< (GMAC Offset: 0x108) Frames Transmitted Register */ 4891 __I uint32_t GMAC_BCFT; /**< (GMAC Offset: 0x10C) Broadcast Frames Transmitted Register */ 4892 __I uint32_t GMAC_MFT; /**< (GMAC Offset: 0x110) Multicast Frames Transmitted Register */ 4893 __I uint32_t GMAC_PFT; /**< (GMAC Offset: 0x114) Pause Frames Transmitted Register */ 4894 __I uint32_t GMAC_BFT64; /**< (GMAC Offset: 0x118) 64 Byte Frames Transmitted Register */ 4895 __I uint32_t GMAC_TBFT127; /**< (GMAC Offset: 0x11C) 65 to 127 Byte Frames Transmitted Register */ 4896 __I uint32_t GMAC_TBFT255; /**< (GMAC Offset: 0x120) 128 to 255 Byte Frames Transmitted Register */ 4897 __I uint32_t GMAC_TBFT511; /**< (GMAC Offset: 0x124) 256 to 511 Byte Frames Transmitted Register */ 4898 __I uint32_t GMAC_TBFT1023; /**< (GMAC Offset: 0x128) 512 to 1023 Byte Frames Transmitted Register */ 4899 __I uint32_t GMAC_TBFT1518; /**< (GMAC Offset: 0x12C) 1024 to 1518 Byte Frames Transmitted Register */ 4900 __I uint32_t GMAC_GTBFT1518; /**< (GMAC Offset: 0x130) Greater Than 1518 Byte Frames Transmitted Register */ 4901 __I uint32_t GMAC_TUR; /**< (GMAC Offset: 0x134) Transmit Underruns Register */ 4902 __I uint32_t GMAC_SCF; /**< (GMAC Offset: 0x138) Single Collision Frames Register */ 4903 __I uint32_t GMAC_MCF; /**< (GMAC Offset: 0x13C) Multiple Collision Frames Register */ 4904 __I uint32_t GMAC_EC; /**< (GMAC Offset: 0x140) Excessive Collisions Register */ 4905 __I uint32_t GMAC_LC; /**< (GMAC Offset: 0x144) Late Collisions Register */ 4906 __I uint32_t GMAC_DTF; /**< (GMAC Offset: 0x148) Deferred Transmission Frames Register */ 4907 __I uint32_t GMAC_CSE; /**< (GMAC Offset: 0x14C) Carrier Sense Errors Register */ 4908 __I uint32_t GMAC_ORLO; /**< (GMAC Offset: 0x150) Octets Received Low Received Register */ 4909 __I uint32_t GMAC_ORHI; /**< (GMAC Offset: 0x154) Octets Received High Received Register */ 4910 __I uint32_t GMAC_FR; /**< (GMAC Offset: 0x158) Frames Received Register */ 4911 __I uint32_t GMAC_BCFR; /**< (GMAC Offset: 0x15C) Broadcast Frames Received Register */ 4912 __I uint32_t GMAC_MFR; /**< (GMAC Offset: 0x160) Multicast Frames Received Register */ 4913 __I uint32_t GMAC_PFR; /**< (GMAC Offset: 0x164) Pause Frames Received Register */ 4914 __I uint32_t GMAC_BFR64; /**< (GMAC Offset: 0x168) 64 Byte Frames Received Register */ 4915 __I uint32_t GMAC_TBFR127; /**< (GMAC Offset: 0x16C) 65 to 127 Byte Frames Received Register */ 4916 __I uint32_t GMAC_TBFR255; /**< (GMAC Offset: 0x170) 128 to 255 Byte Frames Received Register */ 4917 __I uint32_t GMAC_TBFR511; /**< (GMAC Offset: 0x174) 256 to 511 Byte Frames Received Register */ 4918 __I uint32_t GMAC_TBFR1023; /**< (GMAC Offset: 0x178) 512 to 1023 Byte Frames Received Register */ 4919 __I uint32_t GMAC_TBFR1518; /**< (GMAC Offset: 0x17C) 1024 to 1518 Byte Frames Received Register */ 4920 __I uint32_t GMAC_TMXBFR; /**< (GMAC Offset: 0x180) 1519 to Maximum Byte Frames Received Register */ 4921 __I uint32_t GMAC_UFR; /**< (GMAC Offset: 0x184) Undersize Frames Received Register */ 4922 __I uint32_t GMAC_OFR; /**< (GMAC Offset: 0x188) Oversize Frames Received Register */ 4923 __I uint32_t GMAC_JR; /**< (GMAC Offset: 0x18C) Jabbers Received Register */ 4924 __I uint32_t GMAC_FCSE; /**< (GMAC Offset: 0x190) Frame Check Sequence Errors Register */ 4925 __I uint32_t GMAC_LFFE; /**< (GMAC Offset: 0x194) Length Field Frame Errors Register */ 4926 __I uint32_t GMAC_RSE; /**< (GMAC Offset: 0x198) Receive Symbol Errors Register */ 4927 __I uint32_t GMAC_AE; /**< (GMAC Offset: 0x19C) Alignment Errors Register */ 4928 __I uint32_t GMAC_RRE; /**< (GMAC Offset: 0x1A0) Receive Resource Errors Register */ 4929 __I uint32_t GMAC_ROE; /**< (GMAC Offset: 0x1A4) Receive Overrun Register */ 4930 __I uint32_t GMAC_IHCE; /**< (GMAC Offset: 0x1A8) IP Header Checksum Errors Register */ 4931 __I uint32_t GMAC_TCE; /**< (GMAC Offset: 0x1AC) TCP Checksum Errors Register */ 4932 __I uint32_t GMAC_UCE; /**< (GMAC Offset: 0x1B0) UDP Checksum Errors Register */ 4933 __I uint8_t Reserved4[8]; 4934 __IO uint32_t GMAC_TISUBN; /**< (GMAC Offset: 0x1BC) 1588 Timer Increment Sub-nanoseconds Register */ 4935 __IO uint32_t GMAC_TSH; /**< (GMAC Offset: 0x1C0) 1588 Timer Seconds High Register */ 4936 __I uint8_t Reserved5[12]; 4937 __IO uint32_t GMAC_TSL; /**< (GMAC Offset: 0x1D0) 1588 Timer Seconds Low Register */ 4938 __IO uint32_t GMAC_TN; /**< (GMAC Offset: 0x1D4) 1588 Timer Nanoseconds Register */ 4939 __O uint32_t GMAC_TA; /**< (GMAC Offset: 0x1D8) 1588 Timer Adjust Register */ 4940 __IO uint32_t GMAC_TI; /**< (GMAC Offset: 0x1DC) 1588 Timer Increment Register */ 4941 __I uint32_t GMAC_EFTSL; /**< (GMAC Offset: 0x1E0) PTP Event Frame Transmitted Seconds Low Register */ 4942 __I uint32_t GMAC_EFTN; /**< (GMAC Offset: 0x1E4) PTP Event Frame Transmitted Nanoseconds Register */ 4943 __I uint32_t GMAC_EFRSL; /**< (GMAC Offset: 0x1E8) PTP Event Frame Received Seconds Low Register */ 4944 __I uint32_t GMAC_EFRN; /**< (GMAC Offset: 0x1EC) PTP Event Frame Received Nanoseconds Register */ 4945 __I uint32_t GMAC_PEFTSL; /**< (GMAC Offset: 0x1F0) PTP Peer Event Frame Transmitted Seconds Low Register */ 4946 __I uint32_t GMAC_PEFTN; /**< (GMAC Offset: 0x1F4) PTP Peer Event Frame Transmitted Nanoseconds Register */ 4947 __I uint32_t GMAC_PEFRSL; /**< (GMAC Offset: 0x1F8) PTP Peer Event Frame Received Seconds Low Register */ 4948 __I uint32_t GMAC_PEFRN; /**< (GMAC Offset: 0x1FC) PTP Peer Event Frame Received Nanoseconds Register */ 4949 __I uint8_t Reserved6[512]; 4950 __I uint32_t GMAC_ISRPQ[2]; /**< (GMAC Offset: 0x400) Interrupt Status Register Priority Queue (index = 1) 0 */ 4951 __I uint8_t Reserved7[56]; 4952 __IO uint32_t GMAC_TBQBAPQ[2]; /**< (GMAC Offset: 0x440) Transmit Buffer Queue Base Address Register Priority Queue (index = 1) 0 */ 4953 __I uint8_t Reserved8[56]; 4954 __IO uint32_t GMAC_RBQBAPQ[2]; /**< (GMAC Offset: 0x480) Receive Buffer Queue Base Address Register Priority Queue (index = 1) 0 */ 4955 __I uint8_t Reserved9[24]; 4956 __IO uint32_t GMAC_RBSRPQ[2]; /**< (GMAC Offset: 0x4A0) Receive Buffer Size Register Priority Queue (index = 1) 0 */ 4957 __I uint8_t Reserved10[20]; 4958 __IO uint32_t GMAC_CBSCR; /**< (GMAC Offset: 0x4BC) Credit-Based Shaping Control Register */ 4959 __IO uint32_t GMAC_CBSISQA; /**< (GMAC Offset: 0x4C0) Credit-Based Shaping IdleSlope Register for Queue A */ 4960 __IO uint32_t GMAC_CBSISQB; /**< (GMAC Offset: 0x4C4) Credit-Based Shaping IdleSlope Register for Queue B */ 4961 __I uint8_t Reserved11[56]; 4962 __IO uint32_t GMAC_ST1RPQ[4]; /**< (GMAC Offset: 0x500) Screening Type 1 Register Priority Queue (index = 0) 0 */ 4963 __I uint8_t Reserved12[48]; 4964 __IO uint32_t GMAC_ST2RPQ[8]; /**< (GMAC Offset: 0x540) Screening Type 2 Register Priority Queue (index = 0) 0 */ 4965 __I uint8_t Reserved13[160]; 4966 __O uint32_t GMAC_IERPQ[2]; /**< (GMAC Offset: 0x600) Interrupt Enable Register Priority Queue (index = 1) 0 */ 4967 __I uint8_t Reserved14[24]; 4968 __O uint32_t GMAC_IDRPQ[2]; /**< (GMAC Offset: 0x620) Interrupt Disable Register Priority Queue (index = 1) 0 */ 4969 __I uint8_t Reserved15[24]; 4970 __IO uint32_t GMAC_IMRPQ[2]; /**< (GMAC Offset: 0x640) Interrupt Mask Register Priority Queue (index = 1) 0 */ 4971 __I uint8_t Reserved16[152]; 4972 __IO uint32_t GMAC_ST2ER[4]; /**< (GMAC Offset: 0x6E0) Screening Type 2 Ethertype Register (index = 0) 0 */ 4973 __I uint8_t Reserved17[16]; 4974 __IO uint32_t GMAC_ST2CW00; /**< (GMAC Offset: 0x700) Screening Type 2 Compare Word 0 Register (index = 0) */ 4975 __IO uint32_t GMAC_ST2CW10; /**< (GMAC Offset: 0x704) Screening Type 2 Compare Word 1 Register (index = 0) */ 4976 __IO uint32_t GMAC_ST2CW01; /**< (GMAC Offset: 0x708) Screening Type 2 Compare Word 0 Register (index = 1) */ 4977 __IO uint32_t GMAC_ST2CW11; /**< (GMAC Offset: 0x70C) Screening Type 2 Compare Word 1 Register (index = 1) */ 4978 __IO uint32_t GMAC_ST2CW02; /**< (GMAC Offset: 0x710) Screening Type 2 Compare Word 0 Register (index = 2) */ 4979 __IO uint32_t GMAC_ST2CW12; /**< (GMAC Offset: 0x714) Screening Type 2 Compare Word 1 Register (index = 2) */ 4980 __IO uint32_t GMAC_ST2CW03; /**< (GMAC Offset: 0x718) Screening Type 2 Compare Word 0 Register (index = 3) */ 4981 __IO uint32_t GMAC_ST2CW13; /**< (GMAC Offset: 0x71C) Screening Type 2 Compare Word 1 Register (index = 3) */ 4982 __IO uint32_t GMAC_ST2CW04; /**< (GMAC Offset: 0x720) Screening Type 2 Compare Word 0 Register (index = 4) */ 4983 __IO uint32_t GMAC_ST2CW14; /**< (GMAC Offset: 0x724) Screening Type 2 Compare Word 1 Register (index = 4) */ 4984 __IO uint32_t GMAC_ST2CW05; /**< (GMAC Offset: 0x728) Screening Type 2 Compare Word 0 Register (index = 5) */ 4985 __IO uint32_t GMAC_ST2CW15; /**< (GMAC Offset: 0x72C) Screening Type 2 Compare Word 1 Register (index = 5) */ 4986 __IO uint32_t GMAC_ST2CW06; /**< (GMAC Offset: 0x730) Screening Type 2 Compare Word 0 Register (index = 6) */ 4987 __IO uint32_t GMAC_ST2CW16; /**< (GMAC Offset: 0x734) Screening Type 2 Compare Word 1 Register (index = 6) */ 4988 __IO uint32_t GMAC_ST2CW07; /**< (GMAC Offset: 0x738) Screening Type 2 Compare Word 0 Register (index = 7) */ 4989 __IO uint32_t GMAC_ST2CW17; /**< (GMAC Offset: 0x73C) Screening Type 2 Compare Word 1 Register (index = 7) */ 4990 __IO uint32_t GMAC_ST2CW08; /**< (GMAC Offset: 0x740) Screening Type 2 Compare Word 0 Register (index = 8) */ 4991 __IO uint32_t GMAC_ST2CW18; /**< (GMAC Offset: 0x744) Screening Type 2 Compare Word 1 Register (index = 8) */ 4992 __IO uint32_t GMAC_ST2CW09; /**< (GMAC Offset: 0x748) Screening Type 2 Compare Word 0 Register (index = 9) */ 4993 __IO uint32_t GMAC_ST2CW19; /**< (GMAC Offset: 0x74C) Screening Type 2 Compare Word 1 Register (index = 9) */ 4994 __IO uint32_t GMAC_ST2CW010; /**< (GMAC Offset: 0x750) Screening Type 2 Compare Word 0 Register (index = 10) */ 4995 __IO uint32_t GMAC_ST2CW110; /**< (GMAC Offset: 0x754) Screening Type 2 Compare Word 1 Register (index = 10) */ 4996 __IO uint32_t GMAC_ST2CW011; /**< (GMAC Offset: 0x758) Screening Type 2 Compare Word 0 Register (index = 11) */ 4997 __IO uint32_t GMAC_ST2CW111; /**< (GMAC Offset: 0x75C) Screening Type 2 Compare Word 1 Register (index = 11) */ 4998 __IO uint32_t GMAC_ST2CW012; /**< (GMAC Offset: 0x760) Screening Type 2 Compare Word 0 Register (index = 12) */ 4999 __IO uint32_t GMAC_ST2CW112; /**< (GMAC Offset: 0x764) Screening Type 2 Compare Word 1 Register (index = 12) */ 5000 __IO uint32_t GMAC_ST2CW013; /**< (GMAC Offset: 0x768) Screening Type 2 Compare Word 0 Register (index = 13) */ 5001 __IO uint32_t GMAC_ST2CW113; /**< (GMAC Offset: 0x76C) Screening Type 2 Compare Word 1 Register (index = 13) */ 5002 __IO uint32_t GMAC_ST2CW014; /**< (GMAC Offset: 0x770) Screening Type 2 Compare Word 0 Register (index = 14) */ 5003 __IO uint32_t GMAC_ST2CW114; /**< (GMAC Offset: 0x774) Screening Type 2 Compare Word 1 Register (index = 14) */ 5004 __IO uint32_t GMAC_ST2CW015; /**< (GMAC Offset: 0x778) Screening Type 2 Compare Word 0 Register (index = 15) */ 5005 __IO uint32_t GMAC_ST2CW115; /**< (GMAC Offset: 0x77C) Screening Type 2 Compare Word 1 Register (index = 15) */ 5006 __IO uint32_t GMAC_ST2CW016; /**< (GMAC Offset: 0x780) Screening Type 2 Compare Word 0 Register (index = 16) */ 5007 __IO uint32_t GMAC_ST2CW116; /**< (GMAC Offset: 0x784) Screening Type 2 Compare Word 1 Register (index = 16) */ 5008 __IO uint32_t GMAC_ST2CW017; /**< (GMAC Offset: 0x788) Screening Type 2 Compare Word 0 Register (index = 17) */ 5009 __IO uint32_t GMAC_ST2CW117; /**< (GMAC Offset: 0x78C) Screening Type 2 Compare Word 1 Register (index = 17) */ 5010 __IO uint32_t GMAC_ST2CW018; /**< (GMAC Offset: 0x790) Screening Type 2 Compare Word 0 Register (index = 18) */ 5011 __IO uint32_t GMAC_ST2CW118; /**< (GMAC Offset: 0x794) Screening Type 2 Compare Word 1 Register (index = 18) */ 5012 __IO uint32_t GMAC_ST2CW019; /**< (GMAC Offset: 0x798) Screening Type 2 Compare Word 0 Register (index = 19) */ 5013 __IO uint32_t GMAC_ST2CW119; /**< (GMAC Offset: 0x79C) Screening Type 2 Compare Word 1 Register (index = 19) */ 5014 __IO uint32_t GMAC_ST2CW020; /**< (GMAC Offset: 0x7A0) Screening Type 2 Compare Word 0 Register (index = 20) */ 5015 __IO uint32_t GMAC_ST2CW120; /**< (GMAC Offset: 0x7A4) Screening Type 2 Compare Word 1 Register (index = 20) */ 5016 __IO uint32_t GMAC_ST2CW021; /**< (GMAC Offset: 0x7A8) Screening Type 2 Compare Word 0 Register (index = 21) */ 5017 __IO uint32_t GMAC_ST2CW121; /**< (GMAC Offset: 0x7AC) Screening Type 2 Compare Word 1 Register (index = 21) */ 5018 __IO uint32_t GMAC_ST2CW022; /**< (GMAC Offset: 0x7B0) Screening Type 2 Compare Word 0 Register (index = 22) */ 5019 __IO uint32_t GMAC_ST2CW122; /**< (GMAC Offset: 0x7B4) Screening Type 2 Compare Word 1 Register (index = 22) */ 5020 __IO uint32_t GMAC_ST2CW023; /**< (GMAC Offset: 0x7B8) Screening Type 2 Compare Word 0 Register (index = 23) */ 5021 __IO uint32_t GMAC_ST2CW123; /**< (GMAC Offset: 0x7BC) Screening Type 2 Compare Word 1 Register (index = 23) */ 5022 } Gmac; 5023 5024 #elif COMPONENT_TYPEDEF_STYLE == 'N' 5025 /** \brief GMAC_SA hardware registers */ 5026 typedef struct { 5027 __IO GMAC_SAB_Type GMAC_SAB; /**< Offset: 0x00 (R/W 32) Specific Address 1 Bottom Register */ 5028 __IO GMAC_SAT_Type GMAC_SAT; /**< Offset: 0x04 (R/W 32) Specific Address 1 Top Register */ 5029 } GmacSa; 5030 5031 /** \brief GMAC hardware registers */ 5032 typedef struct { 5033 __IO GMAC_NCR_Type GMAC_NCR; /**< Offset: 0x00 (R/W 32) Network Control Register */ 5034 __IO GMAC_NCFGR_Type GMAC_NCFGR; /**< Offset: 0x04 (R/W 32) Network Configuration Register */ 5035 __I GMAC_NSR_Type GMAC_NSR; /**< Offset: 0x08 (R/ 32) Network Status Register */ 5036 __IO GMAC_UR_Type GMAC_UR; /**< Offset: 0x0C (R/W 32) User Register */ 5037 __IO GMAC_DCFGR_Type GMAC_DCFGR; /**< Offset: 0x10 (R/W 32) DMA Configuration Register */ 5038 __IO GMAC_TSR_Type GMAC_TSR; /**< Offset: 0x14 (R/W 32) Transmit Status Register */ 5039 __IO GMAC_RBQB_Type GMAC_RBQB; /**< Offset: 0x18 (R/W 32) Receive Buffer Queue Base Address Register */ 5040 __IO GMAC_TBQB_Type GMAC_TBQB; /**< Offset: 0x1C (R/W 32) Transmit Buffer Queue Base Address Register */ 5041 __IO GMAC_RSR_Type GMAC_RSR; /**< Offset: 0x20 (R/W 32) Receive Status Register */ 5042 __I GMAC_ISR_Type GMAC_ISR; /**< Offset: 0x24 (R/ 32) Interrupt Status Register */ 5043 __O GMAC_IER_Type GMAC_IER; /**< Offset: 0x28 ( /W 32) Interrupt Enable Register */ 5044 __O GMAC_IDR_Type GMAC_IDR; /**< Offset: 0x2C ( /W 32) Interrupt Disable Register */ 5045 __IO GMAC_IMR_Type GMAC_IMR; /**< Offset: 0x30 (R/W 32) Interrupt Mask Register */ 5046 __IO GMAC_MAN_Type GMAC_MAN; /**< Offset: 0x34 (R/W 32) PHY Maintenance Register */ 5047 __I GMAC_RPQ_Type GMAC_RPQ; /**< Offset: 0x38 (R/ 32) Received Pause Quantum Register */ 5048 __IO GMAC_TPQ_Type GMAC_TPQ; /**< Offset: 0x3C (R/W 32) Transmit Pause Quantum Register */ 5049 __IO GMAC_TPSF_Type GMAC_TPSF; /**< Offset: 0x40 (R/W 32) TX Partial Store and Forward Register */ 5050 __IO GMAC_RPSF_Type GMAC_RPSF; /**< Offset: 0x44 (R/W 32) RX Partial Store and Forward Register */ 5051 __IO GMAC_RJFML_Type GMAC_RJFML; /**< Offset: 0x48 (R/W 32) RX Jumbo Frame Max Length Register */ 5052 __I uint8_t Reserved1[52]; 5053 __IO GMAC_HRB_Type GMAC_HRB; /**< Offset: 0x80 (R/W 32) Hash Register Bottom */ 5054 __IO GMAC_HRT_Type GMAC_HRT; /**< Offset: 0x84 (R/W 32) Hash Register Top */ 5055 GmacSa GMAC_SA[4]; /**< Offset: 0x88 Specific Address 1 Bottom Register */ 5056 __IO GMAC_TIDM1_Type GMAC_TIDM1; /**< Offset: 0xA8 (R/W 32) Type ID Match 1 Register */ 5057 __IO GMAC_TIDM2_Type GMAC_TIDM2; /**< Offset: 0xAC (R/W 32) Type ID Match 2 Register */ 5058 __IO GMAC_TIDM3_Type GMAC_TIDM3; /**< Offset: 0xB0 (R/W 32) Type ID Match 3 Register */ 5059 __IO GMAC_TIDM4_Type GMAC_TIDM4; /**< Offset: 0xB4 (R/W 32) Type ID Match 4 Register */ 5060 __IO GMAC_WOL_Type GMAC_WOL; /**< Offset: 0xB8 (R/W 32) Wake on LAN Register */ 5061 __IO GMAC_IPGS_Type GMAC_IPGS; /**< Offset: 0xBC (R/W 32) IPG Stretch Register */ 5062 __IO GMAC_SVLAN_Type GMAC_SVLAN; /**< Offset: 0xC0 (R/W 32) Stacked VLAN Register */ 5063 __IO GMAC_TPFCP_Type GMAC_TPFCP; /**< Offset: 0xC4 (R/W 32) Transmit PFC Pause Register */ 5064 __IO GMAC_SAMB1_Type GMAC_SAMB1; /**< Offset: 0xC8 (R/W 32) Specific Address 1 Mask Bottom Register */ 5065 __IO GMAC_SAMT1_Type GMAC_SAMT1; /**< Offset: 0xCC (R/W 32) Specific Address 1 Mask Top Register */ 5066 __I uint8_t Reserved2[12]; 5067 __IO GMAC_NSC_Type GMAC_NSC; /**< Offset: 0xDC (R/W 32) 1588 Timer Nanosecond Comparison Register */ 5068 __IO GMAC_SCL_Type GMAC_SCL; /**< Offset: 0xE0 (R/W 32) 1588 Timer Second Comparison Low Register */ 5069 __IO GMAC_SCH_Type GMAC_SCH; /**< Offset: 0xE4 (R/W 32) 1588 Timer Second Comparison High Register */ 5070 __I GMAC_EFTSH_Type GMAC_EFTSH; /**< Offset: 0xE8 (R/ 32) PTP Event Frame Transmitted Seconds High Register */ 5071 __I GMAC_EFRSH_Type GMAC_EFRSH; /**< Offset: 0xEC (R/ 32) PTP Event Frame Received Seconds High Register */ 5072 __I GMAC_PEFTSH_Type GMAC_PEFTSH; /**< Offset: 0xF0 (R/ 32) PTP Peer Event Frame Transmitted Seconds High Register */ 5073 __I GMAC_PEFRSH_Type GMAC_PEFRSH; /**< Offset: 0xF4 (R/ 32) PTP Peer Event Frame Received Seconds High Register */ 5074 __I uint8_t Reserved3[4]; 5075 __I GMAC_MID_Type GMAC_MID; /**< Offset: 0xFC (R/ 32) Module ID Register */ 5076 __I GMAC_OTLO_Type GMAC_OTLO; /**< Offset: 0x100 (R/ 32) Octets Transmitted Low Register */ 5077 __I GMAC_OTHI_Type GMAC_OTHI; /**< Offset: 0x104 (R/ 32) Octets Transmitted High Register */ 5078 __I GMAC_FT_Type GMAC_FT; /**< Offset: 0x108 (R/ 32) Frames Transmitted Register */ 5079 __I GMAC_BCFT_Type GMAC_BCFT; /**< Offset: 0x10C (R/ 32) Broadcast Frames Transmitted Register */ 5080 __I GMAC_MFT_Type GMAC_MFT; /**< Offset: 0x110 (R/ 32) Multicast Frames Transmitted Register */ 5081 __I GMAC_PFT_Type GMAC_PFT; /**< Offset: 0x114 (R/ 32) Pause Frames Transmitted Register */ 5082 __I GMAC_BFT64_Type GMAC_BFT64; /**< Offset: 0x118 (R/ 32) 64 Byte Frames Transmitted Register */ 5083 __I GMAC_TBFT127_Type GMAC_TBFT127; /**< Offset: 0x11C (R/ 32) 65 to 127 Byte Frames Transmitted Register */ 5084 __I GMAC_TBFT255_Type GMAC_TBFT255; /**< Offset: 0x120 (R/ 32) 128 to 255 Byte Frames Transmitted Register */ 5085 __I GMAC_TBFT511_Type GMAC_TBFT511; /**< Offset: 0x124 (R/ 32) 256 to 511 Byte Frames Transmitted Register */ 5086 __I GMAC_TBFT1023_Type GMAC_TBFT1023; /**< Offset: 0x128 (R/ 32) 512 to 1023 Byte Frames Transmitted Register */ 5087 __I GMAC_TBFT1518_Type GMAC_TBFT1518; /**< Offset: 0x12C (R/ 32) 1024 to 1518 Byte Frames Transmitted Register */ 5088 __I GMAC_GTBFT1518_Type GMAC_GTBFT1518; /**< Offset: 0x130 (R/ 32) Greater Than 1518 Byte Frames Transmitted Register */ 5089 __I GMAC_TUR_Type GMAC_TUR; /**< Offset: 0x134 (R/ 32) Transmit Underruns Register */ 5090 __I GMAC_SCF_Type GMAC_SCF; /**< Offset: 0x138 (R/ 32) Single Collision Frames Register */ 5091 __I GMAC_MCF_Type GMAC_MCF; /**< Offset: 0x13C (R/ 32) Multiple Collision Frames Register */ 5092 __I GMAC_EC_Type GMAC_EC; /**< Offset: 0x140 (R/ 32) Excessive Collisions Register */ 5093 __I GMAC_LC_Type GMAC_LC; /**< Offset: 0x144 (R/ 32) Late Collisions Register */ 5094 __I GMAC_DTF_Type GMAC_DTF; /**< Offset: 0x148 (R/ 32) Deferred Transmission Frames Register */ 5095 __I GMAC_CSE_Type GMAC_CSE; /**< Offset: 0x14C (R/ 32) Carrier Sense Errors Register */ 5096 __I GMAC_ORLO_Type GMAC_ORLO; /**< Offset: 0x150 (R/ 32) Octets Received Low Received Register */ 5097 __I GMAC_ORHI_Type GMAC_ORHI; /**< Offset: 0x154 (R/ 32) Octets Received High Received Register */ 5098 __I GMAC_FR_Type GMAC_FR; /**< Offset: 0x158 (R/ 32) Frames Received Register */ 5099 __I GMAC_BCFR_Type GMAC_BCFR; /**< Offset: 0x15C (R/ 32) Broadcast Frames Received Register */ 5100 __I GMAC_MFR_Type GMAC_MFR; /**< Offset: 0x160 (R/ 32) Multicast Frames Received Register */ 5101 __I GMAC_PFR_Type GMAC_PFR; /**< Offset: 0x164 (R/ 32) Pause Frames Received Register */ 5102 __I GMAC_BFR64_Type GMAC_BFR64; /**< Offset: 0x168 (R/ 32) 64 Byte Frames Received Register */ 5103 __I GMAC_TBFR127_Type GMAC_TBFR127; /**< Offset: 0x16C (R/ 32) 65 to 127 Byte Frames Received Register */ 5104 __I GMAC_TBFR255_Type GMAC_TBFR255; /**< Offset: 0x170 (R/ 32) 128 to 255 Byte Frames Received Register */ 5105 __I GMAC_TBFR511_Type GMAC_TBFR511; /**< Offset: 0x174 (R/ 32) 256 to 511 Byte Frames Received Register */ 5106 __I GMAC_TBFR1023_Type GMAC_TBFR1023; /**< Offset: 0x178 (R/ 32) 512 to 1023 Byte Frames Received Register */ 5107 __I GMAC_TBFR1518_Type GMAC_TBFR1518; /**< Offset: 0x17C (R/ 32) 1024 to 1518 Byte Frames Received Register */ 5108 __I GMAC_TMXBFR_Type GMAC_TMXBFR; /**< Offset: 0x180 (R/ 32) 1519 to Maximum Byte Frames Received Register */ 5109 __I GMAC_UFR_Type GMAC_UFR; /**< Offset: 0x184 (R/ 32) Undersize Frames Received Register */ 5110 __I GMAC_OFR_Type GMAC_OFR; /**< Offset: 0x188 (R/ 32) Oversize Frames Received Register */ 5111 __I GMAC_JR_Type GMAC_JR; /**< Offset: 0x18C (R/ 32) Jabbers Received Register */ 5112 __I GMAC_FCSE_Type GMAC_FCSE; /**< Offset: 0x190 (R/ 32) Frame Check Sequence Errors Register */ 5113 __I GMAC_LFFE_Type GMAC_LFFE; /**< Offset: 0x194 (R/ 32) Length Field Frame Errors Register */ 5114 __I GMAC_RSE_Type GMAC_RSE; /**< Offset: 0x198 (R/ 32) Receive Symbol Errors Register */ 5115 __I GMAC_AE_Type GMAC_AE; /**< Offset: 0x19C (R/ 32) Alignment Errors Register */ 5116 __I GMAC_RRE_Type GMAC_RRE; /**< Offset: 0x1A0 (R/ 32) Receive Resource Errors Register */ 5117 __I GMAC_ROE_Type GMAC_ROE; /**< Offset: 0x1A4 (R/ 32) Receive Overrun Register */ 5118 __I GMAC_IHCE_Type GMAC_IHCE; /**< Offset: 0x1A8 (R/ 32) IP Header Checksum Errors Register */ 5119 __I GMAC_TCE_Type GMAC_TCE; /**< Offset: 0x1AC (R/ 32) TCP Checksum Errors Register */ 5120 __I GMAC_UCE_Type GMAC_UCE; /**< Offset: 0x1B0 (R/ 32) UDP Checksum Errors Register */ 5121 __I uint8_t Reserved4[8]; 5122 __IO GMAC_TISUBN_Type GMAC_TISUBN; /**< Offset: 0x1BC (R/W 32) 1588 Timer Increment Sub-nanoseconds Register */ 5123 __IO GMAC_TSH_Type GMAC_TSH; /**< Offset: 0x1C0 (R/W 32) 1588 Timer Seconds High Register */ 5124 __I uint8_t Reserved5[12]; 5125 __IO GMAC_TSL_Type GMAC_TSL; /**< Offset: 0x1D0 (R/W 32) 1588 Timer Seconds Low Register */ 5126 __IO GMAC_TN_Type GMAC_TN; /**< Offset: 0x1D4 (R/W 32) 1588 Timer Nanoseconds Register */ 5127 __O GMAC_TA_Type GMAC_TA; /**< Offset: 0x1D8 ( /W 32) 1588 Timer Adjust Register */ 5128 __IO GMAC_TI_Type GMAC_TI; /**< Offset: 0x1DC (R/W 32) 1588 Timer Increment Register */ 5129 __I GMAC_EFTSL_Type GMAC_EFTSL; /**< Offset: 0x1E0 (R/ 32) PTP Event Frame Transmitted Seconds Low Register */ 5130 __I GMAC_EFTN_Type GMAC_EFTN; /**< Offset: 0x1E4 (R/ 32) PTP Event Frame Transmitted Nanoseconds Register */ 5131 __I GMAC_EFRSL_Type GMAC_EFRSL; /**< Offset: 0x1E8 (R/ 32) PTP Event Frame Received Seconds Low Register */ 5132 __I GMAC_EFRN_Type GMAC_EFRN; /**< Offset: 0x1EC (R/ 32) PTP Event Frame Received Nanoseconds Register */ 5133 __I GMAC_PEFTSL_Type GMAC_PEFTSL; /**< Offset: 0x1F0 (R/ 32) PTP Peer Event Frame Transmitted Seconds Low Register */ 5134 __I GMAC_PEFTN_Type GMAC_PEFTN; /**< Offset: 0x1F4 (R/ 32) PTP Peer Event Frame Transmitted Nanoseconds Register */ 5135 __I GMAC_PEFRSL_Type GMAC_PEFRSL; /**< Offset: 0x1F8 (R/ 32) PTP Peer Event Frame Received Seconds Low Register */ 5136 __I GMAC_PEFRN_Type GMAC_PEFRN; /**< Offset: 0x1FC (R/ 32) PTP Peer Event Frame Received Nanoseconds Register */ 5137 __I uint8_t Reserved6[512]; 5138 __I GMAC_ISRPQ_Type GMAC_ISRPQ[2]; /**< Offset: 0x400 (R/ 32) Interrupt Status Register Priority Queue (index = 1) 0 */ 5139 __I uint8_t Reserved7[56]; 5140 __IO GMAC_TBQBAPQ_Type GMAC_TBQBAPQ[2]; /**< Offset: 0x440 (R/W 32) Transmit Buffer Queue Base Address Register Priority Queue (index = 1) 0 */ 5141 __I uint8_t Reserved8[56]; 5142 __IO GMAC_RBQBAPQ_Type GMAC_RBQBAPQ[2]; /**< Offset: 0x480 (R/W 32) Receive Buffer Queue Base Address Register Priority Queue (index = 1) 0 */ 5143 __I uint8_t Reserved9[24]; 5144 __IO GMAC_RBSRPQ_Type GMAC_RBSRPQ[2]; /**< Offset: 0x4A0 (R/W 32) Receive Buffer Size Register Priority Queue (index = 1) 0 */ 5145 __I uint8_t Reserved10[20]; 5146 __IO GMAC_CBSCR_Type GMAC_CBSCR; /**< Offset: 0x4BC (R/W 32) Credit-Based Shaping Control Register */ 5147 __IO GMAC_CBSISQA_Type GMAC_CBSISQA; /**< Offset: 0x4C0 (R/W 32) Credit-Based Shaping IdleSlope Register for Queue A */ 5148 __IO GMAC_CBSISQB_Type GMAC_CBSISQB; /**< Offset: 0x4C4 (R/W 32) Credit-Based Shaping IdleSlope Register for Queue B */ 5149 __I uint8_t Reserved11[56]; 5150 __IO GMAC_ST1RPQ_Type GMAC_ST1RPQ[4]; /**< Offset: 0x500 (R/W 32) Screening Type 1 Register Priority Queue (index = 0) 0 */ 5151 __I uint8_t Reserved12[48]; 5152 __IO GMAC_ST2RPQ_Type GMAC_ST2RPQ[8]; /**< Offset: 0x540 (R/W 32) Screening Type 2 Register Priority Queue (index = 0) 0 */ 5153 __I uint8_t Reserved13[160]; 5154 __O GMAC_IERPQ_Type GMAC_IERPQ[2]; /**< Offset: 0x600 ( /W 32) Interrupt Enable Register Priority Queue (index = 1) 0 */ 5155 __I uint8_t Reserved14[24]; 5156 __O GMAC_IDRPQ_Type GMAC_IDRPQ[2]; /**< Offset: 0x620 ( /W 32) Interrupt Disable Register Priority Queue (index = 1) 0 */ 5157 __I uint8_t Reserved15[24]; 5158 __IO GMAC_IMRPQ_Type GMAC_IMRPQ[2]; /**< Offset: 0x640 (R/W 32) Interrupt Mask Register Priority Queue (index = 1) 0 */ 5159 __I uint8_t Reserved16[152]; 5160 __IO GMAC_ST2ER_Type GMAC_ST2ER[4]; /**< Offset: 0x6E0 (R/W 32) Screening Type 2 Ethertype Register (index = 0) 0 */ 5161 __I uint8_t Reserved17[16]; 5162 __IO GMAC_ST2CW00_Type GMAC_ST2CW00; /**< Offset: 0x700 (R/W 32) Screening Type 2 Compare Word 0 Register (index = 0) */ 5163 __IO GMAC_ST2CW10_Type GMAC_ST2CW10; /**< Offset: 0x704 (R/W 32) Screening Type 2 Compare Word 1 Register (index = 0) */ 5164 __IO GMAC_ST2CW01_Type GMAC_ST2CW01; /**< Offset: 0x708 (R/W 32) Screening Type 2 Compare Word 0 Register (index = 1) */ 5165 __IO GMAC_ST2CW11_Type GMAC_ST2CW11; /**< Offset: 0x70C (R/W 32) Screening Type 2 Compare Word 1 Register (index = 1) */ 5166 __IO GMAC_ST2CW02_Type GMAC_ST2CW02; /**< Offset: 0x710 (R/W 32) Screening Type 2 Compare Word 0 Register (index = 2) */ 5167 __IO GMAC_ST2CW12_Type GMAC_ST2CW12; /**< Offset: 0x714 (R/W 32) Screening Type 2 Compare Word 1 Register (index = 2) */ 5168 __IO GMAC_ST2CW03_Type GMAC_ST2CW03; /**< Offset: 0x718 (R/W 32) Screening Type 2 Compare Word 0 Register (index = 3) */ 5169 __IO GMAC_ST2CW13_Type GMAC_ST2CW13; /**< Offset: 0x71C (R/W 32) Screening Type 2 Compare Word 1 Register (index = 3) */ 5170 __IO GMAC_ST2CW04_Type GMAC_ST2CW04; /**< Offset: 0x720 (R/W 32) Screening Type 2 Compare Word 0 Register (index = 4) */ 5171 __IO GMAC_ST2CW14_Type GMAC_ST2CW14; /**< Offset: 0x724 (R/W 32) Screening Type 2 Compare Word 1 Register (index = 4) */ 5172 __IO GMAC_ST2CW05_Type GMAC_ST2CW05; /**< Offset: 0x728 (R/W 32) Screening Type 2 Compare Word 0 Register (index = 5) */ 5173 __IO GMAC_ST2CW15_Type GMAC_ST2CW15; /**< Offset: 0x72C (R/W 32) Screening Type 2 Compare Word 1 Register (index = 5) */ 5174 __IO GMAC_ST2CW06_Type GMAC_ST2CW06; /**< Offset: 0x730 (R/W 32) Screening Type 2 Compare Word 0 Register (index = 6) */ 5175 __IO GMAC_ST2CW16_Type GMAC_ST2CW16; /**< Offset: 0x734 (R/W 32) Screening Type 2 Compare Word 1 Register (index = 6) */ 5176 __IO GMAC_ST2CW07_Type GMAC_ST2CW07; /**< Offset: 0x738 (R/W 32) Screening Type 2 Compare Word 0 Register (index = 7) */ 5177 __IO GMAC_ST2CW17_Type GMAC_ST2CW17; /**< Offset: 0x73C (R/W 32) Screening Type 2 Compare Word 1 Register (index = 7) */ 5178 __IO GMAC_ST2CW08_Type GMAC_ST2CW08; /**< Offset: 0x740 (R/W 32) Screening Type 2 Compare Word 0 Register (index = 8) */ 5179 __IO GMAC_ST2CW18_Type GMAC_ST2CW18; /**< Offset: 0x744 (R/W 32) Screening Type 2 Compare Word 1 Register (index = 8) */ 5180 __IO GMAC_ST2CW09_Type GMAC_ST2CW09; /**< Offset: 0x748 (R/W 32) Screening Type 2 Compare Word 0 Register (index = 9) */ 5181 __IO GMAC_ST2CW19_Type GMAC_ST2CW19; /**< Offset: 0x74C (R/W 32) Screening Type 2 Compare Word 1 Register (index = 9) */ 5182 __IO GMAC_ST2CW010_Type GMAC_ST2CW010; /**< Offset: 0x750 (R/W 32) Screening Type 2 Compare Word 0 Register (index = 10) */ 5183 __IO GMAC_ST2CW110_Type GMAC_ST2CW110; /**< Offset: 0x754 (R/W 32) Screening Type 2 Compare Word 1 Register (index = 10) */ 5184 __IO GMAC_ST2CW011_Type GMAC_ST2CW011; /**< Offset: 0x758 (R/W 32) Screening Type 2 Compare Word 0 Register (index = 11) */ 5185 __IO GMAC_ST2CW111_Type GMAC_ST2CW111; /**< Offset: 0x75C (R/W 32) Screening Type 2 Compare Word 1 Register (index = 11) */ 5186 __IO GMAC_ST2CW012_Type GMAC_ST2CW012; /**< Offset: 0x760 (R/W 32) Screening Type 2 Compare Word 0 Register (index = 12) */ 5187 __IO GMAC_ST2CW112_Type GMAC_ST2CW112; /**< Offset: 0x764 (R/W 32) Screening Type 2 Compare Word 1 Register (index = 12) */ 5188 __IO GMAC_ST2CW013_Type GMAC_ST2CW013; /**< Offset: 0x768 (R/W 32) Screening Type 2 Compare Word 0 Register (index = 13) */ 5189 __IO GMAC_ST2CW113_Type GMAC_ST2CW113; /**< Offset: 0x76C (R/W 32) Screening Type 2 Compare Word 1 Register (index = 13) */ 5190 __IO GMAC_ST2CW014_Type GMAC_ST2CW014; /**< Offset: 0x770 (R/W 32) Screening Type 2 Compare Word 0 Register (index = 14) */ 5191 __IO GMAC_ST2CW114_Type GMAC_ST2CW114; /**< Offset: 0x774 (R/W 32) Screening Type 2 Compare Word 1 Register (index = 14) */ 5192 __IO GMAC_ST2CW015_Type GMAC_ST2CW015; /**< Offset: 0x778 (R/W 32) Screening Type 2 Compare Word 0 Register (index = 15) */ 5193 __IO GMAC_ST2CW115_Type GMAC_ST2CW115; /**< Offset: 0x77C (R/W 32) Screening Type 2 Compare Word 1 Register (index = 15) */ 5194 __IO GMAC_ST2CW016_Type GMAC_ST2CW016; /**< Offset: 0x780 (R/W 32) Screening Type 2 Compare Word 0 Register (index = 16) */ 5195 __IO GMAC_ST2CW116_Type GMAC_ST2CW116; /**< Offset: 0x784 (R/W 32) Screening Type 2 Compare Word 1 Register (index = 16) */ 5196 __IO GMAC_ST2CW017_Type GMAC_ST2CW017; /**< Offset: 0x788 (R/W 32) Screening Type 2 Compare Word 0 Register (index = 17) */ 5197 __IO GMAC_ST2CW117_Type GMAC_ST2CW117; /**< Offset: 0x78C (R/W 32) Screening Type 2 Compare Word 1 Register (index = 17) */ 5198 __IO GMAC_ST2CW018_Type GMAC_ST2CW018; /**< Offset: 0x790 (R/W 32) Screening Type 2 Compare Word 0 Register (index = 18) */ 5199 __IO GMAC_ST2CW118_Type GMAC_ST2CW118; /**< Offset: 0x794 (R/W 32) Screening Type 2 Compare Word 1 Register (index = 18) */ 5200 __IO GMAC_ST2CW019_Type GMAC_ST2CW019; /**< Offset: 0x798 (R/W 32) Screening Type 2 Compare Word 0 Register (index = 19) */ 5201 __IO GMAC_ST2CW119_Type GMAC_ST2CW119; /**< Offset: 0x79C (R/W 32) Screening Type 2 Compare Word 1 Register (index = 19) */ 5202 __IO GMAC_ST2CW020_Type GMAC_ST2CW020; /**< Offset: 0x7A0 (R/W 32) Screening Type 2 Compare Word 0 Register (index = 20) */ 5203 __IO GMAC_ST2CW120_Type GMAC_ST2CW120; /**< Offset: 0x7A4 (R/W 32) Screening Type 2 Compare Word 1 Register (index = 20) */ 5204 __IO GMAC_ST2CW021_Type GMAC_ST2CW021; /**< Offset: 0x7A8 (R/W 32) Screening Type 2 Compare Word 0 Register (index = 21) */ 5205 __IO GMAC_ST2CW121_Type GMAC_ST2CW121; /**< Offset: 0x7AC (R/W 32) Screening Type 2 Compare Word 1 Register (index = 21) */ 5206 __IO GMAC_ST2CW022_Type GMAC_ST2CW022; /**< Offset: 0x7B0 (R/W 32) Screening Type 2 Compare Word 0 Register (index = 22) */ 5207 __IO GMAC_ST2CW122_Type GMAC_ST2CW122; /**< Offset: 0x7B4 (R/W 32) Screening Type 2 Compare Word 1 Register (index = 22) */ 5208 __IO GMAC_ST2CW023_Type GMAC_ST2CW023; /**< Offset: 0x7B8 (R/W 32) Screening Type 2 Compare Word 0 Register (index = 23) */ 5209 __IO GMAC_ST2CW123_Type GMAC_ST2CW123; /**< Offset: 0x7BC (R/W 32) Screening Type 2 Compare Word 1 Register (index = 23) */ 5210 } Gmac; 5211 5212 #else /* COMPONENT_TYPEDEF_STYLE */ 5213 #error Unknown component typedef style 5214 #endif /* COMPONENT_TYPEDEF_STYLE */ 5215 5216 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 5217 /** @} end of Gigabit Ethernet MAC */ 5218 5219 #endif /* _SAMV71_GMAC_COMPONENT_H_ */ 5220
