1 /* ---------------------------------------------------------------------------- */ 2 /* Atmel Microcontroller Software Support */ 3 /* SAM Software Package License */ 4 /* ---------------------------------------------------------------------------- */ 5 /* Copyright (c) %copyright_year%, Atmel Corporation */ 6 /* */ 7 /* All rights reserved. */ 8 /* */ 9 /* Redistribution and use in source and binary forms, with or without */ 10 /* modification, are permitted provided that the following condition is met: */ 11 /* */ 12 /* - Redistributions of source code must retain the above copyright notice, */ 13 /* this list of conditions and the disclaimer below. */ 14 /* */ 15 /* Atmel's name may not be used to endorse or promote products derived from */ 16 /* this software without specific prior written permission. */ 17 /* */ 18 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ 19 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ 20 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ 21 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ 22 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ 23 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ 24 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ 25 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ 26 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ 27 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ 28 /* ---------------------------------------------------------------------------- */ 29 30 #ifndef _SAM4S16B_ 31 #define _SAM4S16B_ 32 33 /** \addtogroup SAM4S16B_definitions SAM4S16B definitions 34 This file defines all structures and symbols for SAM4S16B: 35 - registers and bitfields 36 - peripheral base address 37 - peripheral ID 38 - PIO definitions 39 */ 40 /*@{*/ 41 42 #ifdef __cplusplus 43 extern "C" { 44 #endif 45 46 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 47 #include <stdint.h> 48 #endif 49 50 /* ************************************************************************** */ 51 /* CMSIS DEFINITIONS FOR SAM4S16B */ 52 /* ************************************************************************** */ 53 /** \addtogroup SAM4S16B_cmsis CMSIS Definitions */ 54 /*@{*/ 55 56 /**< Interrupt Number Definition */ 57 typedef enum IRQn 58 { 59 /****** Cortex-M4 Processor Exceptions Numbers ******************************/ 60 NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ 61 HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ 62 MemoryManagement_IRQn = -12, /**< 4 Cortex-M4 Memory Management Interrupt */ 63 BusFault_IRQn = -11, /**< 5 Cortex-M4 Bus Fault Interrupt */ 64 UsageFault_IRQn = -10, /**< 6 Cortex-M4 Usage Fault Interrupt */ 65 SVCall_IRQn = -5, /**< 11 Cortex-M4 SV Call Interrupt */ 66 DebugMonitor_IRQn = -4, /**< 12 Cortex-M4 Debug Monitor Interrupt */ 67 PendSV_IRQn = -2, /**< 14 Cortex-M4 Pend SV Interrupt */ 68 SysTick_IRQn = -1, /**< 15 Cortex-M4 System Tick Interrupt */ 69 /****** SAM4S16B specific Interrupt Numbers *********************************/ 70 71 SUPC_IRQn = 0, /**< 0 SAM4S16B Supply Controller (SUPC) */ 72 RSTC_IRQn = 1, /**< 1 SAM4S16B Reset Controller (RSTC) */ 73 RTC_IRQn = 2, /**< 2 SAM4S16B Real Time Clock (RTC) */ 74 RTT_IRQn = 3, /**< 3 SAM4S16B Real Time Timer (RTT) */ 75 WDT_IRQn = 4, /**< 4 SAM4S16B Watchdog Timer (WDT) */ 76 PMC_IRQn = 5, /**< 5 SAM4S16B Power Management Controller (PMC) */ 77 EFC0_IRQn = 6, /**< 6 SAM4S16B Enhanced Embedded Flash Controller 0 (EFC0) */ 78 UART0_IRQn = 8, /**< 8 SAM4S16B UART 0 (UART0) */ 79 UART1_IRQn = 9, /**< 9 SAM4S16B UART 1 (UART1) */ 80 PIOA_IRQn = 11, /**< 11 SAM4S16B Parallel I/O Controller A (PIOA) */ 81 PIOB_IRQn = 12, /**< 12 SAM4S16B Parallel I/O Controller B (PIOB) */ 82 USART0_IRQn = 14, /**< 14 SAM4S16B USART 0 (USART0) */ 83 USART1_IRQn = 15, /**< 15 SAM4S16B USART 1 (USART1) */ 84 HSMCI_IRQn = 18, /**< 18 SAM4S16B Multimedia Card Interface (HSMCI) */ 85 TWI0_IRQn = 19, /**< 19 SAM4S16B Two Wire Interface 0 (TWI0) */ 86 TWI1_IRQn = 20, /**< 20 SAM4S16B Two Wire Interface 1 (TWI1) */ 87 SPI_IRQn = 21, /**< 21 SAM4S16B Serial Peripheral Interface (SPI) */ 88 SSC_IRQn = 22, /**< 22 SAM4S16B Synchronous Serial Controller (SSC) */ 89 TC0_IRQn = 23, /**< 23 SAM4S16B Timer/Counter 0 (TC0) */ 90 TC1_IRQn = 24, /**< 24 SAM4S16B Timer/Counter 1 (TC1) */ 91 TC2_IRQn = 25, /**< 25 SAM4S16B Timer/Counter 2 (TC2) */ 92 ADC_IRQn = 29, /**< 29 SAM4S16B Analog To Digital Converter (ADC) */ 93 DACC_IRQn = 30, /**< 30 SAM4S16B Digital To Analog Converter (DACC) */ 94 PWM_IRQn = 31, /**< 31 SAM4S16B Pulse Width Modulation (PWM) */ 95 CRCCU_IRQn = 32, /**< 32 SAM4S16B CRC Calculation Unit (CRCCU) */ 96 ACC_IRQn = 33, /**< 33 SAM4S16B Analog Comparator (ACC) */ 97 UDP_IRQn = 34, /**< 34 SAM4S16B USB Device Port (UDP) */ 98 99 PERIPH_COUNT_IRQn = 35 /**< Number of peripheral IDs */ 100 } IRQn_Type; 101 102 typedef struct _DeviceVectors 103 { 104 /* Stack pointer */ 105 void* pvStack; 106 107 /* Cortex-M handlers */ 108 void* pfnReset_Handler; 109 void* pfnNMI_Handler; 110 void* pfnHardFault_Handler; 111 void* pfnMemManage_Handler; 112 void* pfnBusFault_Handler; 113 void* pfnUsageFault_Handler; 114 void* pfnReserved1_Handler; 115 void* pfnReserved2_Handler; 116 void* pfnReserved3_Handler; 117 void* pfnReserved4_Handler; 118 void* pfnSVC_Handler; 119 void* pfnDebugMon_Handler; 120 void* pfnReserved5_Handler; 121 void* pfnPendSV_Handler; 122 void* pfnSysTick_Handler; 123 124 /* Peripheral handlers */ 125 void* pfnSUPC_Handler; /* 0 Supply Controller */ 126 void* pfnRSTC_Handler; /* 1 Reset Controller */ 127 void* pfnRTC_Handler; /* 2 Real Time Clock */ 128 void* pfnRTT_Handler; /* 3 Real Time Timer */ 129 void* pfnWDT_Handler; /* 4 Watchdog Timer */ 130 void* pfnPMC_Handler; /* 5 Power Management Controller */ 131 void* pfnEFC0_Handler; /* 6 Enhanced Embedded Flash Controller 0 */ 132 void* pvReserved7; 133 void* pfnUART0_Handler; /* 8 UART 0 */ 134 void* pfnUART1_Handler; /* 9 UART 1 */ 135 void* pvReserved10; 136 void* pfnPIOA_Handler; /* 11 Parallel I/O Controller A */ 137 void* pfnPIOB_Handler; /* 12 Parallel I/O Controller B */ 138 void* pvReserved13; 139 void* pfnUSART0_Handler; /* 14 USART 0 */ 140 void* pfnUSART1_Handler; /* 15 USART 1 */ 141 void* pvReserved16; 142 void* pvReserved17; 143 void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ 144 void* pfnTWI0_Handler; /* 19 Two Wire Interface 0 */ 145 void* pfnTWI1_Handler; /* 20 Two Wire Interface 1 */ 146 void* pfnSPI_Handler; /* 21 Serial Peripheral Interface */ 147 void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ 148 void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ 149 void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ 150 void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ 151 void* pvReserved26; 152 void* pvReserved27; 153 void* pvReserved28; 154 void* pfnADC_Handler; /* 29 Analog To Digital Converter */ 155 void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ 156 void* pfnPWM_Handler; /* 31 Pulse Width Modulation */ 157 void* pfnCRCCU_Handler; /* 32 CRC Calculation Unit */ 158 void* pfnACC_Handler; /* 33 Analog Comparator */ 159 void* pfnUDP_Handler; /* 34 USB Device Port */ 160 } DeviceVectors; 161 162 /* Cortex-M4 core handlers */ 163 void Reset_Handler ( void ); 164 void NMI_Handler ( void ); 165 void HardFault_Handler ( void ); 166 void MemManage_Handler ( void ); 167 void BusFault_Handler ( void ); 168 void UsageFault_Handler ( void ); 169 void SVC_Handler ( void ); 170 void DebugMon_Handler ( void ); 171 void PendSV_Handler ( void ); 172 void SysTick_Handler ( void ); 173 174 /* Peripherals handlers */ 175 void ACC_Handler ( void ); 176 void ADC_Handler ( void ); 177 void CRCCU_Handler ( void ); 178 void DACC_Handler ( void ); 179 void EFC0_Handler ( void ); 180 void HSMCI_Handler ( void ); 181 void PIOA_Handler ( void ); 182 void PIOB_Handler ( void ); 183 void PMC_Handler ( void ); 184 void PWM_Handler ( void ); 185 void RSTC_Handler ( void ); 186 void RTC_Handler ( void ); 187 void RTT_Handler ( void ); 188 void SPI_Handler ( void ); 189 void SSC_Handler ( void ); 190 void SUPC_Handler ( void ); 191 void TC0_Handler ( void ); 192 void TC1_Handler ( void ); 193 void TC2_Handler ( void ); 194 void TWI0_Handler ( void ); 195 void TWI1_Handler ( void ); 196 void UART0_Handler ( void ); 197 void UART1_Handler ( void ); 198 void UDP_Handler ( void ); 199 void USART0_Handler ( void ); 200 void USART1_Handler ( void ); 201 void WDT_Handler ( void ); 202 203 /** 204 * \brief Configuration of the Cortex-M4 Processor and Core Peripherals 205 */ 206 207 #define __CM4_REV 0x0001 /**< SAM4S16B core revision number ([15:8] revision number, [7:0] patch number) */ 208 #define __MPU_PRESENT 1 /**< SAM4S16B does provide a MPU */ 209 #define __FPU_PRESENT 0 /**< SAM4S16B does not provide a FPU */ 210 #define __NVIC_PRIO_BITS 4 /**< SAM4S16B uses 4 Bits for the Priority Levels */ 211 #define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ 212 213 /* 214 * \brief CMSIS includes 215 */ 216 217 #include <core_cm4.h> 218 #if !defined DONT_USE_CMSIS_INIT 219 #include "system_sam4s.h" 220 #endif /* DONT_USE_CMSIS_INIT */ 221 222 /*@}*/ 223 224 /* ************************************************************************** */ 225 /** SOFTWARE PERIPHERAL API DEFINITION FOR SAM4S16B */ 226 /* ************************************************************************** */ 227 /** \addtogroup SAM4S16B_api Peripheral Software API */ 228 /*@{*/ 229 230 #include "component/acc.h" 231 #include "component/adc.h" 232 #include "component/chipid.h" 233 #include "component/crccu.h" 234 #include "component/dacc.h" 235 #include "component/efc.h" 236 #include "component/gpbr.h" 237 #include "component/hsmci.h" 238 #include "component/matrix.h" 239 #include "component/pdc.h" 240 #include "component/pio.h" 241 #include "component/pmc.h" 242 #include "component/pwm.h" 243 #include "component/rstc.h" 244 #include "component/rtc.h" 245 #include "component/rtt.h" 246 #include "component/spi.h" 247 #include "component/ssc.h" 248 #include "component/supc.h" 249 #include "component/tc.h" 250 #include "component/twi.h" 251 #include "component/uart.h" 252 #include "component/udp.h" 253 #include "component/usart.h" 254 #include "component/wdt.h" 255 /*@}*/ 256 257 /* ************************************************************************** */ 258 /* REGISTER ACCESS DEFINITIONS FOR SAM4S16B */ 259 /* ************************************************************************** */ 260 /** \addtogroup SAM4S16B_reg Registers Access Definitions */ 261 /*@{*/ 262 263 #include "instance/hsmci.h" 264 #include "instance/ssc.h" 265 #include "instance/spi.h" 266 #include "instance/tc0.h" 267 #include "instance/twi0.h" 268 #include "instance/twi1.h" 269 #include "instance/pwm.h" 270 #include "instance/usart0.h" 271 #include "instance/usart1.h" 272 #include "instance/udp.h" 273 #include "instance/adc.h" 274 #include "instance/dacc.h" 275 #include "instance/acc.h" 276 #include "instance/crccu.h" 277 #include "instance/matrix.h" 278 #include "instance/pmc.h" 279 #include "instance/uart0.h" 280 #include "instance/chipid.h" 281 #include "instance/uart1.h" 282 #include "instance/efc0.h" 283 #include "instance/pioa.h" 284 #include "instance/piob.h" 285 #include "instance/rstc.h" 286 #include "instance/supc.h" 287 #include "instance/rtt.h" 288 #include "instance/wdt.h" 289 #include "instance/rtc.h" 290 #include "instance/gpbr.h" 291 /*@}*/ 292 293 /* ************************************************************************** */ 294 /* PERIPHERAL ID DEFINITIONS FOR SAM4S16B */ 295 /* ************************************************************************** */ 296 /** \addtogroup SAM4S16B_id Peripheral Ids Definitions */ 297 /*@{*/ 298 299 #define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ 300 #define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ 301 #define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ 302 #define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ 303 #define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ 304 #define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ 305 #define ID_EFC0 ( 6) /**< \brief Enhanced Embedded Flash Controller 0 (EFC0) */ 306 #define ID_UART0 ( 8) /**< \brief UART 0 (UART0) */ 307 #define ID_UART1 ( 9) /**< \brief UART 1 (UART1) */ 308 #define ID_PIOA (11) /**< \brief Parallel I/O Controller A (PIOA) */ 309 #define ID_PIOB (12) /**< \brief Parallel I/O Controller B (PIOB) */ 310 #define ID_USART0 (14) /**< \brief USART 0 (USART0) */ 311 #define ID_USART1 (15) /**< \brief USART 1 (USART1) */ 312 #define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ 313 #define ID_TWI0 (19) /**< \brief Two Wire Interface 0 (TWI0) */ 314 #define ID_TWI1 (20) /**< \brief Two Wire Interface 1 (TWI1) */ 315 #define ID_SPI (21) /**< \brief Serial Peripheral Interface (SPI) */ 316 #define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ 317 #define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ 318 #define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ 319 #define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ 320 #define ID_ADC (29) /**< \brief Analog To Digital Converter (ADC) */ 321 #define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ 322 #define ID_PWM (31) /**< \brief Pulse Width Modulation (PWM) */ 323 #define ID_CRCCU (32) /**< \brief CRC Calculation Unit (CRCCU) */ 324 #define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ 325 #define ID_UDP (34) /**< \brief USB Device Port (UDP) */ 326 327 #define ID_PERIPH_COUNT (35) /**< \brief Number of peripheral IDs */ 328 /*@}*/ 329 330 /* ************************************************************************** */ 331 /* BASE ADDRESS DEFINITIONS FOR SAM4S16B */ 332 /* ************************************************************************** */ 333 /** \addtogroup SAM4S16B_base Peripheral Base Address Definitions */ 334 /*@{*/ 335 336 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 337 #define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ 338 #define PDC_HSMCI (0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */ 339 #define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ 340 #define PDC_SSC (0x40004100U) /**< \brief (PDC_SSC ) Base Address */ 341 #define SPI (0x40008000U) /**< \brief (SPI ) Base Address */ 342 #define PDC_SPI (0x40008100U) /**< \brief (PDC_SPI ) Base Address */ 343 #define TC0 (0x40010000U) /**< \brief (TC0 ) Base Address */ 344 #define TWI0 (0x40018000U) /**< \brief (TWI0 ) Base Address */ 345 #define PDC_TWI0 (0x40018100U) /**< \brief (PDC_TWI0 ) Base Address */ 346 #define TWI1 (0x4001C000U) /**< \brief (TWI1 ) Base Address */ 347 #define PDC_TWI1 (0x4001C100U) /**< \brief (PDC_TWI1 ) Base Address */ 348 #define PWM (0x40020000U) /**< \brief (PWM ) Base Address */ 349 #define PDC_PWM (0x40020100U) /**< \brief (PDC_PWM ) Base Address */ 350 #define USART0 (0x40024000U) /**< \brief (USART0 ) Base Address */ 351 #define PDC_USART0 (0x40024100U) /**< \brief (PDC_USART0) Base Address */ 352 #define USART1 (0x40028000U) /**< \brief (USART1 ) Base Address */ 353 #define PDC_USART1 (0x40028100U) /**< \brief (PDC_USART1) Base Address */ 354 #define UDP (0x40034000U) /**< \brief (UDP ) Base Address */ 355 #define ADC (0x40038000U) /**< \brief (ADC ) Base Address */ 356 #define PDC_ADC (0x40038100U) /**< \brief (PDC_ADC ) Base Address */ 357 #define DACC (0x4003C000U) /**< \brief (DACC ) Base Address */ 358 #define PDC_DACC (0x4003C100U) /**< \brief (PDC_DACC ) Base Address */ 359 #define ACC (0x40040000U) /**< \brief (ACC ) Base Address */ 360 #define CRCCU (0x40044000U) /**< \brief (CRCCU ) Base Address */ 361 #define MATRIX (0x400E0200U) /**< \brief (MATRIX ) Base Address */ 362 #define PMC (0x400E0400U) /**< \brief (PMC ) Base Address */ 363 #define UART0 (0x400E0600U) /**< \brief (UART0 ) Base Address */ 364 #define PDC_UART0 (0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */ 365 #define CHIPID (0x400E0740U) /**< \brief (CHIPID ) Base Address */ 366 #define UART1 (0x400E0800U) /**< \brief (UART1 ) Base Address */ 367 #define PDC_UART1 (0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */ 368 #define EFC0 (0x400E0A00U) /**< \brief (EFC0 ) Base Address */ 369 #define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ 370 #define PDC_PIOA (0x400E0F68U) /**< \brief (PDC_PIOA ) Base Address */ 371 #define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ 372 #define RSTC (0x400E1400U) /**< \brief (RSTC ) Base Address */ 373 #define SUPC (0x400E1410U) /**< \brief (SUPC ) Base Address */ 374 #define RTT (0x400E1430U) /**< \brief (RTT ) Base Address */ 375 #define WDT (0x400E1450U) /**< \brief (WDT ) Base Address */ 376 #define RTC (0x400E1460U) /**< \brief (RTC ) Base Address */ 377 #define GPBR (0x400E1490U) /**< \brief (GPBR ) Base Address */ 378 #else 379 #define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ 380 #define PDC_HSMCI ((Pdc *)0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */ 381 #define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ 382 #define PDC_SSC ((Pdc *)0x40004100U) /**< \brief (PDC_SSC ) Base Address */ 383 #define SPI ((Spi *)0x40008000U) /**< \brief (SPI ) Base Address */ 384 #define PDC_SPI ((Pdc *)0x40008100U) /**< \brief (PDC_SPI ) Base Address */ 385 #define TC0 ((Tc *)0x40010000U) /**< \brief (TC0 ) Base Address */ 386 #define TWI0 ((Twi *)0x40018000U) /**< \brief (TWI0 ) Base Address */ 387 #define PDC_TWI0 ((Pdc *)0x40018100U) /**< \brief (PDC_TWI0 ) Base Address */ 388 #define TWI1 ((Twi *)0x4001C000U) /**< \brief (TWI1 ) Base Address */ 389 #define PDC_TWI1 ((Pdc *)0x4001C100U) /**< \brief (PDC_TWI1 ) Base Address */ 390 #define PWM ((Pwm *)0x40020000U) /**< \brief (PWM ) Base Address */ 391 #define PDC_PWM ((Pdc *)0x40020100U) /**< \brief (PDC_PWM ) Base Address */ 392 #define USART0 ((Usart *)0x40024000U) /**< \brief (USART0 ) Base Address */ 393 #define PDC_USART0 ((Pdc *)0x40024100U) /**< \brief (PDC_USART0) Base Address */ 394 #define USART1 ((Usart *)0x40028000U) /**< \brief (USART1 ) Base Address */ 395 #define PDC_USART1 ((Pdc *)0x40028100U) /**< \brief (PDC_USART1) Base Address */ 396 #define UDP ((Udp *)0x40034000U) /**< \brief (UDP ) Base Address */ 397 #define ADC ((Adc *)0x40038000U) /**< \brief (ADC ) Base Address */ 398 #define PDC_ADC ((Pdc *)0x40038100U) /**< \brief (PDC_ADC ) Base Address */ 399 #define DACC ((Dacc *)0x4003C000U) /**< \brief (DACC ) Base Address */ 400 #define PDC_DACC ((Pdc *)0x4003C100U) /**< \brief (PDC_DACC ) Base Address */ 401 #define ACC ((Acc *)0x40040000U) /**< \brief (ACC ) Base Address */ 402 #define CRCCU ((Crccu *)0x40044000U) /**< \brief (CRCCU ) Base Address */ 403 #define MATRIX ((Matrix *)0x400E0200U) /**< \brief (MATRIX ) Base Address */ 404 #define PMC ((Pmc *)0x400E0400U) /**< \brief (PMC ) Base Address */ 405 #define UART0 ((Uart *)0x400E0600U) /**< \brief (UART0 ) Base Address */ 406 #define PDC_UART0 ((Pdc *)0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */ 407 #define CHIPID ((Chipid *)0x400E0740U) /**< \brief (CHIPID ) Base Address */ 408 #define UART1 ((Uart *)0x400E0800U) /**< \brief (UART1 ) Base Address */ 409 #define PDC_UART1 ((Pdc *)0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */ 410 #define EFC0 ((Efc *)0x400E0A00U) /**< \brief (EFC0 ) Base Address */ 411 #define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ 412 #define PDC_PIOA ((Pdc *)0x400E0F68U) /**< \brief (PDC_PIOA ) Base Address */ 413 #define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ 414 #define RSTC ((Rstc *)0x400E1400U) /**< \brief (RSTC ) Base Address */ 415 #define SUPC ((Supc *)0x400E1410U) /**< \brief (SUPC ) Base Address */ 416 #define RTT ((Rtt *)0x400E1430U) /**< \brief (RTT ) Base Address */ 417 #define WDT ((Wdt *)0x400E1450U) /**< \brief (WDT ) Base Address */ 418 #define RTC ((Rtc *)0x400E1460U) /**< \brief (RTC ) Base Address */ 419 #define GPBR ((Gpbr *)0x400E1490U) /**< \brief (GPBR ) Base Address */ 420 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 421 /*@}*/ 422 423 /* ************************************************************************** */ 424 /* PIO DEFINITIONS FOR SAM4S16B */ 425 /* ************************************************************************** */ 426 /** \addtogroup SAM4S16B_pio Peripheral Pio Definitions */ 427 /*@{*/ 428 429 #include "pio/sam4s16b.h" 430 /*@}*/ 431 432 /* ************************************************************************** */ 433 /* MEMORY MAPPING DEFINITIONS FOR SAM4S16B */ 434 /* ************************************************************************** */ 435 436 #define IFLASH0_SIZE (0x100000u) 437 #define IFLASH0_PAGE_SIZE (512u) 438 #define IFLASH0_LOCK_REGION_SIZE (8192u) 439 #define IFLASH0_NB_OF_PAGES (2048u) 440 #define IFLASH0_NB_OF_LOCK_BITS (128u) 441 #define IRAM_SIZE (0x20000u) 442 #define IFLASH_SIZE (IFLASH0_SIZE) 443 444 #define IFLASH0_ADDR (0x00400000u) /**< Internal Flash 0 base address */ 445 #define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ 446 #define IRAM_ADDR (0x20000000u) /**< Internal RAM base address */ 447 #define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ 448 #define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ 449 #define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ 450 #define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ 451 452 /* ************************************************************************** */ 453 /* MISCELLANEOUS DEFINITIONS FOR SAM4S16B */ 454 /* ************************************************************************** */ 455 456 #define CHIP_JTAGID (0x05B3203FUL) 457 #define CHIP_CIDR (0x289C0CE0UL) 458 #define CHIP_EXID (0x0UL) 459 #define NB_CH_ADC (10UL) 460 #define NB_CH_DAC (2UL) 461 #define USB_DEVICE_MAX_EP (8UL) 462 463 /* ************************************************************************** */ 464 /* ELECTRICAL DEFINITIONS FOR SAM4S16B */ 465 /* ************************************************************************** */ 466 467 /* Device characteristics */ 468 #define CHIP_FREQ_SLCK_RC_MIN (20000UL) 469 #define CHIP_FREQ_SLCK_RC (32000UL) 470 #define CHIP_FREQ_SLCK_RC_MAX (44000UL) 471 #define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) 472 #define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) 473 #define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) 474 #define CHIP_FREQ_CPU_MAX (120000000UL) 475 #define CHIP_FREQ_XTAL_32K (32768UL) 476 477 /* Embedded Flash Write Wait State */ 478 #define CHIP_FLASH_WRITE_WAIT_STATE (6U) 479 480 #if defined __SAM4S2A__ || defined __SAM4S2B__ || defined __SAM4S2C__ || \ 481 defined __SAM4S4A__ || defined __SAM4S4B__ || defined __SAM4S4C__ 482 483 /* Embedded Flash Read Wait State (VDDCORE set at 1.20V and VDDIO 3.3V) */ 484 #define CHIP_FREQ_FWS_0 (29000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ 485 #define CHIP_FREQ_FWS_1 (58000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ 486 #define CHIP_FREQ_FWS_2 (88000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ 487 #define CHIP_FREQ_FWS_3 (10800000UL) /**< \brief Maximum operating frequency when FWS is 3 */ 488 #define CHIP_FREQ_FWS_4 (120000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ 489 490 #else /* SAM4S8/S16/SA16/SD16/SD32 */ 491 492 /* Embedded Flash Read Wait State (VDDCORE set at 1.20V and VDDIO 3.3V) */ 493 #define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ 494 #define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ 495 #define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ 496 #define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ 497 #define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ 498 #define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ 499 500 #endif 501 502 /* HYSTeresis levels: please refer to Electrical Characteristics */ 503 #define ACC_ACR_HYST_50MV_MAX (0x01UL) 504 #define ACC_ACR_HYST_90MV_MAX (0x11UL) 505 506 507 508 #ifdef __cplusplus 509 } 510 #endif 511 512 /*@}*/ 513 514 #endif /* _SAM4S16B_ */ 515
