1 /** 2 * \file 3 * 4 * \brief Peripheral I/O description for SAM4LS4C 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAM4LS4C_PIO_ 30 #define _SAM4LS4C_PIO_ 31 32 #define PIN_PA00 0 /**< \brief Pin Number for PA00 */ 33 #define GPIO_PA00 _UL_(1 << 0) /**< \brief GPIO Mask for PA00 */ 34 #define PIN_PA01 1 /**< \brief Pin Number for PA01 */ 35 #define GPIO_PA01 _UL_(1 << 1) /**< \brief GPIO Mask for PA01 */ 36 #define PIN_PA02 2 /**< \brief Pin Number for PA02 */ 37 #define GPIO_PA02 _UL_(1 << 2) /**< \brief GPIO Mask for PA02 */ 38 #define PIN_PA03 3 /**< \brief Pin Number for PA03 */ 39 #define GPIO_PA03 _UL_(1 << 3) /**< \brief GPIO Mask for PA03 */ 40 #define PIN_PA04 4 /**< \brief Pin Number for PA04 */ 41 #define GPIO_PA04 _UL_(1 << 4) /**< \brief GPIO Mask for PA04 */ 42 #define PIN_PA05 5 /**< \brief Pin Number for PA05 */ 43 #define GPIO_PA05 _UL_(1 << 5) /**< \brief GPIO Mask for PA05 */ 44 #define PIN_PA06 6 /**< \brief Pin Number for PA06 */ 45 #define GPIO_PA06 _UL_(1 << 6) /**< \brief GPIO Mask for PA06 */ 46 #define PIN_PA07 7 /**< \brief Pin Number for PA07 */ 47 #define GPIO_PA07 _UL_(1 << 7) /**< \brief GPIO Mask for PA07 */ 48 #define PIN_PA08 8 /**< \brief Pin Number for PA08 */ 49 #define GPIO_PA08 _UL_(1 << 8) /**< \brief GPIO Mask for PA08 */ 50 #define PIN_PA09 9 /**< \brief Pin Number for PA09 */ 51 #define GPIO_PA09 _UL_(1 << 9) /**< \brief GPIO Mask for PA09 */ 52 #define PIN_PA10 10 /**< \brief Pin Number for PA10 */ 53 #define GPIO_PA10 _UL_(1 << 10) /**< \brief GPIO Mask for PA10 */ 54 #define PIN_PA11 11 /**< \brief Pin Number for PA11 */ 55 #define GPIO_PA11 _UL_(1 << 11) /**< \brief GPIO Mask for PA11 */ 56 #define PIN_PA12 12 /**< \brief Pin Number for PA12 */ 57 #define GPIO_PA12 _UL_(1 << 12) /**< \brief GPIO Mask for PA12 */ 58 #define PIN_PA13 13 /**< \brief Pin Number for PA13 */ 59 #define GPIO_PA13 _UL_(1 << 13) /**< \brief GPIO Mask for PA13 */ 60 #define PIN_PA14 14 /**< \brief Pin Number for PA14 */ 61 #define GPIO_PA14 _UL_(1 << 14) /**< \brief GPIO Mask for PA14 */ 62 #define PIN_PA15 15 /**< \brief Pin Number for PA15 */ 63 #define GPIO_PA15 _UL_(1 << 15) /**< \brief GPIO Mask for PA15 */ 64 #define PIN_PA16 16 /**< \brief Pin Number for PA16 */ 65 #define GPIO_PA16 _UL_(1 << 16) /**< \brief GPIO Mask for PA16 */ 66 #define PIN_PA17 17 /**< \brief Pin Number for PA17 */ 67 #define GPIO_PA17 _UL_(1 << 17) /**< \brief GPIO Mask for PA17 */ 68 #define PIN_PA18 18 /**< \brief Pin Number for PA18 */ 69 #define GPIO_PA18 _UL_(1 << 18) /**< \brief GPIO Mask for PA18 */ 70 #define PIN_PA19 19 /**< \brief Pin Number for PA19 */ 71 #define GPIO_PA19 _UL_(1 << 19) /**< \brief GPIO Mask for PA19 */ 72 #define PIN_PA20 20 /**< \brief Pin Number for PA20 */ 73 #define GPIO_PA20 _UL_(1 << 20) /**< \brief GPIO Mask for PA20 */ 74 #define PIN_PA21 21 /**< \brief Pin Number for PA21 */ 75 #define GPIO_PA21 _UL_(1 << 21) /**< \brief GPIO Mask for PA21 */ 76 #define PIN_PA22 22 /**< \brief Pin Number for PA22 */ 77 #define GPIO_PA22 _UL_(1 << 22) /**< \brief GPIO Mask for PA22 */ 78 #define PIN_PA23 23 /**< \brief Pin Number for PA23 */ 79 #define GPIO_PA23 _UL_(1 << 23) /**< \brief GPIO Mask for PA23 */ 80 #define PIN_PA24 24 /**< \brief Pin Number for PA24 */ 81 #define GPIO_PA24 _UL_(1 << 24) /**< \brief GPIO Mask for PA24 */ 82 #define PIN_PA25 25 /**< \brief Pin Number for PA25 */ 83 #define GPIO_PA25 _UL_(1 << 25) /**< \brief GPIO Mask for PA25 */ 84 #define PIN_PA26 26 /**< \brief Pin Number for PA26 */ 85 #define GPIO_PA26 _UL_(1 << 26) /**< \brief GPIO Mask for PA26 */ 86 #define PIN_PA27 27 /**< \brief Pin Number for PA27 */ 87 #define GPIO_PA27 _UL_(1 << 27) /**< \brief GPIO Mask for PA27 */ 88 #define PIN_PA28 28 /**< \brief Pin Number for PA28 */ 89 #define GPIO_PA28 _UL_(1 << 28) /**< \brief GPIO Mask for PA28 */ 90 #define PIN_PA29 29 /**< \brief Pin Number for PA29 */ 91 #define GPIO_PA29 _UL_(1 << 29) /**< \brief GPIO Mask for PA29 */ 92 #define PIN_PA30 30 /**< \brief Pin Number for PA30 */ 93 #define GPIO_PA30 _UL_(1 << 30) /**< \brief GPIO Mask for PA30 */ 94 #define PIN_PA31 31 /**< \brief Pin Number for PA31 */ 95 #define GPIO_PA31 _UL_(1 << 31) /**< \brief GPIO Mask for PA31 */ 96 #define PIN_PB00 32 /**< \brief Pin Number for PB00 */ 97 #define GPIO_PB00 _UL_(1 << 0) /**< \brief GPIO Mask for PB00 */ 98 #define PIN_PB01 33 /**< \brief Pin Number for PB01 */ 99 #define GPIO_PB01 _UL_(1 << 1) /**< \brief GPIO Mask for PB01 */ 100 #define PIN_PB02 34 /**< \brief Pin Number for PB02 */ 101 #define GPIO_PB02 _UL_(1 << 2) /**< \brief GPIO Mask for PB02 */ 102 #define PIN_PB03 35 /**< \brief Pin Number for PB03 */ 103 #define GPIO_PB03 _UL_(1 << 3) /**< \brief GPIO Mask for PB03 */ 104 #define PIN_PB04 36 /**< \brief Pin Number for PB04 */ 105 #define GPIO_PB04 _UL_(1 << 4) /**< \brief GPIO Mask for PB04 */ 106 #define PIN_PB05 37 /**< \brief Pin Number for PB05 */ 107 #define GPIO_PB05 _UL_(1 << 5) /**< \brief GPIO Mask for PB05 */ 108 #define PIN_PB06 38 /**< \brief Pin Number for PB06 */ 109 #define GPIO_PB06 _UL_(1 << 6) /**< \brief GPIO Mask for PB06 */ 110 #define PIN_PB07 39 /**< \brief Pin Number for PB07 */ 111 #define GPIO_PB07 _UL_(1 << 7) /**< \brief GPIO Mask for PB07 */ 112 #define PIN_PB08 40 /**< \brief Pin Number for PB08 */ 113 #define GPIO_PB08 _UL_(1 << 8) /**< \brief GPIO Mask for PB08 */ 114 #define PIN_PB09 41 /**< \brief Pin Number for PB09 */ 115 #define GPIO_PB09 _UL_(1 << 9) /**< \brief GPIO Mask for PB09 */ 116 #define PIN_PB10 42 /**< \brief Pin Number for PB10 */ 117 #define GPIO_PB10 _UL_(1 << 10) /**< \brief GPIO Mask for PB10 */ 118 #define PIN_PB11 43 /**< \brief Pin Number for PB11 */ 119 #define GPIO_PB11 _UL_(1 << 11) /**< \brief GPIO Mask for PB11 */ 120 #define PIN_PB12 44 /**< \brief Pin Number for PB12 */ 121 #define GPIO_PB12 _UL_(1 << 12) /**< \brief GPIO Mask for PB12 */ 122 #define PIN_PB13 45 /**< \brief Pin Number for PB13 */ 123 #define GPIO_PB13 _UL_(1 << 13) /**< \brief GPIO Mask for PB13 */ 124 #define PIN_PB14 46 /**< \brief Pin Number for PB14 */ 125 #define GPIO_PB14 _UL_(1 << 14) /**< \brief GPIO Mask for PB14 */ 126 #define PIN_PB15 47 /**< \brief Pin Number for PB15 */ 127 #define GPIO_PB15 _UL_(1 << 15) /**< \brief GPIO Mask for PB15 */ 128 #define PIN_PC00 64 /**< \brief Pin Number for PC00 */ 129 #define GPIO_PC00 _UL_(1 << 0) /**< \brief GPIO Mask for PC00 */ 130 #define PIN_PC01 65 /**< \brief Pin Number for PC01 */ 131 #define GPIO_PC01 _UL_(1 << 1) /**< \brief GPIO Mask for PC01 */ 132 #define PIN_PC02 66 /**< \brief Pin Number for PC02 */ 133 #define GPIO_PC02 _UL_(1 << 2) /**< \brief GPIO Mask for PC02 */ 134 #define PIN_PC03 67 /**< \brief Pin Number for PC03 */ 135 #define GPIO_PC03 _UL_(1 << 3) /**< \brief GPIO Mask for PC03 */ 136 #define PIN_PC04 68 /**< \brief Pin Number for PC04 */ 137 #define GPIO_PC04 _UL_(1 << 4) /**< \brief GPIO Mask for PC04 */ 138 #define PIN_PC05 69 /**< \brief Pin Number for PC05 */ 139 #define GPIO_PC05 _UL_(1 << 5) /**< \brief GPIO Mask for PC05 */ 140 #define PIN_PC06 70 /**< \brief Pin Number for PC06 */ 141 #define GPIO_PC06 _UL_(1 << 6) /**< \brief GPIO Mask for PC06 */ 142 #define PIN_PC07 71 /**< \brief Pin Number for PC07 */ 143 #define GPIO_PC07 _UL_(1 << 7) /**< \brief GPIO Mask for PC07 */ 144 #define PIN_PC08 72 /**< \brief Pin Number for PC08 */ 145 #define GPIO_PC08 _UL_(1 << 8) /**< \brief GPIO Mask for PC08 */ 146 #define PIN_PC09 73 /**< \brief Pin Number for PC09 */ 147 #define GPIO_PC09 _UL_(1 << 9) /**< \brief GPIO Mask for PC09 */ 148 #define PIN_PC10 74 /**< \brief Pin Number for PC10 */ 149 #define GPIO_PC10 _UL_(1 << 10) /**< \brief GPIO Mask for PC10 */ 150 #define PIN_PC11 75 /**< \brief Pin Number for PC11 */ 151 #define GPIO_PC11 _UL_(1 << 11) /**< \brief GPIO Mask for PC11 */ 152 #define PIN_PC12 76 /**< \brief Pin Number for PC12 */ 153 #define GPIO_PC12 _UL_(1 << 12) /**< \brief GPIO Mask for PC12 */ 154 #define PIN_PC13 77 /**< \brief Pin Number for PC13 */ 155 #define GPIO_PC13 _UL_(1 << 13) /**< \brief GPIO Mask for PC13 */ 156 #define PIN_PC14 78 /**< \brief Pin Number for PC14 */ 157 #define GPIO_PC14 _UL_(1 << 14) /**< \brief GPIO Mask for PC14 */ 158 #define PIN_PC15 79 /**< \brief Pin Number for PC15 */ 159 #define GPIO_PC15 _UL_(1 << 15) /**< \brief GPIO Mask for PC15 */ 160 #define PIN_PC16 80 /**< \brief Pin Number for PC16 */ 161 #define GPIO_PC16 _UL_(1 << 16) /**< \brief GPIO Mask for PC16 */ 162 #define PIN_PC17 81 /**< \brief Pin Number for PC17 */ 163 #define GPIO_PC17 _UL_(1 << 17) /**< \brief GPIO Mask for PC17 */ 164 #define PIN_PC18 82 /**< \brief Pin Number for PC18 */ 165 #define GPIO_PC18 _UL_(1 << 18) /**< \brief GPIO Mask for PC18 */ 166 #define PIN_PC19 83 /**< \brief Pin Number for PC19 */ 167 #define GPIO_PC19 _UL_(1 << 19) /**< \brief GPIO Mask for PC19 */ 168 #define PIN_PC20 84 /**< \brief Pin Number for PC20 */ 169 #define GPIO_PC20 _UL_(1 << 20) /**< \brief GPIO Mask for PC20 */ 170 #define PIN_PC21 85 /**< \brief Pin Number for PC21 */ 171 #define GPIO_PC21 _UL_(1 << 21) /**< \brief GPIO Mask for PC21 */ 172 #define PIN_PC22 86 /**< \brief Pin Number for PC22 */ 173 #define GPIO_PC22 _UL_(1 << 22) /**< \brief GPIO Mask for PC22 */ 174 #define PIN_PC23 87 /**< \brief Pin Number for PC23 */ 175 #define GPIO_PC23 _UL_(1 << 23) /**< \brief GPIO Mask for PC23 */ 176 #define PIN_PC24 88 /**< \brief Pin Number for PC24 */ 177 #define GPIO_PC24 _UL_(1 << 24) /**< \brief GPIO Mask for PC24 */ 178 #define PIN_PC25 89 /**< \brief Pin Number for PC25 */ 179 #define GPIO_PC25 _UL_(1 << 25) /**< \brief GPIO Mask for PC25 */ 180 #define PIN_PC26 90 /**< \brief Pin Number for PC26 */ 181 #define GPIO_PC26 _UL_(1 << 26) /**< \brief GPIO Mask for PC26 */ 182 #define PIN_PC27 91 /**< \brief Pin Number for PC27 */ 183 #define GPIO_PC27 _UL_(1 << 27) /**< \brief GPIO Mask for PC27 */ 184 #define PIN_PC28 92 /**< \brief Pin Number for PC28 */ 185 #define GPIO_PC28 _UL_(1 << 28) /**< \brief GPIO Mask for PC28 */ 186 #define PIN_PC29 93 /**< \brief Pin Number for PC29 */ 187 #define GPIO_PC29 _UL_(1 << 29) /**< \brief GPIO Mask for PC29 */ 188 #define PIN_PC30 94 /**< \brief Pin Number for PC30 */ 189 #define GPIO_PC30 _UL_(1 << 30) /**< \brief GPIO Mask for PC30 */ 190 #define PIN_PC31 95 /**< \brief Pin Number for PC31 */ 191 #define GPIO_PC31 _UL_(1 << 31) /**< \brief GPIO Mask for PC31 */ 192 /* ========== GPIO definition for TWIMS0 peripheral ========== */ 193 #define PIN_PA24B_TWIMS0_TWCK _L_(24) /**< \brief TWIMS0 signal: TWCK on PA24 mux B */ 194 #define MUX_PA24B_TWIMS0_TWCK _L_(1) 195 #define PINMUX_PA24B_TWIMS0_TWCK ((PIN_PA24B_TWIMS0_TWCK << 16) | MUX_PA24B_TWIMS0_TWCK) 196 #define GPIO_PA24B_TWIMS0_TWCK _UL_(1 << 24) 197 #define PIN_PA23B_TWIMS0_TWD _L_(23) /**< \brief TWIMS0 signal: TWD on PA23 mux B */ 198 #define MUX_PA23B_TWIMS0_TWD _L_(1) 199 #define PINMUX_PA23B_TWIMS0_TWD ((PIN_PA23B_TWIMS0_TWD << 16) | MUX_PA23B_TWIMS0_TWD) 200 #define GPIO_PA23B_TWIMS0_TWD _UL_(1 << 23) 201 /* ========== GPIO definition for TWIMS1 peripheral ========== */ 202 #define PIN_PB01A_TWIMS1_TWCK _L_(33) /**< \brief TWIMS1 signal: TWCK on PB01 mux A */ 203 #define MUX_PB01A_TWIMS1_TWCK _L_(0) 204 #define PINMUX_PB01A_TWIMS1_TWCK ((PIN_PB01A_TWIMS1_TWCK << 16) | MUX_PB01A_TWIMS1_TWCK) 205 #define GPIO_PB01A_TWIMS1_TWCK _UL_(1 << 1) 206 #define PIN_PB00A_TWIMS1_TWD _L_(32) /**< \brief TWIMS1 signal: TWD on PB00 mux A */ 207 #define MUX_PB00A_TWIMS1_TWD _L_(0) 208 #define PINMUX_PB00A_TWIMS1_TWD ((PIN_PB00A_TWIMS1_TWD << 16) | MUX_PB00A_TWIMS1_TWD) 209 #define GPIO_PB00A_TWIMS1_TWD _UL_(1 << 0) 210 /* ========== GPIO definition for TWIMS2 peripheral ========== */ 211 #define PIN_PA22E_TWIMS2_TWCK _L_(22) /**< \brief TWIMS2 signal: TWCK on PA22 mux E */ 212 #define MUX_PA22E_TWIMS2_TWCK _L_(4) 213 #define PINMUX_PA22E_TWIMS2_TWCK ((PIN_PA22E_TWIMS2_TWCK << 16) | MUX_PA22E_TWIMS2_TWCK) 214 #define GPIO_PA22E_TWIMS2_TWCK _UL_(1 << 22) 215 #define PIN_PA21E_TWIMS2_TWD _L_(21) /**< \brief TWIMS2 signal: TWD on PA21 mux E */ 216 #define MUX_PA21E_TWIMS2_TWD _L_(4) 217 #define PINMUX_PA21E_TWIMS2_TWD ((PIN_PA21E_TWIMS2_TWD << 16) | MUX_PA21E_TWIMS2_TWD) 218 #define GPIO_PA21E_TWIMS2_TWD _UL_(1 << 21) 219 /* ========== GPIO definition for TWIMS3 peripheral ========== */ 220 #define PIN_PB15C_TWIMS3_TWCK _L_(47) /**< \brief TWIMS3 signal: TWCK on PB15 mux C */ 221 #define MUX_PB15C_TWIMS3_TWCK _L_(2) 222 #define PINMUX_PB15C_TWIMS3_TWCK ((PIN_PB15C_TWIMS3_TWCK << 16) | MUX_PB15C_TWIMS3_TWCK) 223 #define GPIO_PB15C_TWIMS3_TWCK _UL_(1 << 15) 224 #define PIN_PB14C_TWIMS3_TWD _L_(46) /**< \brief TWIMS3 signal: TWD on PB14 mux C */ 225 #define MUX_PB14C_TWIMS3_TWD _L_(2) 226 #define PINMUX_PB14C_TWIMS3_TWD ((PIN_PB14C_TWIMS3_TWD << 16) | MUX_PB14C_TWIMS3_TWD) 227 #define GPIO_PB14C_TWIMS3_TWD _UL_(1 << 14) 228 /* ========== GPIO definition for IISC peripheral ========== */ 229 #define PIN_PB05D_IISC_IMCK _L_(37) /**< \brief IISC signal: IMCK on PB05 mux D */ 230 #define MUX_PB05D_IISC_IMCK _L_(3) 231 #define PINMUX_PB05D_IISC_IMCK ((PIN_PB05D_IISC_IMCK << 16) | MUX_PB05D_IISC_IMCK) 232 #define GPIO_PB05D_IISC_IMCK _UL_(1 << 5) 233 #define PIN_PC14D_IISC_IMCK _L_(78) /**< \brief IISC signal: IMCK on PC14 mux D */ 234 #define MUX_PC14D_IISC_IMCK _L_(3) 235 #define PINMUX_PC14D_IISC_IMCK ((PIN_PC14D_IISC_IMCK << 16) | MUX_PC14D_IISC_IMCK) 236 #define GPIO_PC14D_IISC_IMCK _UL_(1 << 14) 237 #define PIN_PA31B_IISC_IMCK _L_(31) /**< \brief IISC signal: IMCK on PA31 mux B */ 238 #define MUX_PA31B_IISC_IMCK _L_(1) 239 #define PINMUX_PA31B_IISC_IMCK ((PIN_PA31B_IISC_IMCK << 16) | MUX_PA31B_IISC_IMCK) 240 #define GPIO_PA31B_IISC_IMCK _UL_(1 << 31) 241 #define PIN_PB02D_IISC_ISCK _L_(34) /**< \brief IISC signal: ISCK on PB02 mux D */ 242 #define MUX_PB02D_IISC_ISCK _L_(3) 243 #define PINMUX_PB02D_IISC_ISCK ((PIN_PB02D_IISC_ISCK << 16) | MUX_PB02D_IISC_ISCK) 244 #define GPIO_PB02D_IISC_ISCK _UL_(1 << 2) 245 #define PIN_PC09D_IISC_ISCK _L_(73) /**< \brief IISC signal: ISCK on PC09 mux D */ 246 #define MUX_PC09D_IISC_ISCK _L_(3) 247 #define PINMUX_PC09D_IISC_ISCK ((PIN_PC09D_IISC_ISCK << 16) | MUX_PC09D_IISC_ISCK) 248 #define GPIO_PC09D_IISC_ISCK _UL_(1 << 9) 249 #define PIN_PA27B_IISC_ISCK _L_(27) /**< \brief IISC signal: ISCK on PA27 mux B */ 250 #define MUX_PA27B_IISC_ISCK _L_(1) 251 #define PINMUX_PA27B_IISC_ISCK ((PIN_PA27B_IISC_ISCK << 16) | MUX_PA27B_IISC_ISCK) 252 #define GPIO_PA27B_IISC_ISCK _UL_(1 << 27) 253 #define PIN_PB03D_IISC_ISDI _L_(35) /**< \brief IISC signal: ISDI on PB03 mux D */ 254 #define MUX_PB03D_IISC_ISDI _L_(3) 255 #define PINMUX_PB03D_IISC_ISDI ((PIN_PB03D_IISC_ISDI << 16) | MUX_PB03D_IISC_ISDI) 256 #define GPIO_PB03D_IISC_ISDI _UL_(1 << 3) 257 #define PIN_PC10D_IISC_ISDI _L_(74) /**< \brief IISC signal: ISDI on PC10 mux D */ 258 #define MUX_PC10D_IISC_ISDI _L_(3) 259 #define PINMUX_PC10D_IISC_ISDI ((PIN_PC10D_IISC_ISDI << 16) | MUX_PC10D_IISC_ISDI) 260 #define GPIO_PC10D_IISC_ISDI _UL_(1 << 10) 261 #define PIN_PA28B_IISC_ISDI _L_(28) /**< \brief IISC signal: ISDI on PA28 mux B */ 262 #define MUX_PA28B_IISC_ISDI _L_(1) 263 #define PINMUX_PA28B_IISC_ISDI ((PIN_PA28B_IISC_ISDI << 16) | MUX_PA28B_IISC_ISDI) 264 #define GPIO_PA28B_IISC_ISDI _UL_(1 << 28) 265 #define PIN_PB04D_IISC_ISDO _L_(36) /**< \brief IISC signal: ISDO on PB04 mux D */ 266 #define MUX_PB04D_IISC_ISDO _L_(3) 267 #define PINMUX_PB04D_IISC_ISDO ((PIN_PB04D_IISC_ISDO << 16) | MUX_PB04D_IISC_ISDO) 268 #define GPIO_PB04D_IISC_ISDO _UL_(1 << 4) 269 #define PIN_PC13D_IISC_ISDO _L_(77) /**< \brief IISC signal: ISDO on PC13 mux D */ 270 #define MUX_PC13D_IISC_ISDO _L_(3) 271 #define PINMUX_PC13D_IISC_ISDO ((PIN_PC13D_IISC_ISDO << 16) | MUX_PC13D_IISC_ISDO) 272 #define GPIO_PC13D_IISC_ISDO _UL_(1 << 13) 273 #define PIN_PA30B_IISC_ISDO _L_(30) /**< \brief IISC signal: ISDO on PA30 mux B */ 274 #define MUX_PA30B_IISC_ISDO _L_(1) 275 #define PINMUX_PA30B_IISC_ISDO ((PIN_PA30B_IISC_ISDO << 16) | MUX_PA30B_IISC_ISDO) 276 #define GPIO_PA30B_IISC_ISDO _UL_(1 << 30) 277 #define PIN_PB06D_IISC_IWS _L_(38) /**< \brief IISC signal: IWS on PB06 mux D */ 278 #define MUX_PB06D_IISC_IWS _L_(3) 279 #define PINMUX_PB06D_IISC_IWS ((PIN_PB06D_IISC_IWS << 16) | MUX_PB06D_IISC_IWS) 280 #define GPIO_PB06D_IISC_IWS _UL_(1 << 6) 281 #define PIN_PC12D_IISC_IWS _L_(76) /**< \brief IISC signal: IWS on PC12 mux D */ 282 #define MUX_PC12D_IISC_IWS _L_(3) 283 #define PINMUX_PC12D_IISC_IWS ((PIN_PC12D_IISC_IWS << 16) | MUX_PC12D_IISC_IWS) 284 #define GPIO_PC12D_IISC_IWS _UL_(1 << 12) 285 #define PIN_PA29B_IISC_IWS _L_(29) /**< \brief IISC signal: IWS on PA29 mux B */ 286 #define MUX_PA29B_IISC_IWS _L_(1) 287 #define PINMUX_PA29B_IISC_IWS ((PIN_PA29B_IISC_IWS << 16) | MUX_PA29B_IISC_IWS) 288 #define GPIO_PA29B_IISC_IWS _UL_(1 << 29) 289 /* ========== GPIO definition for SPI peripheral ========== */ 290 #define PIN_PA03B_SPI_MISO _L_(3) /**< \brief SPI signal: MISO on PA03 mux B */ 291 #define MUX_PA03B_SPI_MISO _L_(1) 292 #define PINMUX_PA03B_SPI_MISO ((PIN_PA03B_SPI_MISO << 16) | MUX_PA03B_SPI_MISO) 293 #define GPIO_PA03B_SPI_MISO _UL_(1 << 3) 294 #define PIN_PB14B_SPI_MISO _L_(46) /**< \brief SPI signal: MISO on PB14 mux B */ 295 #define MUX_PB14B_SPI_MISO _L_(1) 296 #define PINMUX_PB14B_SPI_MISO ((PIN_PB14B_SPI_MISO << 16) | MUX_PB14B_SPI_MISO) 297 #define GPIO_PB14B_SPI_MISO _UL_(1 << 14) 298 #define PIN_PC28B_SPI_MISO _L_(92) /**< \brief SPI signal: MISO on PC28 mux B */ 299 #define MUX_PC28B_SPI_MISO _L_(1) 300 #define PINMUX_PC28B_SPI_MISO ((PIN_PC28B_SPI_MISO << 16) | MUX_PC28B_SPI_MISO) 301 #define GPIO_PC28B_SPI_MISO _UL_(1 << 28) 302 #define PIN_PA21A_SPI_MISO _L_(21) /**< \brief SPI signal: MISO on PA21 mux A */ 303 #define MUX_PA21A_SPI_MISO _L_(0) 304 #define PINMUX_PA21A_SPI_MISO ((PIN_PA21A_SPI_MISO << 16) | MUX_PA21A_SPI_MISO) 305 #define GPIO_PA21A_SPI_MISO _UL_(1 << 21) 306 #define PIN_PA27A_SPI_MISO _L_(27) /**< \brief SPI signal: MISO on PA27 mux A */ 307 #define MUX_PA27A_SPI_MISO _L_(0) 308 #define PINMUX_PA27A_SPI_MISO ((PIN_PA27A_SPI_MISO << 16) | MUX_PA27A_SPI_MISO) 309 #define GPIO_PA27A_SPI_MISO _UL_(1 << 27) 310 #define PIN_PC04A_SPI_MISO _L_(68) /**< \brief SPI signal: MISO on PC04 mux A */ 311 #define MUX_PC04A_SPI_MISO _L_(0) 312 #define PINMUX_PC04A_SPI_MISO ((PIN_PC04A_SPI_MISO << 16) | MUX_PC04A_SPI_MISO) 313 #define GPIO_PC04A_SPI_MISO _UL_(1 << 4) 314 #define PIN_PB15B_SPI_MOSI _L_(47) /**< \brief SPI signal: MOSI on PB15 mux B */ 315 #define MUX_PB15B_SPI_MOSI _L_(1) 316 #define PINMUX_PB15B_SPI_MOSI ((PIN_PB15B_SPI_MOSI << 16) | MUX_PB15B_SPI_MOSI) 317 #define GPIO_PB15B_SPI_MOSI _UL_(1 << 15) 318 #define PIN_PC29B_SPI_MOSI _L_(93) /**< \brief SPI signal: MOSI on PC29 mux B */ 319 #define MUX_PC29B_SPI_MOSI _L_(1) 320 #define PINMUX_PC29B_SPI_MOSI ((PIN_PC29B_SPI_MOSI << 16) | MUX_PC29B_SPI_MOSI) 321 #define GPIO_PC29B_SPI_MOSI _UL_(1 << 29) 322 #define PIN_PA22A_SPI_MOSI _L_(22) /**< \brief SPI signal: MOSI on PA22 mux A */ 323 #define MUX_PA22A_SPI_MOSI _L_(0) 324 #define PINMUX_PA22A_SPI_MOSI ((PIN_PA22A_SPI_MOSI << 16) | MUX_PA22A_SPI_MOSI) 325 #define GPIO_PA22A_SPI_MOSI _UL_(1 << 22) 326 #define PIN_PA28A_SPI_MOSI _L_(28) /**< \brief SPI signal: MOSI on PA28 mux A */ 327 #define MUX_PA28A_SPI_MOSI _L_(0) 328 #define PINMUX_PA28A_SPI_MOSI ((PIN_PA28A_SPI_MOSI << 16) | MUX_PA28A_SPI_MOSI) 329 #define GPIO_PA28A_SPI_MOSI _UL_(1 << 28) 330 #define PIN_PC05A_SPI_MOSI _L_(69) /**< \brief SPI signal: MOSI on PC05 mux A */ 331 #define MUX_PC05A_SPI_MOSI _L_(0) 332 #define PINMUX_PC05A_SPI_MOSI ((PIN_PC05A_SPI_MOSI << 16) | MUX_PC05A_SPI_MOSI) 333 #define GPIO_PC05A_SPI_MOSI _UL_(1 << 5) 334 #define PIN_PA02B_SPI_NPCS0 _L_(2) /**< \brief SPI signal: NPCS0 on PA02 mux B */ 335 #define MUX_PA02B_SPI_NPCS0 _L_(1) 336 #define PINMUX_PA02B_SPI_NPCS0 ((PIN_PA02B_SPI_NPCS0 << 16) | MUX_PA02B_SPI_NPCS0) 337 #define GPIO_PA02B_SPI_NPCS0 _UL_(1 << 2) 338 #define PIN_PC31B_SPI_NPCS0 _L_(95) /**< \brief SPI signal: NPCS0 on PC31 mux B */ 339 #define MUX_PC31B_SPI_NPCS0 _L_(1) 340 #define PINMUX_PC31B_SPI_NPCS0 ((PIN_PC31B_SPI_NPCS0 << 16) | MUX_PC31B_SPI_NPCS0) 341 #define GPIO_PC31B_SPI_NPCS0 _UL_(1 << 31) 342 #define PIN_PA24A_SPI_NPCS0 _L_(24) /**< \brief SPI signal: NPCS0 on PA24 mux A */ 343 #define MUX_PA24A_SPI_NPCS0 _L_(0) 344 #define PINMUX_PA24A_SPI_NPCS0 ((PIN_PA24A_SPI_NPCS0 << 16) | MUX_PA24A_SPI_NPCS0) 345 #define GPIO_PA24A_SPI_NPCS0 _UL_(1 << 24) 346 #define PIN_PA30A_SPI_NPCS0 _L_(30) /**< \brief SPI signal: NPCS0 on PA30 mux A */ 347 #define MUX_PA30A_SPI_NPCS0 _L_(0) 348 #define PINMUX_PA30A_SPI_NPCS0 ((PIN_PA30A_SPI_NPCS0 << 16) | MUX_PA30A_SPI_NPCS0) 349 #define GPIO_PA30A_SPI_NPCS0 _UL_(1 << 30) 350 #define PIN_PC03A_SPI_NPCS0 _L_(67) /**< \brief SPI signal: NPCS0 on PC03 mux A */ 351 #define MUX_PC03A_SPI_NPCS0 _L_(0) 352 #define PINMUX_PC03A_SPI_NPCS0 ((PIN_PC03A_SPI_NPCS0 << 16) | MUX_PC03A_SPI_NPCS0) 353 #define GPIO_PC03A_SPI_NPCS0 _UL_(1 << 3) 354 #define PIN_PA13C_SPI_NPCS1 _L_(13) /**< \brief SPI signal: NPCS1 on PA13 mux C */ 355 #define MUX_PA13C_SPI_NPCS1 _L_(2) 356 #define PINMUX_PA13C_SPI_NPCS1 ((PIN_PA13C_SPI_NPCS1 << 16) | MUX_PA13C_SPI_NPCS1) 357 #define GPIO_PA13C_SPI_NPCS1 _UL_(1 << 13) 358 #define PIN_PB13B_SPI_NPCS1 _L_(45) /**< \brief SPI signal: NPCS1 on PB13 mux B */ 359 #define MUX_PB13B_SPI_NPCS1 _L_(1) 360 #define PINMUX_PB13B_SPI_NPCS1 ((PIN_PB13B_SPI_NPCS1 << 16) | MUX_PB13B_SPI_NPCS1) 361 #define GPIO_PB13B_SPI_NPCS1 _UL_(1 << 13) 362 #define PIN_PA31A_SPI_NPCS1 _L_(31) /**< \brief SPI signal: NPCS1 on PA31 mux A */ 363 #define MUX_PA31A_SPI_NPCS1 _L_(0) 364 #define PINMUX_PA31A_SPI_NPCS1 ((PIN_PA31A_SPI_NPCS1 << 16) | MUX_PA31A_SPI_NPCS1) 365 #define GPIO_PA31A_SPI_NPCS1 _UL_(1 << 31) 366 #define PIN_PC02A_SPI_NPCS1 _L_(66) /**< \brief SPI signal: NPCS1 on PC02 mux A */ 367 #define MUX_PC02A_SPI_NPCS1 _L_(0) 368 #define PINMUX_PC02A_SPI_NPCS1 ((PIN_PC02A_SPI_NPCS1 << 16) | MUX_PC02A_SPI_NPCS1) 369 #define GPIO_PC02A_SPI_NPCS1 _UL_(1 << 2) 370 #define PIN_PA14C_SPI_NPCS2 _L_(14) /**< \brief SPI signal: NPCS2 on PA14 mux C */ 371 #define MUX_PA14C_SPI_NPCS2 _L_(2) 372 #define PINMUX_PA14C_SPI_NPCS2 ((PIN_PA14C_SPI_NPCS2 << 16) | MUX_PA14C_SPI_NPCS2) 373 #define GPIO_PA14C_SPI_NPCS2 _UL_(1 << 14) 374 #define PIN_PB11B_SPI_NPCS2 _L_(43) /**< \brief SPI signal: NPCS2 on PB11 mux B */ 375 #define MUX_PB11B_SPI_NPCS2 _L_(1) 376 #define PINMUX_PB11B_SPI_NPCS2 ((PIN_PB11B_SPI_NPCS2 << 16) | MUX_PB11B_SPI_NPCS2) 377 #define GPIO_PB11B_SPI_NPCS2 _UL_(1 << 11) 378 #define PIN_PC00A_SPI_NPCS2 _L_(64) /**< \brief SPI signal: NPCS2 on PC00 mux A */ 379 #define MUX_PC00A_SPI_NPCS2 _L_(0) 380 #define PINMUX_PC00A_SPI_NPCS2 ((PIN_PC00A_SPI_NPCS2 << 16) | MUX_PC00A_SPI_NPCS2) 381 #define GPIO_PC00A_SPI_NPCS2 _UL_(1 << 0) 382 #define PIN_PA15C_SPI_NPCS3 _L_(15) /**< \brief SPI signal: NPCS3 on PA15 mux C */ 383 #define MUX_PA15C_SPI_NPCS3 _L_(2) 384 #define PINMUX_PA15C_SPI_NPCS3 ((PIN_PA15C_SPI_NPCS3 << 16) | MUX_PA15C_SPI_NPCS3) 385 #define GPIO_PA15C_SPI_NPCS3 _UL_(1 << 15) 386 #define PIN_PB12B_SPI_NPCS3 _L_(44) /**< \brief SPI signal: NPCS3 on PB12 mux B */ 387 #define MUX_PB12B_SPI_NPCS3 _L_(1) 388 #define PINMUX_PB12B_SPI_NPCS3 ((PIN_PB12B_SPI_NPCS3 << 16) | MUX_PB12B_SPI_NPCS3) 389 #define GPIO_PB12B_SPI_NPCS3 _UL_(1 << 12) 390 #define PIN_PC01A_SPI_NPCS3 _L_(65) /**< \brief SPI signal: NPCS3 on PC01 mux A */ 391 #define MUX_PC01A_SPI_NPCS3 _L_(0) 392 #define PINMUX_PC01A_SPI_NPCS3 ((PIN_PC01A_SPI_NPCS3 << 16) | MUX_PC01A_SPI_NPCS3) 393 #define GPIO_PC01A_SPI_NPCS3 _UL_(1 << 1) 394 #define PIN_PC30B_SPI_SCK _L_(94) /**< \brief SPI signal: SCK on PC30 mux B */ 395 #define MUX_PC30B_SPI_SCK _L_(1) 396 #define PINMUX_PC30B_SPI_SCK ((PIN_PC30B_SPI_SCK << 16) | MUX_PC30B_SPI_SCK) 397 #define GPIO_PC30B_SPI_SCK _UL_(1 << 30) 398 #define PIN_PA23A_SPI_SCK _L_(23) /**< \brief SPI signal: SCK on PA23 mux A */ 399 #define MUX_PA23A_SPI_SCK _L_(0) 400 #define PINMUX_PA23A_SPI_SCK ((PIN_PA23A_SPI_SCK << 16) | MUX_PA23A_SPI_SCK) 401 #define GPIO_PA23A_SPI_SCK _UL_(1 << 23) 402 #define PIN_PA29A_SPI_SCK _L_(29) /**< \brief SPI signal: SCK on PA29 mux A */ 403 #define MUX_PA29A_SPI_SCK _L_(0) 404 #define PINMUX_PA29A_SPI_SCK ((PIN_PA29A_SPI_SCK << 16) | MUX_PA29A_SPI_SCK) 405 #define GPIO_PA29A_SPI_SCK _UL_(1 << 29) 406 #define PIN_PC06A_SPI_SCK _L_(70) /**< \brief SPI signal: SCK on PC06 mux A */ 407 #define MUX_PC06A_SPI_SCK _L_(0) 408 #define PINMUX_PC06A_SPI_SCK ((PIN_PC06A_SPI_SCK << 16) | MUX_PC06A_SPI_SCK) 409 #define GPIO_PC06A_SPI_SCK _UL_(1 << 6) 410 /* ========== GPIO definition for TC0 peripheral ========== */ 411 #define PIN_PB07D_TC0_A0 _L_(39) /**< \brief TC0 signal: A0 on PB07 mux D */ 412 #define MUX_PB07D_TC0_A0 _L_(3) 413 #define PINMUX_PB07D_TC0_A0 ((PIN_PB07D_TC0_A0 << 16) | MUX_PB07D_TC0_A0) 414 #define GPIO_PB07D_TC0_A0 _UL_(1 << 7) 415 #define PIN_PA08B_TC0_A0 _L_(8) /**< \brief TC0 signal: A0 on PA08 mux B */ 416 #define MUX_PA08B_TC0_A0 _L_(1) 417 #define PINMUX_PA08B_TC0_A0 ((PIN_PA08B_TC0_A0 << 16) | MUX_PA08B_TC0_A0) 418 #define GPIO_PA08B_TC0_A0 _UL_(1 << 8) 419 #define PIN_PB09D_TC0_A1 _L_(41) /**< \brief TC0 signal: A1 on PB09 mux D */ 420 #define MUX_PB09D_TC0_A1 _L_(3) 421 #define PINMUX_PB09D_TC0_A1 ((PIN_PB09D_TC0_A1 << 16) | MUX_PB09D_TC0_A1) 422 #define GPIO_PB09D_TC0_A1 _UL_(1 << 9) 423 #define PIN_PA10B_TC0_A1 _L_(10) /**< \brief TC0 signal: A1 on PA10 mux B */ 424 #define MUX_PA10B_TC0_A1 _L_(1) 425 #define PINMUX_PA10B_TC0_A1 ((PIN_PA10B_TC0_A1 << 16) | MUX_PA10B_TC0_A1) 426 #define GPIO_PA10B_TC0_A1 _UL_(1 << 10) 427 #define PIN_PB11D_TC0_A2 _L_(43) /**< \brief TC0 signal: A2 on PB11 mux D */ 428 #define MUX_PB11D_TC0_A2 _L_(3) 429 #define PINMUX_PB11D_TC0_A2 ((PIN_PB11D_TC0_A2 << 16) | MUX_PB11D_TC0_A2) 430 #define GPIO_PB11D_TC0_A2 _UL_(1 << 11) 431 #define PIN_PA12B_TC0_A2 _L_(12) /**< \brief TC0 signal: A2 on PA12 mux B */ 432 #define MUX_PA12B_TC0_A2 _L_(1) 433 #define PINMUX_PA12B_TC0_A2 ((PIN_PA12B_TC0_A2 << 16) | MUX_PA12B_TC0_A2) 434 #define GPIO_PA12B_TC0_A2 _UL_(1 << 12) 435 #define PIN_PB08D_TC0_B0 _L_(40) /**< \brief TC0 signal: B0 on PB08 mux D */ 436 #define MUX_PB08D_TC0_B0 _L_(3) 437 #define PINMUX_PB08D_TC0_B0 ((PIN_PB08D_TC0_B0 << 16) | MUX_PB08D_TC0_B0) 438 #define GPIO_PB08D_TC0_B0 _UL_(1 << 8) 439 #define PIN_PA09B_TC0_B0 _L_(9) /**< \brief TC0 signal: B0 on PA09 mux B */ 440 #define MUX_PA09B_TC0_B0 _L_(1) 441 #define PINMUX_PA09B_TC0_B0 ((PIN_PA09B_TC0_B0 << 16) | MUX_PA09B_TC0_B0) 442 #define GPIO_PA09B_TC0_B0 _UL_(1 << 9) 443 #define PIN_PB10D_TC0_B1 _L_(42) /**< \brief TC0 signal: B1 on PB10 mux D */ 444 #define MUX_PB10D_TC0_B1 _L_(3) 445 #define PINMUX_PB10D_TC0_B1 ((PIN_PB10D_TC0_B1 << 16) | MUX_PB10D_TC0_B1) 446 #define GPIO_PB10D_TC0_B1 _UL_(1 << 10) 447 #define PIN_PA11B_TC0_B1 _L_(11) /**< \brief TC0 signal: B1 on PA11 mux B */ 448 #define MUX_PA11B_TC0_B1 _L_(1) 449 #define PINMUX_PA11B_TC0_B1 ((PIN_PA11B_TC0_B1 << 16) | MUX_PA11B_TC0_B1) 450 #define GPIO_PA11B_TC0_B1 _UL_(1 << 11) 451 #define PIN_PB12D_TC0_B2 _L_(44) /**< \brief TC0 signal: B2 on PB12 mux D */ 452 #define MUX_PB12D_TC0_B2 _L_(3) 453 #define PINMUX_PB12D_TC0_B2 ((PIN_PB12D_TC0_B2 << 16) | MUX_PB12D_TC0_B2) 454 #define GPIO_PB12D_TC0_B2 _UL_(1 << 12) 455 #define PIN_PA13B_TC0_B2 _L_(13) /**< \brief TC0 signal: B2 on PA13 mux B */ 456 #define MUX_PA13B_TC0_B2 _L_(1) 457 #define PINMUX_PA13B_TC0_B2 ((PIN_PA13B_TC0_B2 << 16) | MUX_PA13B_TC0_B2) 458 #define GPIO_PA13B_TC0_B2 _UL_(1 << 13) 459 #define PIN_PB13D_TC0_CLK0 _L_(45) /**< \brief TC0 signal: CLK0 on PB13 mux D */ 460 #define MUX_PB13D_TC0_CLK0 _L_(3) 461 #define PINMUX_PB13D_TC0_CLK0 ((PIN_PB13D_TC0_CLK0 << 16) | MUX_PB13D_TC0_CLK0) 462 #define GPIO_PB13D_TC0_CLK0 _UL_(1 << 13) 463 #define PIN_PA14B_TC0_CLK0 _L_(14) /**< \brief TC0 signal: CLK0 on PA14 mux B */ 464 #define MUX_PA14B_TC0_CLK0 _L_(1) 465 #define PINMUX_PA14B_TC0_CLK0 ((PIN_PA14B_TC0_CLK0 << 16) | MUX_PA14B_TC0_CLK0) 466 #define GPIO_PA14B_TC0_CLK0 _UL_(1 << 14) 467 #define PIN_PB14D_TC0_CLK1 _L_(46) /**< \brief TC0 signal: CLK1 on PB14 mux D */ 468 #define MUX_PB14D_TC0_CLK1 _L_(3) 469 #define PINMUX_PB14D_TC0_CLK1 ((PIN_PB14D_TC0_CLK1 << 16) | MUX_PB14D_TC0_CLK1) 470 #define GPIO_PB14D_TC0_CLK1 _UL_(1 << 14) 471 #define PIN_PA15B_TC0_CLK1 _L_(15) /**< \brief TC0 signal: CLK1 on PA15 mux B */ 472 #define MUX_PA15B_TC0_CLK1 _L_(1) 473 #define PINMUX_PA15B_TC0_CLK1 ((PIN_PA15B_TC0_CLK1 << 16) | MUX_PA15B_TC0_CLK1) 474 #define GPIO_PA15B_TC0_CLK1 _UL_(1 << 15) 475 #define PIN_PB15D_TC0_CLK2 _L_(47) /**< \brief TC0 signal: CLK2 on PB15 mux D */ 476 #define MUX_PB15D_TC0_CLK2 _L_(3) 477 #define PINMUX_PB15D_TC0_CLK2 ((PIN_PB15D_TC0_CLK2 << 16) | MUX_PB15D_TC0_CLK2) 478 #define GPIO_PB15D_TC0_CLK2 _UL_(1 << 15) 479 #define PIN_PA16B_TC0_CLK2 _L_(16) /**< \brief TC0 signal: CLK2 on PA16 mux B */ 480 #define MUX_PA16B_TC0_CLK2 _L_(1) 481 #define PINMUX_PA16B_TC0_CLK2 ((PIN_PA16B_TC0_CLK2 << 16) | MUX_PA16B_TC0_CLK2) 482 #define GPIO_PA16B_TC0_CLK2 _UL_(1 << 16) 483 /* ========== GPIO definition for TC1 peripheral ========== */ 484 #define PIN_PC00D_TC1_A0 _L_(64) /**< \brief TC1 signal: A0 on PC00 mux D */ 485 #define MUX_PC00D_TC1_A0 _L_(3) 486 #define PINMUX_PC00D_TC1_A0 ((PIN_PC00D_TC1_A0 << 16) | MUX_PC00D_TC1_A0) 487 #define GPIO_PC00D_TC1_A0 _UL_(1 << 0) 488 #define PIN_PC15A_TC1_A0 _L_(79) /**< \brief TC1 signal: A0 on PC15 mux A */ 489 #define MUX_PC15A_TC1_A0 _L_(0) 490 #define PINMUX_PC15A_TC1_A0 ((PIN_PC15A_TC1_A0 << 16) | MUX_PC15A_TC1_A0) 491 #define GPIO_PC15A_TC1_A0 _UL_(1 << 15) 492 #define PIN_PC02D_TC1_A1 _L_(66) /**< \brief TC1 signal: A1 on PC02 mux D */ 493 #define MUX_PC02D_TC1_A1 _L_(3) 494 #define PINMUX_PC02D_TC1_A1 ((PIN_PC02D_TC1_A1 << 16) | MUX_PC02D_TC1_A1) 495 #define GPIO_PC02D_TC1_A1 _UL_(1 << 2) 496 #define PIN_PC17A_TC1_A1 _L_(81) /**< \brief TC1 signal: A1 on PC17 mux A */ 497 #define MUX_PC17A_TC1_A1 _L_(0) 498 #define PINMUX_PC17A_TC1_A1 ((PIN_PC17A_TC1_A1 << 16) | MUX_PC17A_TC1_A1) 499 #define GPIO_PC17A_TC1_A1 _UL_(1 << 17) 500 #define PIN_PC04D_TC1_A2 _L_(68) /**< \brief TC1 signal: A2 on PC04 mux D */ 501 #define MUX_PC04D_TC1_A2 _L_(3) 502 #define PINMUX_PC04D_TC1_A2 ((PIN_PC04D_TC1_A2 << 16) | MUX_PC04D_TC1_A2) 503 #define GPIO_PC04D_TC1_A2 _UL_(1 << 4) 504 #define PIN_PC19A_TC1_A2 _L_(83) /**< \brief TC1 signal: A2 on PC19 mux A */ 505 #define MUX_PC19A_TC1_A2 _L_(0) 506 #define PINMUX_PC19A_TC1_A2 ((PIN_PC19A_TC1_A2 << 16) | MUX_PC19A_TC1_A2) 507 #define GPIO_PC19A_TC1_A2 _UL_(1 << 19) 508 #define PIN_PC01D_TC1_B0 _L_(65) /**< \brief TC1 signal: B0 on PC01 mux D */ 509 #define MUX_PC01D_TC1_B0 _L_(3) 510 #define PINMUX_PC01D_TC1_B0 ((PIN_PC01D_TC1_B0 << 16) | MUX_PC01D_TC1_B0) 511 #define GPIO_PC01D_TC1_B0 _UL_(1 << 1) 512 #define PIN_PC16A_TC1_B0 _L_(80) /**< \brief TC1 signal: B0 on PC16 mux A */ 513 #define MUX_PC16A_TC1_B0 _L_(0) 514 #define PINMUX_PC16A_TC1_B0 ((PIN_PC16A_TC1_B0 << 16) | MUX_PC16A_TC1_B0) 515 #define GPIO_PC16A_TC1_B0 _UL_(1 << 16) 516 #define PIN_PC03D_TC1_B1 _L_(67) /**< \brief TC1 signal: B1 on PC03 mux D */ 517 #define MUX_PC03D_TC1_B1 _L_(3) 518 #define PINMUX_PC03D_TC1_B1 ((PIN_PC03D_TC1_B1 << 16) | MUX_PC03D_TC1_B1) 519 #define GPIO_PC03D_TC1_B1 _UL_(1 << 3) 520 #define PIN_PC18A_TC1_B1 _L_(82) /**< \brief TC1 signal: B1 on PC18 mux A */ 521 #define MUX_PC18A_TC1_B1 _L_(0) 522 #define PINMUX_PC18A_TC1_B1 ((PIN_PC18A_TC1_B1 << 16) | MUX_PC18A_TC1_B1) 523 #define GPIO_PC18A_TC1_B1 _UL_(1 << 18) 524 #define PIN_PC05D_TC1_B2 _L_(69) /**< \brief TC1 signal: B2 on PC05 mux D */ 525 #define MUX_PC05D_TC1_B2 _L_(3) 526 #define PINMUX_PC05D_TC1_B2 ((PIN_PC05D_TC1_B2 << 16) | MUX_PC05D_TC1_B2) 527 #define GPIO_PC05D_TC1_B2 _UL_(1 << 5) 528 #define PIN_PC20A_TC1_B2 _L_(84) /**< \brief TC1 signal: B2 on PC20 mux A */ 529 #define MUX_PC20A_TC1_B2 _L_(0) 530 #define PINMUX_PC20A_TC1_B2 ((PIN_PC20A_TC1_B2 << 16) | MUX_PC20A_TC1_B2) 531 #define GPIO_PC20A_TC1_B2 _UL_(1 << 20) 532 #define PIN_PC06D_TC1_CLK0 _L_(70) /**< \brief TC1 signal: CLK0 on PC06 mux D */ 533 #define MUX_PC06D_TC1_CLK0 _L_(3) 534 #define PINMUX_PC06D_TC1_CLK0 ((PIN_PC06D_TC1_CLK0 << 16) | MUX_PC06D_TC1_CLK0) 535 #define GPIO_PC06D_TC1_CLK0 _UL_(1 << 6) 536 #define PIN_PC21A_TC1_CLK0 _L_(85) /**< \brief TC1 signal: CLK0 on PC21 mux A */ 537 #define MUX_PC21A_TC1_CLK0 _L_(0) 538 #define PINMUX_PC21A_TC1_CLK0 ((PIN_PC21A_TC1_CLK0 << 16) | MUX_PC21A_TC1_CLK0) 539 #define GPIO_PC21A_TC1_CLK0 _UL_(1 << 21) 540 #define PIN_PC07D_TC1_CLK1 _L_(71) /**< \brief TC1 signal: CLK1 on PC07 mux D */ 541 #define MUX_PC07D_TC1_CLK1 _L_(3) 542 #define PINMUX_PC07D_TC1_CLK1 ((PIN_PC07D_TC1_CLK1 << 16) | MUX_PC07D_TC1_CLK1) 543 #define GPIO_PC07D_TC1_CLK1 _UL_(1 << 7) 544 #define PIN_PC22A_TC1_CLK1 _L_(86) /**< \brief TC1 signal: CLK1 on PC22 mux A */ 545 #define MUX_PC22A_TC1_CLK1 _L_(0) 546 #define PINMUX_PC22A_TC1_CLK1 ((PIN_PC22A_TC1_CLK1 << 16) | MUX_PC22A_TC1_CLK1) 547 #define GPIO_PC22A_TC1_CLK1 _UL_(1 << 22) 548 #define PIN_PC08D_TC1_CLK2 _L_(72) /**< \brief TC1 signal: CLK2 on PC08 mux D */ 549 #define MUX_PC08D_TC1_CLK2 _L_(3) 550 #define PINMUX_PC08D_TC1_CLK2 ((PIN_PC08D_TC1_CLK2 << 16) | MUX_PC08D_TC1_CLK2) 551 #define GPIO_PC08D_TC1_CLK2 _UL_(1 << 8) 552 #define PIN_PC23A_TC1_CLK2 _L_(87) /**< \brief TC1 signal: CLK2 on PC23 mux A */ 553 #define MUX_PC23A_TC1_CLK2 _L_(0) 554 #define PINMUX_PC23A_TC1_CLK2 ((PIN_PC23A_TC1_CLK2 << 16) | MUX_PC23A_TC1_CLK2) 555 #define GPIO_PC23A_TC1_CLK2 _UL_(1 << 23) 556 /* ========== GPIO definition for USART0 peripheral ========== */ 557 #define PIN_PA04B_USART0_CLK _L_(4) /**< \brief USART0 signal: CLK on PA04 mux B */ 558 #define MUX_PA04B_USART0_CLK _L_(1) 559 #define PINMUX_PA04B_USART0_CLK ((PIN_PA04B_USART0_CLK << 16) | MUX_PA04B_USART0_CLK) 560 #define GPIO_PA04B_USART0_CLK _UL_(1 << 4) 561 #define PIN_PC00B_USART0_CLK _L_(64) /**< \brief USART0 signal: CLK on PC00 mux B */ 562 #define MUX_PC00B_USART0_CLK _L_(1) 563 #define PINMUX_PC00B_USART0_CLK ((PIN_PC00B_USART0_CLK << 16) | MUX_PC00B_USART0_CLK) 564 #define GPIO_PC00B_USART0_CLK _UL_(1 << 0) 565 #define PIN_PA10A_USART0_CLK _L_(10) /**< \brief USART0 signal: CLK on PA10 mux A */ 566 #define MUX_PA10A_USART0_CLK _L_(0) 567 #define PINMUX_PA10A_USART0_CLK ((PIN_PA10A_USART0_CLK << 16) | MUX_PA10A_USART0_CLK) 568 #define GPIO_PA10A_USART0_CLK _UL_(1 << 10) 569 #define PIN_PB13A_USART0_CLK _L_(45) /**< \brief USART0 signal: CLK on PB13 mux A */ 570 #define MUX_PB13A_USART0_CLK _L_(0) 571 #define PINMUX_PB13A_USART0_CLK ((PIN_PB13A_USART0_CLK << 16) | MUX_PB13A_USART0_CLK) 572 #define GPIO_PB13A_USART0_CLK _UL_(1 << 13) 573 #define PIN_PC02B_USART0_CTS _L_(66) /**< \brief USART0 signal: CTS on PC02 mux B */ 574 #define MUX_PC02B_USART0_CTS _L_(1) 575 #define PINMUX_PC02B_USART0_CTS ((PIN_PC02B_USART0_CTS << 16) | MUX_PC02B_USART0_CTS) 576 #define GPIO_PC02B_USART0_CTS _UL_(1 << 2) 577 #define PIN_PA09A_USART0_CTS _L_(9) /**< \brief USART0 signal: CTS on PA09 mux A */ 578 #define MUX_PA09A_USART0_CTS _L_(0) 579 #define PINMUX_PA09A_USART0_CTS ((PIN_PA09A_USART0_CTS << 16) | MUX_PA09A_USART0_CTS) 580 #define GPIO_PA09A_USART0_CTS _UL_(1 << 9) 581 #define PIN_PB11A_USART0_CTS _L_(43) /**< \brief USART0 signal: CTS on PB11 mux A */ 582 #define MUX_PB11A_USART0_CTS _L_(0) 583 #define PINMUX_PB11A_USART0_CTS ((PIN_PB11A_USART0_CTS << 16) | MUX_PB11A_USART0_CTS) 584 #define GPIO_PB11A_USART0_CTS _UL_(1 << 11) 585 #define PIN_PA06B_USART0_RTS _L_(6) /**< \brief USART0 signal: RTS on PA06 mux B */ 586 #define MUX_PA06B_USART0_RTS _L_(1) 587 #define PINMUX_PA06B_USART0_RTS ((PIN_PA06B_USART0_RTS << 16) | MUX_PA06B_USART0_RTS) 588 #define GPIO_PA06B_USART0_RTS _UL_(1 << 6) 589 #define PIN_PC01B_USART0_RTS _L_(65) /**< \brief USART0 signal: RTS on PC01 mux B */ 590 #define MUX_PC01B_USART0_RTS _L_(1) 591 #define PINMUX_PC01B_USART0_RTS ((PIN_PC01B_USART0_RTS << 16) | MUX_PC01B_USART0_RTS) 592 #define GPIO_PC01B_USART0_RTS _UL_(1 << 1) 593 #define PIN_PA08A_USART0_RTS _L_(8) /**< \brief USART0 signal: RTS on PA08 mux A */ 594 #define MUX_PA08A_USART0_RTS _L_(0) 595 #define PINMUX_PA08A_USART0_RTS ((PIN_PA08A_USART0_RTS << 16) | MUX_PA08A_USART0_RTS) 596 #define GPIO_PA08A_USART0_RTS _UL_(1 << 8) 597 #define PIN_PB12A_USART0_RTS _L_(44) /**< \brief USART0 signal: RTS on PB12 mux A */ 598 #define MUX_PB12A_USART0_RTS _L_(0) 599 #define PINMUX_PB12A_USART0_RTS ((PIN_PB12A_USART0_RTS << 16) | MUX_PB12A_USART0_RTS) 600 #define GPIO_PB12A_USART0_RTS _UL_(1 << 12) 601 #define PIN_PC02C_USART0_RXD _L_(66) /**< \brief USART0 signal: RXD on PC02 mux C */ 602 #define MUX_PC02C_USART0_RXD _L_(2) 603 #define PINMUX_PC02C_USART0_RXD ((PIN_PC02C_USART0_RXD << 16) | MUX_PC02C_USART0_RXD) 604 #define GPIO_PC02C_USART0_RXD _UL_(1 << 2) 605 #define PIN_PA05B_USART0_RXD _L_(5) /**< \brief USART0 signal: RXD on PA05 mux B */ 606 #define MUX_PA05B_USART0_RXD _L_(1) 607 #define PINMUX_PA05B_USART0_RXD ((PIN_PA05B_USART0_RXD << 16) | MUX_PA05B_USART0_RXD) 608 #define GPIO_PA05B_USART0_RXD _UL_(1 << 5) 609 #define PIN_PB00B_USART0_RXD _L_(32) /**< \brief USART0 signal: RXD on PB00 mux B */ 610 #define MUX_PB00B_USART0_RXD _L_(1) 611 #define PINMUX_PB00B_USART0_RXD ((PIN_PB00B_USART0_RXD << 16) | MUX_PB00B_USART0_RXD) 612 #define GPIO_PB00B_USART0_RXD _UL_(1 << 0) 613 #define PIN_PA11A_USART0_RXD _L_(11) /**< \brief USART0 signal: RXD on PA11 mux A */ 614 #define MUX_PA11A_USART0_RXD _L_(0) 615 #define PINMUX_PA11A_USART0_RXD ((PIN_PA11A_USART0_RXD << 16) | MUX_PA11A_USART0_RXD) 616 #define GPIO_PA11A_USART0_RXD _UL_(1 << 11) 617 #define PIN_PB14A_USART0_RXD _L_(46) /**< \brief USART0 signal: RXD on PB14 mux A */ 618 #define MUX_PB14A_USART0_RXD _L_(0) 619 #define PINMUX_PB14A_USART0_RXD ((PIN_PB14A_USART0_RXD << 16) | MUX_PB14A_USART0_RXD) 620 #define GPIO_PB14A_USART0_RXD _UL_(1 << 14) 621 #define PIN_PC03C_USART0_TXD _L_(67) /**< \brief USART0 signal: TXD on PC03 mux C */ 622 #define MUX_PC03C_USART0_TXD _L_(2) 623 #define PINMUX_PC03C_USART0_TXD ((PIN_PC03C_USART0_TXD << 16) | MUX_PC03C_USART0_TXD) 624 #define GPIO_PC03C_USART0_TXD _UL_(1 << 3) 625 #define PIN_PA07B_USART0_TXD _L_(7) /**< \brief USART0 signal: TXD on PA07 mux B */ 626 #define MUX_PA07B_USART0_TXD _L_(1) 627 #define PINMUX_PA07B_USART0_TXD ((PIN_PA07B_USART0_TXD << 16) | MUX_PA07B_USART0_TXD) 628 #define GPIO_PA07B_USART0_TXD _UL_(1 << 7) 629 #define PIN_PB01B_USART0_TXD _L_(33) /**< \brief USART0 signal: TXD on PB01 mux B */ 630 #define MUX_PB01B_USART0_TXD _L_(1) 631 #define PINMUX_PB01B_USART0_TXD ((PIN_PB01B_USART0_TXD << 16) | MUX_PB01B_USART0_TXD) 632 #define GPIO_PB01B_USART0_TXD _UL_(1 << 1) 633 #define PIN_PA12A_USART0_TXD _L_(12) /**< \brief USART0 signal: TXD on PA12 mux A */ 634 #define MUX_PA12A_USART0_TXD _L_(0) 635 #define PINMUX_PA12A_USART0_TXD ((PIN_PA12A_USART0_TXD << 16) | MUX_PA12A_USART0_TXD) 636 #define GPIO_PA12A_USART0_TXD _UL_(1 << 12) 637 #define PIN_PB15A_USART0_TXD _L_(47) /**< \brief USART0 signal: TXD on PB15 mux A */ 638 #define MUX_PB15A_USART0_TXD _L_(0) 639 #define PINMUX_PB15A_USART0_TXD ((PIN_PB15A_USART0_TXD << 16) | MUX_PB15A_USART0_TXD) 640 #define GPIO_PB15A_USART0_TXD _UL_(1 << 15) 641 /* ========== GPIO definition for USART1 peripheral ========== */ 642 #define PIN_PB03B_USART1_CLK _L_(35) /**< \brief USART1 signal: CLK on PB03 mux B */ 643 #define MUX_PB03B_USART1_CLK _L_(1) 644 #define PINMUX_PB03B_USART1_CLK ((PIN_PB03B_USART1_CLK << 16) | MUX_PB03B_USART1_CLK) 645 #define GPIO_PB03B_USART1_CLK _UL_(1 << 3) 646 #define PIN_PA14A_USART1_CLK _L_(14) /**< \brief USART1 signal: CLK on PA14 mux A */ 647 #define MUX_PA14A_USART1_CLK _L_(0) 648 #define PINMUX_PA14A_USART1_CLK ((PIN_PA14A_USART1_CLK << 16) | MUX_PA14A_USART1_CLK) 649 #define GPIO_PA14A_USART1_CLK _UL_(1 << 14) 650 #define PIN_PC25A_USART1_CLK _L_(89) /**< \brief USART1 signal: CLK on PC25 mux A */ 651 #define MUX_PC25A_USART1_CLK _L_(0) 652 #define PINMUX_PC25A_USART1_CLK ((PIN_PC25A_USART1_CLK << 16) | MUX_PC25A_USART1_CLK) 653 #define GPIO_PC25A_USART1_CLK _UL_(1 << 25) 654 #define PIN_PA21B_USART1_CTS _L_(21) /**< \brief USART1 signal: CTS on PA21 mux B */ 655 #define MUX_PA21B_USART1_CTS _L_(1) 656 #define PINMUX_PA21B_USART1_CTS ((PIN_PA21B_USART1_CTS << 16) | MUX_PA21B_USART1_CTS) 657 #define GPIO_PA21B_USART1_CTS _UL_(1 << 21) 658 #define PIN_PB02B_USART1_RTS _L_(34) /**< \brief USART1 signal: RTS on PB02 mux B */ 659 #define MUX_PB02B_USART1_RTS _L_(1) 660 #define PINMUX_PB02B_USART1_RTS ((PIN_PB02B_USART1_RTS << 16) | MUX_PB02B_USART1_RTS) 661 #define GPIO_PB02B_USART1_RTS _UL_(1 << 2) 662 #define PIN_PA13A_USART1_RTS _L_(13) /**< \brief USART1 signal: RTS on PA13 mux A */ 663 #define MUX_PA13A_USART1_RTS _L_(0) 664 #define PINMUX_PA13A_USART1_RTS ((PIN_PA13A_USART1_RTS << 16) | MUX_PA13A_USART1_RTS) 665 #define GPIO_PA13A_USART1_RTS _UL_(1 << 13) 666 #define PIN_PC24A_USART1_RTS _L_(88) /**< \brief USART1 signal: RTS on PC24 mux A */ 667 #define MUX_PC24A_USART1_RTS _L_(0) 668 #define PINMUX_PC24A_USART1_RTS ((PIN_PC24A_USART1_RTS << 16) | MUX_PC24A_USART1_RTS) 669 #define GPIO_PC24A_USART1_RTS _UL_(1 << 24) 670 #define PIN_PB04B_USART1_RXD _L_(36) /**< \brief USART1 signal: RXD on PB04 mux B */ 671 #define MUX_PB04B_USART1_RXD _L_(1) 672 #define PINMUX_PB04B_USART1_RXD ((PIN_PB04B_USART1_RXD << 16) | MUX_PB04B_USART1_RXD) 673 #define GPIO_PB04B_USART1_RXD _UL_(1 << 4) 674 #define PIN_PA15A_USART1_RXD _L_(15) /**< \brief USART1 signal: RXD on PA15 mux A */ 675 #define MUX_PA15A_USART1_RXD _L_(0) 676 #define PINMUX_PA15A_USART1_RXD ((PIN_PA15A_USART1_RXD << 16) | MUX_PA15A_USART1_RXD) 677 #define GPIO_PA15A_USART1_RXD _UL_(1 << 15) 678 #define PIN_PC26A_USART1_RXD _L_(90) /**< \brief USART1 signal: RXD on PC26 mux A */ 679 #define MUX_PC26A_USART1_RXD _L_(0) 680 #define PINMUX_PC26A_USART1_RXD ((PIN_PC26A_USART1_RXD << 16) | MUX_PC26A_USART1_RXD) 681 #define GPIO_PC26A_USART1_RXD _UL_(1 << 26) 682 #define PIN_PB05B_USART1_TXD _L_(37) /**< \brief USART1 signal: TXD on PB05 mux B */ 683 #define MUX_PB05B_USART1_TXD _L_(1) 684 #define PINMUX_PB05B_USART1_TXD ((PIN_PB05B_USART1_TXD << 16) | MUX_PB05B_USART1_TXD) 685 #define GPIO_PB05B_USART1_TXD _UL_(1 << 5) 686 #define PIN_PA16A_USART1_TXD _L_(16) /**< \brief USART1 signal: TXD on PA16 mux A */ 687 #define MUX_PA16A_USART1_TXD _L_(0) 688 #define PINMUX_PA16A_USART1_TXD ((PIN_PA16A_USART1_TXD << 16) | MUX_PA16A_USART1_TXD) 689 #define GPIO_PA16A_USART1_TXD _UL_(1 << 16) 690 #define PIN_PC27A_USART1_TXD _L_(91) /**< \brief USART1 signal: TXD on PC27 mux A */ 691 #define MUX_PC27A_USART1_TXD _L_(0) 692 #define PINMUX_PC27A_USART1_TXD ((PIN_PC27A_USART1_TXD << 16) | MUX_PC27A_USART1_TXD) 693 #define GPIO_PC27A_USART1_TXD _UL_(1 << 27) 694 /* ========== GPIO definition for USART2 peripheral ========== */ 695 #define PIN_PC08B_USART2_CLK _L_(72) /**< \brief USART2 signal: CLK on PC08 mux B */ 696 #define MUX_PC08B_USART2_CLK _L_(1) 697 #define PINMUX_PC08B_USART2_CLK ((PIN_PC08B_USART2_CLK << 16) | MUX_PC08B_USART2_CLK) 698 #define GPIO_PC08B_USART2_CLK _UL_(1 << 8) 699 #define PIN_PA18A_USART2_CLK _L_(18) /**< \brief USART2 signal: CLK on PA18 mux A */ 700 #define MUX_PA18A_USART2_CLK _L_(0) 701 #define PINMUX_PA18A_USART2_CLK ((PIN_PA18A_USART2_CLK << 16) | MUX_PA18A_USART2_CLK) 702 #define GPIO_PA18A_USART2_CLK _UL_(1 << 18) 703 #define PIN_PC08E_USART2_CTS _L_(72) /**< \brief USART2 signal: CTS on PC08 mux E */ 704 #define MUX_PC08E_USART2_CTS _L_(4) 705 #define PINMUX_PC08E_USART2_CTS ((PIN_PC08E_USART2_CTS << 16) | MUX_PC08E_USART2_CTS) 706 #define GPIO_PC08E_USART2_CTS _UL_(1 << 8) 707 #define PIN_PA22B_USART2_CTS _L_(22) /**< \brief USART2 signal: CTS on PA22 mux B */ 708 #define MUX_PA22B_USART2_CTS _L_(1) 709 #define PINMUX_PA22B_USART2_CTS ((PIN_PA22B_USART2_CTS << 16) | MUX_PA22B_USART2_CTS) 710 #define GPIO_PA22B_USART2_CTS _UL_(1 << 22) 711 #define PIN_PC07B_USART2_RTS _L_(71) /**< \brief USART2 signal: RTS on PC07 mux B */ 712 #define MUX_PC07B_USART2_RTS _L_(1) 713 #define PINMUX_PC07B_USART2_RTS ((PIN_PC07B_USART2_RTS << 16) | MUX_PC07B_USART2_RTS) 714 #define GPIO_PC07B_USART2_RTS _UL_(1 << 7) 715 #define PIN_PA17A_USART2_RTS _L_(17) /**< \brief USART2 signal: RTS on PA17 mux A */ 716 #define MUX_PA17A_USART2_RTS _L_(0) 717 #define PINMUX_PA17A_USART2_RTS ((PIN_PA17A_USART2_RTS << 16) | MUX_PA17A_USART2_RTS) 718 #define GPIO_PA17A_USART2_RTS _UL_(1 << 17) 719 #define PIN_PA25B_USART2_RXD _L_(25) /**< \brief USART2 signal: RXD on PA25 mux B */ 720 #define MUX_PA25B_USART2_RXD _L_(1) 721 #define PINMUX_PA25B_USART2_RXD ((PIN_PA25B_USART2_RXD << 16) | MUX_PA25B_USART2_RXD) 722 #define GPIO_PA25B_USART2_RXD _UL_(1 << 25) 723 #define PIN_PC11B_USART2_RXD _L_(75) /**< \brief USART2 signal: RXD on PC11 mux B */ 724 #define MUX_PC11B_USART2_RXD _L_(1) 725 #define PINMUX_PC11B_USART2_RXD ((PIN_PC11B_USART2_RXD << 16) | MUX_PC11B_USART2_RXD) 726 #define GPIO_PC11B_USART2_RXD _UL_(1 << 11) 727 #define PIN_PA19A_USART2_RXD _L_(19) /**< \brief USART2 signal: RXD on PA19 mux A */ 728 #define MUX_PA19A_USART2_RXD _L_(0) 729 #define PINMUX_PA19A_USART2_RXD ((PIN_PA19A_USART2_RXD << 16) | MUX_PA19A_USART2_RXD) 730 #define GPIO_PA19A_USART2_RXD _UL_(1 << 19) 731 #define PIN_PA26B_USART2_TXD _L_(26) /**< \brief USART2 signal: TXD on PA26 mux B */ 732 #define MUX_PA26B_USART2_TXD _L_(1) 733 #define PINMUX_PA26B_USART2_TXD ((PIN_PA26B_USART2_TXD << 16) | MUX_PA26B_USART2_TXD) 734 #define GPIO_PA26B_USART2_TXD _UL_(1 << 26) 735 #define PIN_PC12B_USART2_TXD _L_(76) /**< \brief USART2 signal: TXD on PC12 mux B */ 736 #define MUX_PC12B_USART2_TXD _L_(1) 737 #define PINMUX_PC12B_USART2_TXD ((PIN_PC12B_USART2_TXD << 16) | MUX_PC12B_USART2_TXD) 738 #define GPIO_PC12B_USART2_TXD _UL_(1 << 12) 739 #define PIN_PA20A_USART2_TXD _L_(20) /**< \brief USART2 signal: TXD on PA20 mux A */ 740 #define MUX_PA20A_USART2_TXD _L_(0) 741 #define PINMUX_PA20A_USART2_TXD ((PIN_PA20A_USART2_TXD << 16) | MUX_PA20A_USART2_TXD) 742 #define GPIO_PA20A_USART2_TXD _UL_(1 << 20) 743 /* ========== GPIO definition for USART3 peripheral ========== */ 744 #define PIN_PA29E_USART3_CLK _L_(29) /**< \brief USART3 signal: CLK on PA29 mux E */ 745 #define MUX_PA29E_USART3_CLK _L_(4) 746 #define PINMUX_PA29E_USART3_CLK ((PIN_PA29E_USART3_CLK << 16) | MUX_PA29E_USART3_CLK) 747 #define GPIO_PA29E_USART3_CLK _UL_(1 << 29) 748 #define PIN_PC14B_USART3_CLK _L_(78) /**< \brief USART3 signal: CLK on PC14 mux B */ 749 #define MUX_PC14B_USART3_CLK _L_(1) 750 #define PINMUX_PC14B_USART3_CLK ((PIN_PC14B_USART3_CLK << 16) | MUX_PC14B_USART3_CLK) 751 #define GPIO_PC14B_USART3_CLK _UL_(1 << 14) 752 #define PIN_PB08A_USART3_CLK _L_(40) /**< \brief USART3 signal: CLK on PB08 mux A */ 753 #define MUX_PB08A_USART3_CLK _L_(0) 754 #define PINMUX_PB08A_USART3_CLK ((PIN_PB08A_USART3_CLK << 16) | MUX_PB08A_USART3_CLK) 755 #define GPIO_PB08A_USART3_CLK _UL_(1 << 8) 756 #define PIN_PC31A_USART3_CLK _L_(95) /**< \brief USART3 signal: CLK on PC31 mux A */ 757 #define MUX_PC31A_USART3_CLK _L_(0) 758 #define PINMUX_PC31A_USART3_CLK ((PIN_PC31A_USART3_CLK << 16) | MUX_PC31A_USART3_CLK) 759 #define GPIO_PC31A_USART3_CLK _UL_(1 << 31) 760 #define PIN_PA28E_USART3_CTS _L_(28) /**< \brief USART3 signal: CTS on PA28 mux E */ 761 #define MUX_PA28E_USART3_CTS _L_(4) 762 #define PINMUX_PA28E_USART3_CTS ((PIN_PA28E_USART3_CTS << 16) | MUX_PA28E_USART3_CTS) 763 #define GPIO_PA28E_USART3_CTS _UL_(1 << 28) 764 #define PIN_PB07A_USART3_CTS _L_(39) /**< \brief USART3 signal: CTS on PB07 mux A */ 765 #define MUX_PB07A_USART3_CTS _L_(0) 766 #define PINMUX_PB07A_USART3_CTS ((PIN_PB07A_USART3_CTS << 16) | MUX_PB07A_USART3_CTS) 767 #define GPIO_PB07A_USART3_CTS _UL_(1 << 7) 768 #define PIN_PA27E_USART3_RTS _L_(27) /**< \brief USART3 signal: RTS on PA27 mux E */ 769 #define MUX_PA27E_USART3_RTS _L_(4) 770 #define PINMUX_PA27E_USART3_RTS ((PIN_PA27E_USART3_RTS << 16) | MUX_PA27E_USART3_RTS) 771 #define GPIO_PA27E_USART3_RTS _UL_(1 << 27) 772 #define PIN_PC13B_USART3_RTS _L_(77) /**< \brief USART3 signal: RTS on PC13 mux B */ 773 #define MUX_PC13B_USART3_RTS _L_(1) 774 #define PINMUX_PC13B_USART3_RTS ((PIN_PC13B_USART3_RTS << 16) | MUX_PC13B_USART3_RTS) 775 #define GPIO_PC13B_USART3_RTS _UL_(1 << 13) 776 #define PIN_PB06A_USART3_RTS _L_(38) /**< \brief USART3 signal: RTS on PB06 mux A */ 777 #define MUX_PB06A_USART3_RTS _L_(0) 778 #define PINMUX_PB06A_USART3_RTS ((PIN_PB06A_USART3_RTS << 16) | MUX_PB06A_USART3_RTS) 779 #define GPIO_PB06A_USART3_RTS _UL_(1 << 6) 780 #define PIN_PC30A_USART3_RTS _L_(94) /**< \brief USART3 signal: RTS on PC30 mux A */ 781 #define MUX_PC30A_USART3_RTS _L_(0) 782 #define PINMUX_PC30A_USART3_RTS ((PIN_PC30A_USART3_RTS << 16) | MUX_PC30A_USART3_RTS) 783 #define GPIO_PC30A_USART3_RTS _UL_(1 << 30) 784 #define PIN_PA30E_USART3_RXD _L_(30) /**< \brief USART3 signal: RXD on PA30 mux E */ 785 #define MUX_PA30E_USART3_RXD _L_(4) 786 #define PINMUX_PA30E_USART3_RXD ((PIN_PA30E_USART3_RXD << 16) | MUX_PA30E_USART3_RXD) 787 #define GPIO_PA30E_USART3_RXD _UL_(1 << 30) 788 #define PIN_PC09B_USART3_RXD _L_(73) /**< \brief USART3 signal: RXD on PC09 mux B */ 789 #define MUX_PC09B_USART3_RXD _L_(1) 790 #define PINMUX_PC09B_USART3_RXD ((PIN_PC09B_USART3_RXD << 16) | MUX_PC09B_USART3_RXD) 791 #define GPIO_PC09B_USART3_RXD _UL_(1 << 9) 792 #define PIN_PB09A_USART3_RXD _L_(41) /**< \brief USART3 signal: RXD on PB09 mux A */ 793 #define MUX_PB09A_USART3_RXD _L_(0) 794 #define PINMUX_PB09A_USART3_RXD ((PIN_PB09A_USART3_RXD << 16) | MUX_PB09A_USART3_RXD) 795 #define GPIO_PB09A_USART3_RXD _UL_(1 << 9) 796 #define PIN_PC28A_USART3_RXD _L_(92) /**< \brief USART3 signal: RXD on PC28 mux A */ 797 #define MUX_PC28A_USART3_RXD _L_(0) 798 #define PINMUX_PC28A_USART3_RXD ((PIN_PC28A_USART3_RXD << 16) | MUX_PC28A_USART3_RXD) 799 #define GPIO_PC28A_USART3_RXD _UL_(1 << 28) 800 #define PIN_PA31E_USART3_TXD _L_(31) /**< \brief USART3 signal: TXD on PA31 mux E */ 801 #define MUX_PA31E_USART3_TXD _L_(4) 802 #define PINMUX_PA31E_USART3_TXD ((PIN_PA31E_USART3_TXD << 16) | MUX_PA31E_USART3_TXD) 803 #define GPIO_PA31E_USART3_TXD _UL_(1 << 31) 804 #define PIN_PC10B_USART3_TXD _L_(74) /**< \brief USART3 signal: TXD on PC10 mux B */ 805 #define MUX_PC10B_USART3_TXD _L_(1) 806 #define PINMUX_PC10B_USART3_TXD ((PIN_PC10B_USART3_TXD << 16) | MUX_PC10B_USART3_TXD) 807 #define GPIO_PC10B_USART3_TXD _UL_(1 << 10) 808 #define PIN_PB10A_USART3_TXD _L_(42) /**< \brief USART3 signal: TXD on PB10 mux A */ 809 #define MUX_PB10A_USART3_TXD _L_(0) 810 #define PINMUX_PB10A_USART3_TXD ((PIN_PB10A_USART3_TXD << 16) | MUX_PB10A_USART3_TXD) 811 #define GPIO_PB10A_USART3_TXD _UL_(1 << 10) 812 #define PIN_PC29A_USART3_TXD _L_(93) /**< \brief USART3 signal: TXD on PC29 mux A */ 813 #define MUX_PC29A_USART3_TXD _L_(0) 814 #define PINMUX_PC29A_USART3_TXD ((PIN_PC29A_USART3_TXD << 16) | MUX_PC29A_USART3_TXD) 815 #define GPIO_PC29A_USART3_TXD _UL_(1 << 29) 816 /* ========== GPIO definition for ADCIFE peripheral ========== */ 817 #define PIN_PA04A_ADCIFE_AD0 _L_(4) /**< \brief ADCIFE signal: AD0 on PA04 mux A */ 818 #define MUX_PA04A_ADCIFE_AD0 _L_(0) 819 #define PINMUX_PA04A_ADCIFE_AD0 ((PIN_PA04A_ADCIFE_AD0 << 16) | MUX_PA04A_ADCIFE_AD0) 820 #define GPIO_PA04A_ADCIFE_AD0 _UL_(1 << 4) 821 #define PIN_PA05A_ADCIFE_AD1 _L_(5) /**< \brief ADCIFE signal: AD1 on PA05 mux A */ 822 #define MUX_PA05A_ADCIFE_AD1 _L_(0) 823 #define PINMUX_PA05A_ADCIFE_AD1 ((PIN_PA05A_ADCIFE_AD1 << 16) | MUX_PA05A_ADCIFE_AD1) 824 #define GPIO_PA05A_ADCIFE_AD1 _UL_(1 << 5) 825 #define PIN_PA07A_ADCIFE_AD2 _L_(7) /**< \brief ADCIFE signal: AD2 on PA07 mux A */ 826 #define MUX_PA07A_ADCIFE_AD2 _L_(0) 827 #define PINMUX_PA07A_ADCIFE_AD2 ((PIN_PA07A_ADCIFE_AD2 << 16) | MUX_PA07A_ADCIFE_AD2) 828 #define GPIO_PA07A_ADCIFE_AD2 _UL_(1 << 7) 829 #define PIN_PB02A_ADCIFE_AD3 _L_(34) /**< \brief ADCIFE signal: AD3 on PB02 mux A */ 830 #define MUX_PB02A_ADCIFE_AD3 _L_(0) 831 #define PINMUX_PB02A_ADCIFE_AD3 ((PIN_PB02A_ADCIFE_AD3 << 16) | MUX_PB02A_ADCIFE_AD3) 832 #define GPIO_PB02A_ADCIFE_AD3 _UL_(1 << 2) 833 #define PIN_PB03A_ADCIFE_AD4 _L_(35) /**< \brief ADCIFE signal: AD4 on PB03 mux A */ 834 #define MUX_PB03A_ADCIFE_AD4 _L_(0) 835 #define PINMUX_PB03A_ADCIFE_AD4 ((PIN_PB03A_ADCIFE_AD4 << 16) | MUX_PB03A_ADCIFE_AD4) 836 #define GPIO_PB03A_ADCIFE_AD4 _UL_(1 << 3) 837 #define PIN_PB04A_ADCIFE_AD5 _L_(36) /**< \brief ADCIFE signal: AD5 on PB04 mux A */ 838 #define MUX_PB04A_ADCIFE_AD5 _L_(0) 839 #define PINMUX_PB04A_ADCIFE_AD5 ((PIN_PB04A_ADCIFE_AD5 << 16) | MUX_PB04A_ADCIFE_AD5) 840 #define GPIO_PB04A_ADCIFE_AD5 _UL_(1 << 4) 841 #define PIN_PB05A_ADCIFE_AD6 _L_(37) /**< \brief ADCIFE signal: AD6 on PB05 mux A */ 842 #define MUX_PB05A_ADCIFE_AD6 _L_(0) 843 #define PINMUX_PB05A_ADCIFE_AD6 ((PIN_PB05A_ADCIFE_AD6 << 16) | MUX_PB05A_ADCIFE_AD6) 844 #define GPIO_PB05A_ADCIFE_AD6 _UL_(1 << 5) 845 #define PIN_PC07A_ADCIFE_AD7 _L_(71) /**< \brief ADCIFE signal: AD7 on PC07 mux A */ 846 #define MUX_PC07A_ADCIFE_AD7 _L_(0) 847 #define PINMUX_PC07A_ADCIFE_AD7 ((PIN_PC07A_ADCIFE_AD7 << 16) | MUX_PC07A_ADCIFE_AD7) 848 #define GPIO_PC07A_ADCIFE_AD7 _UL_(1 << 7) 849 #define PIN_PC08A_ADCIFE_AD8 _L_(72) /**< \brief ADCIFE signal: AD8 on PC08 mux A */ 850 #define MUX_PC08A_ADCIFE_AD8 _L_(0) 851 #define PINMUX_PC08A_ADCIFE_AD8 ((PIN_PC08A_ADCIFE_AD8 << 16) | MUX_PC08A_ADCIFE_AD8) 852 #define GPIO_PC08A_ADCIFE_AD8 _UL_(1 << 8) 853 #define PIN_PC09A_ADCIFE_AD9 _L_(73) /**< \brief ADCIFE signal: AD9 on PC09 mux A */ 854 #define MUX_PC09A_ADCIFE_AD9 _L_(0) 855 #define PINMUX_PC09A_ADCIFE_AD9 ((PIN_PC09A_ADCIFE_AD9 << 16) | MUX_PC09A_ADCIFE_AD9) 856 #define GPIO_PC09A_ADCIFE_AD9 _UL_(1 << 9) 857 #define PIN_PC10A_ADCIFE_AD10 _L_(74) /**< \brief ADCIFE signal: AD10 on PC10 mux A */ 858 #define MUX_PC10A_ADCIFE_AD10 _L_(0) 859 #define PINMUX_PC10A_ADCIFE_AD10 ((PIN_PC10A_ADCIFE_AD10 << 16) | MUX_PC10A_ADCIFE_AD10) 860 #define GPIO_PC10A_ADCIFE_AD10 _UL_(1 << 10) 861 #define PIN_PC11A_ADCIFE_AD11 _L_(75) /**< \brief ADCIFE signal: AD11 on PC11 mux A */ 862 #define MUX_PC11A_ADCIFE_AD11 _L_(0) 863 #define PINMUX_PC11A_ADCIFE_AD11 ((PIN_PC11A_ADCIFE_AD11 << 16) | MUX_PC11A_ADCIFE_AD11) 864 #define GPIO_PC11A_ADCIFE_AD11 _UL_(1 << 11) 865 #define PIN_PC12A_ADCIFE_AD12 _L_(76) /**< \brief ADCIFE signal: AD12 on PC12 mux A */ 866 #define MUX_PC12A_ADCIFE_AD12 _L_(0) 867 #define PINMUX_PC12A_ADCIFE_AD12 ((PIN_PC12A_ADCIFE_AD12 << 16) | MUX_PC12A_ADCIFE_AD12) 868 #define GPIO_PC12A_ADCIFE_AD12 _UL_(1 << 12) 869 #define PIN_PC13A_ADCIFE_AD13 _L_(77) /**< \brief ADCIFE signal: AD13 on PC13 mux A */ 870 #define MUX_PC13A_ADCIFE_AD13 _L_(0) 871 #define PINMUX_PC13A_ADCIFE_AD13 ((PIN_PC13A_ADCIFE_AD13 << 16) | MUX_PC13A_ADCIFE_AD13) 872 #define GPIO_PC13A_ADCIFE_AD13 _UL_(1 << 13) 873 #define PIN_PC14A_ADCIFE_AD14 _L_(78) /**< \brief ADCIFE signal: AD14 on PC14 mux A */ 874 #define MUX_PC14A_ADCIFE_AD14 _L_(0) 875 #define PINMUX_PC14A_ADCIFE_AD14 ((PIN_PC14A_ADCIFE_AD14 << 16) | MUX_PC14A_ADCIFE_AD14) 876 #define GPIO_PC14A_ADCIFE_AD14 _UL_(1 << 14) 877 #define PIN_PA05E_ADCIFE_TRIGGER _L_(5) /**< \brief ADCIFE signal: TRIGGER on PA05 mux E */ 878 #define MUX_PA05E_ADCIFE_TRIGGER _L_(4) 879 #define PINMUX_PA05E_ADCIFE_TRIGGER ((PIN_PA05E_ADCIFE_TRIGGER << 16) | MUX_PA05E_ADCIFE_TRIGGER) 880 #define GPIO_PA05E_ADCIFE_TRIGGER _UL_(1 << 5) 881 /* ========== GPIO definition for DACC peripheral ========== */ 882 #define PIN_PB04E_DACC_EXT_TRIG0 _L_(36) /**< \brief DACC signal: EXT_TRIG0 on PB04 mux E */ 883 #define MUX_PB04E_DACC_EXT_TRIG0 _L_(4) 884 #define PINMUX_PB04E_DACC_EXT_TRIG0 ((PIN_PB04E_DACC_EXT_TRIG0 << 16) | MUX_PB04E_DACC_EXT_TRIG0) 885 #define GPIO_PB04E_DACC_EXT_TRIG0 _UL_(1 << 4) 886 #define PIN_PA06A_DACC_VOUT _L_(6) /**< \brief DACC signal: VOUT on PA06 mux A */ 887 #define MUX_PA06A_DACC_VOUT _L_(0) 888 #define PINMUX_PA06A_DACC_VOUT ((PIN_PA06A_DACC_VOUT << 16) | MUX_PA06A_DACC_VOUT) 889 #define GPIO_PA06A_DACC_VOUT _UL_(1 << 6) 890 /* ========== GPIO definition for ACIFC peripheral ========== */ 891 #define PIN_PA06E_ACIFC_ACAN0 _L_(6) /**< \brief ACIFC signal: ACAN0 on PA06 mux E */ 892 #define MUX_PA06E_ACIFC_ACAN0 _L_(4) 893 #define PINMUX_PA06E_ACIFC_ACAN0 ((PIN_PA06E_ACIFC_ACAN0 << 16) | MUX_PA06E_ACIFC_ACAN0) 894 #define GPIO_PA06E_ACIFC_ACAN0 _UL_(1 << 6) 895 #define PIN_PC09E_ACIFC_ACAN1 _L_(73) /**< \brief ACIFC signal: ACAN1 on PC09 mux E */ 896 #define MUX_PC09E_ACIFC_ACAN1 _L_(4) 897 #define PINMUX_PC09E_ACIFC_ACAN1 ((PIN_PC09E_ACIFC_ACAN1 << 16) | MUX_PC09E_ACIFC_ACAN1) 898 #define GPIO_PC09E_ACIFC_ACAN1 _UL_(1 << 9) 899 #define PIN_PA07E_ACIFC_ACAP0 _L_(7) /**< \brief ACIFC signal: ACAP0 on PA07 mux E */ 900 #define MUX_PA07E_ACIFC_ACAP0 _L_(4) 901 #define PINMUX_PA07E_ACIFC_ACAP0 ((PIN_PA07E_ACIFC_ACAP0 << 16) | MUX_PA07E_ACIFC_ACAP0) 902 #define GPIO_PA07E_ACIFC_ACAP0 _UL_(1 << 7) 903 #define PIN_PC10E_ACIFC_ACAP1 _L_(74) /**< \brief ACIFC signal: ACAP1 on PC10 mux E */ 904 #define MUX_PC10E_ACIFC_ACAP1 _L_(4) 905 #define PINMUX_PC10E_ACIFC_ACAP1 ((PIN_PC10E_ACIFC_ACAP1 << 16) | MUX_PC10E_ACIFC_ACAP1) 906 #define GPIO_PC10E_ACIFC_ACAP1 _UL_(1 << 10) 907 #define PIN_PB02E_ACIFC_ACBN0 _L_(34) /**< \brief ACIFC signal: ACBN0 on PB02 mux E */ 908 #define MUX_PB02E_ACIFC_ACBN0 _L_(4) 909 #define PINMUX_PB02E_ACIFC_ACBN0 ((PIN_PB02E_ACIFC_ACBN0 << 16) | MUX_PB02E_ACIFC_ACBN0) 910 #define GPIO_PB02E_ACIFC_ACBN0 _UL_(1 << 2) 911 #define PIN_PC13E_ACIFC_ACBN1 _L_(77) /**< \brief ACIFC signal: ACBN1 on PC13 mux E */ 912 #define MUX_PC13E_ACIFC_ACBN1 _L_(4) 913 #define PINMUX_PC13E_ACIFC_ACBN1 ((PIN_PC13E_ACIFC_ACBN1 << 16) | MUX_PC13E_ACIFC_ACBN1) 914 #define GPIO_PC13E_ACIFC_ACBN1 _UL_(1 << 13) 915 #define PIN_PB03E_ACIFC_ACBP0 _L_(35) /**< \brief ACIFC signal: ACBP0 on PB03 mux E */ 916 #define MUX_PB03E_ACIFC_ACBP0 _L_(4) 917 #define PINMUX_PB03E_ACIFC_ACBP0 ((PIN_PB03E_ACIFC_ACBP0 << 16) | MUX_PB03E_ACIFC_ACBP0) 918 #define GPIO_PB03E_ACIFC_ACBP0 _UL_(1 << 3) 919 #define PIN_PC14E_ACIFC_ACBP1 _L_(78) /**< \brief ACIFC signal: ACBP1 on PC14 mux E */ 920 #define MUX_PC14E_ACIFC_ACBP1 _L_(4) 921 #define PINMUX_PC14E_ACIFC_ACBP1 ((PIN_PC14E_ACIFC_ACBP1 << 16) | MUX_PC14E_ACIFC_ACBP1) 922 #define GPIO_PC14E_ACIFC_ACBP1 _UL_(1 << 14) 923 /* ========== GPIO definition for GLOC peripheral ========== */ 924 #define PIN_PA06D_GLOC_IN0 _L_(6) /**< \brief GLOC signal: IN0 on PA06 mux D */ 925 #define MUX_PA06D_GLOC_IN0 _L_(3) 926 #define PINMUX_PA06D_GLOC_IN0 ((PIN_PA06D_GLOC_IN0 << 16) | MUX_PA06D_GLOC_IN0) 927 #define GPIO_PA06D_GLOC_IN0 _UL_(1 << 6) 928 #define PIN_PA20D_GLOC_IN0 _L_(20) /**< \brief GLOC signal: IN0 on PA20 mux D */ 929 #define MUX_PA20D_GLOC_IN0 _L_(3) 930 #define PINMUX_PA20D_GLOC_IN0 ((PIN_PA20D_GLOC_IN0 << 16) | MUX_PA20D_GLOC_IN0) 931 #define GPIO_PA20D_GLOC_IN0 _UL_(1 << 20) 932 #define PIN_PA04D_GLOC_IN1 _L_(4) /**< \brief GLOC signal: IN1 on PA04 mux D */ 933 #define MUX_PA04D_GLOC_IN1 _L_(3) 934 #define PINMUX_PA04D_GLOC_IN1 ((PIN_PA04D_GLOC_IN1 << 16) | MUX_PA04D_GLOC_IN1) 935 #define GPIO_PA04D_GLOC_IN1 _UL_(1 << 4) 936 #define PIN_PA21D_GLOC_IN1 _L_(21) /**< \brief GLOC signal: IN1 on PA21 mux D */ 937 #define MUX_PA21D_GLOC_IN1 _L_(3) 938 #define PINMUX_PA21D_GLOC_IN1 ((PIN_PA21D_GLOC_IN1 << 16) | MUX_PA21D_GLOC_IN1) 939 #define GPIO_PA21D_GLOC_IN1 _UL_(1 << 21) 940 #define PIN_PA05D_GLOC_IN2 _L_(5) /**< \brief GLOC signal: IN2 on PA05 mux D */ 941 #define MUX_PA05D_GLOC_IN2 _L_(3) 942 #define PINMUX_PA05D_GLOC_IN2 ((PIN_PA05D_GLOC_IN2 << 16) | MUX_PA05D_GLOC_IN2) 943 #define GPIO_PA05D_GLOC_IN2 _UL_(1 << 5) 944 #define PIN_PA22D_GLOC_IN2 _L_(22) /**< \brief GLOC signal: IN2 on PA22 mux D */ 945 #define MUX_PA22D_GLOC_IN2 _L_(3) 946 #define PINMUX_PA22D_GLOC_IN2 ((PIN_PA22D_GLOC_IN2 << 16) | MUX_PA22D_GLOC_IN2) 947 #define GPIO_PA22D_GLOC_IN2 _UL_(1 << 22) 948 #define PIN_PA07D_GLOC_IN3 _L_(7) /**< \brief GLOC signal: IN3 on PA07 mux D */ 949 #define MUX_PA07D_GLOC_IN3 _L_(3) 950 #define PINMUX_PA07D_GLOC_IN3 ((PIN_PA07D_GLOC_IN3 << 16) | MUX_PA07D_GLOC_IN3) 951 #define GPIO_PA07D_GLOC_IN3 _UL_(1 << 7) 952 #define PIN_PA23D_GLOC_IN3 _L_(23) /**< \brief GLOC signal: IN3 on PA23 mux D */ 953 #define MUX_PA23D_GLOC_IN3 _L_(3) 954 #define PINMUX_PA23D_GLOC_IN3 ((PIN_PA23D_GLOC_IN3 << 16) | MUX_PA23D_GLOC_IN3) 955 #define GPIO_PA23D_GLOC_IN3 _UL_(1 << 23) 956 #define PIN_PA27D_GLOC_IN4 _L_(27) /**< \brief GLOC signal: IN4 on PA27 mux D */ 957 #define MUX_PA27D_GLOC_IN4 _L_(3) 958 #define PINMUX_PA27D_GLOC_IN4 ((PIN_PA27D_GLOC_IN4 << 16) | MUX_PA27D_GLOC_IN4) 959 #define GPIO_PA27D_GLOC_IN4 _UL_(1 << 27) 960 #define PIN_PC15D_GLOC_IN4 _L_(79) /**< \brief GLOC signal: IN4 on PC15 mux D */ 961 #define MUX_PC15D_GLOC_IN4 _L_(3) 962 #define PINMUX_PC15D_GLOC_IN4 ((PIN_PC15D_GLOC_IN4 << 16) | MUX_PC15D_GLOC_IN4) 963 #define GPIO_PC15D_GLOC_IN4 _UL_(1 << 15) 964 #define PIN_PB06C_GLOC_IN4 _L_(38) /**< \brief GLOC signal: IN4 on PB06 mux C */ 965 #define MUX_PB06C_GLOC_IN4 _L_(2) 966 #define PINMUX_PB06C_GLOC_IN4 ((PIN_PB06C_GLOC_IN4 << 16) | MUX_PB06C_GLOC_IN4) 967 #define GPIO_PB06C_GLOC_IN4 _UL_(1 << 6) 968 #define PIN_PC28C_GLOC_IN4 _L_(92) /**< \brief GLOC signal: IN4 on PC28 mux C */ 969 #define MUX_PC28C_GLOC_IN4 _L_(2) 970 #define PINMUX_PC28C_GLOC_IN4 ((PIN_PC28C_GLOC_IN4 << 16) | MUX_PC28C_GLOC_IN4) 971 #define GPIO_PC28C_GLOC_IN4 _UL_(1 << 28) 972 #define PIN_PA28D_GLOC_IN5 _L_(28) /**< \brief GLOC signal: IN5 on PA28 mux D */ 973 #define MUX_PA28D_GLOC_IN5 _L_(3) 974 #define PINMUX_PA28D_GLOC_IN5 ((PIN_PA28D_GLOC_IN5 << 16) | MUX_PA28D_GLOC_IN5) 975 #define GPIO_PA28D_GLOC_IN5 _UL_(1 << 28) 976 #define PIN_PC16D_GLOC_IN5 _L_(80) /**< \brief GLOC signal: IN5 on PC16 mux D */ 977 #define MUX_PC16D_GLOC_IN5 _L_(3) 978 #define PINMUX_PC16D_GLOC_IN5 ((PIN_PC16D_GLOC_IN5 << 16) | MUX_PC16D_GLOC_IN5) 979 #define GPIO_PC16D_GLOC_IN5 _UL_(1 << 16) 980 #define PIN_PB07C_GLOC_IN5 _L_(39) /**< \brief GLOC signal: IN5 on PB07 mux C */ 981 #define MUX_PB07C_GLOC_IN5 _L_(2) 982 #define PINMUX_PB07C_GLOC_IN5 ((PIN_PB07C_GLOC_IN5 << 16) | MUX_PB07C_GLOC_IN5) 983 #define GPIO_PB07C_GLOC_IN5 _UL_(1 << 7) 984 #define PIN_PC29C_GLOC_IN5 _L_(93) /**< \brief GLOC signal: IN5 on PC29 mux C */ 985 #define MUX_PC29C_GLOC_IN5 _L_(2) 986 #define PINMUX_PC29C_GLOC_IN5 ((PIN_PC29C_GLOC_IN5 << 16) | MUX_PC29C_GLOC_IN5) 987 #define GPIO_PC29C_GLOC_IN5 _UL_(1 << 29) 988 #define PIN_PA29D_GLOC_IN6 _L_(29) /**< \brief GLOC signal: IN6 on PA29 mux D */ 989 #define MUX_PA29D_GLOC_IN6 _L_(3) 990 #define PINMUX_PA29D_GLOC_IN6 ((PIN_PA29D_GLOC_IN6 << 16) | MUX_PA29D_GLOC_IN6) 991 #define GPIO_PA29D_GLOC_IN6 _UL_(1 << 29) 992 #define PIN_PC17D_GLOC_IN6 _L_(81) /**< \brief GLOC signal: IN6 on PC17 mux D */ 993 #define MUX_PC17D_GLOC_IN6 _L_(3) 994 #define PINMUX_PC17D_GLOC_IN6 ((PIN_PC17D_GLOC_IN6 << 16) | MUX_PC17D_GLOC_IN6) 995 #define GPIO_PC17D_GLOC_IN6 _UL_(1 << 17) 996 #define PIN_PB08C_GLOC_IN6 _L_(40) /**< \brief GLOC signal: IN6 on PB08 mux C */ 997 #define MUX_PB08C_GLOC_IN6 _L_(2) 998 #define PINMUX_PB08C_GLOC_IN6 ((PIN_PB08C_GLOC_IN6 << 16) | MUX_PB08C_GLOC_IN6) 999 #define GPIO_PB08C_GLOC_IN6 _UL_(1 << 8) 1000 #define PIN_PC30C_GLOC_IN6 _L_(94) /**< \brief GLOC signal: IN6 on PC30 mux C */ 1001 #define MUX_PC30C_GLOC_IN6 _L_(2) 1002 #define PINMUX_PC30C_GLOC_IN6 ((PIN_PC30C_GLOC_IN6 << 16) | MUX_PC30C_GLOC_IN6) 1003 #define GPIO_PC30C_GLOC_IN6 _UL_(1 << 30) 1004 #define PIN_PA30D_GLOC_IN7 _L_(30) /**< \brief GLOC signal: IN7 on PA30 mux D */ 1005 #define MUX_PA30D_GLOC_IN7 _L_(3) 1006 #define PINMUX_PA30D_GLOC_IN7 ((PIN_PA30D_GLOC_IN7 << 16) | MUX_PA30D_GLOC_IN7) 1007 #define GPIO_PA30D_GLOC_IN7 _UL_(1 << 30) 1008 #define PIN_PC18D_GLOC_IN7 _L_(82) /**< \brief GLOC signal: IN7 on PC18 mux D */ 1009 #define MUX_PC18D_GLOC_IN7 _L_(3) 1010 #define PINMUX_PC18D_GLOC_IN7 ((PIN_PC18D_GLOC_IN7 << 16) | MUX_PC18D_GLOC_IN7) 1011 #define GPIO_PC18D_GLOC_IN7 _UL_(1 << 18) 1012 #define PIN_PB09C_GLOC_IN7 _L_(41) /**< \brief GLOC signal: IN7 on PB09 mux C */ 1013 #define MUX_PB09C_GLOC_IN7 _L_(2) 1014 #define PINMUX_PB09C_GLOC_IN7 ((PIN_PB09C_GLOC_IN7 << 16) | MUX_PB09C_GLOC_IN7) 1015 #define GPIO_PB09C_GLOC_IN7 _UL_(1 << 9) 1016 #define PIN_PA08D_GLOC_OUT0 _L_(8) /**< \brief GLOC signal: OUT0 on PA08 mux D */ 1017 #define MUX_PA08D_GLOC_OUT0 _L_(3) 1018 #define PINMUX_PA08D_GLOC_OUT0 ((PIN_PA08D_GLOC_OUT0 << 16) | MUX_PA08D_GLOC_OUT0) 1019 #define GPIO_PA08D_GLOC_OUT0 _UL_(1 << 8) 1020 #define PIN_PA24D_GLOC_OUT0 _L_(24) /**< \brief GLOC signal: OUT0 on PA24 mux D */ 1021 #define MUX_PA24D_GLOC_OUT0 _L_(3) 1022 #define PINMUX_PA24D_GLOC_OUT0 ((PIN_PA24D_GLOC_OUT0 << 16) | MUX_PA24D_GLOC_OUT0) 1023 #define GPIO_PA24D_GLOC_OUT0 _UL_(1 << 24) 1024 #define PIN_PA31D_GLOC_OUT1 _L_(31) /**< \brief GLOC signal: OUT1 on PA31 mux D */ 1025 #define MUX_PA31D_GLOC_OUT1 _L_(3) 1026 #define PINMUX_PA31D_GLOC_OUT1 ((PIN_PA31D_GLOC_OUT1 << 16) | MUX_PA31D_GLOC_OUT1) 1027 #define GPIO_PA31D_GLOC_OUT1 _UL_(1 << 31) 1028 #define PIN_PC19D_GLOC_OUT1 _L_(83) /**< \brief GLOC signal: OUT1 on PC19 mux D */ 1029 #define MUX_PC19D_GLOC_OUT1 _L_(3) 1030 #define PINMUX_PC19D_GLOC_OUT1 ((PIN_PC19D_GLOC_OUT1 << 16) | MUX_PC19D_GLOC_OUT1) 1031 #define GPIO_PC19D_GLOC_OUT1 _UL_(1 << 19) 1032 #define PIN_PB10C_GLOC_OUT1 _L_(42) /**< \brief GLOC signal: OUT1 on PB10 mux C */ 1033 #define MUX_PB10C_GLOC_OUT1 _L_(2) 1034 #define PINMUX_PB10C_GLOC_OUT1 ((PIN_PB10C_GLOC_OUT1 << 16) | MUX_PB10C_GLOC_OUT1) 1035 #define GPIO_PB10C_GLOC_OUT1 _UL_(1 << 10) 1036 #define PIN_PC31C_GLOC_OUT1 _L_(95) /**< \brief GLOC signal: OUT1 on PC31 mux C */ 1037 #define MUX_PC31C_GLOC_OUT1 _L_(2) 1038 #define PINMUX_PC31C_GLOC_OUT1 ((PIN_PC31C_GLOC_OUT1 << 16) | MUX_PC31C_GLOC_OUT1) 1039 #define GPIO_PC31C_GLOC_OUT1 _UL_(1 << 31) 1040 /* ========== GPIO definition for ABDACB peripheral ========== */ 1041 #define PIN_PA31C_ABDACB_CLK _L_(31) /**< \brief ABDACB signal: CLK on PA31 mux C */ 1042 #define MUX_PA31C_ABDACB_CLK _L_(2) 1043 #define PINMUX_PA31C_ABDACB_CLK ((PIN_PA31C_ABDACB_CLK << 16) | MUX_PA31C_ABDACB_CLK) 1044 #define GPIO_PA31C_ABDACB_CLK _UL_(1 << 31) 1045 #define PIN_PC12C_ABDACB_CLK _L_(76) /**< \brief ABDACB signal: CLK on PC12 mux C */ 1046 #define MUX_PC12C_ABDACB_CLK _L_(2) 1047 #define PINMUX_PC12C_ABDACB_CLK ((PIN_PC12C_ABDACB_CLK << 16) | MUX_PC12C_ABDACB_CLK) 1048 #define GPIO_PC12C_ABDACB_CLK _UL_(1 << 12) 1049 #define PIN_PA27C_ABDACB_DAC0 _L_(27) /**< \brief ABDACB signal: DAC0 on PA27 mux C */ 1050 #define MUX_PA27C_ABDACB_DAC0 _L_(2) 1051 #define PINMUX_PA27C_ABDACB_DAC0 ((PIN_PA27C_ABDACB_DAC0 << 16) | MUX_PA27C_ABDACB_DAC0) 1052 #define GPIO_PA27C_ABDACB_DAC0 _UL_(1 << 27) 1053 #define PIN_PB02C_ABDACB_DAC0 _L_(34) /**< \brief ABDACB signal: DAC0 on PB02 mux C */ 1054 #define MUX_PB02C_ABDACB_DAC0 _L_(2) 1055 #define PINMUX_PB02C_ABDACB_DAC0 ((PIN_PB02C_ABDACB_DAC0 << 16) | MUX_PB02C_ABDACB_DAC0) 1056 #define GPIO_PB02C_ABDACB_DAC0 _UL_(1 << 2) 1057 #define PIN_PC09C_ABDACB_DAC0 _L_(73) /**< \brief ABDACB signal: DAC0 on PC09 mux C */ 1058 #define MUX_PC09C_ABDACB_DAC0 _L_(2) 1059 #define PINMUX_PC09C_ABDACB_DAC0 ((PIN_PC09C_ABDACB_DAC0 << 16) | MUX_PC09C_ABDACB_DAC0) 1060 #define GPIO_PC09C_ABDACB_DAC0 _UL_(1 << 9) 1061 #define PIN_PA17B_ABDACB_DAC0 _L_(17) /**< \brief ABDACB signal: DAC0 on PA17 mux B */ 1062 #define MUX_PA17B_ABDACB_DAC0 _L_(1) 1063 #define PINMUX_PA17B_ABDACB_DAC0 ((PIN_PA17B_ABDACB_DAC0 << 16) | MUX_PA17B_ABDACB_DAC0) 1064 #define GPIO_PA17B_ABDACB_DAC0 _UL_(1 << 17) 1065 #define PIN_PA29C_ABDACB_DAC1 _L_(29) /**< \brief ABDACB signal: DAC1 on PA29 mux C */ 1066 #define MUX_PA29C_ABDACB_DAC1 _L_(2) 1067 #define PINMUX_PA29C_ABDACB_DAC1 ((PIN_PA29C_ABDACB_DAC1 << 16) | MUX_PA29C_ABDACB_DAC1) 1068 #define GPIO_PA29C_ABDACB_DAC1 _UL_(1 << 29) 1069 #define PIN_PB04C_ABDACB_DAC1 _L_(36) /**< \brief ABDACB signal: DAC1 on PB04 mux C */ 1070 #define MUX_PB04C_ABDACB_DAC1 _L_(2) 1071 #define PINMUX_PB04C_ABDACB_DAC1 ((PIN_PB04C_ABDACB_DAC1 << 16) | MUX_PB04C_ABDACB_DAC1) 1072 #define GPIO_PB04C_ABDACB_DAC1 _UL_(1 << 4) 1073 #define PIN_PC13C_ABDACB_DAC1 _L_(77) /**< \brief ABDACB signal: DAC1 on PC13 mux C */ 1074 #define MUX_PC13C_ABDACB_DAC1 _L_(2) 1075 #define PINMUX_PC13C_ABDACB_DAC1 ((PIN_PC13C_ABDACB_DAC1 << 16) | MUX_PC13C_ABDACB_DAC1) 1076 #define GPIO_PC13C_ABDACB_DAC1 _UL_(1 << 13) 1077 #define PIN_PA19B_ABDACB_DAC1 _L_(19) /**< \brief ABDACB signal: DAC1 on PA19 mux B */ 1078 #define MUX_PA19B_ABDACB_DAC1 _L_(1) 1079 #define PINMUX_PA19B_ABDACB_DAC1 ((PIN_PA19B_ABDACB_DAC1 << 16) | MUX_PA19B_ABDACB_DAC1) 1080 #define GPIO_PA19B_ABDACB_DAC1 _UL_(1 << 19) 1081 #define PIN_PA28C_ABDACB_DACN0 _L_(28) /**< \brief ABDACB signal: DACN0 on PA28 mux C */ 1082 #define MUX_PA28C_ABDACB_DACN0 _L_(2) 1083 #define PINMUX_PA28C_ABDACB_DACN0 ((PIN_PA28C_ABDACB_DACN0 << 16) | MUX_PA28C_ABDACB_DACN0) 1084 #define GPIO_PA28C_ABDACB_DACN0 _UL_(1 << 28) 1085 #define PIN_PB03C_ABDACB_DACN0 _L_(35) /**< \brief ABDACB signal: DACN0 on PB03 mux C */ 1086 #define MUX_PB03C_ABDACB_DACN0 _L_(2) 1087 #define PINMUX_PB03C_ABDACB_DACN0 ((PIN_PB03C_ABDACB_DACN0 << 16) | MUX_PB03C_ABDACB_DACN0) 1088 #define GPIO_PB03C_ABDACB_DACN0 _UL_(1 << 3) 1089 #define PIN_PC10C_ABDACB_DACN0 _L_(74) /**< \brief ABDACB signal: DACN0 on PC10 mux C */ 1090 #define MUX_PC10C_ABDACB_DACN0 _L_(2) 1091 #define PINMUX_PC10C_ABDACB_DACN0 ((PIN_PC10C_ABDACB_DACN0 << 16) | MUX_PC10C_ABDACB_DACN0) 1092 #define GPIO_PC10C_ABDACB_DACN0 _UL_(1 << 10) 1093 #define PIN_PA18B_ABDACB_DACN0 _L_(18) /**< \brief ABDACB signal: DACN0 on PA18 mux B */ 1094 #define MUX_PA18B_ABDACB_DACN0 _L_(1) 1095 #define PINMUX_PA18B_ABDACB_DACN0 ((PIN_PA18B_ABDACB_DACN0 << 16) | MUX_PA18B_ABDACB_DACN0) 1096 #define GPIO_PA18B_ABDACB_DACN0 _UL_(1 << 18) 1097 #define PIN_PA30C_ABDACB_DACN1 _L_(30) /**< \brief ABDACB signal: DACN1 on PA30 mux C */ 1098 #define MUX_PA30C_ABDACB_DACN1 _L_(2) 1099 #define PINMUX_PA30C_ABDACB_DACN1 ((PIN_PA30C_ABDACB_DACN1 << 16) | MUX_PA30C_ABDACB_DACN1) 1100 #define GPIO_PA30C_ABDACB_DACN1 _UL_(1 << 30) 1101 #define PIN_PB05C_ABDACB_DACN1 _L_(37) /**< \brief ABDACB signal: DACN1 on PB05 mux C */ 1102 #define MUX_PB05C_ABDACB_DACN1 _L_(2) 1103 #define PINMUX_PB05C_ABDACB_DACN1 ((PIN_PB05C_ABDACB_DACN1 << 16) | MUX_PB05C_ABDACB_DACN1) 1104 #define GPIO_PB05C_ABDACB_DACN1 _UL_(1 << 5) 1105 #define PIN_PC14C_ABDACB_DACN1 _L_(78) /**< \brief ABDACB signal: DACN1 on PC14 mux C */ 1106 #define MUX_PC14C_ABDACB_DACN1 _L_(2) 1107 #define PINMUX_PC14C_ABDACB_DACN1 ((PIN_PC14C_ABDACB_DACN1 << 16) | MUX_PC14C_ABDACB_DACN1) 1108 #define GPIO_PC14C_ABDACB_DACN1 _UL_(1 << 14) 1109 #define PIN_PA20B_ABDACB_DACN1 _L_(20) /**< \brief ABDACB signal: DACN1 on PA20 mux B */ 1110 #define MUX_PA20B_ABDACB_DACN1 _L_(1) 1111 #define PINMUX_PA20B_ABDACB_DACN1 ((PIN_PA20B_ABDACB_DACN1 << 16) | MUX_PA20B_ABDACB_DACN1) 1112 #define GPIO_PA20B_ABDACB_DACN1 _UL_(1 << 20) 1113 /* ========== GPIO definition for PARC peripheral ========== */ 1114 #define PIN_PA17D_PARC_PCCK _L_(17) /**< \brief PARC signal: PCCK on PA17 mux D */ 1115 #define MUX_PA17D_PARC_PCCK _L_(3) 1116 #define PINMUX_PA17D_PARC_PCCK ((PIN_PA17D_PARC_PCCK << 16) | MUX_PA17D_PARC_PCCK) 1117 #define GPIO_PA17D_PARC_PCCK _UL_(1 << 17) 1118 #define PIN_PC21D_PARC_PCCK _L_(85) /**< \brief PARC signal: PCCK on PC21 mux D */ 1119 #define MUX_PC21D_PARC_PCCK _L_(3) 1120 #define PINMUX_PC21D_PARC_PCCK ((PIN_PC21D_PARC_PCCK << 16) | MUX_PC21D_PARC_PCCK) 1121 #define GPIO_PC21D_PARC_PCCK _UL_(1 << 21) 1122 #define PIN_PA09D_PARC_PCDATA0 _L_(9) /**< \brief PARC signal: PCDATA0 on PA09 mux D */ 1123 #define MUX_PA09D_PARC_PCDATA0 _L_(3) 1124 #define PINMUX_PA09D_PARC_PCDATA0 ((PIN_PA09D_PARC_PCDATA0 << 16) | MUX_PA09D_PARC_PCDATA0) 1125 #define GPIO_PA09D_PARC_PCDATA0 _UL_(1 << 9) 1126 #define PIN_PC24D_PARC_PCDATA0 _L_(88) /**< \brief PARC signal: PCDATA0 on PC24 mux D */ 1127 #define MUX_PC24D_PARC_PCDATA0 _L_(3) 1128 #define PINMUX_PC24D_PARC_PCDATA0 ((PIN_PC24D_PARC_PCDATA0 << 16) | MUX_PC24D_PARC_PCDATA0) 1129 #define GPIO_PC24D_PARC_PCDATA0 _UL_(1 << 24) 1130 #define PIN_PA10D_PARC_PCDATA1 _L_(10) /**< \brief PARC signal: PCDATA1 on PA10 mux D */ 1131 #define MUX_PA10D_PARC_PCDATA1 _L_(3) 1132 #define PINMUX_PA10D_PARC_PCDATA1 ((PIN_PA10D_PARC_PCDATA1 << 16) | MUX_PA10D_PARC_PCDATA1) 1133 #define GPIO_PA10D_PARC_PCDATA1 _UL_(1 << 10) 1134 #define PIN_PC25D_PARC_PCDATA1 _L_(89) /**< \brief PARC signal: PCDATA1 on PC25 mux D */ 1135 #define MUX_PC25D_PARC_PCDATA1 _L_(3) 1136 #define PINMUX_PC25D_PARC_PCDATA1 ((PIN_PC25D_PARC_PCDATA1 << 16) | MUX_PC25D_PARC_PCDATA1) 1137 #define GPIO_PC25D_PARC_PCDATA1 _UL_(1 << 25) 1138 #define PIN_PA11D_PARC_PCDATA2 _L_(11) /**< \brief PARC signal: PCDATA2 on PA11 mux D */ 1139 #define MUX_PA11D_PARC_PCDATA2 _L_(3) 1140 #define PINMUX_PA11D_PARC_PCDATA2 ((PIN_PA11D_PARC_PCDATA2 << 16) | MUX_PA11D_PARC_PCDATA2) 1141 #define GPIO_PA11D_PARC_PCDATA2 _UL_(1 << 11) 1142 #define PIN_PC26D_PARC_PCDATA2 _L_(90) /**< \brief PARC signal: PCDATA2 on PC26 mux D */ 1143 #define MUX_PC26D_PARC_PCDATA2 _L_(3) 1144 #define PINMUX_PC26D_PARC_PCDATA2 ((PIN_PC26D_PARC_PCDATA2 << 16) | MUX_PC26D_PARC_PCDATA2) 1145 #define GPIO_PC26D_PARC_PCDATA2 _UL_(1 << 26) 1146 #define PIN_PA12D_PARC_PCDATA3 _L_(12) /**< \brief PARC signal: PCDATA3 on PA12 mux D */ 1147 #define MUX_PA12D_PARC_PCDATA3 _L_(3) 1148 #define PINMUX_PA12D_PARC_PCDATA3 ((PIN_PA12D_PARC_PCDATA3 << 16) | MUX_PA12D_PARC_PCDATA3) 1149 #define GPIO_PA12D_PARC_PCDATA3 _UL_(1 << 12) 1150 #define PIN_PC27D_PARC_PCDATA3 _L_(91) /**< \brief PARC signal: PCDATA3 on PC27 mux D */ 1151 #define MUX_PC27D_PARC_PCDATA3 _L_(3) 1152 #define PINMUX_PC27D_PARC_PCDATA3 ((PIN_PC27D_PARC_PCDATA3 << 16) | MUX_PC27D_PARC_PCDATA3) 1153 #define GPIO_PC27D_PARC_PCDATA3 _UL_(1 << 27) 1154 #define PIN_PA13D_PARC_PCDATA4 _L_(13) /**< \brief PARC signal: PCDATA4 on PA13 mux D */ 1155 #define MUX_PA13D_PARC_PCDATA4 _L_(3) 1156 #define PINMUX_PA13D_PARC_PCDATA4 ((PIN_PA13D_PARC_PCDATA4 << 16) | MUX_PA13D_PARC_PCDATA4) 1157 #define GPIO_PA13D_PARC_PCDATA4 _UL_(1 << 13) 1158 #define PIN_PC28D_PARC_PCDATA4 _L_(92) /**< \brief PARC signal: PCDATA4 on PC28 mux D */ 1159 #define MUX_PC28D_PARC_PCDATA4 _L_(3) 1160 #define PINMUX_PC28D_PARC_PCDATA4 ((PIN_PC28D_PARC_PCDATA4 << 16) | MUX_PC28D_PARC_PCDATA4) 1161 #define GPIO_PC28D_PARC_PCDATA4 _UL_(1 << 28) 1162 #define PIN_PA14D_PARC_PCDATA5 _L_(14) /**< \brief PARC signal: PCDATA5 on PA14 mux D */ 1163 #define MUX_PA14D_PARC_PCDATA5 _L_(3) 1164 #define PINMUX_PA14D_PARC_PCDATA5 ((PIN_PA14D_PARC_PCDATA5 << 16) | MUX_PA14D_PARC_PCDATA5) 1165 #define GPIO_PA14D_PARC_PCDATA5 _UL_(1 << 14) 1166 #define PIN_PC29D_PARC_PCDATA5 _L_(93) /**< \brief PARC signal: PCDATA5 on PC29 mux D */ 1167 #define MUX_PC29D_PARC_PCDATA5 _L_(3) 1168 #define PINMUX_PC29D_PARC_PCDATA5 ((PIN_PC29D_PARC_PCDATA5 << 16) | MUX_PC29D_PARC_PCDATA5) 1169 #define GPIO_PC29D_PARC_PCDATA5 _UL_(1 << 29) 1170 #define PIN_PA15D_PARC_PCDATA6 _L_(15) /**< \brief PARC signal: PCDATA6 on PA15 mux D */ 1171 #define MUX_PA15D_PARC_PCDATA6 _L_(3) 1172 #define PINMUX_PA15D_PARC_PCDATA6 ((PIN_PA15D_PARC_PCDATA6 << 16) | MUX_PA15D_PARC_PCDATA6) 1173 #define GPIO_PA15D_PARC_PCDATA6 _UL_(1 << 15) 1174 #define PIN_PC30D_PARC_PCDATA6 _L_(94) /**< \brief PARC signal: PCDATA6 on PC30 mux D */ 1175 #define MUX_PC30D_PARC_PCDATA6 _L_(3) 1176 #define PINMUX_PC30D_PARC_PCDATA6 ((PIN_PC30D_PARC_PCDATA6 << 16) | MUX_PC30D_PARC_PCDATA6) 1177 #define GPIO_PC30D_PARC_PCDATA6 _UL_(1 << 30) 1178 #define PIN_PA16D_PARC_PCDATA7 _L_(16) /**< \brief PARC signal: PCDATA7 on PA16 mux D */ 1179 #define MUX_PA16D_PARC_PCDATA7 _L_(3) 1180 #define PINMUX_PA16D_PARC_PCDATA7 ((PIN_PA16D_PARC_PCDATA7 << 16) | MUX_PA16D_PARC_PCDATA7) 1181 #define GPIO_PA16D_PARC_PCDATA7 _UL_(1 << 16) 1182 #define PIN_PC31D_PARC_PCDATA7 _L_(95) /**< \brief PARC signal: PCDATA7 on PC31 mux D */ 1183 #define MUX_PC31D_PARC_PCDATA7 _L_(3) 1184 #define PINMUX_PC31D_PARC_PCDATA7 ((PIN_PC31D_PARC_PCDATA7 << 16) | MUX_PC31D_PARC_PCDATA7) 1185 #define GPIO_PC31D_PARC_PCDATA7 _UL_(1 << 31) 1186 #define PIN_PA18D_PARC_PCEN1 _L_(18) /**< \brief PARC signal: PCEN1 on PA18 mux D */ 1187 #define MUX_PA18D_PARC_PCEN1 _L_(3) 1188 #define PINMUX_PA18D_PARC_PCEN1 ((PIN_PA18D_PARC_PCEN1 << 16) | MUX_PA18D_PARC_PCEN1) 1189 #define GPIO_PA18D_PARC_PCEN1 _UL_(1 << 18) 1190 #define PIN_PC22D_PARC_PCEN1 _L_(86) /**< \brief PARC signal: PCEN1 on PC22 mux D */ 1191 #define MUX_PC22D_PARC_PCEN1 _L_(3) 1192 #define PINMUX_PC22D_PARC_PCEN1 ((PIN_PC22D_PARC_PCEN1 << 16) | MUX_PC22D_PARC_PCEN1) 1193 #define GPIO_PC22D_PARC_PCEN1 _UL_(1 << 22) 1194 #define PIN_PA19D_PARC_PCEN2 _L_(19) /**< \brief PARC signal: PCEN2 on PA19 mux D */ 1195 #define MUX_PA19D_PARC_PCEN2 _L_(3) 1196 #define PINMUX_PA19D_PARC_PCEN2 ((PIN_PA19D_PARC_PCEN2 << 16) | MUX_PA19D_PARC_PCEN2) 1197 #define GPIO_PA19D_PARC_PCEN2 _UL_(1 << 19) 1198 #define PIN_PC23D_PARC_PCEN2 _L_(87) /**< \brief PARC signal: PCEN2 on PC23 mux D */ 1199 #define MUX_PC23D_PARC_PCEN2 _L_(3) 1200 #define PINMUX_PC23D_PARC_PCEN2 ((PIN_PC23D_PARC_PCEN2 << 16) | MUX_PC23D_PARC_PCEN2) 1201 #define GPIO_PC23D_PARC_PCEN2 _UL_(1 << 23) 1202 /* ========== GPIO definition for CATB peripheral ========== */ 1203 #define PIN_PA02G_CATB_DIS _L_(2) /**< \brief CATB signal: DIS on PA02 mux G */ 1204 #define MUX_PA02G_CATB_DIS _L_(6) 1205 #define PINMUX_PA02G_CATB_DIS ((PIN_PA02G_CATB_DIS << 16) | MUX_PA02G_CATB_DIS) 1206 #define GPIO_PA02G_CATB_DIS _UL_(1 << 2) 1207 #define PIN_PA12G_CATB_DIS _L_(12) /**< \brief CATB signal: DIS on PA12 mux G */ 1208 #define MUX_PA12G_CATB_DIS _L_(6) 1209 #define PINMUX_PA12G_CATB_DIS ((PIN_PA12G_CATB_DIS << 16) | MUX_PA12G_CATB_DIS) 1210 #define GPIO_PA12G_CATB_DIS _UL_(1 << 12) 1211 #define PIN_PA23G_CATB_DIS _L_(23) /**< \brief CATB signal: DIS on PA23 mux G */ 1212 #define MUX_PA23G_CATB_DIS _L_(6) 1213 #define PINMUX_PA23G_CATB_DIS ((PIN_PA23G_CATB_DIS << 16) | MUX_PA23G_CATB_DIS) 1214 #define GPIO_PA23G_CATB_DIS _UL_(1 << 23) 1215 #define PIN_PA31G_CATB_DIS _L_(31) /**< \brief CATB signal: DIS on PA31 mux G */ 1216 #define MUX_PA31G_CATB_DIS _L_(6) 1217 #define PINMUX_PA31G_CATB_DIS ((PIN_PA31G_CATB_DIS << 16) | MUX_PA31G_CATB_DIS) 1218 #define GPIO_PA31G_CATB_DIS _UL_(1 << 31) 1219 #define PIN_PB03G_CATB_DIS _L_(35) /**< \brief CATB signal: DIS on PB03 mux G */ 1220 #define MUX_PB03G_CATB_DIS _L_(6) 1221 #define PINMUX_PB03G_CATB_DIS ((PIN_PB03G_CATB_DIS << 16) | MUX_PB03G_CATB_DIS) 1222 #define GPIO_PB03G_CATB_DIS _UL_(1 << 3) 1223 #define PIN_PB12G_CATB_DIS _L_(44) /**< \brief CATB signal: DIS on PB12 mux G */ 1224 #define MUX_PB12G_CATB_DIS _L_(6) 1225 #define PINMUX_PB12G_CATB_DIS ((PIN_PB12G_CATB_DIS << 16) | MUX_PB12G_CATB_DIS) 1226 #define GPIO_PB12G_CATB_DIS _UL_(1 << 12) 1227 #define PIN_PC05G_CATB_DIS _L_(69) /**< \brief CATB signal: DIS on PC05 mux G */ 1228 #define MUX_PC05G_CATB_DIS _L_(6) 1229 #define PINMUX_PC05G_CATB_DIS ((PIN_PC05G_CATB_DIS << 16) | MUX_PC05G_CATB_DIS) 1230 #define GPIO_PC05G_CATB_DIS _UL_(1 << 5) 1231 #define PIN_PC14G_CATB_DIS _L_(78) /**< \brief CATB signal: DIS on PC14 mux G */ 1232 #define MUX_PC14G_CATB_DIS _L_(6) 1233 #define PINMUX_PC14G_CATB_DIS ((PIN_PC14G_CATB_DIS << 16) | MUX_PC14G_CATB_DIS) 1234 #define GPIO_PC14G_CATB_DIS _UL_(1 << 14) 1235 #define PIN_PC23G_CATB_DIS _L_(87) /**< \brief CATB signal: DIS on PC23 mux G */ 1236 #define MUX_PC23G_CATB_DIS _L_(6) 1237 #define PINMUX_PC23G_CATB_DIS ((PIN_PC23G_CATB_DIS << 16) | MUX_PC23G_CATB_DIS) 1238 #define GPIO_PC23G_CATB_DIS _UL_(1 << 23) 1239 #define PIN_PA04G_CATB_SENSE0 _L_(4) /**< \brief CATB signal: SENSE0 on PA04 mux G */ 1240 #define MUX_PA04G_CATB_SENSE0 _L_(6) 1241 #define PINMUX_PA04G_CATB_SENSE0 ((PIN_PA04G_CATB_SENSE0 << 16) | MUX_PA04G_CATB_SENSE0) 1242 #define GPIO_PA04G_CATB_SENSE0 _UL_(1 << 4) 1243 #define PIN_PA27G_CATB_SENSE0 _L_(27) /**< \brief CATB signal: SENSE0 on PA27 mux G */ 1244 #define MUX_PA27G_CATB_SENSE0 _L_(6) 1245 #define PINMUX_PA27G_CATB_SENSE0 ((PIN_PA27G_CATB_SENSE0 << 16) | MUX_PA27G_CATB_SENSE0) 1246 #define GPIO_PA27G_CATB_SENSE0 _UL_(1 << 27) 1247 #define PIN_PB13G_CATB_SENSE0 _L_(45) /**< \brief CATB signal: SENSE0 on PB13 mux G */ 1248 #define MUX_PB13G_CATB_SENSE0 _L_(6) 1249 #define PINMUX_PB13G_CATB_SENSE0 ((PIN_PB13G_CATB_SENSE0 << 16) | MUX_PB13G_CATB_SENSE0) 1250 #define GPIO_PB13G_CATB_SENSE0 _UL_(1 << 13) 1251 #define PIN_PA05G_CATB_SENSE1 _L_(5) /**< \brief CATB signal: SENSE1 on PA05 mux G */ 1252 #define MUX_PA05G_CATB_SENSE1 _L_(6) 1253 #define PINMUX_PA05G_CATB_SENSE1 ((PIN_PA05G_CATB_SENSE1 << 16) | MUX_PA05G_CATB_SENSE1) 1254 #define GPIO_PA05G_CATB_SENSE1 _UL_(1 << 5) 1255 #define PIN_PA28G_CATB_SENSE1 _L_(28) /**< \brief CATB signal: SENSE1 on PA28 mux G */ 1256 #define MUX_PA28G_CATB_SENSE1 _L_(6) 1257 #define PINMUX_PA28G_CATB_SENSE1 ((PIN_PA28G_CATB_SENSE1 << 16) | MUX_PA28G_CATB_SENSE1) 1258 #define GPIO_PA28G_CATB_SENSE1 _UL_(1 << 28) 1259 #define PIN_PB14G_CATB_SENSE1 _L_(46) /**< \brief CATB signal: SENSE1 on PB14 mux G */ 1260 #define MUX_PB14G_CATB_SENSE1 _L_(6) 1261 #define PINMUX_PB14G_CATB_SENSE1 ((PIN_PB14G_CATB_SENSE1 << 16) | MUX_PB14G_CATB_SENSE1) 1262 #define GPIO_PB14G_CATB_SENSE1 _UL_(1 << 14) 1263 #define PIN_PA06G_CATB_SENSE2 _L_(6) /**< \brief CATB signal: SENSE2 on PA06 mux G */ 1264 #define MUX_PA06G_CATB_SENSE2 _L_(6) 1265 #define PINMUX_PA06G_CATB_SENSE2 ((PIN_PA06G_CATB_SENSE2 << 16) | MUX_PA06G_CATB_SENSE2) 1266 #define GPIO_PA06G_CATB_SENSE2 _UL_(1 << 6) 1267 #define PIN_PA29G_CATB_SENSE2 _L_(29) /**< \brief CATB signal: SENSE2 on PA29 mux G */ 1268 #define MUX_PA29G_CATB_SENSE2 _L_(6) 1269 #define PINMUX_PA29G_CATB_SENSE2 ((PIN_PA29G_CATB_SENSE2 << 16) | MUX_PA29G_CATB_SENSE2) 1270 #define GPIO_PA29G_CATB_SENSE2 _UL_(1 << 29) 1271 #define PIN_PB15G_CATB_SENSE2 _L_(47) /**< \brief CATB signal: SENSE2 on PB15 mux G */ 1272 #define MUX_PB15G_CATB_SENSE2 _L_(6) 1273 #define PINMUX_PB15G_CATB_SENSE2 ((PIN_PB15G_CATB_SENSE2 << 16) | MUX_PB15G_CATB_SENSE2) 1274 #define GPIO_PB15G_CATB_SENSE2 _UL_(1 << 15) 1275 #define PIN_PA07G_CATB_SENSE3 _L_(7) /**< \brief CATB signal: SENSE3 on PA07 mux G */ 1276 #define MUX_PA07G_CATB_SENSE3 _L_(6) 1277 #define PINMUX_PA07G_CATB_SENSE3 ((PIN_PA07G_CATB_SENSE3 << 16) | MUX_PA07G_CATB_SENSE3) 1278 #define GPIO_PA07G_CATB_SENSE3 _UL_(1 << 7) 1279 #define PIN_PA30G_CATB_SENSE3 _L_(30) /**< \brief CATB signal: SENSE3 on PA30 mux G */ 1280 #define MUX_PA30G_CATB_SENSE3 _L_(6) 1281 #define PINMUX_PA30G_CATB_SENSE3 ((PIN_PA30G_CATB_SENSE3 << 16) | MUX_PA30G_CATB_SENSE3) 1282 #define GPIO_PA30G_CATB_SENSE3 _UL_(1 << 30) 1283 #define PIN_PC00G_CATB_SENSE3 _L_(64) /**< \brief CATB signal: SENSE3 on PC00 mux G */ 1284 #define MUX_PC00G_CATB_SENSE3 _L_(6) 1285 #define PINMUX_PC00G_CATB_SENSE3 ((PIN_PC00G_CATB_SENSE3 << 16) | MUX_PC00G_CATB_SENSE3) 1286 #define GPIO_PC00G_CATB_SENSE3 _UL_(1 << 0) 1287 #define PIN_PA08G_CATB_SENSE4 _L_(8) /**< \brief CATB signal: SENSE4 on PA08 mux G */ 1288 #define MUX_PA08G_CATB_SENSE4 _L_(6) 1289 #define PINMUX_PA08G_CATB_SENSE4 ((PIN_PA08G_CATB_SENSE4 << 16) | MUX_PA08G_CATB_SENSE4) 1290 #define GPIO_PA08G_CATB_SENSE4 _UL_(1 << 8) 1291 #define PIN_PC01G_CATB_SENSE4 _L_(65) /**< \brief CATB signal: SENSE4 on PC01 mux G */ 1292 #define MUX_PC01G_CATB_SENSE4 _L_(6) 1293 #define PINMUX_PC01G_CATB_SENSE4 ((PIN_PC01G_CATB_SENSE4 << 16) | MUX_PC01G_CATB_SENSE4) 1294 #define GPIO_PC01G_CATB_SENSE4 _UL_(1 << 1) 1295 #define PIN_PA09G_CATB_SENSE5 _L_(9) /**< \brief CATB signal: SENSE5 on PA09 mux G */ 1296 #define MUX_PA09G_CATB_SENSE5 _L_(6) 1297 #define PINMUX_PA09G_CATB_SENSE5 ((PIN_PA09G_CATB_SENSE5 << 16) | MUX_PA09G_CATB_SENSE5) 1298 #define GPIO_PA09G_CATB_SENSE5 _UL_(1 << 9) 1299 #define PIN_PC02G_CATB_SENSE5 _L_(66) /**< \brief CATB signal: SENSE5 on PC02 mux G */ 1300 #define MUX_PC02G_CATB_SENSE5 _L_(6) 1301 #define PINMUX_PC02G_CATB_SENSE5 ((PIN_PC02G_CATB_SENSE5 << 16) | MUX_PC02G_CATB_SENSE5) 1302 #define GPIO_PC02G_CATB_SENSE5 _UL_(1 << 2) 1303 #define PIN_PA10G_CATB_SENSE6 _L_(10) /**< \brief CATB signal: SENSE6 on PA10 mux G */ 1304 #define MUX_PA10G_CATB_SENSE6 _L_(6) 1305 #define PINMUX_PA10G_CATB_SENSE6 ((PIN_PA10G_CATB_SENSE6 << 16) | MUX_PA10G_CATB_SENSE6) 1306 #define GPIO_PA10G_CATB_SENSE6 _UL_(1 << 10) 1307 #define PIN_PC03G_CATB_SENSE6 _L_(67) /**< \brief CATB signal: SENSE6 on PC03 mux G */ 1308 #define MUX_PC03G_CATB_SENSE6 _L_(6) 1309 #define PINMUX_PC03G_CATB_SENSE6 ((PIN_PC03G_CATB_SENSE6 << 16) | MUX_PC03G_CATB_SENSE6) 1310 #define GPIO_PC03G_CATB_SENSE6 _UL_(1 << 3) 1311 #define PIN_PA11G_CATB_SENSE7 _L_(11) /**< \brief CATB signal: SENSE7 on PA11 mux G */ 1312 #define MUX_PA11G_CATB_SENSE7 _L_(6) 1313 #define PINMUX_PA11G_CATB_SENSE7 ((PIN_PA11G_CATB_SENSE7 << 16) | MUX_PA11G_CATB_SENSE7) 1314 #define GPIO_PA11G_CATB_SENSE7 _UL_(1 << 11) 1315 #define PIN_PC04G_CATB_SENSE7 _L_(68) /**< \brief CATB signal: SENSE7 on PC04 mux G */ 1316 #define MUX_PC04G_CATB_SENSE7 _L_(6) 1317 #define PINMUX_PC04G_CATB_SENSE7 ((PIN_PC04G_CATB_SENSE7 << 16) | MUX_PC04G_CATB_SENSE7) 1318 #define GPIO_PC04G_CATB_SENSE7 _UL_(1 << 4) 1319 #define PIN_PA13G_CATB_SENSE8 _L_(13) /**< \brief CATB signal: SENSE8 on PA13 mux G */ 1320 #define MUX_PA13G_CATB_SENSE8 _L_(6) 1321 #define PINMUX_PA13G_CATB_SENSE8 ((PIN_PA13G_CATB_SENSE8 << 16) | MUX_PA13G_CATB_SENSE8) 1322 #define GPIO_PA13G_CATB_SENSE8 _UL_(1 << 13) 1323 #define PIN_PC06G_CATB_SENSE8 _L_(70) /**< \brief CATB signal: SENSE8 on PC06 mux G */ 1324 #define MUX_PC06G_CATB_SENSE8 _L_(6) 1325 #define PINMUX_PC06G_CATB_SENSE8 ((PIN_PC06G_CATB_SENSE8 << 16) | MUX_PC06G_CATB_SENSE8) 1326 #define GPIO_PC06G_CATB_SENSE8 _UL_(1 << 6) 1327 #define PIN_PA14G_CATB_SENSE9 _L_(14) /**< \brief CATB signal: SENSE9 on PA14 mux G */ 1328 #define MUX_PA14G_CATB_SENSE9 _L_(6) 1329 #define PINMUX_PA14G_CATB_SENSE9 ((PIN_PA14G_CATB_SENSE9 << 16) | MUX_PA14G_CATB_SENSE9) 1330 #define GPIO_PA14G_CATB_SENSE9 _UL_(1 << 14) 1331 #define PIN_PC07G_CATB_SENSE9 _L_(71) /**< \brief CATB signal: SENSE9 on PC07 mux G */ 1332 #define MUX_PC07G_CATB_SENSE9 _L_(6) 1333 #define PINMUX_PC07G_CATB_SENSE9 ((PIN_PC07G_CATB_SENSE9 << 16) | MUX_PC07G_CATB_SENSE9) 1334 #define GPIO_PC07G_CATB_SENSE9 _UL_(1 << 7) 1335 #define PIN_PA15G_CATB_SENSE10 _L_(15) /**< \brief CATB signal: SENSE10 on PA15 mux G */ 1336 #define MUX_PA15G_CATB_SENSE10 _L_(6) 1337 #define PINMUX_PA15G_CATB_SENSE10 ((PIN_PA15G_CATB_SENSE10 << 16) | MUX_PA15G_CATB_SENSE10) 1338 #define GPIO_PA15G_CATB_SENSE10 _UL_(1 << 15) 1339 #define PIN_PC08G_CATB_SENSE10 _L_(72) /**< \brief CATB signal: SENSE10 on PC08 mux G */ 1340 #define MUX_PC08G_CATB_SENSE10 _L_(6) 1341 #define PINMUX_PC08G_CATB_SENSE10 ((PIN_PC08G_CATB_SENSE10 << 16) | MUX_PC08G_CATB_SENSE10) 1342 #define GPIO_PC08G_CATB_SENSE10 _UL_(1 << 8) 1343 #define PIN_PA16G_CATB_SENSE11 _L_(16) /**< \brief CATB signal: SENSE11 on PA16 mux G */ 1344 #define MUX_PA16G_CATB_SENSE11 _L_(6) 1345 #define PINMUX_PA16G_CATB_SENSE11 ((PIN_PA16G_CATB_SENSE11 << 16) | MUX_PA16G_CATB_SENSE11) 1346 #define GPIO_PA16G_CATB_SENSE11 _UL_(1 << 16) 1347 #define PIN_PC09G_CATB_SENSE11 _L_(73) /**< \brief CATB signal: SENSE11 on PC09 mux G */ 1348 #define MUX_PC09G_CATB_SENSE11 _L_(6) 1349 #define PINMUX_PC09G_CATB_SENSE11 ((PIN_PC09G_CATB_SENSE11 << 16) | MUX_PC09G_CATB_SENSE11) 1350 #define GPIO_PC09G_CATB_SENSE11 _UL_(1 << 9) 1351 #define PIN_PA17G_CATB_SENSE12 _L_(17) /**< \brief CATB signal: SENSE12 on PA17 mux G */ 1352 #define MUX_PA17G_CATB_SENSE12 _L_(6) 1353 #define PINMUX_PA17G_CATB_SENSE12 ((PIN_PA17G_CATB_SENSE12 << 16) | MUX_PA17G_CATB_SENSE12) 1354 #define GPIO_PA17G_CATB_SENSE12 _UL_(1 << 17) 1355 #define PIN_PC10G_CATB_SENSE12 _L_(74) /**< \brief CATB signal: SENSE12 on PC10 mux G */ 1356 #define MUX_PC10G_CATB_SENSE12 _L_(6) 1357 #define PINMUX_PC10G_CATB_SENSE12 ((PIN_PC10G_CATB_SENSE12 << 16) | MUX_PC10G_CATB_SENSE12) 1358 #define GPIO_PC10G_CATB_SENSE12 _UL_(1 << 10) 1359 #define PIN_PA18G_CATB_SENSE13 _L_(18) /**< \brief CATB signal: SENSE13 on PA18 mux G */ 1360 #define MUX_PA18G_CATB_SENSE13 _L_(6) 1361 #define PINMUX_PA18G_CATB_SENSE13 ((PIN_PA18G_CATB_SENSE13 << 16) | MUX_PA18G_CATB_SENSE13) 1362 #define GPIO_PA18G_CATB_SENSE13 _UL_(1 << 18) 1363 #define PIN_PC11G_CATB_SENSE13 _L_(75) /**< \brief CATB signal: SENSE13 on PC11 mux G */ 1364 #define MUX_PC11G_CATB_SENSE13 _L_(6) 1365 #define PINMUX_PC11G_CATB_SENSE13 ((PIN_PC11G_CATB_SENSE13 << 16) | MUX_PC11G_CATB_SENSE13) 1366 #define GPIO_PC11G_CATB_SENSE13 _UL_(1 << 11) 1367 #define PIN_PA19G_CATB_SENSE14 _L_(19) /**< \brief CATB signal: SENSE14 on PA19 mux G */ 1368 #define MUX_PA19G_CATB_SENSE14 _L_(6) 1369 #define PINMUX_PA19G_CATB_SENSE14 ((PIN_PA19G_CATB_SENSE14 << 16) | MUX_PA19G_CATB_SENSE14) 1370 #define GPIO_PA19G_CATB_SENSE14 _UL_(1 << 19) 1371 #define PIN_PC12G_CATB_SENSE14 _L_(76) /**< \brief CATB signal: SENSE14 on PC12 mux G */ 1372 #define MUX_PC12G_CATB_SENSE14 _L_(6) 1373 #define PINMUX_PC12G_CATB_SENSE14 ((PIN_PC12G_CATB_SENSE14 << 16) | MUX_PC12G_CATB_SENSE14) 1374 #define GPIO_PC12G_CATB_SENSE14 _UL_(1 << 12) 1375 #define PIN_PA20G_CATB_SENSE15 _L_(20) /**< \brief CATB signal: SENSE15 on PA20 mux G */ 1376 #define MUX_PA20G_CATB_SENSE15 _L_(6) 1377 #define PINMUX_PA20G_CATB_SENSE15 ((PIN_PA20G_CATB_SENSE15 << 16) | MUX_PA20G_CATB_SENSE15) 1378 #define GPIO_PA20G_CATB_SENSE15 _UL_(1 << 20) 1379 #define PIN_PC13G_CATB_SENSE15 _L_(77) /**< \brief CATB signal: SENSE15 on PC13 mux G */ 1380 #define MUX_PC13G_CATB_SENSE15 _L_(6) 1381 #define PINMUX_PC13G_CATB_SENSE15 ((PIN_PC13G_CATB_SENSE15 << 16) | MUX_PC13G_CATB_SENSE15) 1382 #define GPIO_PC13G_CATB_SENSE15 _UL_(1 << 13) 1383 #define PIN_PA21G_CATB_SENSE16 _L_(21) /**< \brief CATB signal: SENSE16 on PA21 mux G */ 1384 #define MUX_PA21G_CATB_SENSE16 _L_(6) 1385 #define PINMUX_PA21G_CATB_SENSE16 ((PIN_PA21G_CATB_SENSE16 << 16) | MUX_PA21G_CATB_SENSE16) 1386 #define GPIO_PA21G_CATB_SENSE16 _UL_(1 << 21) 1387 #define PIN_PC15G_CATB_SENSE16 _L_(79) /**< \brief CATB signal: SENSE16 on PC15 mux G */ 1388 #define MUX_PC15G_CATB_SENSE16 _L_(6) 1389 #define PINMUX_PC15G_CATB_SENSE16 ((PIN_PC15G_CATB_SENSE16 << 16) | MUX_PC15G_CATB_SENSE16) 1390 #define GPIO_PC15G_CATB_SENSE16 _UL_(1 << 15) 1391 #define PIN_PA22G_CATB_SENSE17 _L_(22) /**< \brief CATB signal: SENSE17 on PA22 mux G */ 1392 #define MUX_PA22G_CATB_SENSE17 _L_(6) 1393 #define PINMUX_PA22G_CATB_SENSE17 ((PIN_PA22G_CATB_SENSE17 << 16) | MUX_PA22G_CATB_SENSE17) 1394 #define GPIO_PA22G_CATB_SENSE17 _UL_(1 << 22) 1395 #define PIN_PC16G_CATB_SENSE17 _L_(80) /**< \brief CATB signal: SENSE17 on PC16 mux G */ 1396 #define MUX_PC16G_CATB_SENSE17 _L_(6) 1397 #define PINMUX_PC16G_CATB_SENSE17 ((PIN_PC16G_CATB_SENSE17 << 16) | MUX_PC16G_CATB_SENSE17) 1398 #define GPIO_PC16G_CATB_SENSE17 _UL_(1 << 16) 1399 #define PIN_PA24G_CATB_SENSE18 _L_(24) /**< \brief CATB signal: SENSE18 on PA24 mux G */ 1400 #define MUX_PA24G_CATB_SENSE18 _L_(6) 1401 #define PINMUX_PA24G_CATB_SENSE18 ((PIN_PA24G_CATB_SENSE18 << 16) | MUX_PA24G_CATB_SENSE18) 1402 #define GPIO_PA24G_CATB_SENSE18 _UL_(1 << 24) 1403 #define PIN_PC17G_CATB_SENSE18 _L_(81) /**< \brief CATB signal: SENSE18 on PC17 mux G */ 1404 #define MUX_PC17G_CATB_SENSE18 _L_(6) 1405 #define PINMUX_PC17G_CATB_SENSE18 ((PIN_PC17G_CATB_SENSE18 << 16) | MUX_PC17G_CATB_SENSE18) 1406 #define GPIO_PC17G_CATB_SENSE18 _UL_(1 << 17) 1407 #define PIN_PA25G_CATB_SENSE19 _L_(25) /**< \brief CATB signal: SENSE19 on PA25 mux G */ 1408 #define MUX_PA25G_CATB_SENSE19 _L_(6) 1409 #define PINMUX_PA25G_CATB_SENSE19 ((PIN_PA25G_CATB_SENSE19 << 16) | MUX_PA25G_CATB_SENSE19) 1410 #define GPIO_PA25G_CATB_SENSE19 _UL_(1 << 25) 1411 #define PIN_PC18G_CATB_SENSE19 _L_(82) /**< \brief CATB signal: SENSE19 on PC18 mux G */ 1412 #define MUX_PC18G_CATB_SENSE19 _L_(6) 1413 #define PINMUX_PC18G_CATB_SENSE19 ((PIN_PC18G_CATB_SENSE19 << 16) | MUX_PC18G_CATB_SENSE19) 1414 #define GPIO_PC18G_CATB_SENSE19 _UL_(1 << 18) 1415 #define PIN_PA26G_CATB_SENSE20 _L_(26) /**< \brief CATB signal: SENSE20 on PA26 mux G */ 1416 #define MUX_PA26G_CATB_SENSE20 _L_(6) 1417 #define PINMUX_PA26G_CATB_SENSE20 ((PIN_PA26G_CATB_SENSE20 << 16) | MUX_PA26G_CATB_SENSE20) 1418 #define GPIO_PA26G_CATB_SENSE20 _UL_(1 << 26) 1419 #define PIN_PC19G_CATB_SENSE20 _L_(83) /**< \brief CATB signal: SENSE20 on PC19 mux G */ 1420 #define MUX_PC19G_CATB_SENSE20 _L_(6) 1421 #define PINMUX_PC19G_CATB_SENSE20 ((PIN_PC19G_CATB_SENSE20 << 16) | MUX_PC19G_CATB_SENSE20) 1422 #define GPIO_PC19G_CATB_SENSE20 _UL_(1 << 19) 1423 #define PIN_PB00G_CATB_SENSE21 _L_(32) /**< \brief CATB signal: SENSE21 on PB00 mux G */ 1424 #define MUX_PB00G_CATB_SENSE21 _L_(6) 1425 #define PINMUX_PB00G_CATB_SENSE21 ((PIN_PB00G_CATB_SENSE21 << 16) | MUX_PB00G_CATB_SENSE21) 1426 #define GPIO_PB00G_CATB_SENSE21 _UL_(1 << 0) 1427 #define PIN_PC20G_CATB_SENSE21 _L_(84) /**< \brief CATB signal: SENSE21 on PC20 mux G */ 1428 #define MUX_PC20G_CATB_SENSE21 _L_(6) 1429 #define PINMUX_PC20G_CATB_SENSE21 ((PIN_PC20G_CATB_SENSE21 << 16) | MUX_PC20G_CATB_SENSE21) 1430 #define GPIO_PC20G_CATB_SENSE21 _UL_(1 << 20) 1431 #define PIN_PB01G_CATB_SENSE22 _L_(33) /**< \brief CATB signal: SENSE22 on PB01 mux G */ 1432 #define MUX_PB01G_CATB_SENSE22 _L_(6) 1433 #define PINMUX_PB01G_CATB_SENSE22 ((PIN_PB01G_CATB_SENSE22 << 16) | MUX_PB01G_CATB_SENSE22) 1434 #define GPIO_PB01G_CATB_SENSE22 _UL_(1 << 1) 1435 #define PIN_PC21G_CATB_SENSE22 _L_(85) /**< \brief CATB signal: SENSE22 on PC21 mux G */ 1436 #define MUX_PC21G_CATB_SENSE22 _L_(6) 1437 #define PINMUX_PC21G_CATB_SENSE22 ((PIN_PC21G_CATB_SENSE22 << 16) | MUX_PC21G_CATB_SENSE22) 1438 #define GPIO_PC21G_CATB_SENSE22 _UL_(1 << 21) 1439 #define PIN_PB02G_CATB_SENSE23 _L_(34) /**< \brief CATB signal: SENSE23 on PB02 mux G */ 1440 #define MUX_PB02G_CATB_SENSE23 _L_(6) 1441 #define PINMUX_PB02G_CATB_SENSE23 ((PIN_PB02G_CATB_SENSE23 << 16) | MUX_PB02G_CATB_SENSE23) 1442 #define GPIO_PB02G_CATB_SENSE23 _UL_(1 << 2) 1443 #define PIN_PC22G_CATB_SENSE23 _L_(86) /**< \brief CATB signal: SENSE23 on PC22 mux G */ 1444 #define MUX_PC22G_CATB_SENSE23 _L_(6) 1445 #define PINMUX_PC22G_CATB_SENSE23 ((PIN_PC22G_CATB_SENSE23 << 16) | MUX_PC22G_CATB_SENSE23) 1446 #define GPIO_PC22G_CATB_SENSE23 _UL_(1 << 22) 1447 #define PIN_PB04G_CATB_SENSE24 _L_(36) /**< \brief CATB signal: SENSE24 on PB04 mux G */ 1448 #define MUX_PB04G_CATB_SENSE24 _L_(6) 1449 #define PINMUX_PB04G_CATB_SENSE24 ((PIN_PB04G_CATB_SENSE24 << 16) | MUX_PB04G_CATB_SENSE24) 1450 #define GPIO_PB04G_CATB_SENSE24 _UL_(1 << 4) 1451 #define PIN_PC24G_CATB_SENSE24 _L_(88) /**< \brief CATB signal: SENSE24 on PC24 mux G */ 1452 #define MUX_PC24G_CATB_SENSE24 _L_(6) 1453 #define PINMUX_PC24G_CATB_SENSE24 ((PIN_PC24G_CATB_SENSE24 << 16) | MUX_PC24G_CATB_SENSE24) 1454 #define GPIO_PC24G_CATB_SENSE24 _UL_(1 << 24) 1455 #define PIN_PB05G_CATB_SENSE25 _L_(37) /**< \brief CATB signal: SENSE25 on PB05 mux G */ 1456 #define MUX_PB05G_CATB_SENSE25 _L_(6) 1457 #define PINMUX_PB05G_CATB_SENSE25 ((PIN_PB05G_CATB_SENSE25 << 16) | MUX_PB05G_CATB_SENSE25) 1458 #define GPIO_PB05G_CATB_SENSE25 _UL_(1 << 5) 1459 #define PIN_PC25G_CATB_SENSE25 _L_(89) /**< \brief CATB signal: SENSE25 on PC25 mux G */ 1460 #define MUX_PC25G_CATB_SENSE25 _L_(6) 1461 #define PINMUX_PC25G_CATB_SENSE25 ((PIN_PC25G_CATB_SENSE25 << 16) | MUX_PC25G_CATB_SENSE25) 1462 #define GPIO_PC25G_CATB_SENSE25 _UL_(1 << 25) 1463 #define PIN_PB06G_CATB_SENSE26 _L_(38) /**< \brief CATB signal: SENSE26 on PB06 mux G */ 1464 #define MUX_PB06G_CATB_SENSE26 _L_(6) 1465 #define PINMUX_PB06G_CATB_SENSE26 ((PIN_PB06G_CATB_SENSE26 << 16) | MUX_PB06G_CATB_SENSE26) 1466 #define GPIO_PB06G_CATB_SENSE26 _UL_(1 << 6) 1467 #define PIN_PC26G_CATB_SENSE26 _L_(90) /**< \brief CATB signal: SENSE26 on PC26 mux G */ 1468 #define MUX_PC26G_CATB_SENSE26 _L_(6) 1469 #define PINMUX_PC26G_CATB_SENSE26 ((PIN_PC26G_CATB_SENSE26 << 16) | MUX_PC26G_CATB_SENSE26) 1470 #define GPIO_PC26G_CATB_SENSE26 _UL_(1 << 26) 1471 #define PIN_PB07G_CATB_SENSE27 _L_(39) /**< \brief CATB signal: SENSE27 on PB07 mux G */ 1472 #define MUX_PB07G_CATB_SENSE27 _L_(6) 1473 #define PINMUX_PB07G_CATB_SENSE27 ((PIN_PB07G_CATB_SENSE27 << 16) | MUX_PB07G_CATB_SENSE27) 1474 #define GPIO_PB07G_CATB_SENSE27 _UL_(1 << 7) 1475 #define PIN_PC27G_CATB_SENSE27 _L_(91) /**< \brief CATB signal: SENSE27 on PC27 mux G */ 1476 #define MUX_PC27G_CATB_SENSE27 _L_(6) 1477 #define PINMUX_PC27G_CATB_SENSE27 ((PIN_PC27G_CATB_SENSE27 << 16) | MUX_PC27G_CATB_SENSE27) 1478 #define GPIO_PC27G_CATB_SENSE27 _UL_(1 << 27) 1479 #define PIN_PB08G_CATB_SENSE28 _L_(40) /**< \brief CATB signal: SENSE28 on PB08 mux G */ 1480 #define MUX_PB08G_CATB_SENSE28 _L_(6) 1481 #define PINMUX_PB08G_CATB_SENSE28 ((PIN_PB08G_CATB_SENSE28 << 16) | MUX_PB08G_CATB_SENSE28) 1482 #define GPIO_PB08G_CATB_SENSE28 _UL_(1 << 8) 1483 #define PIN_PC28G_CATB_SENSE28 _L_(92) /**< \brief CATB signal: SENSE28 on PC28 mux G */ 1484 #define MUX_PC28G_CATB_SENSE28 _L_(6) 1485 #define PINMUX_PC28G_CATB_SENSE28 ((PIN_PC28G_CATB_SENSE28 << 16) | MUX_PC28G_CATB_SENSE28) 1486 #define GPIO_PC28G_CATB_SENSE28 _UL_(1 << 28) 1487 #define PIN_PB09G_CATB_SENSE29 _L_(41) /**< \brief CATB signal: SENSE29 on PB09 mux G */ 1488 #define MUX_PB09G_CATB_SENSE29 _L_(6) 1489 #define PINMUX_PB09G_CATB_SENSE29 ((PIN_PB09G_CATB_SENSE29 << 16) | MUX_PB09G_CATB_SENSE29) 1490 #define GPIO_PB09G_CATB_SENSE29 _UL_(1 << 9) 1491 #define PIN_PC29G_CATB_SENSE29 _L_(93) /**< \brief CATB signal: SENSE29 on PC29 mux G */ 1492 #define MUX_PC29G_CATB_SENSE29 _L_(6) 1493 #define PINMUX_PC29G_CATB_SENSE29 ((PIN_PC29G_CATB_SENSE29 << 16) | MUX_PC29G_CATB_SENSE29) 1494 #define GPIO_PC29G_CATB_SENSE29 _UL_(1 << 29) 1495 #define PIN_PB10G_CATB_SENSE30 _L_(42) /**< \brief CATB signal: SENSE30 on PB10 mux G */ 1496 #define MUX_PB10G_CATB_SENSE30 _L_(6) 1497 #define PINMUX_PB10G_CATB_SENSE30 ((PIN_PB10G_CATB_SENSE30 << 16) | MUX_PB10G_CATB_SENSE30) 1498 #define GPIO_PB10G_CATB_SENSE30 _UL_(1 << 10) 1499 #define PIN_PC30G_CATB_SENSE30 _L_(94) /**< \brief CATB signal: SENSE30 on PC30 mux G */ 1500 #define MUX_PC30G_CATB_SENSE30 _L_(6) 1501 #define PINMUX_PC30G_CATB_SENSE30 ((PIN_PC30G_CATB_SENSE30 << 16) | MUX_PC30G_CATB_SENSE30) 1502 #define GPIO_PC30G_CATB_SENSE30 _UL_(1 << 30) 1503 #define PIN_PB11G_CATB_SENSE31 _L_(43) /**< \brief CATB signal: SENSE31 on PB11 mux G */ 1504 #define MUX_PB11G_CATB_SENSE31 _L_(6) 1505 #define PINMUX_PB11G_CATB_SENSE31 ((PIN_PB11G_CATB_SENSE31 << 16) | MUX_PB11G_CATB_SENSE31) 1506 #define GPIO_PB11G_CATB_SENSE31 _UL_(1 << 11) 1507 #define PIN_PC31G_CATB_SENSE31 _L_(95) /**< \brief CATB signal: SENSE31 on PC31 mux G */ 1508 #define MUX_PC31G_CATB_SENSE31 _L_(6) 1509 #define PINMUX_PC31G_CATB_SENSE31 ((PIN_PC31G_CATB_SENSE31 << 16) | MUX_PC31G_CATB_SENSE31) 1510 #define GPIO_PC31G_CATB_SENSE31 _UL_(1 << 31) 1511 /* ========== GPIO definition for USBC peripheral ========== */ 1512 #define PIN_PA25A_USBC_DM _L_(25) /**< \brief USBC signal: DM on PA25 mux A */ 1513 #define MUX_PA25A_USBC_DM _L_(0) 1514 #define PINMUX_PA25A_USBC_DM ((PIN_PA25A_USBC_DM << 16) | MUX_PA25A_USBC_DM) 1515 #define GPIO_PA25A_USBC_DM _UL_(1 << 25) 1516 #define PIN_PA26A_USBC_DP _L_(26) /**< \brief USBC signal: DP on PA26 mux A */ 1517 #define MUX_PA26A_USBC_DP _L_(0) 1518 #define PINMUX_PA26A_USBC_DP ((PIN_PA26A_USBC_DP << 16) | MUX_PA26A_USBC_DP) 1519 #define GPIO_PA26A_USBC_DP _UL_(1 << 26) 1520 /* ========== GPIO definition for PEVC peripheral ========== */ 1521 #define PIN_PA08C_PEVC_PAD_EVT0 _L_(8) /**< \brief PEVC signal: PAD_EVT0 on PA08 mux C */ 1522 #define MUX_PA08C_PEVC_PAD_EVT0 _L_(2) 1523 #define PINMUX_PA08C_PEVC_PAD_EVT0 ((PIN_PA08C_PEVC_PAD_EVT0 << 16) | MUX_PA08C_PEVC_PAD_EVT0) 1524 #define GPIO_PA08C_PEVC_PAD_EVT0 _UL_(1 << 8) 1525 #define PIN_PB12C_PEVC_PAD_EVT0 _L_(44) /**< \brief PEVC signal: PAD_EVT0 on PB12 mux C */ 1526 #define MUX_PB12C_PEVC_PAD_EVT0 _L_(2) 1527 #define PINMUX_PB12C_PEVC_PAD_EVT0 ((PIN_PB12C_PEVC_PAD_EVT0 << 16) | MUX_PB12C_PEVC_PAD_EVT0) 1528 #define GPIO_PB12C_PEVC_PAD_EVT0 _UL_(1 << 12) 1529 #define PIN_PC07C_PEVC_PAD_EVT0 _L_(71) /**< \brief PEVC signal: PAD_EVT0 on PC07 mux C */ 1530 #define MUX_PC07C_PEVC_PAD_EVT0 _L_(2) 1531 #define PINMUX_PC07C_PEVC_PAD_EVT0 ((PIN_PC07C_PEVC_PAD_EVT0 << 16) | MUX_PC07C_PEVC_PAD_EVT0) 1532 #define GPIO_PC07C_PEVC_PAD_EVT0 _UL_(1 << 7) 1533 #define PIN_PC24C_PEVC_PAD_EVT0 _L_(88) /**< \brief PEVC signal: PAD_EVT0 on PC24 mux C */ 1534 #define MUX_PC24C_PEVC_PAD_EVT0 _L_(2) 1535 #define PINMUX_PC24C_PEVC_PAD_EVT0 ((PIN_PC24C_PEVC_PAD_EVT0 << 16) | MUX_PC24C_PEVC_PAD_EVT0) 1536 #define GPIO_PC24C_PEVC_PAD_EVT0 _UL_(1 << 24) 1537 #define PIN_PA09C_PEVC_PAD_EVT1 _L_(9) /**< \brief PEVC signal: PAD_EVT1 on PA09 mux C */ 1538 #define MUX_PA09C_PEVC_PAD_EVT1 _L_(2) 1539 #define PINMUX_PA09C_PEVC_PAD_EVT1 ((PIN_PA09C_PEVC_PAD_EVT1 << 16) | MUX_PA09C_PEVC_PAD_EVT1) 1540 #define GPIO_PA09C_PEVC_PAD_EVT1 _UL_(1 << 9) 1541 #define PIN_PB13C_PEVC_PAD_EVT1 _L_(45) /**< \brief PEVC signal: PAD_EVT1 on PB13 mux C */ 1542 #define MUX_PB13C_PEVC_PAD_EVT1 _L_(2) 1543 #define PINMUX_PB13C_PEVC_PAD_EVT1 ((PIN_PB13C_PEVC_PAD_EVT1 << 16) | MUX_PB13C_PEVC_PAD_EVT1) 1544 #define GPIO_PB13C_PEVC_PAD_EVT1 _UL_(1 << 13) 1545 #define PIN_PC08C_PEVC_PAD_EVT1 _L_(72) /**< \brief PEVC signal: PAD_EVT1 on PC08 mux C */ 1546 #define MUX_PC08C_PEVC_PAD_EVT1 _L_(2) 1547 #define PINMUX_PC08C_PEVC_PAD_EVT1 ((PIN_PC08C_PEVC_PAD_EVT1 << 16) | MUX_PC08C_PEVC_PAD_EVT1) 1548 #define GPIO_PC08C_PEVC_PAD_EVT1 _UL_(1 << 8) 1549 #define PIN_PC25C_PEVC_PAD_EVT1 _L_(89) /**< \brief PEVC signal: PAD_EVT1 on PC25 mux C */ 1550 #define MUX_PC25C_PEVC_PAD_EVT1 _L_(2) 1551 #define PINMUX_PC25C_PEVC_PAD_EVT1 ((PIN_PC25C_PEVC_PAD_EVT1 << 16) | MUX_PC25C_PEVC_PAD_EVT1) 1552 #define GPIO_PC25C_PEVC_PAD_EVT1 _UL_(1 << 25) 1553 #define PIN_PA10C_PEVC_PAD_EVT2 _L_(10) /**< \brief PEVC signal: PAD_EVT2 on PA10 mux C */ 1554 #define MUX_PA10C_PEVC_PAD_EVT2 _L_(2) 1555 #define PINMUX_PA10C_PEVC_PAD_EVT2 ((PIN_PA10C_PEVC_PAD_EVT2 << 16) | MUX_PA10C_PEVC_PAD_EVT2) 1556 #define GPIO_PA10C_PEVC_PAD_EVT2 _UL_(1 << 10) 1557 #define PIN_PC11C_PEVC_PAD_EVT2 _L_(75) /**< \brief PEVC signal: PAD_EVT2 on PC11 mux C */ 1558 #define MUX_PC11C_PEVC_PAD_EVT2 _L_(2) 1559 #define PINMUX_PC11C_PEVC_PAD_EVT2 ((PIN_PC11C_PEVC_PAD_EVT2 << 16) | MUX_PC11C_PEVC_PAD_EVT2) 1560 #define GPIO_PC11C_PEVC_PAD_EVT2 _UL_(1 << 11) 1561 #define PIN_PC26C_PEVC_PAD_EVT2 _L_(90) /**< \brief PEVC signal: PAD_EVT2 on PC26 mux C */ 1562 #define MUX_PC26C_PEVC_PAD_EVT2 _L_(2) 1563 #define PINMUX_PC26C_PEVC_PAD_EVT2 ((PIN_PC26C_PEVC_PAD_EVT2 << 16) | MUX_PC26C_PEVC_PAD_EVT2) 1564 #define GPIO_PC26C_PEVC_PAD_EVT2 _UL_(1 << 26) 1565 #define PIN_PB09B_PEVC_PAD_EVT2 _L_(41) /**< \brief PEVC signal: PAD_EVT2 on PB09 mux B */ 1566 #define MUX_PB09B_PEVC_PAD_EVT2 _L_(1) 1567 #define PINMUX_PB09B_PEVC_PAD_EVT2 ((PIN_PB09B_PEVC_PAD_EVT2 << 16) | MUX_PB09B_PEVC_PAD_EVT2) 1568 #define GPIO_PB09B_PEVC_PAD_EVT2 _UL_(1 << 9) 1569 #define PIN_PA11C_PEVC_PAD_EVT3 _L_(11) /**< \brief PEVC signal: PAD_EVT3 on PA11 mux C */ 1570 #define MUX_PA11C_PEVC_PAD_EVT3 _L_(2) 1571 #define PINMUX_PA11C_PEVC_PAD_EVT3 ((PIN_PA11C_PEVC_PAD_EVT3 << 16) | MUX_PA11C_PEVC_PAD_EVT3) 1572 #define GPIO_PA11C_PEVC_PAD_EVT3 _UL_(1 << 11) 1573 #define PIN_PC27C_PEVC_PAD_EVT3 _L_(91) /**< \brief PEVC signal: PAD_EVT3 on PC27 mux C */ 1574 #define MUX_PC27C_PEVC_PAD_EVT3 _L_(2) 1575 #define PINMUX_PC27C_PEVC_PAD_EVT3 ((PIN_PC27C_PEVC_PAD_EVT3 << 16) | MUX_PC27C_PEVC_PAD_EVT3) 1576 #define GPIO_PC27C_PEVC_PAD_EVT3 _UL_(1 << 27) 1577 #define PIN_PB10B_PEVC_PAD_EVT3 _L_(42) /**< \brief PEVC signal: PAD_EVT3 on PB10 mux B */ 1578 #define MUX_PB10B_PEVC_PAD_EVT3 _L_(1) 1579 #define PINMUX_PB10B_PEVC_PAD_EVT3 ((PIN_PB10B_PEVC_PAD_EVT3 << 16) | MUX_PB10B_PEVC_PAD_EVT3) 1580 #define GPIO_PB10B_PEVC_PAD_EVT3 _UL_(1 << 10) 1581 /* ========== GPIO definition for SCIF peripheral ========== */ 1582 #define PIN_PA19E_SCIF_GCLK0 _L_(19) /**< \brief SCIF signal: GCLK0 on PA19 mux E */ 1583 #define MUX_PA19E_SCIF_GCLK0 _L_(4) 1584 #define PINMUX_PA19E_SCIF_GCLK0 ((PIN_PA19E_SCIF_GCLK0 << 16) | MUX_PA19E_SCIF_GCLK0) 1585 #define GPIO_PA19E_SCIF_GCLK0 _UL_(1 << 19) 1586 #define PIN_PB10E_SCIF_GCLK0 _L_(42) /**< \brief SCIF signal: GCLK0 on PB10 mux E */ 1587 #define MUX_PB10E_SCIF_GCLK0 _L_(4) 1588 #define PINMUX_PB10E_SCIF_GCLK0 ((PIN_PB10E_SCIF_GCLK0 << 16) | MUX_PB10E_SCIF_GCLK0) 1589 #define GPIO_PB10E_SCIF_GCLK0 _UL_(1 << 10) 1590 #define PIN_PC26E_SCIF_GCLK0 _L_(90) /**< \brief SCIF signal: GCLK0 on PC26 mux E */ 1591 #define MUX_PC26E_SCIF_GCLK0 _L_(4) 1592 #define PINMUX_PC26E_SCIF_GCLK0 ((PIN_PC26E_SCIF_GCLK0 << 16) | MUX_PC26E_SCIF_GCLK0) 1593 #define GPIO_PC26E_SCIF_GCLK0 _UL_(1 << 26) 1594 #define PIN_PA02A_SCIF_GCLK0 _L_(2) /**< \brief SCIF signal: GCLK0 on PA02 mux A */ 1595 #define MUX_PA02A_SCIF_GCLK0 _L_(0) 1596 #define PINMUX_PA02A_SCIF_GCLK0 ((PIN_PA02A_SCIF_GCLK0 << 16) | MUX_PA02A_SCIF_GCLK0) 1597 #define GPIO_PA02A_SCIF_GCLK0 _UL_(1 << 2) 1598 #define PIN_PA20E_SCIF_GCLK1 _L_(20) /**< \brief SCIF signal: GCLK1 on PA20 mux E */ 1599 #define MUX_PA20E_SCIF_GCLK1 _L_(4) 1600 #define PINMUX_PA20E_SCIF_GCLK1 ((PIN_PA20E_SCIF_GCLK1 << 16) | MUX_PA20E_SCIF_GCLK1) 1601 #define GPIO_PA20E_SCIF_GCLK1 _UL_(1 << 20) 1602 #define PIN_PB11E_SCIF_GCLK1 _L_(43) /**< \brief SCIF signal: GCLK1 on PB11 mux E */ 1603 #define MUX_PB11E_SCIF_GCLK1 _L_(4) 1604 #define PINMUX_PB11E_SCIF_GCLK1 ((PIN_PB11E_SCIF_GCLK1 << 16) | MUX_PB11E_SCIF_GCLK1) 1605 #define GPIO_PB11E_SCIF_GCLK1 _UL_(1 << 11) 1606 #define PIN_PC27E_SCIF_GCLK1 _L_(91) /**< \brief SCIF signal: GCLK1 on PC27 mux E */ 1607 #define MUX_PC27E_SCIF_GCLK1 _L_(4) 1608 #define PINMUX_PC27E_SCIF_GCLK1 ((PIN_PC27E_SCIF_GCLK1 << 16) | MUX_PC27E_SCIF_GCLK1) 1609 #define GPIO_PC27E_SCIF_GCLK1 _UL_(1 << 27) 1610 #define PIN_PB12E_SCIF_GCLK2 _L_(44) /**< \brief SCIF signal: GCLK2 on PB12 mux E */ 1611 #define MUX_PB12E_SCIF_GCLK2 _L_(4) 1612 #define PINMUX_PB12E_SCIF_GCLK2 ((PIN_PB12E_SCIF_GCLK2 << 16) | MUX_PB12E_SCIF_GCLK2) 1613 #define GPIO_PB12E_SCIF_GCLK2 _UL_(1 << 12) 1614 #define PIN_PC28E_SCIF_GCLK2 _L_(92) /**< \brief SCIF signal: GCLK2 on PC28 mux E */ 1615 #define MUX_PC28E_SCIF_GCLK2 _L_(4) 1616 #define PINMUX_PC28E_SCIF_GCLK2 ((PIN_PC28E_SCIF_GCLK2 << 16) | MUX_PC28E_SCIF_GCLK2) 1617 #define GPIO_PC28E_SCIF_GCLK2 _UL_(1 << 28) 1618 #define PIN_PB13E_SCIF_GCLK3 _L_(45) /**< \brief SCIF signal: GCLK3 on PB13 mux E */ 1619 #define MUX_PB13E_SCIF_GCLK3 _L_(4) 1620 #define PINMUX_PB13E_SCIF_GCLK3 ((PIN_PB13E_SCIF_GCLK3 << 16) | MUX_PB13E_SCIF_GCLK3) 1621 #define GPIO_PB13E_SCIF_GCLK3 _UL_(1 << 13) 1622 #define PIN_PC29E_SCIF_GCLK3 _L_(93) /**< \brief SCIF signal: GCLK3 on PC29 mux E */ 1623 #define MUX_PC29E_SCIF_GCLK3 _L_(4) 1624 #define PINMUX_PC29E_SCIF_GCLK3 ((PIN_PC29E_SCIF_GCLK3 << 16) | MUX_PC29E_SCIF_GCLK3) 1625 #define GPIO_PC29E_SCIF_GCLK3 _UL_(1 << 29) 1626 #define PIN_PA23E_SCIF_GCLK_IN0 _L_(23) /**< \brief SCIF signal: GCLK_IN0 on PA23 mux E */ 1627 #define MUX_PA23E_SCIF_GCLK_IN0 _L_(4) 1628 #define PINMUX_PA23E_SCIF_GCLK_IN0 ((PIN_PA23E_SCIF_GCLK_IN0 << 16) | MUX_PA23E_SCIF_GCLK_IN0) 1629 #define GPIO_PA23E_SCIF_GCLK_IN0 _UL_(1 << 23) 1630 #define PIN_PB14E_SCIF_GCLK_IN0 _L_(46) /**< \brief SCIF signal: GCLK_IN0 on PB14 mux E */ 1631 #define MUX_PB14E_SCIF_GCLK_IN0 _L_(4) 1632 #define PINMUX_PB14E_SCIF_GCLK_IN0 ((PIN_PB14E_SCIF_GCLK_IN0 << 16) | MUX_PB14E_SCIF_GCLK_IN0) 1633 #define GPIO_PB14E_SCIF_GCLK_IN0 _UL_(1 << 14) 1634 #define PIN_PC30E_SCIF_GCLK_IN0 _L_(94) /**< \brief SCIF signal: GCLK_IN0 on PC30 mux E */ 1635 #define MUX_PC30E_SCIF_GCLK_IN0 _L_(4) 1636 #define PINMUX_PC30E_SCIF_GCLK_IN0 ((PIN_PC30E_SCIF_GCLK_IN0 << 16) | MUX_PC30E_SCIF_GCLK_IN0) 1637 #define GPIO_PC30E_SCIF_GCLK_IN0 _UL_(1 << 30) 1638 #define PIN_PA24E_SCIF_GCLK_IN1 _L_(24) /**< \brief SCIF signal: GCLK_IN1 on PA24 mux E */ 1639 #define MUX_PA24E_SCIF_GCLK_IN1 _L_(4) 1640 #define PINMUX_PA24E_SCIF_GCLK_IN1 ((PIN_PA24E_SCIF_GCLK_IN1 << 16) | MUX_PA24E_SCIF_GCLK_IN1) 1641 #define GPIO_PA24E_SCIF_GCLK_IN1 _UL_(1 << 24) 1642 #define PIN_PB15E_SCIF_GCLK_IN1 _L_(47) /**< \brief SCIF signal: GCLK_IN1 on PB15 mux E */ 1643 #define MUX_PB15E_SCIF_GCLK_IN1 _L_(4) 1644 #define PINMUX_PB15E_SCIF_GCLK_IN1 ((PIN_PB15E_SCIF_GCLK_IN1 << 16) | MUX_PB15E_SCIF_GCLK_IN1) 1645 #define GPIO_PB15E_SCIF_GCLK_IN1 _UL_(1 << 15) 1646 #define PIN_PC31E_SCIF_GCLK_IN1 _L_(95) /**< \brief SCIF signal: GCLK_IN1 on PC31 mux E */ 1647 #define MUX_PC31E_SCIF_GCLK_IN1 _L_(4) 1648 #define PINMUX_PC31E_SCIF_GCLK_IN1 ((PIN_PC31E_SCIF_GCLK_IN1 << 16) | MUX_PC31E_SCIF_GCLK_IN1) 1649 #define GPIO_PC31E_SCIF_GCLK_IN1 _UL_(1 << 31) 1650 /* ========== GPIO definition for EIC peripheral ========== */ 1651 #define PIN_PB01C_EIC_EXTINT0 _L_(33) /**< \brief EIC signal: EXTINT0 on PB01 mux C */ 1652 #define MUX_PB01C_EIC_EXTINT0 _L_(2) 1653 #define PINMUX_PB01C_EIC_EXTINT0 ((PIN_PB01C_EIC_EXTINT0 << 16) | MUX_PB01C_EIC_EXTINT0) 1654 #define GPIO_PB01C_EIC_EXTINT0 _UL_(1 << 1) 1655 #define PIN_PB01C_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB01 External Interrupt Line */ 1656 #define PIN_PA06C_EIC_EXTINT1 _L_(6) /**< \brief EIC signal: EXTINT1 on PA06 mux C */ 1657 #define MUX_PA06C_EIC_EXTINT1 _L_(2) 1658 #define PINMUX_PA06C_EIC_EXTINT1 ((PIN_PA06C_EIC_EXTINT1 << 16) | MUX_PA06C_EIC_EXTINT1) 1659 #define GPIO_PA06C_EIC_EXTINT1 _UL_(1 << 6) 1660 #define PIN_PA06C_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ 1661 #define PIN_PA16C_EIC_EXTINT1 _L_(16) /**< \brief EIC signal: EXTINT1 on PA16 mux C */ 1662 #define MUX_PA16C_EIC_EXTINT1 _L_(2) 1663 #define PINMUX_PA16C_EIC_EXTINT1 ((PIN_PA16C_EIC_EXTINT1 << 16) | MUX_PA16C_EIC_EXTINT1) 1664 #define GPIO_PA16C_EIC_EXTINT1 _UL_(1 << 16) 1665 #define PIN_PA16C_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ 1666 #define PIN_PC24B_EIC_EXTINT1 _L_(88) /**< \brief EIC signal: EXTINT1 on PC24 mux B */ 1667 #define MUX_PC24B_EIC_EXTINT1 _L_(1) 1668 #define PINMUX_PC24B_EIC_EXTINT1 ((PIN_PC24B_EIC_EXTINT1 << 16) | MUX_PC24B_EIC_EXTINT1) 1669 #define GPIO_PC24B_EIC_EXTINT1 _UL_(1 << 24) 1670 #define PIN_PC24B_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC24 External Interrupt Line */ 1671 #define PIN_PA04C_EIC_EXTINT2 _L_(4) /**< \brief EIC signal: EXTINT2 on PA04 mux C */ 1672 #define MUX_PA04C_EIC_EXTINT2 _L_(2) 1673 #define PINMUX_PA04C_EIC_EXTINT2 ((PIN_PA04C_EIC_EXTINT2 << 16) | MUX_PA04C_EIC_EXTINT2) 1674 #define GPIO_PA04C_EIC_EXTINT2 _UL_(1 << 4) 1675 #define PIN_PA04C_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */ 1676 #define PIN_PA17C_EIC_EXTINT2 _L_(17) /**< \brief EIC signal: EXTINT2 on PA17 mux C */ 1677 #define MUX_PA17C_EIC_EXTINT2 _L_(2) 1678 #define PINMUX_PA17C_EIC_EXTINT2 ((PIN_PA17C_EIC_EXTINT2 << 16) | MUX_PA17C_EIC_EXTINT2) 1679 #define GPIO_PA17C_EIC_EXTINT2 _UL_(1 << 17) 1680 #define PIN_PA17C_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ 1681 #define PIN_PC25B_EIC_EXTINT2 _L_(89) /**< \brief EIC signal: EXTINT2 on PC25 mux B */ 1682 #define MUX_PC25B_EIC_EXTINT2 _L_(1) 1683 #define PINMUX_PC25B_EIC_EXTINT2 ((PIN_PC25B_EIC_EXTINT2 << 16) | MUX_PC25B_EIC_EXTINT2) 1684 #define GPIO_PC25B_EIC_EXTINT2 _UL_(1 << 25) 1685 #define PIN_PC25B_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC25 External Interrupt Line */ 1686 #define PIN_PA05C_EIC_EXTINT3 _L_(5) /**< \brief EIC signal: EXTINT3 on PA05 mux C */ 1687 #define MUX_PA05C_EIC_EXTINT3 _L_(2) 1688 #define PINMUX_PA05C_EIC_EXTINT3 ((PIN_PA05C_EIC_EXTINT3 << 16) | MUX_PA05C_EIC_EXTINT3) 1689 #define GPIO_PA05C_EIC_EXTINT3 _UL_(1 << 5) 1690 #define PIN_PA05C_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */ 1691 #define PIN_PA18C_EIC_EXTINT3 _L_(18) /**< \brief EIC signal: EXTINT3 on PA18 mux C */ 1692 #define MUX_PA18C_EIC_EXTINT3 _L_(2) 1693 #define PINMUX_PA18C_EIC_EXTINT3 ((PIN_PA18C_EIC_EXTINT3 << 16) | MUX_PA18C_EIC_EXTINT3) 1694 #define GPIO_PA18C_EIC_EXTINT3 _UL_(1 << 18) 1695 #define PIN_PA18C_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ 1696 #define PIN_PC26B_EIC_EXTINT3 _L_(90) /**< \brief EIC signal: EXTINT3 on PC26 mux B */ 1697 #define MUX_PC26B_EIC_EXTINT3 _L_(1) 1698 #define PINMUX_PC26B_EIC_EXTINT3 ((PIN_PC26B_EIC_EXTINT3 << 16) | MUX_PC26B_EIC_EXTINT3) 1699 #define GPIO_PC26B_EIC_EXTINT3 _UL_(1 << 26) 1700 #define PIN_PC26B_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC26 External Interrupt Line */ 1701 #define PIN_PA07C_EIC_EXTINT4 _L_(7) /**< \brief EIC signal: EXTINT4 on PA07 mux C */ 1702 #define MUX_PA07C_EIC_EXTINT4 _L_(2) 1703 #define PINMUX_PA07C_EIC_EXTINT4 ((PIN_PA07C_EIC_EXTINT4 << 16) | MUX_PA07C_EIC_EXTINT4) 1704 #define GPIO_PA07C_EIC_EXTINT4 _UL_(1 << 7) 1705 #define PIN_PA07C_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ 1706 #define PIN_PA19C_EIC_EXTINT4 _L_(19) /**< \brief EIC signal: EXTINT4 on PA19 mux C */ 1707 #define MUX_PA19C_EIC_EXTINT4 _L_(2) 1708 #define PINMUX_PA19C_EIC_EXTINT4 ((PIN_PA19C_EIC_EXTINT4 << 16) | MUX_PA19C_EIC_EXTINT4) 1709 #define GPIO_PA19C_EIC_EXTINT4 _UL_(1 << 19) 1710 #define PIN_PA19C_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ 1711 #define PIN_PC27B_EIC_EXTINT4 _L_(91) /**< \brief EIC signal: EXTINT4 on PC27 mux B */ 1712 #define MUX_PC27B_EIC_EXTINT4 _L_(1) 1713 #define PINMUX_PC27B_EIC_EXTINT4 ((PIN_PC27B_EIC_EXTINT4 << 16) | MUX_PC27B_EIC_EXTINT4) 1714 #define GPIO_PC27B_EIC_EXTINT4 _UL_(1 << 27) 1715 #define PIN_PC27B_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PC27 External Interrupt Line */ 1716 #define PIN_PA20C_EIC_EXTINT5 _L_(20) /**< \brief EIC signal: EXTINT5 on PA20 mux C */ 1717 #define MUX_PA20C_EIC_EXTINT5 _L_(2) 1718 #define PINMUX_PA20C_EIC_EXTINT5 ((PIN_PA20C_EIC_EXTINT5 << 16) | MUX_PA20C_EIC_EXTINT5) 1719 #define GPIO_PA20C_EIC_EXTINT5 _UL_(1 << 20) 1720 #define PIN_PA20C_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */ 1721 #define PIN_PC03B_EIC_EXTINT5 _L_(67) /**< \brief EIC signal: EXTINT5 on PC03 mux B */ 1722 #define MUX_PC03B_EIC_EXTINT5 _L_(1) 1723 #define PINMUX_PC03B_EIC_EXTINT5 ((PIN_PC03B_EIC_EXTINT5 << 16) | MUX_PC03B_EIC_EXTINT5) 1724 #define GPIO_PC03B_EIC_EXTINT5 _UL_(1 << 3) 1725 #define PIN_PC03B_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PC03 External Interrupt Line */ 1726 #define PIN_PA21C_EIC_EXTINT6 _L_(21) /**< \brief EIC signal: EXTINT6 on PA21 mux C */ 1727 #define MUX_PA21C_EIC_EXTINT6 _L_(2) 1728 #define PINMUX_PA21C_EIC_EXTINT6 ((PIN_PA21C_EIC_EXTINT6 << 16) | MUX_PA21C_EIC_EXTINT6) 1729 #define GPIO_PA21C_EIC_EXTINT6 _UL_(1 << 21) 1730 #define PIN_PA21C_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */ 1731 #define PIN_PC04B_EIC_EXTINT6 _L_(68) /**< \brief EIC signal: EXTINT6 on PC04 mux B */ 1732 #define MUX_PC04B_EIC_EXTINT6 _L_(1) 1733 #define PINMUX_PC04B_EIC_EXTINT6 ((PIN_PC04B_EIC_EXTINT6 << 16) | MUX_PC04B_EIC_EXTINT6) 1734 #define GPIO_PC04B_EIC_EXTINT6 _UL_(1 << 4) 1735 #define PIN_PC04B_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PC04 External Interrupt Line */ 1736 #define PIN_PA22C_EIC_EXTINT7 _L_(22) /**< \brief EIC signal: EXTINT7 on PA22 mux C */ 1737 #define MUX_PA22C_EIC_EXTINT7 _L_(2) 1738 #define PINMUX_PA22C_EIC_EXTINT7 ((PIN_PA22C_EIC_EXTINT7 << 16) | MUX_PA22C_EIC_EXTINT7) 1739 #define GPIO_PA22C_EIC_EXTINT7 _UL_(1 << 22) 1740 #define PIN_PA22C_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */ 1741 #define PIN_PC05B_EIC_EXTINT7 _L_(69) /**< \brief EIC signal: EXTINT7 on PC05 mux B */ 1742 #define MUX_PC05B_EIC_EXTINT7 _L_(1) 1743 #define PINMUX_PC05B_EIC_EXTINT7 ((PIN_PC05B_EIC_EXTINT7 << 16) | MUX_PC05B_EIC_EXTINT7) 1744 #define GPIO_PC05B_EIC_EXTINT7 _UL_(1 << 5) 1745 #define PIN_PC05B_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PC05 External Interrupt Line */ 1746 #define PIN_PA23C_EIC_EXTINT8 _L_(23) /**< \brief EIC signal: EXTINT8 on PA23 mux C */ 1747 #define MUX_PA23C_EIC_EXTINT8 _L_(2) 1748 #define PINMUX_PA23C_EIC_EXTINT8 ((PIN_PA23C_EIC_EXTINT8 << 16) | MUX_PA23C_EIC_EXTINT8) 1749 #define GPIO_PA23C_EIC_EXTINT8 _UL_(1 << 23) 1750 #define PIN_PA23C_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */ 1751 #define PIN_PC06B_EIC_EXTINT8 _L_(70) /**< \brief EIC signal: EXTINT8 on PC06 mux B */ 1752 #define MUX_PC06B_EIC_EXTINT8 _L_(1) 1753 #define PINMUX_PC06B_EIC_EXTINT8 ((PIN_PC06B_EIC_EXTINT8 << 16) | MUX_PC06B_EIC_EXTINT8) 1754 #define GPIO_PC06B_EIC_EXTINT8 _UL_(1 << 6) 1755 #define PIN_PC06B_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PC06 External Interrupt Line */ 1756 1757 #endif /* _SAM4LS4C_PIO_ */ 1758
