1 /* ---------------------------------------------------------------------------- */ 2 /* Atmel Microcontroller Software Support */ 3 /* SAM Software Package License */ 4 /* ---------------------------------------------------------------------------- */ 5 /* Copyright (c) %copyright_year%, Atmel Corporation */ 6 /* */ 7 /* All rights reserved. */ 8 /* */ 9 /* Redistribution and use in source and binary forms, with or without */ 10 /* modification, are permitted provided that the following condition is met: */ 11 /* */ 12 /* - Redistributions of source code must retain the above copyright notice, */ 13 /* this list of conditions and the disclaimer below. */ 14 /* */ 15 /* Atmel's name may not be used to endorse or promote products derived from */ 16 /* this software without specific prior written permission. */ 17 /* */ 18 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ 19 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ 20 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ 21 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ 22 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ 23 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ 24 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ 25 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ 26 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ 27 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ 28 /* ---------------------------------------------------------------------------- */ 29 30 #ifndef _SAM4E_UART1_INSTANCE_ 31 #define _SAM4E_UART1_INSTANCE_ 32 33 /* ========== Register definition for UART1 peripheral ========== */ 34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 35 #define REG_UART1_CR (0x40060600U) /**< \brief (UART1) Control Register */ 36 #define REG_UART1_MR (0x40060604U) /**< \brief (UART1) Mode Register */ 37 #define REG_UART1_IER (0x40060608U) /**< \brief (UART1) Interrupt Enable Register */ 38 #define REG_UART1_IDR (0x4006060CU) /**< \brief (UART1) Interrupt Disable Register */ 39 #define REG_UART1_IMR (0x40060610U) /**< \brief (UART1) Interrupt Mask Register */ 40 #define REG_UART1_SR (0x40060614U) /**< \brief (UART1) Status Register */ 41 #define REG_UART1_RHR (0x40060618U) /**< \brief (UART1) Receive Holding Register */ 42 #define REG_UART1_THR (0x4006061CU) /**< \brief (UART1) Transmit Holding Register */ 43 #define REG_UART1_BRGR (0x40060620U) /**< \brief (UART1) Baud Rate Generator Register */ 44 #define REG_UART1_RPR (0x40060700U) /**< \brief (UART1) Receive Pointer Register */ 45 #define REG_UART1_RCR (0x40060704U) /**< \brief (UART1) Receive Counter Register */ 46 #define REG_UART1_TPR (0x40060708U) /**< \brief (UART1) Transmit Pointer Register */ 47 #define REG_UART1_TCR (0x4006070CU) /**< \brief (UART1) Transmit Counter Register */ 48 #define REG_UART1_RNPR (0x40060710U) /**< \brief (UART1) Receive Next Pointer Register */ 49 #define REG_UART1_RNCR (0x40060714U) /**< \brief (UART1) Receive Next Counter Register */ 50 #define REG_UART1_TNPR (0x40060718U) /**< \brief (UART1) Transmit Next Pointer Register */ 51 #define REG_UART1_TNCR (0x4006071CU) /**< \brief (UART1) Transmit Next Counter Register */ 52 #define REG_UART1_PTCR (0x40060720U) /**< \brief (UART1) Transfer Control Register */ 53 #define REG_UART1_PTSR (0x40060724U) /**< \brief (UART1) Transfer Status Register */ 54 #else 55 #define REG_UART1_CR (*(WoReg*)0x40060600U) /**< \brief (UART1) Control Register */ 56 #define REG_UART1_MR (*(RwReg*)0x40060604U) /**< \brief (UART1) Mode Register */ 57 #define REG_UART1_IER (*(WoReg*)0x40060608U) /**< \brief (UART1) Interrupt Enable Register */ 58 #define REG_UART1_IDR (*(WoReg*)0x4006060CU) /**< \brief (UART1) Interrupt Disable Register */ 59 #define REG_UART1_IMR (*(RoReg*)0x40060610U) /**< \brief (UART1) Interrupt Mask Register */ 60 #define REG_UART1_SR (*(RoReg*)0x40060614U) /**< \brief (UART1) Status Register */ 61 #define REG_UART1_RHR (*(RoReg*)0x40060618U) /**< \brief (UART1) Receive Holding Register */ 62 #define REG_UART1_THR (*(WoReg*)0x4006061CU) /**< \brief (UART1) Transmit Holding Register */ 63 #define REG_UART1_BRGR (*(RwReg*)0x40060620U) /**< \brief (UART1) Baud Rate Generator Register */ 64 #define REG_UART1_RPR (*(RwReg*)0x40060700U) /**< \brief (UART1) Receive Pointer Register */ 65 #define REG_UART1_RCR (*(RwReg*)0x40060704U) /**< \brief (UART1) Receive Counter Register */ 66 #define REG_UART1_TPR (*(RwReg*)0x40060708U) /**< \brief (UART1) Transmit Pointer Register */ 67 #define REG_UART1_TCR (*(RwReg*)0x4006070CU) /**< \brief (UART1) Transmit Counter Register */ 68 #define REG_UART1_RNPR (*(RwReg*)0x40060710U) /**< \brief (UART1) Receive Next Pointer Register */ 69 #define REG_UART1_RNCR (*(RwReg*)0x40060714U) /**< \brief (UART1) Receive Next Counter Register */ 70 #define REG_UART1_TNPR (*(RwReg*)0x40060718U) /**< \brief (UART1) Transmit Next Pointer Register */ 71 #define REG_UART1_TNCR (*(RwReg*)0x4006071CU) /**< \brief (UART1) Transmit Next Counter Register */ 72 #define REG_UART1_PTCR (*(WoReg*)0x40060720U) /**< \brief (UART1) Transfer Control Register */ 73 #define REG_UART1_PTSR (*(RoReg*)0x40060724U) /**< \brief (UART1) Transfer Status Register */ 74 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 75 76 #endif /* _SAM4E_UART1_INSTANCE_ */ 77
