1 /* 2 * Autogenerated file 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #include <dt-bindings/pinctrl/atmel_sam_pinctrl.h> 8 9 /* pa0_gpio */ 10 #define PA0_GPIO \ 11 SAM_PINMUX(a, 0, gpio, gpio) 12 13 /* pa0a_pwmc0_pwmh0 */ 14 #define PA0A_PWMC0_PWMH0 \ 15 SAM_PINMUX(a, 0, a, periph) 16 17 /* pa0b_tc0_tioa0 */ 18 #define PA0B_TC0_TIOA0 \ 19 SAM_PINMUX(a, 0, b, periph) 20 21 /* pa0d_i2sc0_mck */ 22 #define PA0D_I2SC0_MCK \ 23 SAM_PINMUX(a, 0, d, periph) 24 25 /* pa0x_supc_wkup0 */ 26 #define PA0X_SUPC_WKUP0 \ 27 SAM_PINMUX(a, 0, wkup0, wakeup) 28 29 /* pa1_gpio */ 30 #define PA1_GPIO \ 31 SAM_PINMUX(a, 1, gpio, gpio) 32 33 /* pa1a_pwmc0_pwml0 */ 34 #define PA1A_PWMC0_PWML0 \ 35 SAM_PINMUX(a, 1, a, periph) 36 37 /* pa1b_tc0_tiob0 */ 38 #define PA1B_TC0_TIOB0 \ 39 SAM_PINMUX(a, 1, b, periph) 40 41 /* pa1d_i2sc0_ck */ 42 #define PA1D_I2SC0_CK \ 43 SAM_PINMUX(a, 1, d, periph) 44 45 /* pa1x_supc_wkup1 */ 46 #define PA1X_SUPC_WKUP1 \ 47 SAM_PINMUX(a, 1, wkup1, wakeup) 48 49 /* pa2_gpio */ 50 #define PA2_GPIO \ 51 SAM_PINMUX(a, 2, gpio, gpio) 52 53 /* pa2a_pwmc0_pwmh1 */ 54 #define PA2A_PWMC0_PWMH1 \ 55 SAM_PINMUX(a, 2, a, periph) 56 57 /* pa2c_dacc_datrg */ 58 #define PA2C_DACC_DATRG \ 59 SAM_PINMUX(a, 2, c, periph) 60 61 /* pa2x_supc_wkup2 */ 62 #define PA2X_SUPC_WKUP2 \ 63 SAM_PINMUX(a, 2, wkup2, wakeup) 64 65 /* pa3_gpio */ 66 #define PA3_GPIO \ 67 SAM_PINMUX(a, 3, gpio, gpio) 68 69 /* pa3a_twi0_twd */ 70 #define PA3A_TWI0_TWD \ 71 SAM_PINMUX(a, 3, a, periph) 72 73 /* pa3b_lon_col1 */ 74 #define PA3B_LON_COL1 \ 75 SAM_PINMUX(a, 3, b, periph) 76 77 /* pa3c_pmc_pck2 */ 78 #define PA3C_PMC_PCK2 \ 79 SAM_PINMUX(a, 3, c, periph) 80 81 /* pa3x_pio_piodc0 */ 82 #define PA3X_PIO_PIODC0 \ 83 SAM_PINMUX(a, 3, x, extra) 84 85 /* pa4_gpio */ 86 #define PA4_GPIO \ 87 SAM_PINMUX(a, 4, gpio, gpio) 88 89 /* pa4a_twi0_twck */ 90 #define PA4A_TWI0_TWCK \ 91 SAM_PINMUX(a, 4, a, periph) 92 93 /* pa4b_tc0_tclk0 */ 94 #define PA4B_TC0_TCLK0 \ 95 SAM_PINMUX(a, 4, b, periph) 96 97 /* pa4c_uart1_txd */ 98 #define PA4C_UART1_TXD \ 99 SAM_PINMUX(a, 4, c, periph) 100 101 /* pa4x_pio_piodc1 */ 102 #define PA4X_PIO_PIODC1 \ 103 SAM_PINMUX(a, 4, x, extra) 104 105 /* pa4x_supc_wkup3 */ 106 #define PA4X_SUPC_WKUP3 \ 107 SAM_PINMUX(a, 4, wkup3, wakeup) 108 109 /* pa5_gpio */ 110 #define PA5_GPIO \ 111 SAM_PINMUX(a, 5, gpio, gpio) 112 113 /* pa5a_pwmc1_pwml3 */ 114 #define PA5A_PWMC1_PWML3 \ 115 SAM_PINMUX(a, 5, a, periph) 116 117 /* pa5b_isi_d4 */ 118 #define PA5B_ISI_D4 \ 119 SAM_PINMUX(a, 5, b, periph) 120 121 /* pa5c_uart1_rxd */ 122 #define PA5C_UART1_RXD \ 123 SAM_PINMUX(a, 5, c, periph) 124 125 /* pa5x_pio_piodc2 */ 126 #define PA5X_PIO_PIODC2 \ 127 SAM_PINMUX(a, 5, x, extra) 128 129 /* pa5x_supc_wkup4 */ 130 #define PA5X_SUPC_WKUP4 \ 131 SAM_PINMUX(a, 5, wkup4, wakeup) 132 133 /* pa6_gpio */ 134 #define PA6_GPIO \ 135 SAM_PINMUX(a, 6, gpio, gpio) 136 137 /* pa6b_pmc_pck0 */ 138 #define PA6B_PMC_PCK0 \ 139 SAM_PINMUX(a, 6, b, periph) 140 141 /* pa6c_uart1_txd */ 142 #define PA6C_UART1_TXD \ 143 SAM_PINMUX(a, 6, c, periph) 144 145 /* pa7_gpio */ 146 #define PA7_GPIO \ 147 SAM_PINMUX(a, 7, gpio, gpio) 148 149 /* pa7b_pwmc0_pwmh3 */ 150 #define PA7B_PWMC0_PWMH3 \ 151 SAM_PINMUX(a, 7, b, periph) 152 153 /* pa7s_supc_xin32 */ 154 #define PA7S_SUPC_XIN32 \ 155 SAM_PINMUX(a, 7, s, system) 156 157 /* pa8_gpio */ 158 #define PA8_GPIO \ 159 SAM_PINMUX(a, 8, gpio, gpio) 160 161 /* pa8a_pwmc1_pwmh3 */ 162 #define PA8A_PWMC1_PWMH3 \ 163 SAM_PINMUX(a, 8, a, periph) 164 165 /* pa8b_afe0_adtrg */ 166 #define PA8B_AFE0_ADTRG \ 167 SAM_PINMUX(a, 8, b, periph) 168 169 /* pa8s_supc_xout32 */ 170 #define PA8S_SUPC_XOUT32 \ 171 SAM_PINMUX(a, 8, s, system) 172 173 /* pa9_gpio */ 174 #define PA9_GPIO \ 175 SAM_PINMUX(a, 9, gpio, gpio) 176 177 /* pa9a_uart0_rxd */ 178 #define PA9A_UART0_RXD \ 179 SAM_PINMUX(a, 9, a, periph) 180 181 /* pa9b_isi_d3 */ 182 #define PA9B_ISI_D3 \ 183 SAM_PINMUX(a, 9, b, periph) 184 185 /* pa9c_pwmc0_pwmfi0 */ 186 #define PA9C_PWMC0_PWMFI0 \ 187 SAM_PINMUX(a, 9, c, periph) 188 189 /* pa9x_pio_piodc3 */ 190 #define PA9X_PIO_PIODC3 \ 191 SAM_PINMUX(a, 9, x, extra) 192 193 /* pa9x_supc_wkup6 */ 194 #define PA9X_SUPC_WKUP6 \ 195 SAM_PINMUX(a, 9, wkup6, wakeup) 196 197 /* pa10_gpio */ 198 #define PA10_GPIO \ 199 SAM_PINMUX(a, 10, gpio, gpio) 200 201 /* pa10a_uart0_txd */ 202 #define PA10A_UART0_TXD \ 203 SAM_PINMUX(a, 10, a, periph) 204 205 /* pa10b_pwmc0_pwmextrg0 */ 206 #define PA10B_PWMC0_PWMEXTRG0 \ 207 SAM_PINMUX(a, 10, b, periph) 208 209 /* pa10c_ssc_rd */ 210 #define PA10C_SSC_RD \ 211 SAM_PINMUX(a, 10, c, periph) 212 213 /* pa10x_pio_piodc4 */ 214 #define PA10X_PIO_PIODC4 \ 215 SAM_PINMUX(a, 10, x, extra) 216 217 /* pa11_gpio */ 218 #define PA11_GPIO \ 219 SAM_PINMUX(a, 11, gpio, gpio) 220 221 /* pa11a_qspi_qcs */ 222 #define PA11A_QSPI_QCS \ 223 SAM_PINMUX(a, 11, a, periph) 224 225 /* pa11b_pwmc0_pwmh0 */ 226 #define PA11B_PWMC0_PWMH0 \ 227 SAM_PINMUX(a, 11, b, periph) 228 229 /* pa11c_pwmc1_pwml0 */ 230 #define PA11C_PWMC1_PWML0 \ 231 SAM_PINMUX(a, 11, c, periph) 232 233 /* pa11x_pio_piodc5 */ 234 #define PA11X_PIO_PIODC5 \ 235 SAM_PINMUX(a, 11, x, extra) 236 237 /* pa11x_supc_wkup7 */ 238 #define PA11X_SUPC_WKUP7 \ 239 SAM_PINMUX(a, 11, wkup7, wakeup) 240 241 /* pa12_gpio */ 242 #define PA12_GPIO \ 243 SAM_PINMUX(a, 12, gpio, gpio) 244 245 /* pa12a_qspi_qio1 */ 246 #define PA12A_QSPI_QIO1 \ 247 SAM_PINMUX(a, 12, a, periph) 248 249 /* pa12b_pwmc0_pwmh1 */ 250 #define PA12B_PWMC0_PWMH1 \ 251 SAM_PINMUX(a, 12, b, periph) 252 253 /* pa12c_pwmc1_pwmh0 */ 254 #define PA12C_PWMC1_PWMH0 \ 255 SAM_PINMUX(a, 12, c, periph) 256 257 /* pa12x_pio_piodc6 */ 258 #define PA12X_PIO_PIODC6 \ 259 SAM_PINMUX(a, 12, x, extra) 260 261 /* pa13_gpio */ 262 #define PA13_GPIO \ 263 SAM_PINMUX(a, 13, gpio, gpio) 264 265 /* pa13a_qspi_qio0 */ 266 #define PA13A_QSPI_QIO0 \ 267 SAM_PINMUX(a, 13, a, periph) 268 269 /* pa13b_pwmc0_pwmh2 */ 270 #define PA13B_PWMC0_PWMH2 \ 271 SAM_PINMUX(a, 13, b, periph) 272 273 /* pa13c_pwmc1_pwml1 */ 274 #define PA13C_PWMC1_PWML1 \ 275 SAM_PINMUX(a, 13, c, periph) 276 277 /* pa13x_pio_piodc7 */ 278 #define PA13X_PIO_PIODC7 \ 279 SAM_PINMUX(a, 13, x, extra) 280 281 /* pa14_gpio */ 282 #define PA14_GPIO \ 283 SAM_PINMUX(a, 14, gpio, gpio) 284 285 /* pa14a_qspi_qsck */ 286 #define PA14A_QSPI_QSCK \ 287 SAM_PINMUX(a, 14, a, periph) 288 289 /* pa14b_pwmc0_pwmh3 */ 290 #define PA14B_PWMC0_PWMH3 \ 291 SAM_PINMUX(a, 14, b, periph) 292 293 /* pa14c_pwmc1_pwmh1 */ 294 #define PA14C_PWMC1_PWMH1 \ 295 SAM_PINMUX(a, 14, c, periph) 296 297 /* pa14x_pio_pioden1 */ 298 #define PA14X_PIO_PIODEN1 \ 299 SAM_PINMUX(a, 14, x, extra) 300 301 /* pa14x_supc_wkup8 */ 302 #define PA14X_SUPC_WKUP8 \ 303 SAM_PINMUX(a, 14, wkup8, wakeup) 304 305 /* pa15_gpio */ 306 #define PA15_GPIO \ 307 SAM_PINMUX(a, 15, gpio, gpio) 308 309 /* pa15b_tc0_tioa1 */ 310 #define PA15B_TC0_TIOA1 \ 311 SAM_PINMUX(a, 15, b, periph) 312 313 /* pa15c_pwmc0_pwml3 */ 314 #define PA15C_PWMC0_PWML3 \ 315 SAM_PINMUX(a, 15, c, periph) 316 317 /* pa15d_i2sc0_ws */ 318 #define PA15D_I2SC0_WS \ 319 SAM_PINMUX(a, 15, d, periph) 320 321 /* pa16_gpio */ 322 #define PA16_GPIO \ 323 SAM_PINMUX(a, 16, gpio, gpio) 324 325 /* pa16b_tc0_tiob1 */ 326 #define PA16B_TC0_TIOB1 \ 327 SAM_PINMUX(a, 16, b, periph) 328 329 /* pa16c_pwmc0_pwml2 */ 330 #define PA16C_PWMC0_PWML2 \ 331 SAM_PINMUX(a, 16, c, periph) 332 333 /* pa16d_i2sc0_di */ 334 #define PA16D_I2SC0_DI \ 335 SAM_PINMUX(a, 16, d, periph) 336 337 /* pa17_gpio */ 338 #define PA17_GPIO \ 339 SAM_PINMUX(a, 17, gpio, gpio) 340 341 /* pa17a_qspi_qio2 */ 342 #define PA17A_QSPI_QIO2 \ 343 SAM_PINMUX(a, 17, a, periph) 344 345 /* pa17b_pmc_pck1 */ 346 #define PA17B_PMC_PCK1 \ 347 SAM_PINMUX(a, 17, b, periph) 348 349 /* pa17c_pwmc0_pwmh3 */ 350 #define PA17C_PWMC0_PWMH3 \ 351 SAM_PINMUX(a, 17, c, periph) 352 353 /* pa17x_afe0_ad6 */ 354 #define PA17X_AFE0_AD6 \ 355 SAM_PINMUX(a, 17, x, extra) 356 357 /* pa18_gpio */ 358 #define PA18_GPIO \ 359 SAM_PINMUX(a, 18, gpio, gpio) 360 361 /* pa18a_pwmc1_pwmextrg1 */ 362 #define PA18A_PWMC1_PWMEXTRG1 \ 363 SAM_PINMUX(a, 18, a, periph) 364 365 /* pa18b_pmc_pck2 */ 366 #define PA18B_PMC_PCK2 \ 367 SAM_PINMUX(a, 18, b, periph) 368 369 /* pa18x_afe0_ad7 */ 370 #define PA18X_AFE0_AD7 \ 371 SAM_PINMUX(a, 18, x, extra) 372 373 /* pa19_gpio */ 374 #define PA19_GPIO \ 375 SAM_PINMUX(a, 19, gpio, gpio) 376 377 /* pa19b_pwmc0_pwml0 */ 378 #define PA19B_PWMC0_PWML0 \ 379 SAM_PINMUX(a, 19, b, periph) 380 381 /* pa19d_i2sc1_mck */ 382 #define PA19D_I2SC1_MCK \ 383 SAM_PINMUX(a, 19, d, periph) 384 385 /* pa19x_afe0_ad8 */ 386 #define PA19X_AFE0_AD8 \ 387 SAM_PINMUX(a, 19, x, extra) 388 389 /* pa19x_supc_wkup9 */ 390 #define PA19X_SUPC_WKUP9 \ 391 SAM_PINMUX(a, 19, wkup9, wakeup) 392 393 /* pa20_gpio */ 394 #define PA20_GPIO \ 395 SAM_PINMUX(a, 20, gpio, gpio) 396 397 /* pa20b_pwmc0_pwml1 */ 398 #define PA20B_PWMC0_PWML1 \ 399 SAM_PINMUX(a, 20, b, periph) 400 401 /* pa20d_i2sc1_ck */ 402 #define PA20D_I2SC1_CK \ 403 SAM_PINMUX(a, 20, d, periph) 404 405 /* pa20x_afe0_ad9 */ 406 #define PA20X_AFE0_AD9 \ 407 SAM_PINMUX(a, 20, x, extra) 408 409 /* pa20x_supc_wkup10 */ 410 #define PA20X_SUPC_WKUP10 \ 411 SAM_PINMUX(a, 20, wkup10, wakeup) 412 413 /* pa21_gpio */ 414 #define PA21_GPIO \ 415 SAM_PINMUX(a, 21, gpio, gpio) 416 417 /* pa21a_usart1_rxd */ 418 #define PA21A_USART1_RXD \ 419 SAM_PINMUX(a, 21, a, periph) 420 421 /* pa21b_pmc_pck1 */ 422 #define PA21B_PMC_PCK1 \ 423 SAM_PINMUX(a, 21, b, periph) 424 425 /* pa21c_pwmc1_pwmfi0 */ 426 #define PA21C_PWMC1_PWMFI0 \ 427 SAM_PINMUX(a, 21, c, periph) 428 429 /* pa21x_afe0_ad1 */ 430 #define PA21X_AFE0_AD1 \ 431 SAM_PINMUX(a, 21, x, extra) 432 433 /* pa21x_pio_piodcen2 */ 434 #define PA21X_PIO_PIODCEN2 \ 435 SAM_PINMUX(a, 21, x, extra) 436 437 /* pa22_gpio */ 438 #define PA22_GPIO \ 439 SAM_PINMUX(a, 22, gpio, gpio) 440 441 /* pa22a_ssc_rk */ 442 #define PA22A_SSC_RK \ 443 SAM_PINMUX(a, 22, a, periph) 444 445 /* pa22b_pwmc0_pwmextrg1 */ 446 #define PA22B_PWMC0_PWMEXTRG1 \ 447 SAM_PINMUX(a, 22, b, periph) 448 449 /* pa22x_pio_piodcclk */ 450 #define PA22X_PIO_PIODCCLK \ 451 SAM_PINMUX(a, 22, x, extra) 452 453 /* pa23_gpio */ 454 #define PA23_GPIO \ 455 SAM_PINMUX(a, 23, gpio, gpio) 456 457 /* pa23a_usart1_sck */ 458 #define PA23A_USART1_SCK \ 459 SAM_PINMUX(a, 23, a, periph) 460 461 /* pa23b_pwmc0_pwmh0 */ 462 #define PA23B_PWMC0_PWMH0 \ 463 SAM_PINMUX(a, 23, b, periph) 464 465 /* pa23d_pwmc1_pwml2 */ 466 #define PA23D_PWMC1_PWML2 \ 467 SAM_PINMUX(a, 23, d, periph) 468 469 /* pa24_gpio */ 470 #define PA24_GPIO \ 471 SAM_PINMUX(a, 24, gpio, gpio) 472 473 /* pa24a_usart1_rts */ 474 #define PA24A_USART1_RTS \ 475 SAM_PINMUX(a, 24, a, periph) 476 477 /* pa24b_pwmc0_pwmh1 */ 478 #define PA24B_PWMC0_PWMH1 \ 479 SAM_PINMUX(a, 24, b, periph) 480 481 /* pa24d_isi_pck */ 482 #define PA24D_ISI_PCK \ 483 SAM_PINMUX(a, 24, d, periph) 484 485 /* pa25_gpio */ 486 #define PA25_GPIO \ 487 SAM_PINMUX(a, 25, gpio, gpio) 488 489 /* pa25a_usart1_cts */ 490 #define PA25A_USART1_CTS \ 491 SAM_PINMUX(a, 25, a, periph) 492 493 /* pa25b_pwmc0_pwmh2 */ 494 #define PA25B_PWMC0_PWMH2 \ 495 SAM_PINMUX(a, 25, b, periph) 496 497 /* pa25d_hsmci_mcck */ 498 #define PA25D_HSMCI_MCCK \ 499 SAM_PINMUX(a, 25, d, periph) 500 501 /* pa26_gpio */ 502 #define PA26_GPIO \ 503 SAM_PINMUX(a, 26, gpio, gpio) 504 505 /* pa26a_usart1_dcd */ 506 #define PA26A_USART1_DCD \ 507 SAM_PINMUX(a, 26, a, periph) 508 509 /* pa26b_tc0_tioa2 */ 510 #define PA26B_TC0_TIOA2 \ 511 SAM_PINMUX(a, 26, b, periph) 512 513 /* pa26c_hsmci_mcda2 */ 514 #define PA26C_HSMCI_MCDA2 \ 515 SAM_PINMUX(a, 26, c, periph) 516 517 /* pa26d_pwmc1_pwmfi1 */ 518 #define PA26D_PWMC1_PWMFI1 \ 519 SAM_PINMUX(a, 26, d, periph) 520 521 /* pa27_gpio */ 522 #define PA27_GPIO \ 523 SAM_PINMUX(a, 27, gpio, gpio) 524 525 /* pa27a_usart1_dtr */ 526 #define PA27A_USART1_DTR \ 527 SAM_PINMUX(a, 27, a, periph) 528 529 /* pa27b_tc0_tiob2 */ 530 #define PA27B_TC0_TIOB2 \ 531 SAM_PINMUX(a, 27, b, periph) 532 533 /* pa27c_hsmci_mcda3 */ 534 #define PA27C_HSMCI_MCDA3 \ 535 SAM_PINMUX(a, 27, c, periph) 536 537 /* pa27d_isi_d7 */ 538 #define PA27D_ISI_D7 \ 539 SAM_PINMUX(a, 27, d, periph) 540 541 /* pa28_gpio */ 542 #define PA28_GPIO \ 543 SAM_PINMUX(a, 28, gpio, gpio) 544 545 /* pa28a_usart1_dsr */ 546 #define PA28A_USART1_DSR \ 547 SAM_PINMUX(a, 28, a, periph) 548 549 /* pa28b_tc0_tclk1 */ 550 #define PA28B_TC0_TCLK1 \ 551 SAM_PINMUX(a, 28, b, periph) 552 553 /* pa28c_hsmci_mccda */ 554 #define PA28C_HSMCI_MCCDA \ 555 SAM_PINMUX(a, 28, c, periph) 556 557 /* pa28d_pwmc1_pwmfi2 */ 558 #define PA28D_PWMC1_PWMFI2 \ 559 SAM_PINMUX(a, 28, d, periph) 560 561 /* pa29_gpio */ 562 #define PA29_GPIO \ 563 SAM_PINMUX(a, 29, gpio, gpio) 564 565 /* pa29a_usart1_ri */ 566 #define PA29A_USART1_RI \ 567 SAM_PINMUX(a, 29, a, periph) 568 569 /* pa29b_tc0_tclk2 */ 570 #define PA29B_TC0_TCLK2 \ 571 SAM_PINMUX(a, 29, b, periph) 572 573 /* pa30_gpio */ 574 #define PA30_GPIO \ 575 SAM_PINMUX(a, 30, gpio, gpio) 576 577 /* pa30a_pwmc0_pwml2 */ 578 #define PA30A_PWMC0_PWML2 \ 579 SAM_PINMUX(a, 30, a, periph) 580 581 /* pa30b_pwmc1_pwmextrg0 */ 582 #define PA30B_PWMC1_PWMEXTRG0 \ 583 SAM_PINMUX(a, 30, b, periph) 584 585 /* pa30c_hsmci_mcda0 */ 586 #define PA30C_HSMCI_MCDA0 \ 587 SAM_PINMUX(a, 30, c, periph) 588 589 /* pa30d_i2sc0_do */ 590 #define PA30D_I2SC0_DO \ 591 SAM_PINMUX(a, 30, d, periph) 592 593 /* pa30x_supc_wkup11 */ 594 #define PA30X_SUPC_WKUP11 \ 595 SAM_PINMUX(a, 30, wkup11, wakeup) 596 597 /* pa31_gpio */ 598 #define PA31_GPIO \ 599 SAM_PINMUX(a, 31, gpio, gpio) 600 601 /* pa31a_spi0_npcs1 */ 602 #define PA31A_SPI0_NPCS1 \ 603 SAM_PINMUX(a, 31, a, periph) 604 605 /* pa31b_pmc_pck2 */ 606 #define PA31B_PMC_PCK2 \ 607 SAM_PINMUX(a, 31, b, periph) 608 609 /* pa31c_hsmci_mcda1 */ 610 #define PA31C_HSMCI_MCDA1 \ 611 SAM_PINMUX(a, 31, c, periph) 612 613 /* pa31d_pwmc1_pwmh2 */ 614 #define PA31D_PWMC1_PWMH2 \ 615 SAM_PINMUX(a, 31, d, periph) 616 617 /* pb0_gpio */ 618 #define PB0_GPIO \ 619 SAM_PINMUX(b, 0, gpio, gpio) 620 621 /* pb0a_pwmc0_pwmh0 */ 622 #define PB0A_PWMC0_PWMH0 \ 623 SAM_PINMUX(b, 0, a, periph) 624 625 /* pb0c_usart0_rxd */ 626 #define PB0C_USART0_RXD \ 627 SAM_PINMUX(b, 0, c, periph) 628 629 /* pb0d_ssc_tf */ 630 #define PB0D_SSC_TF \ 631 SAM_PINMUX(b, 0, d, periph) 632 633 /* pb0x_afe0_ad10 */ 634 #define PB0X_AFE0_AD10 \ 635 SAM_PINMUX(b, 0, x, extra) 636 637 /* pb0x_rtc_out0 */ 638 #define PB0X_RTC_OUT0 \ 639 SAM_PINMUX(b, 0, x, extra) 640 641 /* pb1_gpio */ 642 #define PB1_GPIO \ 643 SAM_PINMUX(b, 1, gpio, gpio) 644 645 /* pb1a_pwmc0_pwmh1 */ 646 #define PB1A_PWMC0_PWMH1 \ 647 SAM_PINMUX(b, 1, a, periph) 648 649 /* pb1b_gmac_gtsucomp */ 650 #define PB1B_GMAC_GTSUCOMP \ 651 SAM_PINMUX(b, 1, b, periph) 652 653 /* pb1c_usart0_txd */ 654 #define PB1C_USART0_TXD \ 655 SAM_PINMUX(b, 1, c, periph) 656 657 /* pb1d_ssc_tk */ 658 #define PB1D_SSC_TK \ 659 SAM_PINMUX(b, 1, d, periph) 660 661 /* pb1x_afe1_ad0 */ 662 #define PB1X_AFE1_AD0 \ 663 SAM_PINMUX(b, 1, x, extra) 664 665 /* pb1x_rtc_out1 */ 666 #define PB1X_RTC_OUT1 \ 667 SAM_PINMUX(b, 1, x, extra) 668 669 /* pb2_gpio */ 670 #define PB2_GPIO \ 671 SAM_PINMUX(b, 2, gpio, gpio) 672 673 /* pb2a_can0_tx */ 674 #define PB2A_CAN0_TX \ 675 SAM_PINMUX(b, 2, a, periph) 676 677 /* pb2c_usart0_cts */ 678 #define PB2C_USART0_CTS \ 679 SAM_PINMUX(b, 2, c, periph) 680 681 /* pb2d_spi0_npcs0 */ 682 #define PB2D_SPI0_NPCS0 \ 683 SAM_PINMUX(b, 2, d, periph) 684 685 /* pb2x_afe0_ad5 */ 686 #define PB2X_AFE0_AD5 \ 687 SAM_PINMUX(b, 2, x, extra) 688 689 /* pb3_gpio */ 690 #define PB3_GPIO \ 691 SAM_PINMUX(b, 3, gpio, gpio) 692 693 /* pb3a_can0_rx */ 694 #define PB3A_CAN0_RX \ 695 SAM_PINMUX(b, 3, a, periph) 696 697 /* pb3b_pmc_pck2 */ 698 #define PB3B_PMC_PCK2 \ 699 SAM_PINMUX(b, 3, b, periph) 700 701 /* pb3c_usart0_rts */ 702 #define PB3C_USART0_RTS \ 703 SAM_PINMUX(b, 3, c, periph) 704 705 /* pb3d_isi_d2 */ 706 #define PB3D_ISI_D2 \ 707 SAM_PINMUX(b, 3, d, periph) 708 709 /* pb3x_afe0_ad2 */ 710 #define PB3X_AFE0_AD2 \ 711 SAM_PINMUX(b, 3, x, extra) 712 713 /* pb3x_supc_wkup12 */ 714 #define PB3X_SUPC_WKUP12 \ 715 SAM_PINMUX(b, 3, wkup12, wakeup) 716 717 /* pb4_gpio */ 718 #define PB4_GPIO \ 719 SAM_PINMUX(b, 4, gpio, gpio) 720 721 /* pb4a_twi1_twd */ 722 #define PB4A_TWI1_TWD \ 723 SAM_PINMUX(b, 4, a, periph) 724 725 /* pb4b_pwmc0_pwmh2 */ 726 #define PB4B_PWMC0_PWMH2 \ 727 SAM_PINMUX(b, 4, b, periph) 728 729 /* pb4c_mlb_clk */ 730 #define PB4C_MLB_CLK \ 731 SAM_PINMUX(b, 4, c, periph) 732 733 /* pb4d_usart1_txd */ 734 #define PB4D_USART1_TXD \ 735 SAM_PINMUX(b, 4, d, periph) 736 737 /* pb4s_jtag_tdi */ 738 #define PB4S_JTAG_TDI \ 739 SAM_PINMUX(b, 4, s, system) 740 741 /* pb5_gpio */ 742 #define PB5_GPIO \ 743 SAM_PINMUX(b, 5, gpio, gpio) 744 745 /* pb5a_twi1_twck */ 746 #define PB5A_TWI1_TWCK \ 747 SAM_PINMUX(b, 5, a, periph) 748 749 /* pb5b_pwmc0_pwml0 */ 750 #define PB5B_PWMC0_PWML0 \ 751 SAM_PINMUX(b, 5, b, periph) 752 753 /* pb5c_mlb_dat */ 754 #define PB5C_MLB_DAT \ 755 SAM_PINMUX(b, 5, c, periph) 756 757 /* pb5d_ssc_td */ 758 #define PB5D_SSC_TD \ 759 SAM_PINMUX(b, 5, d, periph) 760 761 /* pb5s_jtag_tdo */ 762 #define PB5S_JTAG_TDO \ 763 SAM_PINMUX(b, 5, s, system) 764 765 /* pb5s_swd_traceswo */ 766 #define PB5S_SWD_TRACESWO \ 767 SAM_PINMUX(b, 5, s, system) 768 769 /* pb5x_supc_wkup13 */ 770 #define PB5X_SUPC_WKUP13 \ 771 SAM_PINMUX(b, 5, wkup13, wakeup) 772 773 /* pb6_gpio */ 774 #define PB6_GPIO \ 775 SAM_PINMUX(b, 6, gpio, gpio) 776 777 /* pb6s_jtag_tms */ 778 #define PB6S_JTAG_TMS \ 779 SAM_PINMUX(b, 6, s, system) 780 781 /* pb6s_swd_swdio */ 782 #define PB6S_SWD_SWDIO \ 783 SAM_PINMUX(b, 6, s, system) 784 785 /* pb7_gpio */ 786 #define PB7_GPIO \ 787 SAM_PINMUX(b, 7, gpio, gpio) 788 789 /* pb7s_jtag_tck */ 790 #define PB7S_JTAG_TCK \ 791 SAM_PINMUX(b, 7, s, system) 792 793 /* pb7s_swd_swclk */ 794 #define PB7S_SWD_SWCLK \ 795 SAM_PINMUX(b, 7, s, system) 796 797 /* pb8_gpio */ 798 #define PB8_GPIO \ 799 SAM_PINMUX(b, 8, gpio, gpio) 800 801 /* pb8s_supc_xout */ 802 #define PB8S_SUPC_XOUT \ 803 SAM_PINMUX(b, 8, s, system) 804 805 /* pb9_gpio */ 806 #define PB9_GPIO \ 807 SAM_PINMUX(b, 9, gpio, gpio) 808 809 /* pb9s_supc_xin */ 810 #define PB9S_SUPC_XIN \ 811 SAM_PINMUX(b, 9, s, system) 812 813 /* pb12_gpio */ 814 #define PB12_GPIO \ 815 SAM_PINMUX(b, 12, gpio, gpio) 816 817 /* pb12a_pwmc0_pwml1 */ 818 #define PB12A_PWMC0_PWML1 \ 819 SAM_PINMUX(b, 12, a, periph) 820 821 /* pb12b_gmac_gtsucomp */ 822 #define PB12B_GMAC_GTSUCOMP \ 823 SAM_PINMUX(b, 12, b, periph) 824 825 /* pb12d_pcm_pck0 */ 826 #define PB12D_PCM_PCK0 \ 827 SAM_PINMUX(b, 12, d, periph) 828 829 /* pb12s_flash_erase */ 830 #define PB12S_FLASH_ERASE \ 831 SAM_PINMUX(b, 12, s, system) 832 833 /* pb13_gpio */ 834 #define PB13_GPIO \ 835 SAM_PINMUX(b, 13, gpio, gpio) 836 837 /* pb13a_pwmc0_pwml2 */ 838 #define PB13A_PWMC0_PWML2 \ 839 SAM_PINMUX(b, 13, a, periph) 840 841 /* pb13b_pcm_pck0 */ 842 #define PB13B_PCM_PCK0 \ 843 SAM_PINMUX(b, 13, b, periph) 844 845 /* pb13c_usart0_sck */ 846 #define PB13C_USART0_SCK \ 847 SAM_PINMUX(b, 13, c, periph) 848 849 /* pb13x_dacc_dac0 */ 850 #define PB13X_DACC_DAC0 \ 851 SAM_PINMUX(b, 13, x, extra) 852 853 /* pd0_gpio */ 854 #define PD0_GPIO \ 855 SAM_PINMUX(d, 0, gpio, gpio) 856 857 /* pd0a_gmac_gtxck */ 858 #define PD0A_GMAC_GTXCK \ 859 SAM_PINMUX(d, 0, a, periph) 860 861 /* pd0b_pwmc1_pwml0 */ 862 #define PD0B_PWMC1_PWML0 \ 863 SAM_PINMUX(d, 0, b, periph) 864 865 /* pd0c_spi1_npcs1 */ 866 #define PD0C_SPI1_NPCS1 \ 867 SAM_PINMUX(d, 0, c, periph) 868 869 /* pd0d_usart0_dcd */ 870 #define PD0D_USART0_DCD \ 871 SAM_PINMUX(d, 0, d, periph) 872 873 /* pd0x_dacc_dac1 */ 874 #define PD0X_DACC_DAC1 \ 875 SAM_PINMUX(d, 0, x, extra) 876 877 /* pd1_gpio */ 878 #define PD1_GPIO \ 879 SAM_PINMUX(d, 1, gpio, gpio) 880 881 /* pd1a_gmac_gtxen */ 882 #define PD1A_GMAC_GTXEN \ 883 SAM_PINMUX(d, 1, a, periph) 884 885 /* pd1b_pwmc1_pwmh0 */ 886 #define PD1B_PWMC1_PWMH0 \ 887 SAM_PINMUX(d, 1, b, periph) 888 889 /* pd1c_spi1_npcs2 */ 890 #define PD1C_SPI1_NPCS2 \ 891 SAM_PINMUX(d, 1, c, periph) 892 893 /* pd1d_usart0_dtr */ 894 #define PD1D_USART0_DTR \ 895 SAM_PINMUX(d, 1, d, periph) 896 897 /* pd2_gpio */ 898 #define PD2_GPIO \ 899 SAM_PINMUX(d, 2, gpio, gpio) 900 901 /* pd2a_gmac_gtx0 */ 902 #define PD2A_GMAC_GTX0 \ 903 SAM_PINMUX(d, 2, a, periph) 904 905 /* pd2b_pwmc1_pwml1 */ 906 #define PD2B_PWMC1_PWML1 \ 907 SAM_PINMUX(d, 2, b, periph) 908 909 /* pd2c_spi1_npcs3 */ 910 #define PD2C_SPI1_NPCS3 \ 911 SAM_PINMUX(d, 2, c, periph) 912 913 /* pd2d_usart0_dsr */ 914 #define PD2D_USART0_DSR \ 915 SAM_PINMUX(d, 2, d, periph) 916 917 /* pd3_gpio */ 918 #define PD3_GPIO \ 919 SAM_PINMUX(d, 3, gpio, gpio) 920 921 /* pd3a_gmac_gtx1 */ 922 #define PD3A_GMAC_GTX1 \ 923 SAM_PINMUX(d, 3, a, periph) 924 925 /* pd3b_pwmc1_pwmh1 */ 926 #define PD3B_PWMC1_PWMH1 \ 927 SAM_PINMUX(d, 3, b, periph) 928 929 /* pd3c_uart4_txd */ 930 #define PD3C_UART4_TXD \ 931 SAM_PINMUX(d, 3, c, periph) 932 933 /* pd3d_usart0_ri */ 934 #define PD3D_USART0_RI \ 935 SAM_PINMUX(d, 3, d, periph) 936 937 /* pd4_gpio */ 938 #define PD4_GPIO \ 939 SAM_PINMUX(d, 4, gpio, gpio) 940 941 /* pd4a_gmac_grxdv */ 942 #define PD4A_GMAC_GRXDV \ 943 SAM_PINMUX(d, 4, a, periph) 944 945 /* pd4b_pwmc1_pwml2 */ 946 #define PD4B_PWMC1_PWML2 \ 947 SAM_PINMUX(d, 4, b, periph) 948 949 /* pd4c_trace_d0 */ 950 #define PD4C_TRACE_D0 \ 951 SAM_PINMUX(d, 4, c, periph) 952 953 /* pd4d_usart2_dcd */ 954 #define PD4D_USART2_DCD \ 955 SAM_PINMUX(d, 4, d, periph) 956 957 /* pd5_gpio */ 958 #define PD5_GPIO \ 959 SAM_PINMUX(d, 5, gpio, gpio) 960 961 /* pd5a_gmac_grx0 */ 962 #define PD5A_GMAC_GRX0 \ 963 SAM_PINMUX(d, 5, a, periph) 964 965 /* pd5b_pwmc1_pwmh2 */ 966 #define PD5B_PWMC1_PWMH2 \ 967 SAM_PINMUX(d, 5, b, periph) 968 969 /* pd5c_trace_d1 */ 970 #define PD5C_TRACE_D1 \ 971 SAM_PINMUX(d, 5, c, periph) 972 973 /* pd5d_usart2_dtr */ 974 #define PD5D_USART2_DTR \ 975 SAM_PINMUX(d, 5, d, periph) 976 977 /* pd6_gpio */ 978 #define PD6_GPIO \ 979 SAM_PINMUX(d, 6, gpio, gpio) 980 981 /* pd6a_gmac_grx1 */ 982 #define PD6A_GMAC_GRX1 \ 983 SAM_PINMUX(d, 6, a, periph) 984 985 /* pd6b_pwmc1_pwml3 */ 986 #define PD6B_PWMC1_PWML3 \ 987 SAM_PINMUX(d, 6, b, periph) 988 989 /* pd6c_trace_d2 */ 990 #define PD6C_TRACE_D2 \ 991 SAM_PINMUX(d, 6, c, periph) 992 993 /* pd6d_usart2_dsr */ 994 #define PD6D_USART2_DSR \ 995 SAM_PINMUX(d, 6, d, periph) 996 997 /* pd8_gpio */ 998 #define PD8_GPIO \ 999 SAM_PINMUX(d, 8, gpio, gpio) 1000 1001 /* pd8a_gmac_gmdc */ 1002 #define PD8A_GMAC_GMDC \ 1003 SAM_PINMUX(d, 8, a, periph) 1004 1005 /* pd8b_pwmc0_pwmfi1 */ 1006 #define PD8B_PWMC0_PWMFI1 \ 1007 SAM_PINMUX(d, 8, b, periph) 1008 1009 /* pd8d_trace_clk */ 1010 #define PD8D_TRACE_CLK \ 1011 SAM_PINMUX(d, 8, d, periph) 1012 1013 /* pd9_gpio */ 1014 #define PD9_GPIO \ 1015 SAM_PINMUX(d, 9, gpio, gpio) 1016 1017 /* pd9a_gmac_gmdio */ 1018 #define PD9A_GMAC_GMDIO \ 1019 SAM_PINMUX(d, 9, a, periph) 1020 1021 /* pd9b_pwmc0_pwmfi2 */ 1022 #define PD9B_PWMC0_PWMFI2 \ 1023 SAM_PINMUX(d, 9, b, periph) 1024 1025 /* pd9c_afe1_adtrg */ 1026 #define PD9C_AFE1_ADTRG \ 1027 SAM_PINMUX(d, 9, c, periph) 1028 1029 /* pd10_gpio */ 1030 #define PD10_GPIO \ 1031 SAM_PINMUX(d, 10, gpio, gpio) 1032 1033 /* pd10a_gmac_gcrs */ 1034 #define PD10A_GMAC_GCRS \ 1035 SAM_PINMUX(d, 10, a, periph) 1036 1037 /* pd10b_pwmc0_pwml0 */ 1038 #define PD10B_PWMC0_PWML0 \ 1039 SAM_PINMUX(d, 10, b, periph) 1040 1041 /* pd10c_ssc_td */ 1042 #define PD10C_SSC_TD \ 1043 SAM_PINMUX(d, 10, c, periph) 1044 1045 /* pd10d_mlb_sig */ 1046 #define PD10D_MLB_SIG \ 1047 SAM_PINMUX(d, 10, d, periph) 1048 1049 /* pd11_gpio */ 1050 #define PD11_GPIO \ 1051 SAM_PINMUX(d, 11, gpio, gpio) 1052 1053 /* pd11a_gmac_grx2 */ 1054 #define PD11A_GMAC_GRX2 \ 1055 SAM_PINMUX(d, 11, a, periph) 1056 1057 /* pd11b_pwmc0_pwmh0 */ 1058 #define PD11B_PWMC0_PWMH0 \ 1059 SAM_PINMUX(d, 11, b, periph) 1060 1061 /* pd11c_gmac_gtsucomp */ 1062 #define PD11C_GMAC_GTSUCOMP \ 1063 SAM_PINMUX(d, 11, c, periph) 1064 1065 /* pd11d_isi_d5 */ 1066 #define PD11D_ISI_D5 \ 1067 SAM_PINMUX(d, 11, d, periph) 1068 1069 /* pd12_gpio */ 1070 #define PD12_GPIO \ 1071 SAM_PINMUX(d, 12, gpio, gpio) 1072 1073 /* pd12a_gmac_grx3 */ 1074 #define PD12A_GMAC_GRX3 \ 1075 SAM_PINMUX(d, 12, a, periph) 1076 1077 /* pd12b_can1_tx */ 1078 #define PD12B_CAN1_TX \ 1079 SAM_PINMUX(d, 12, b, periph) 1080 1081 /* pd12c_spi0_npcs2 */ 1082 #define PD12C_SPI0_NPCS2 \ 1083 SAM_PINMUX(d, 12, c, periph) 1084 1085 /* pd12d_isi_d6 */ 1086 #define PD12D_ISI_D6 \ 1087 SAM_PINMUX(d, 12, d, periph) 1088 1089 /* pd13_gpio */ 1090 #define PD13_GPIO \ 1091 SAM_PINMUX(d, 13, gpio, gpio) 1092 1093 /* pd13a_gmac_gcol */ 1094 #define PD13A_GMAC_GCOL \ 1095 SAM_PINMUX(d, 13, a, periph) 1096 1097 /* pd14_gpio */ 1098 #define PD14_GPIO \ 1099 SAM_PINMUX(d, 14, gpio, gpio) 1100 1101 /* pd14a_gmac_grxck */ 1102 #define PD14A_GMAC_GRXCK \ 1103 SAM_PINMUX(d, 14, a, periph) 1104 1105 /* pd15_gpio */ 1106 #define PD15_GPIO \ 1107 SAM_PINMUX(d, 15, gpio, gpio) 1108 1109 /* pd15a_gmac_gtx2 */ 1110 #define PD15A_GMAC_GTX2 \ 1111 SAM_PINMUX(d, 15, a, periph) 1112 1113 /* pd15b_usart2_rxd */ 1114 #define PD15B_USART2_RXD \ 1115 SAM_PINMUX(d, 15, b, periph) 1116 1117 /* pd16_gpio */ 1118 #define PD16_GPIO \ 1119 SAM_PINMUX(d, 16, gpio, gpio) 1120 1121 /* pd16a_gmac_gtx3 */ 1122 #define PD16A_GMAC_GTX3 \ 1123 SAM_PINMUX(d, 16, a, periph) 1124 1125 /* pd16b_usart2_txd */ 1126 #define PD16B_USART2_TXD \ 1127 SAM_PINMUX(d, 16, b, periph) 1128 1129 /* pd17_gpio */ 1130 #define PD17_GPIO \ 1131 SAM_PINMUX(d, 17, gpio, gpio) 1132 1133 /* pd17a_gmac_gtxer */ 1134 #define PD17A_GMAC_GTXER \ 1135 SAM_PINMUX(d, 17, a, periph) 1136 1137 /* pd17b_usart2_sck */ 1138 #define PD17B_USART2_SCK \ 1139 SAM_PINMUX(d, 17, b, periph) 1140 1141 /* pd18_gpio */ 1142 #define PD18_GPIO \ 1143 SAM_PINMUX(d, 18, gpio, gpio) 1144 1145 /* pd18b_usart2_rts */ 1146 #define PD18B_USART2_RTS \ 1147 SAM_PINMUX(d, 18, b, periph) 1148 1149 /* pd18c_uart4_rxd */ 1150 #define PD18C_UART4_RXD \ 1151 SAM_PINMUX(d, 18, c, periph) 1152 1153 /* pd19_gpio */ 1154 #define PD19_GPIO \ 1155 SAM_PINMUX(d, 19, gpio, gpio) 1156 1157 /* pd19b_usart2_cts */ 1158 #define PD19B_USART2_CTS \ 1159 SAM_PINMUX(d, 19, b, periph) 1160 1161 /* pd19c_uart4_txd */ 1162 #define PD19C_UART4_TXD \ 1163 SAM_PINMUX(d, 19, c, periph) 1164 1165 /* pd20_gpio */ 1166 #define PD20_GPIO \ 1167 SAM_PINMUX(d, 20, gpio, gpio) 1168 1169 /* pd20a_pwmc0_pwmh0 */ 1170 #define PD20A_PWMC0_PWMH0 \ 1171 SAM_PINMUX(d, 20, a, periph) 1172 1173 /* pd20b_spi0_miso */ 1174 #define PD20B_SPI0_MISO \ 1175 SAM_PINMUX(d, 20, b, periph) 1176 1177 /* pd20c_gmac_gtsucomp */ 1178 #define PD20C_GMAC_GTSUCOMP \ 1179 SAM_PINMUX(d, 20, c, periph) 1180 1181 /* pd21_gpio */ 1182 #define PD21_GPIO \ 1183 SAM_PINMUX(d, 21, gpio, gpio) 1184 1185 /* pd21a_pwmc0_pwmh1 */ 1186 #define PD21A_PWMC0_PWMH1 \ 1187 SAM_PINMUX(d, 21, a, periph) 1188 1189 /* pd21b_spi0_mosi */ 1190 #define PD21B_SPI0_MOSI \ 1191 SAM_PINMUX(d, 21, b, periph) 1192 1193 /* pd21c_tc3_tioa11 */ 1194 #define PD21C_TC3_TIOA11 \ 1195 SAM_PINMUX(d, 21, c, periph) 1196 1197 /* pd21d_isi_d1 */ 1198 #define PD21D_ISI_D1 \ 1199 SAM_PINMUX(d, 21, d, periph) 1200 1201 /* pd22_gpio */ 1202 #define PD22_GPIO \ 1203 SAM_PINMUX(d, 22, gpio, gpio) 1204 1205 /* pd22a_pwmc0_pwmh2 */ 1206 #define PD22A_PWMC0_PWMH2 \ 1207 SAM_PINMUX(d, 22, a, periph) 1208 1209 /* pd22b_spi0_spck */ 1210 #define PD22B_SPI0_SPCK \ 1211 SAM_PINMUX(d, 22, b, periph) 1212 1213 /* pd22c_tc3_tiob11 */ 1214 #define PD22C_TC3_TIOB11 \ 1215 SAM_PINMUX(d, 22, c, periph) 1216 1217 /* pd22d_isi_d0 */ 1218 #define PD22D_ISI_D0 \ 1219 SAM_PINMUX(d, 22, d, periph) 1220 1221 /* pd24_gpio */ 1222 #define PD24_GPIO \ 1223 SAM_PINMUX(d, 24, gpio, gpio) 1224 1225 /* pd24a_pwmc0_pwml0 */ 1226 #define PD24A_PWMC0_PWML0 \ 1227 SAM_PINMUX(d, 24, a, periph) 1228 1229 /* pd24b_ssc_rf */ 1230 #define PD24B_SSC_RF \ 1231 SAM_PINMUX(d, 24, b, periph) 1232 1233 /* pd24c_tc3_tclk11 */ 1234 #define PD24C_TC3_TCLK11 \ 1235 SAM_PINMUX(d, 24, c, periph) 1236 1237 /* pd24d_isi_hsync */ 1238 #define PD24D_ISI_HSYNC \ 1239 SAM_PINMUX(d, 24, d, periph) 1240 1241 /* pd25_gpio */ 1242 #define PD25_GPIO \ 1243 SAM_PINMUX(d, 25, gpio, gpio) 1244 1245 /* pd25a_pwmc0_pwml1 */ 1246 #define PD25A_PWMC0_PWML1 \ 1247 SAM_PINMUX(d, 25, a, periph) 1248 1249 /* pd25b_spi0_npcs1 */ 1250 #define PD25B_SPI0_NPCS1 \ 1251 SAM_PINMUX(d, 25, b, periph) 1252 1253 /* pd25c_uart2_rxd */ 1254 #define PD25C_UART2_RXD \ 1255 SAM_PINMUX(d, 25, c, periph) 1256 1257 /* pd25d_isi_vsync */ 1258 #define PD25D_ISI_VSYNC \ 1259 SAM_PINMUX(d, 25, d, periph) 1260 1261 /* pd26_gpio */ 1262 #define PD26_GPIO \ 1263 SAM_PINMUX(d, 26, gpio, gpio) 1264 1265 /* pd26a_pwmc0_pwml2 */ 1266 #define PD26A_PWMC0_PWML2 \ 1267 SAM_PINMUX(d, 26, a, periph) 1268 1269 /* pd26b_ssc_td */ 1270 #define PD26B_SSC_TD \ 1271 SAM_PINMUX(d, 26, b, periph) 1272 1273 /* pd26c_uart2_txd */ 1274 #define PD26C_UART2_TXD \ 1275 SAM_PINMUX(d, 26, c, periph) 1276 1277 /* pd26d_uart1_txd */ 1278 #define PD26D_UART1_TXD \ 1279 SAM_PINMUX(d, 26, d, periph) 1280 1281 /* pd27_gpio */ 1282 #define PD27_GPIO \ 1283 SAM_PINMUX(d, 27, gpio, gpio) 1284 1285 /* pd27a_pwmc0_pwml3 */ 1286 #define PD27A_PWMC0_PWML3 \ 1287 SAM_PINMUX(d, 27, a, periph) 1288 1289 /* pd27b_spi0_npcs3 */ 1290 #define PD27B_SPI0_NPCS3 \ 1291 SAM_PINMUX(d, 27, b, periph) 1292 1293 /* pd27c_twi2_twd */ 1294 #define PD27C_TWI2_TWD \ 1295 SAM_PINMUX(d, 27, c, periph) 1296 1297 /* pd27d_isi_d8 */ 1298 #define PD27D_ISI_D8 \ 1299 SAM_PINMUX(d, 27, d, periph) 1300 1301 /* pd28_gpio */ 1302 #define PD28_GPIO \ 1303 SAM_PINMUX(d, 28, gpio, gpio) 1304 1305 /* pd28a_uart3_rxd */ 1306 #define PD28A_UART3_RXD \ 1307 SAM_PINMUX(d, 28, a, periph) 1308 1309 /* pd28b_can1_rx */ 1310 #define PD28B_CAN1_RX \ 1311 SAM_PINMUX(d, 28, b, periph) 1312 1313 /* pd28c_twi2_twck */ 1314 #define PD28C_TWI2_TWCK \ 1315 SAM_PINMUX(d, 28, c, periph) 1316 1317 /* pd28d_isi_d9 */ 1318 #define PD28D_ISI_D9 \ 1319 SAM_PINMUX(d, 28, d, periph) 1320 1321 /* pd28x_supc_wkup5 */ 1322 #define PD28X_SUPC_WKUP5 \ 1323 SAM_PINMUX(d, 28, wkup5, wakeup) 1324 1325 /* pd30_gpio */ 1326 #define PD30_GPIO \ 1327 SAM_PINMUX(d, 30, gpio, gpio) 1328 1329 /* pd30a_uart3_txd */ 1330 #define PD30A_UART3_TXD \ 1331 SAM_PINMUX(d, 30, a, periph) 1332 1333 /* pd30d_isi_d10 */ 1334 #define PD30D_ISI_D10 \ 1335 SAM_PINMUX(d, 30, d, periph) 1336 1337 /* pd30x_afe0_ad0 */ 1338 #define PD30X_AFE0_AD0 \ 1339 SAM_PINMUX(d, 30, x, extra) 1340 1341 /* pd31_gpio */ 1342 #define PD31_GPIO \ 1343 SAM_PINMUX(d, 31, gpio, gpio) 1344 1345 /* pd31a_qspi_qio3 */ 1346 #define PD31A_QSPI_QIO3 \ 1347 SAM_PINMUX(d, 31, a, periph) 1348 1349 /* pd31b_uart3_txd */ 1350 #define PD31B_UART3_TXD \ 1351 SAM_PINMUX(d, 31, b, periph) 1352 1353 /* pd31c_pmc_pck2 */ 1354 #define PD31C_PMC_PCK2 \ 1355 SAM_PINMUX(d, 31, c, periph) 1356 1357 /* pd31d_isi_d11 */ 1358 #define PD31D_ISI_D11 \ 1359 SAM_PINMUX(d, 31, d, periph) 1360
