1 /* 2 * Autogenerated file 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #include <dt-bindings/pinctrl/atmel_sam_pinctrl.h> 8 9 /* 10 * WARNING: this variant has package exception. 11 * 12 * Read datasheet topics related to I/O Multiplexing and Considerations or 13 * Peripheral Signal Multiplexing on I/O Lines for more information. 14 */ 15 16 /* pa3_gpio */ 17 #define PA3_GPIO \ 18 SAM_PINMUX(a, 3, gpio, gpio) 19 20 /* pa3a_twi0_twd */ 21 #define PA3A_TWI0_TWD \ 22 SAM_PINMUX(a, 3, a, periph) 23 24 /* pa3b_lon_col1 */ 25 #define PA3B_LON_COL1 \ 26 SAM_PINMUX(a, 3, b, periph) 27 28 /* pa3c_pmc_pck2 */ 29 #define PA3C_PMC_PCK2 \ 30 SAM_PINMUX(a, 3, c, periph) 31 32 /* pa3x_pio_piodc0 */ 33 #define PA3X_PIO_PIODC0 \ 34 SAM_PINMUX(a, 3, x, extra) 35 36 /* pa4_gpio */ 37 #define PA4_GPIO \ 38 SAM_PINMUX(a, 4, gpio, gpio) 39 40 /* pa4a_twi0_twck */ 41 #define PA4A_TWI0_TWCK \ 42 SAM_PINMUX(a, 4, a, periph) 43 44 /* pa4b_tc0_tclk0 */ 45 #define PA4B_TC0_TCLK0 \ 46 SAM_PINMUX(a, 4, b, periph) 47 48 /* pa4c_uart1_txd */ 49 #define PA4C_UART1_TXD \ 50 SAM_PINMUX(a, 4, c, periph) 51 52 /* pa4x_pio_piodc1 */ 53 #define PA4X_PIO_PIODC1 \ 54 SAM_PINMUX(a, 4, x, extra) 55 56 /* pa4x_supc_wkup3 */ 57 #define PA4X_SUPC_WKUP3 \ 58 SAM_PINMUX(a, 4, wkup3, wakeup) 59 60 /* pa5_gpio */ 61 #define PA5_GPIO \ 62 SAM_PINMUX(a, 5, gpio, gpio) 63 64 /* pa5a_pwmc1_pwml3 */ 65 #define PA5A_PWMC1_PWML3 \ 66 SAM_PINMUX(a, 5, a, periph) 67 68 /* pa5b_isi_d4 */ 69 #define PA5B_ISI_D4 \ 70 SAM_PINMUX(a, 5, b, periph) 71 72 /* pa5c_uart1_rxd */ 73 #define PA5C_UART1_RXD \ 74 SAM_PINMUX(a, 5, c, periph) 75 76 /* pa5x_pio_piodc2 */ 77 #define PA5X_PIO_PIODC2 \ 78 SAM_PINMUX(a, 5, x, extra) 79 80 /* pa5x_supc_wkup4 */ 81 #define PA5X_SUPC_WKUP4 \ 82 SAM_PINMUX(a, 5, wkup4, wakeup) 83 84 /* pa6_gpio */ 85 #define PA6_GPIO \ 86 SAM_PINMUX(a, 6, gpio, gpio) 87 88 /* pa6b_pmc_pck0 */ 89 #define PA6B_PMC_PCK0 \ 90 SAM_PINMUX(a, 6, b, periph) 91 92 /* pa6c_uart1_txd */ 93 #define PA6C_UART1_TXD \ 94 SAM_PINMUX(a, 6, c, periph) 95 96 /* pa7_gpio */ 97 #define PA7_GPIO \ 98 SAM_PINMUX(a, 7, gpio, gpio) 99 100 /* pa7b_pwmc0_pwmh3 */ 101 #define PA7B_PWMC0_PWMH3 \ 102 SAM_PINMUX(a, 7, b, periph) 103 104 /* pa7s_supc_xin32 */ 105 #define PA7S_SUPC_XIN32 \ 106 SAM_PINMUX(a, 7, s, system) 107 108 /* pa8_gpio */ 109 #define PA8_GPIO \ 110 SAM_PINMUX(a, 8, gpio, gpio) 111 112 /* pa8a_pwmc1_pwmh3 */ 113 #define PA8A_PWMC1_PWMH3 \ 114 SAM_PINMUX(a, 8, a, periph) 115 116 /* pa8b_afe0_adtrg */ 117 #define PA8B_AFE0_ADTRG \ 118 SAM_PINMUX(a, 8, b, periph) 119 120 /* pa8s_supc_xout32 */ 121 #define PA8S_SUPC_XOUT32 \ 122 SAM_PINMUX(a, 8, s, system) 123 124 /* pa9_gpio */ 125 #define PA9_GPIO \ 126 SAM_PINMUX(a, 9, gpio, gpio) 127 128 /* pa9a_uart0_rxd */ 129 #define PA9A_UART0_RXD \ 130 SAM_PINMUX(a, 9, a, periph) 131 132 /* pa9b_isi_d3 */ 133 #define PA9B_ISI_D3 \ 134 SAM_PINMUX(a, 9, b, periph) 135 136 /* pa9c_pwmc0_pwmfi0 */ 137 #define PA9C_PWMC0_PWMFI0 \ 138 SAM_PINMUX(a, 9, c, periph) 139 140 /* pa9x_pio_piodc3 */ 141 #define PA9X_PIO_PIODC3 \ 142 SAM_PINMUX(a, 9, x, extra) 143 144 /* pa9x_supc_wkup6 */ 145 #define PA9X_SUPC_WKUP6 \ 146 SAM_PINMUX(a, 9, wkup6, wakeup) 147 148 /* pa10_gpio */ 149 #define PA10_GPIO \ 150 SAM_PINMUX(a, 10, gpio, gpio) 151 152 /* pa10a_uart0_txd */ 153 #define PA10A_UART0_TXD \ 154 SAM_PINMUX(a, 10, a, periph) 155 156 /* pa10b_pwmc0_pwmextrg0 */ 157 #define PA10B_PWMC0_PWMEXTRG0 \ 158 SAM_PINMUX(a, 10, b, periph) 159 160 /* pa10c_ssc_rd */ 161 #define PA10C_SSC_RD \ 162 SAM_PINMUX(a, 10, c, periph) 163 164 /* pa10x_pio_piodc4 */ 165 #define PA10X_PIO_PIODC4 \ 166 SAM_PINMUX(a, 10, x, extra) 167 168 /* pa11_gpio */ 169 #define PA11_GPIO \ 170 SAM_PINMUX(a, 11, gpio, gpio) 171 172 /* pa11a_qspi_qcs */ 173 #define PA11A_QSPI_QCS \ 174 SAM_PINMUX(a, 11, a, periph) 175 176 /* pa11b_pwmc0_pwmh0 */ 177 #define PA11B_PWMC0_PWMH0 \ 178 SAM_PINMUX(a, 11, b, periph) 179 180 /* pa11c_pwmc1_pwml0 */ 181 #define PA11C_PWMC1_PWML0 \ 182 SAM_PINMUX(a, 11, c, periph) 183 184 /* pa11x_pio_piodc5 */ 185 #define PA11X_PIO_PIODC5 \ 186 SAM_PINMUX(a, 11, x, extra) 187 188 /* pa11x_supc_wkup7 */ 189 #define PA11X_SUPC_WKUP7 \ 190 SAM_PINMUX(a, 11, wkup7, wakeup) 191 192 /* pa12_gpio */ 193 #define PA12_GPIO \ 194 SAM_PINMUX(a, 12, gpio, gpio) 195 196 /* pa12a_qspi_qio1 */ 197 #define PA12A_QSPI_QIO1 \ 198 SAM_PINMUX(a, 12, a, periph) 199 200 /* pa12b_pwmc0_pwmh1 */ 201 #define PA12B_PWMC0_PWMH1 \ 202 SAM_PINMUX(a, 12, b, periph) 203 204 /* pa12c_pwmc1_pwmh0 */ 205 #define PA12C_PWMC1_PWMH0 \ 206 SAM_PINMUX(a, 12, c, periph) 207 208 /* pa12x_pio_piodc6 */ 209 #define PA12X_PIO_PIODC6 \ 210 SAM_PINMUX(a, 12, x, extra) 211 212 /* pa13_gpio */ 213 #define PA13_GPIO \ 214 SAM_PINMUX(a, 13, gpio, gpio) 215 216 /* pa13a_qspi_qio0 */ 217 #define PA13A_QSPI_QIO0 \ 218 SAM_PINMUX(a, 13, a, periph) 219 220 /* pa13b_pwmc0_pwmh2 */ 221 #define PA13B_PWMC0_PWMH2 \ 222 SAM_PINMUX(a, 13, b, periph) 223 224 /* pa13c_pwmc1_pwml1 */ 225 #define PA13C_PWMC1_PWML1 \ 226 SAM_PINMUX(a, 13, c, periph) 227 228 /* pa13x_pio_piodc7 */ 229 #define PA13X_PIO_PIODC7 \ 230 SAM_PINMUX(a, 13, x, extra) 231 232 /* pa14_gpio */ 233 #define PA14_GPIO \ 234 SAM_PINMUX(a, 14, gpio, gpio) 235 236 /* pa14a_qspi_qsck */ 237 #define PA14A_QSPI_QSCK \ 238 SAM_PINMUX(a, 14, a, periph) 239 240 /* pa14b_pwmc0_pwmh3 */ 241 #define PA14B_PWMC0_PWMH3 \ 242 SAM_PINMUX(a, 14, b, periph) 243 244 /* pa14c_pwmc1_pwmh1 */ 245 #define PA14C_PWMC1_PWMH1 \ 246 SAM_PINMUX(a, 14, c, periph) 247 248 /* pa14x_pio_pioden1 */ 249 #define PA14X_PIO_PIODEN1 \ 250 SAM_PINMUX(a, 14, x, extra) 251 252 /* pa14x_supc_wkup8 */ 253 #define PA14X_SUPC_WKUP8 \ 254 SAM_PINMUX(a, 14, wkup8, wakeup) 255 256 /* pa21_gpio */ 257 #define PA21_GPIO \ 258 SAM_PINMUX(a, 21, gpio, gpio) 259 260 /* pa21a_usart1_rxd */ 261 #define PA21A_USART1_RXD \ 262 SAM_PINMUX(a, 21, a, periph) 263 264 /* pa21b_pmc_pck1 */ 265 #define PA21B_PMC_PCK1 \ 266 SAM_PINMUX(a, 21, b, periph) 267 268 /* pa21c_pwmc1_pwmfi0 */ 269 #define PA21C_PWMC1_PWMFI0 \ 270 SAM_PINMUX(a, 21, c, periph) 271 272 /* pa21x_afe0_ad1 */ 273 #define PA21X_AFE0_AD1 \ 274 SAM_PINMUX(a, 21, x, extra) 275 276 /* pa21x_pio_piodcen2 */ 277 #define PA21X_PIO_PIODCEN2 \ 278 SAM_PINMUX(a, 21, x, extra) 279 280 /* pa22_gpio */ 281 #define PA22_GPIO \ 282 SAM_PINMUX(a, 22, gpio, gpio) 283 284 /* pa22a_ssc_rk */ 285 #define PA22A_SSC_RK \ 286 SAM_PINMUX(a, 22, a, periph) 287 288 /* pa22b_pwmc0_pwmextrg1 */ 289 #define PA22B_PWMC0_PWMEXTRG1 \ 290 SAM_PINMUX(a, 22, b, periph) 291 292 /* pa22x_pio_piodcclk */ 293 #define PA22X_PIO_PIODCCLK \ 294 SAM_PINMUX(a, 22, x, extra) 295 296 /* pa24_gpio */ 297 #define PA24_GPIO \ 298 SAM_PINMUX(a, 24, gpio, gpio) 299 300 /* pa24a_usart1_rts */ 301 #define PA24A_USART1_RTS \ 302 SAM_PINMUX(a, 24, a, periph) 303 304 /* pa24b_pwmc0_pwmh1 */ 305 #define PA24B_PWMC0_PWMH1 \ 306 SAM_PINMUX(a, 24, b, periph) 307 308 /* pa24d_isi_pck */ 309 #define PA24D_ISI_PCK \ 310 SAM_PINMUX(a, 24, d, periph) 311 312 /* pa27_gpio */ 313 #define PA27_GPIO \ 314 SAM_PINMUX(a, 27, gpio, gpio) 315 316 /* pa27a_usart1_dtr */ 317 #define PA27A_USART1_DTR \ 318 SAM_PINMUX(a, 27, a, periph) 319 320 /* pa27b_tc0_tiob2 */ 321 #define PA27B_TC0_TIOB2 \ 322 SAM_PINMUX(a, 27, b, periph) 323 324 /* pa27c_hsmci_mcda3 */ 325 #define PA27C_HSMCI_MCDA3 \ 326 SAM_PINMUX(a, 27, c, periph) 327 328 /* pa27d_isi_d7 */ 329 #define PA27D_ISI_D7 \ 330 SAM_PINMUX(a, 27, d, periph) 331 332 /* pa30_gpio */ 333 #define PA30_GPIO \ 334 SAM_PINMUX(a, 30, gpio, gpio) 335 336 /* pa30a_pwmc0_pwml2 */ 337 #define PA30A_PWMC0_PWML2 \ 338 SAM_PINMUX(a, 30, a, periph) 339 340 /* pa30b_pwmc1_pwmextrg0 */ 341 #define PA30B_PWMC1_PWMEXTRG0 \ 342 SAM_PINMUX(a, 30, b, periph) 343 344 /* pa30c_hsmci_mcda0 */ 345 #define PA30C_HSMCI_MCDA0 \ 346 SAM_PINMUX(a, 30, c, periph) 347 348 /* pa30d_i2sc0_do */ 349 #define PA30D_I2SC0_DO \ 350 SAM_PINMUX(a, 30, d, periph) 351 352 /* pa30x_supc_wkup11 */ 353 #define PA30X_SUPC_WKUP11 \ 354 SAM_PINMUX(a, 30, wkup11, wakeup) 355 356 /* pb0_gpio */ 357 #define PB0_GPIO \ 358 SAM_PINMUX(b, 0, gpio, gpio) 359 360 /* pb0a_pwmc0_pwmh0 */ 361 #define PB0A_PWMC0_PWMH0 \ 362 SAM_PINMUX(b, 0, a, periph) 363 364 /* pb0c_usart0_rxd */ 365 #define PB0C_USART0_RXD \ 366 SAM_PINMUX(b, 0, c, periph) 367 368 /* pb0d_ssc_tf */ 369 #define PB0D_SSC_TF \ 370 SAM_PINMUX(b, 0, d, periph) 371 372 /* pb0x_afe0_ad10 */ 373 #define PB0X_AFE0_AD10 \ 374 SAM_PINMUX(b, 0, x, extra) 375 376 /* pb0x_rtc_out0 */ 377 #define PB0X_RTC_OUT0 \ 378 SAM_PINMUX(b, 0, x, extra) 379 380 /* pb1_gpio */ 381 #define PB1_GPIO \ 382 SAM_PINMUX(b, 1, gpio, gpio) 383 384 /* pb1a_pwmc0_pwmh1 */ 385 #define PB1A_PWMC0_PWMH1 \ 386 SAM_PINMUX(b, 1, a, periph) 387 388 /* pb1b_gmac_gtsucomp */ 389 #define PB1B_GMAC_GTSUCOMP \ 390 SAM_PINMUX(b, 1, b, periph) 391 392 /* pb1c_usart0_txd */ 393 #define PB1C_USART0_TXD \ 394 SAM_PINMUX(b, 1, c, periph) 395 396 /* pb1d_ssc_tk */ 397 #define PB1D_SSC_TK \ 398 SAM_PINMUX(b, 1, d, periph) 399 400 /* pb1x_afe1_ad0 */ 401 #define PB1X_AFE1_AD0 \ 402 SAM_PINMUX(b, 1, x, extra) 403 404 /* pb1x_rtc_out1 */ 405 #define PB1X_RTC_OUT1 \ 406 SAM_PINMUX(b, 1, x, extra) 407 408 /* pb2_gpio */ 409 #define PB2_GPIO \ 410 SAM_PINMUX(b, 2, gpio, gpio) 411 412 /* pb2a_can0_tx */ 413 #define PB2A_CAN0_TX \ 414 SAM_PINMUX(b, 2, a, periph) 415 416 /* pb2c_usart0_cts */ 417 #define PB2C_USART0_CTS \ 418 SAM_PINMUX(b, 2, c, periph) 419 420 /* pb2d_spi0_npcs0 */ 421 #define PB2D_SPI0_NPCS0 \ 422 SAM_PINMUX(b, 2, d, periph) 423 424 /* pb2x_afe0_ad5 */ 425 #define PB2X_AFE0_AD5 \ 426 SAM_PINMUX(b, 2, x, extra) 427 428 /* pb3_gpio */ 429 #define PB3_GPIO \ 430 SAM_PINMUX(b, 3, gpio, gpio) 431 432 /* pb3a_can0_rx */ 433 #define PB3A_CAN0_RX \ 434 SAM_PINMUX(b, 3, a, periph) 435 436 /* pb3b_pmc_pck2 */ 437 #define PB3B_PMC_PCK2 \ 438 SAM_PINMUX(b, 3, b, periph) 439 440 /* pb3c_usart0_rts */ 441 #define PB3C_USART0_RTS \ 442 SAM_PINMUX(b, 3, c, periph) 443 444 /* pb3d_isi_d2 */ 445 #define PB3D_ISI_D2 \ 446 SAM_PINMUX(b, 3, d, periph) 447 448 /* pb3x_afe0_ad2 */ 449 #define PB3X_AFE0_AD2 \ 450 SAM_PINMUX(b, 3, x, extra) 451 452 /* pb3x_supc_wkup12 */ 453 #define PB3X_SUPC_WKUP12 \ 454 SAM_PINMUX(b, 3, wkup12, wakeup) 455 456 /* pb4_gpio */ 457 #define PB4_GPIO \ 458 SAM_PINMUX(b, 4, gpio, gpio) 459 460 /* pb4a_twi1_twd */ 461 #define PB4A_TWI1_TWD \ 462 SAM_PINMUX(b, 4, a, periph) 463 464 /* pb4b_pwmc0_pwmh2 */ 465 #define PB4B_PWMC0_PWMH2 \ 466 SAM_PINMUX(b, 4, b, periph) 467 468 /* pb4c_mlb_clk */ 469 #define PB4C_MLB_CLK \ 470 SAM_PINMUX(b, 4, c, periph) 471 472 /* pb4d_usart1_txd */ 473 #define PB4D_USART1_TXD \ 474 SAM_PINMUX(b, 4, d, periph) 475 476 /* pb4s_jtag_tdi */ 477 #define PB4S_JTAG_TDI \ 478 SAM_PINMUX(b, 4, s, system) 479 480 /* pb5_gpio */ 481 #define PB5_GPIO \ 482 SAM_PINMUX(b, 5, gpio, gpio) 483 484 /* pb5a_twi1_twck */ 485 #define PB5A_TWI1_TWCK \ 486 SAM_PINMUX(b, 5, a, periph) 487 488 /* pb5b_pwmc0_pwml0 */ 489 #define PB5B_PWMC0_PWML0 \ 490 SAM_PINMUX(b, 5, b, periph) 491 492 /* pb5c_mlb_dat */ 493 #define PB5C_MLB_DAT \ 494 SAM_PINMUX(b, 5, c, periph) 495 496 /* pb5d_ssc_td */ 497 #define PB5D_SSC_TD \ 498 SAM_PINMUX(b, 5, d, periph) 499 500 /* pb5s_jtag_tdo */ 501 #define PB5S_JTAG_TDO \ 502 SAM_PINMUX(b, 5, s, system) 503 504 /* pb5s_swd_traceswo */ 505 #define PB5S_SWD_TRACESWO \ 506 SAM_PINMUX(b, 5, s, system) 507 508 /* pb5x_supc_wkup13 */ 509 #define PB5X_SUPC_WKUP13 \ 510 SAM_PINMUX(b, 5, wkup13, wakeup) 511 512 /* pb6_gpio */ 513 #define PB6_GPIO \ 514 SAM_PINMUX(b, 6, gpio, gpio) 515 516 /* pb6s_jtag_tms */ 517 #define PB6S_JTAG_TMS \ 518 SAM_PINMUX(b, 6, s, system) 519 520 /* pb6s_swd_swdio */ 521 #define PB6S_SWD_SWDIO \ 522 SAM_PINMUX(b, 6, s, system) 523 524 /* pb7_gpio */ 525 #define PB7_GPIO \ 526 SAM_PINMUX(b, 7, gpio, gpio) 527 528 /* pb7s_jtag_tck */ 529 #define PB7S_JTAG_TCK \ 530 SAM_PINMUX(b, 7, s, system) 531 532 /* pb7s_swd_swclk */ 533 #define PB7S_SWD_SWCLK \ 534 SAM_PINMUX(b, 7, s, system) 535 536 /* pb8_gpio */ 537 #define PB8_GPIO \ 538 SAM_PINMUX(b, 8, gpio, gpio) 539 540 /* pb8s_supc_xout */ 541 #define PB8S_SUPC_XOUT \ 542 SAM_PINMUX(b, 8, s, system) 543 544 /* pb9_gpio */ 545 #define PB9_GPIO \ 546 SAM_PINMUX(b, 9, gpio, gpio) 547 548 /* pb9s_supc_xin */ 549 #define PB9S_SUPC_XIN \ 550 SAM_PINMUX(b, 9, s, system) 551 552 /* pb12_gpio */ 553 #define PB12_GPIO \ 554 SAM_PINMUX(b, 12, gpio, gpio) 555 556 /* pb12a_pwmc0_pwml1 */ 557 #define PB12A_PWMC0_PWML1 \ 558 SAM_PINMUX(b, 12, a, periph) 559 560 /* pb12b_gmac_gtsucomp */ 561 #define PB12B_GMAC_GTSUCOMP \ 562 SAM_PINMUX(b, 12, b, periph) 563 564 /* pb12d_pcm_pck0 */ 565 #define PB12D_PCM_PCK0 \ 566 SAM_PINMUX(b, 12, d, periph) 567 568 /* pb12s_flash_erase */ 569 #define PB12S_FLASH_ERASE \ 570 SAM_PINMUX(b, 12, s, system) 571 572 /* pd0_gpio */ 573 #define PD0_GPIO \ 574 SAM_PINMUX(d, 0, gpio, gpio) 575 576 /* pd0a_gmac_gtxck */ 577 #define PD0A_GMAC_GTXCK \ 578 SAM_PINMUX(d, 0, a, periph) 579 580 /* pd0b_pwmc1_pwml0 */ 581 #define PD0B_PWMC1_PWML0 \ 582 SAM_PINMUX(d, 0, b, periph) 583 584 /* pd0c_spi1_npcs1 */ 585 #define PD0C_SPI1_NPCS1 \ 586 SAM_PINMUX(d, 0, c, periph) 587 588 /* pd0d_usart0_dcd */ 589 #define PD0D_USART0_DCD \ 590 SAM_PINMUX(d, 0, d, periph) 591 592 /* pd0x_dacc_dac1 */ 593 #define PD0X_DACC_DAC1 \ 594 SAM_PINMUX(d, 0, x, extra) 595 596 /* pd1_gpio */ 597 #define PD1_GPIO \ 598 SAM_PINMUX(d, 1, gpio, gpio) 599 600 /* pd1a_gmac_gtxen */ 601 #define PD1A_GMAC_GTXEN \ 602 SAM_PINMUX(d, 1, a, periph) 603 604 /* pd1b_pwmc1_pwmh0 */ 605 #define PD1B_PWMC1_PWMH0 \ 606 SAM_PINMUX(d, 1, b, periph) 607 608 /* pd1c_spi1_npcs2 */ 609 #define PD1C_SPI1_NPCS2 \ 610 SAM_PINMUX(d, 1, c, periph) 611 612 /* pd1d_usart0_dtr */ 613 #define PD1D_USART0_DTR \ 614 SAM_PINMUX(d, 1, d, periph) 615 616 /* pd2_gpio */ 617 #define PD2_GPIO \ 618 SAM_PINMUX(d, 2, gpio, gpio) 619 620 /* pd2a_gmac_gtx0 */ 621 #define PD2A_GMAC_GTX0 \ 622 SAM_PINMUX(d, 2, a, periph) 623 624 /* pd2b_pwmc1_pwml1 */ 625 #define PD2B_PWMC1_PWML1 \ 626 SAM_PINMUX(d, 2, b, periph) 627 628 /* pd2c_spi1_npcs3 */ 629 #define PD2C_SPI1_NPCS3 \ 630 SAM_PINMUX(d, 2, c, periph) 631 632 /* pd2d_usart0_dsr */ 633 #define PD2D_USART0_DSR \ 634 SAM_PINMUX(d, 2, d, periph) 635 636 /* pd3_gpio */ 637 #define PD3_GPIO \ 638 SAM_PINMUX(d, 3, gpio, gpio) 639 640 /* pd3a_gmac_gtx1 */ 641 #define PD3A_GMAC_GTX1 \ 642 SAM_PINMUX(d, 3, a, periph) 643 644 /* pd3b_pwmc1_pwmh1 */ 645 #define PD3B_PWMC1_PWMH1 \ 646 SAM_PINMUX(d, 3, b, periph) 647 648 /* pd3c_uart4_txd */ 649 #define PD3C_UART4_TXD \ 650 SAM_PINMUX(d, 3, c, periph) 651 652 /* pd3d_usart0_ri */ 653 #define PD3D_USART0_RI \ 654 SAM_PINMUX(d, 3, d, periph) 655 656 /* pd4_gpio */ 657 #define PD4_GPIO \ 658 SAM_PINMUX(d, 4, gpio, gpio) 659 660 /* pd4a_gmac_grxdv */ 661 #define PD4A_GMAC_GRXDV \ 662 SAM_PINMUX(d, 4, a, periph) 663 664 /* pd4b_pwmc1_pwml2 */ 665 #define PD4B_PWMC1_PWML2 \ 666 SAM_PINMUX(d, 4, b, periph) 667 668 /* pd4c_trace_d0 */ 669 #define PD4C_TRACE_D0 \ 670 SAM_PINMUX(d, 4, c, periph) 671 672 /* pd4d_usart2_dcd */ 673 #define PD4D_USART2_DCD \ 674 SAM_PINMUX(d, 4, d, periph) 675 676 /* pd5_gpio */ 677 #define PD5_GPIO \ 678 SAM_PINMUX(d, 5, gpio, gpio) 679 680 /* pd5a_gmac_grx0 */ 681 #define PD5A_GMAC_GRX0 \ 682 SAM_PINMUX(d, 5, a, periph) 683 684 /* pd5b_pwmc1_pwmh2 */ 685 #define PD5B_PWMC1_PWMH2 \ 686 SAM_PINMUX(d, 5, b, periph) 687 688 /* pd5c_trace_d1 */ 689 #define PD5C_TRACE_D1 \ 690 SAM_PINMUX(d, 5, c, periph) 691 692 /* pd5d_usart2_dtr */ 693 #define PD5D_USART2_DTR \ 694 SAM_PINMUX(d, 5, d, periph) 695 696 /* pd6_gpio */ 697 #define PD6_GPIO \ 698 SAM_PINMUX(d, 6, gpio, gpio) 699 700 /* pd6a_gmac_grx1 */ 701 #define PD6A_GMAC_GRX1 \ 702 SAM_PINMUX(d, 6, a, periph) 703 704 /* pd6b_pwmc1_pwml3 */ 705 #define PD6B_PWMC1_PWML3 \ 706 SAM_PINMUX(d, 6, b, periph) 707 708 /* pd6c_trace_d2 */ 709 #define PD6C_TRACE_D2 \ 710 SAM_PINMUX(d, 6, c, periph) 711 712 /* pd6d_usart2_dsr */ 713 #define PD6D_USART2_DSR \ 714 SAM_PINMUX(d, 6, d, periph) 715 716 /* pd7_gpio */ 717 #define PD7_GPIO \ 718 SAM_PINMUX(d, 7, gpio, gpio) 719 720 /* pd7a_gmac_grxer */ 721 #define PD7A_GMAC_GRXER \ 722 SAM_PINMUX(d, 7, a, periph) 723 724 /* pd7b_pwmc1_pwmh3 */ 725 #define PD7B_PWMC1_PWMH3 \ 726 SAM_PINMUX(d, 7, b, periph) 727 728 /* pd7c_trace_d3 */ 729 #define PD7C_TRACE_D3 \ 730 SAM_PINMUX(d, 7, c, periph) 731 732 /* pd7d_usart2_ri */ 733 #define PD7D_USART2_RI \ 734 SAM_PINMUX(d, 7, d, periph) 735 736 /* pd8_gpio */ 737 #define PD8_GPIO \ 738 SAM_PINMUX(d, 8, gpio, gpio) 739 740 /* pd8a_gmac_gmdc */ 741 #define PD8A_GMAC_GMDC \ 742 SAM_PINMUX(d, 8, a, periph) 743 744 /* pd8b_pwmc0_pwmfi1 */ 745 #define PD8B_PWMC0_PWMFI1 \ 746 SAM_PINMUX(d, 8, b, periph) 747 748 /* pd8d_trace_clk */ 749 #define PD8D_TRACE_CLK \ 750 SAM_PINMUX(d, 8, d, periph) 751 752 /* pd9_gpio */ 753 #define PD9_GPIO \ 754 SAM_PINMUX(d, 9, gpio, gpio) 755 756 /* pd9a_gmac_gmdio */ 757 #define PD9A_GMAC_GMDIO \ 758 SAM_PINMUX(d, 9, a, periph) 759 760 /* pd9b_pwmc0_pwmfi2 */ 761 #define PD9B_PWMC0_PWMFI2 \ 762 SAM_PINMUX(d, 9, b, periph) 763 764 /* pd9c_afe1_adtrg */ 765 #define PD9C_AFE1_ADTRG \ 766 SAM_PINMUX(d, 9, c, periph) 767 768 /* pd10_gpio */ 769 #define PD10_GPIO \ 770 SAM_PINMUX(d, 10, gpio, gpio) 771 772 /* pd10a_gmac_gcrs */ 773 #define PD10A_GMAC_GCRS \ 774 SAM_PINMUX(d, 10, a, periph) 775 776 /* pd10b_pwmc0_pwml0 */ 777 #define PD10B_PWMC0_PWML0 \ 778 SAM_PINMUX(d, 10, b, periph) 779 780 /* pd10c_ssc_td */ 781 #define PD10C_SSC_TD \ 782 SAM_PINMUX(d, 10, c, periph) 783 784 /* pd10d_mlb_sig */ 785 #define PD10D_MLB_SIG \ 786 SAM_PINMUX(d, 10, d, periph) 787 788 /* pd11_gpio */ 789 #define PD11_GPIO \ 790 SAM_PINMUX(d, 11, gpio, gpio) 791 792 /* pd11a_gmac_grx2 */ 793 #define PD11A_GMAC_GRX2 \ 794 SAM_PINMUX(d, 11, a, periph) 795 796 /* pd11b_pwmc0_pwmh0 */ 797 #define PD11B_PWMC0_PWMH0 \ 798 SAM_PINMUX(d, 11, b, periph) 799 800 /* pd11c_gmac_gtsucomp */ 801 #define PD11C_GMAC_GTSUCOMP \ 802 SAM_PINMUX(d, 11, c, periph) 803 804 /* pd11d_isi_d5 */ 805 #define PD11D_ISI_D5 \ 806 SAM_PINMUX(d, 11, d, periph) 807 808 /* pd12_gpio */ 809 #define PD12_GPIO \ 810 SAM_PINMUX(d, 12, gpio, gpio) 811 812 /* pd12a_gmac_grx3 */ 813 #define PD12A_GMAC_GRX3 \ 814 SAM_PINMUX(d, 12, a, periph) 815 816 /* pd12b_can1_tx */ 817 #define PD12B_CAN1_TX \ 818 SAM_PINMUX(d, 12, b, periph) 819 820 /* pd12c_spi0_npcs2 */ 821 #define PD12C_SPI0_NPCS2 \ 822 SAM_PINMUX(d, 12, c, periph) 823 824 /* pd12d_isi_d6 */ 825 #define PD12D_ISI_D6 \ 826 SAM_PINMUX(d, 12, d, periph) 827 828 /* pd21_gpio */ 829 #define PD21_GPIO \ 830 SAM_PINMUX(d, 21, gpio, gpio) 831 832 /* pd21a_pwmc0_pwmh1 */ 833 #define PD21A_PWMC0_PWMH1 \ 834 SAM_PINMUX(d, 21, a, periph) 835 836 /* pd21b_spi0_mosi */ 837 #define PD21B_SPI0_MOSI \ 838 SAM_PINMUX(d, 21, b, periph) 839 840 /* pd21c_tc3_tioa11 */ 841 #define PD21C_TC3_TIOA11 \ 842 SAM_PINMUX(d, 21, c, periph) 843 844 /* pd21d_isi_d1 */ 845 #define PD21D_ISI_D1 \ 846 SAM_PINMUX(d, 21, d, periph) 847 848 /* pd22_gpio */ 849 #define PD22_GPIO \ 850 SAM_PINMUX(d, 22, gpio, gpio) 851 852 /* pd22a_pwmc0_pwmh2 */ 853 #define PD22A_PWMC0_PWMH2 \ 854 SAM_PINMUX(d, 22, a, periph) 855 856 /* pd22b_spi0_spck */ 857 #define PD22B_SPI0_SPCK \ 858 SAM_PINMUX(d, 22, b, periph) 859 860 /* pd22c_tc3_tiob11 */ 861 #define PD22C_TC3_TIOB11 \ 862 SAM_PINMUX(d, 22, c, periph) 863 864 /* pd22d_isi_d0 */ 865 #define PD22D_ISI_D0 \ 866 SAM_PINMUX(d, 22, d, periph) 867 868 /* pd24_gpio */ 869 #define PD24_GPIO \ 870 SAM_PINMUX(d, 24, gpio, gpio) 871 872 /* pd24a_pwmc0_pwml0 */ 873 #define PD24A_PWMC0_PWML0 \ 874 SAM_PINMUX(d, 24, a, periph) 875 876 /* pd24b_ssc_rf */ 877 #define PD24B_SSC_RF \ 878 SAM_PINMUX(d, 24, b, periph) 879 880 /* pd24c_tc3_tclk11 */ 881 #define PD24C_TC3_TCLK11 \ 882 SAM_PINMUX(d, 24, c, periph) 883 884 /* pd24d_isi_hsync */ 885 #define PD24D_ISI_HSYNC \ 886 SAM_PINMUX(d, 24, d, periph) 887 888 /* pd25_gpio */ 889 #define PD25_GPIO \ 890 SAM_PINMUX(d, 25, gpio, gpio) 891 892 /* pd25a_pwmc0_pwml1 */ 893 #define PD25A_PWMC0_PWML1 \ 894 SAM_PINMUX(d, 25, a, periph) 895 896 /* pd25b_spi0_npcs1 */ 897 #define PD25B_SPI0_NPCS1 \ 898 SAM_PINMUX(d, 25, b, periph) 899 900 /* pd25c_uart2_rxd */ 901 #define PD25C_UART2_RXD \ 902 SAM_PINMUX(d, 25, c, periph) 903 904 /* pd25d_isi_vsync */ 905 #define PD25D_ISI_VSYNC \ 906 SAM_PINMUX(d, 25, d, periph) 907 908 /* pd26_gpio */ 909 #define PD26_GPIO \ 910 SAM_PINMUX(d, 26, gpio, gpio) 911 912 /* pd26a_pwmc0_pwml2 */ 913 #define PD26A_PWMC0_PWML2 \ 914 SAM_PINMUX(d, 26, a, periph) 915 916 /* pd26b_ssc_td */ 917 #define PD26B_SSC_TD \ 918 SAM_PINMUX(d, 26, b, periph) 919 920 /* pd26c_uart2_txd */ 921 #define PD26C_UART2_TXD \ 922 SAM_PINMUX(d, 26, c, periph) 923 924 /* pd26d_uart1_txd */ 925 #define PD26D_UART1_TXD \ 926 SAM_PINMUX(d, 26, d, periph) 927 928 /* pd31_gpio */ 929 #define PD31_GPIO \ 930 SAM_PINMUX(d, 31, gpio, gpio) 931 932 /* pd31a_qspi_qio3 */ 933 #define PD31A_QSPI_QIO3 \ 934 SAM_PINMUX(d, 31, a, periph) 935 936 /* pd31b_uart3_txd */ 937 #define PD31B_UART3_TXD \ 938 SAM_PINMUX(d, 31, b, periph) 939 940 /* pd31c_pmc_pck2 */ 941 #define PD31C_PMC_PCK2 \ 942 SAM_PINMUX(d, 31, c, periph) 943 944 /* pd31d_isi_d11 */ 945 #define PD31D_ISI_D11 \ 946 SAM_PINMUX(d, 31, d, periph) 947
