1 /* 2 * Autogenerated file 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #include <dt-bindings/pinctrl/atmel_sam_pinctrl.h> 8 9 /* pa0_gpio */ 10 #define PA0_GPIO \ 11 SAM_PINMUX(a, 0, gpio, gpio) 12 13 /* pa0a_eic_extint0 */ 14 #define PA0A_EIC_EXTINT0 \ 15 SAM_PINMUX(a, 0, a, periph) 16 17 /* pa0d_sercom1_pad0 */ 18 #define PA0D_SERCOM1_PAD0 \ 19 SAM_PINMUX(a, 0, d, periph) 20 21 /* pa0e_tcc2_wo0 */ 22 #define PA0E_TCC2_WO0 \ 23 SAM_PINMUX(a, 0, e, periph) 24 25 /* pa1_gpio */ 26 #define PA1_GPIO \ 27 SAM_PINMUX(a, 1, gpio, gpio) 28 29 /* pa1a_eic_extint1 */ 30 #define PA1A_EIC_EXTINT1 \ 31 SAM_PINMUX(a, 1, a, periph) 32 33 /* pa1d_sercom1_pad1 */ 34 #define PA1D_SERCOM1_PAD1 \ 35 SAM_PINMUX(a, 1, d, periph) 36 37 /* pa1e_tcc2_wo1 */ 38 #define PA1E_TCC2_WO1 \ 39 SAM_PINMUX(a, 1, e, periph) 40 41 /* pa4_gpio */ 42 #define PA4_GPIO \ 43 SAM_PINMUX(a, 4, gpio, gpio) 44 45 /* pa4a_eic_extint4 */ 46 #define PA4A_EIC_EXTINT4 \ 47 SAM_PINMUX(a, 4, a, periph) 48 49 /* pa4b_adc_ain4 */ 50 #define PA4B_ADC_AIN4 \ 51 SAM_PINMUX(a, 4, b, periph) 52 53 /* pa4d_sercom0_pad0 */ 54 #define PA4D_SERCOM0_PAD0 \ 55 SAM_PINMUX(a, 4, d, periph) 56 57 /* pa4e_tcc0_wo0 */ 58 #define PA4E_TCC0_WO0 \ 59 SAM_PINMUX(a, 4, e, periph) 60 61 /* pa5_gpio */ 62 #define PA5_GPIO \ 63 SAM_PINMUX(a, 5, gpio, gpio) 64 65 /* pa5a_eic_extint5 */ 66 #define PA5A_EIC_EXTINT5 \ 67 SAM_PINMUX(a, 5, a, periph) 68 69 /* pa5b_adc_ain5 */ 70 #define PA5B_ADC_AIN5 \ 71 SAM_PINMUX(a, 5, b, periph) 72 73 /* pa5d_sercom0_pad1 */ 74 #define PA5D_SERCOM0_PAD1 \ 75 SAM_PINMUX(a, 5, d, periph) 76 77 /* pa5e_tcc0_wo1 */ 78 #define PA5E_TCC0_WO1 \ 79 SAM_PINMUX(a, 5, e, periph) 80 81 /* pa6_gpio */ 82 #define PA6_GPIO \ 83 SAM_PINMUX(a, 6, gpio, gpio) 84 85 /* pa6a_eic_extint6 */ 86 #define PA6A_EIC_EXTINT6 \ 87 SAM_PINMUX(a, 6, a, periph) 88 89 /* pa6b_adc_ain6 */ 90 #define PA6B_ADC_AIN6 \ 91 SAM_PINMUX(a, 6, b, periph) 92 93 /* pa6b_ptc_y4 */ 94 #define PA6B_PTC_Y4 \ 95 SAM_PINMUX(a, 6, b, periph) 96 97 /* pa6d_sercom0_pad2 */ 98 #define PA6D_SERCOM0_PAD2 \ 99 SAM_PINMUX(a, 6, d, periph) 100 101 /* pa6e_tcc1_wo0 */ 102 #define PA6E_TCC1_WO0 \ 103 SAM_PINMUX(a, 6, e, periph) 104 105 /* pa7_gpio */ 106 #define PA7_GPIO \ 107 SAM_PINMUX(a, 7, gpio, gpio) 108 109 /* pa7a_eic_extint7 */ 110 #define PA7A_EIC_EXTINT7 \ 111 SAM_PINMUX(a, 7, a, periph) 112 113 /* pa7b_adc_ain7 */ 114 #define PA7B_ADC_AIN7 \ 115 SAM_PINMUX(a, 7, b, periph) 116 117 /* pa7d_sercom0_pad3 */ 118 #define PA7D_SERCOM0_PAD3 \ 119 SAM_PINMUX(a, 7, d, periph) 120 121 /* pa7e_tcc1_wo1 */ 122 #define PA7E_TCC1_WO1 \ 123 SAM_PINMUX(a, 7, e, periph) 124 125 /* pa8_gpio */ 126 #define PA8_GPIO \ 127 SAM_PINMUX(a, 8, gpio, gpio) 128 129 /* pa8a_eic_nmi */ 130 #define PA8A_EIC_NMI \ 131 SAM_PINMUX(a, 8, a, periph) 132 133 /* pa8b_adc_ain16 */ 134 #define PA8B_ADC_AIN16 \ 135 SAM_PINMUX(a, 8, b, periph) 136 137 /* pa8b_ptc_x0 */ 138 #define PA8B_PTC_X0 \ 139 SAM_PINMUX(a, 8, b, periph) 140 141 /* pa8b_ptc_y6 */ 142 #define PA8B_PTC_Y6 \ 143 SAM_PINMUX(a, 8, b, periph) 144 145 /* pa8c_sercom0_pad0 */ 146 #define PA8C_SERCOM0_PAD0 \ 147 SAM_PINMUX(a, 8, c, periph) 148 149 /* pa8d_sercom2_pad0 */ 150 #define PA8D_SERCOM2_PAD0 \ 151 SAM_PINMUX(a, 8, d, periph) 152 153 /* pa8e_tcc0_wo0 */ 154 #define PA8E_TCC0_WO0 \ 155 SAM_PINMUX(a, 8, e, periph) 156 157 /* pa8f_tcc1_wo2 */ 158 #define PA8F_TCC1_WO2 \ 159 SAM_PINMUX(a, 8, f, periph) 160 161 /* pa9_gpio */ 162 #define PA9_GPIO \ 163 SAM_PINMUX(a, 9, gpio, gpio) 164 165 /* pa9a_eic_extint9 */ 166 #define PA9A_EIC_EXTINT9 \ 167 SAM_PINMUX(a, 9, a, periph) 168 169 /* pa9b_adc_ain17 */ 170 #define PA9B_ADC_AIN17 \ 171 SAM_PINMUX(a, 9, b, periph) 172 173 /* pa9b_ptc_x1 */ 174 #define PA9B_PTC_X1 \ 175 SAM_PINMUX(a, 9, b, periph) 176 177 /* pa9b_ptc_y7 */ 178 #define PA9B_PTC_Y7 \ 179 SAM_PINMUX(a, 9, b, periph) 180 181 /* pa9c_sercom0_pad1 */ 182 #define PA9C_SERCOM0_PAD1 \ 183 SAM_PINMUX(a, 9, c, periph) 184 185 /* pa9d_sercom2_pad1 */ 186 #define PA9D_SERCOM2_PAD1 \ 187 SAM_PINMUX(a, 9, d, periph) 188 189 /* pa9e_tcc0_wo1 */ 190 #define PA9E_TCC0_WO1 \ 191 SAM_PINMUX(a, 9, e, periph) 192 193 /* pa9f_tcc1_wo3 */ 194 #define PA9F_TCC1_WO3 \ 195 SAM_PINMUX(a, 9, f, periph) 196 197 /* pa10_gpio */ 198 #define PA10_GPIO \ 199 SAM_PINMUX(a, 10, gpio, gpio) 200 201 /* pa10a_eic_extint10 */ 202 #define PA10A_EIC_EXTINT10 \ 203 SAM_PINMUX(a, 10, a, periph) 204 205 /* pa10b_adc_ain18 */ 206 #define PA10B_ADC_AIN18 \ 207 SAM_PINMUX(a, 10, b, periph) 208 209 /* pa10b_ptc_x2 */ 210 #define PA10B_PTC_X2 \ 211 SAM_PINMUX(a, 10, b, periph) 212 213 /* pa10b_ptc_y8 */ 214 #define PA10B_PTC_Y8 \ 215 SAM_PINMUX(a, 10, b, periph) 216 217 /* pa10c_sercom0_pad2 */ 218 #define PA10C_SERCOM0_PAD2 \ 219 SAM_PINMUX(a, 10, c, periph) 220 221 /* pa10d_sercom2_pad2 */ 222 #define PA10D_SERCOM2_PAD2 \ 223 SAM_PINMUX(a, 10, d, periph) 224 225 /* pa10e_tcc1_wo0 */ 226 #define PA10E_TCC1_WO0 \ 227 SAM_PINMUX(a, 10, e, periph) 228 229 /* pa10f_tcc0_wo2 */ 230 #define PA10F_TCC0_WO2 \ 231 SAM_PINMUX(a, 10, f, periph) 232 233 /* pa10h_gclk_io4 */ 234 #define PA10H_GCLK_IO4 \ 235 SAM_PINMUX(a, 10, h, periph) 236 237 /* pa11_gpio */ 238 #define PA11_GPIO \ 239 SAM_PINMUX(a, 11, gpio, gpio) 240 241 /* pa11a_eic_extint11 */ 242 #define PA11A_EIC_EXTINT11 \ 243 SAM_PINMUX(a, 11, a, periph) 244 245 /* pa11b_adc_ain19 */ 246 #define PA11B_ADC_AIN19 \ 247 SAM_PINMUX(a, 11, b, periph) 248 249 /* pa11b_ptc_x3 */ 250 #define PA11B_PTC_X3 \ 251 SAM_PINMUX(a, 11, b, periph) 252 253 /* pa11b_ptc_y9 */ 254 #define PA11B_PTC_Y9 \ 255 SAM_PINMUX(a, 11, b, periph) 256 257 /* pa11c_sercom0_pad3 */ 258 #define PA11C_SERCOM0_PAD3 \ 259 SAM_PINMUX(a, 11, c, periph) 260 261 /* pa11d_sercom2_pad3 */ 262 #define PA11D_SERCOM2_PAD3 \ 263 SAM_PINMUX(a, 11, d, periph) 264 265 /* pa11e_tcc1_wo1 */ 266 #define PA11E_TCC1_WO1 \ 267 SAM_PINMUX(a, 11, e, periph) 268 269 /* pa11f_tcc0_wo3 */ 270 #define PA11F_TCC0_WO3 \ 271 SAM_PINMUX(a, 11, f, periph) 272 273 /* pa11h_gclk_io5 */ 274 #define PA11H_GCLK_IO5 \ 275 SAM_PINMUX(a, 11, h, periph) 276 277 /* pa12_gpio */ 278 #define PA12_GPIO \ 279 SAM_PINMUX(a, 12, gpio, gpio) 280 281 /* pa12a_eic_extint12 */ 282 #define PA12A_EIC_EXTINT12 \ 283 SAM_PINMUX(a, 12, a, periph) 284 285 /* pa12c_sercom2_pad0 */ 286 #define PA12C_SERCOM2_PAD0 \ 287 SAM_PINMUX(a, 12, c, periph) 288 289 /* pa12d_sercom4_pad0 */ 290 #define PA12D_SERCOM4_PAD0 \ 291 SAM_PINMUX(a, 12, d, periph) 292 293 /* pa12e_tcc2_wo0 */ 294 #define PA12E_TCC2_WO0 \ 295 SAM_PINMUX(a, 12, e, periph) 296 297 /* pa12f_tcc0_wo6 */ 298 #define PA12F_TCC0_WO6 \ 299 SAM_PINMUX(a, 12, f, periph) 300 301 /* pa12h_ac_cmp0 */ 302 #define PA12H_AC_CMP0 \ 303 SAM_PINMUX(a, 12, h, periph) 304 305 /* pa13_gpio */ 306 #define PA13_GPIO \ 307 SAM_PINMUX(a, 13, gpio, gpio) 308 309 /* pa13a_eic_extint13 */ 310 #define PA13A_EIC_EXTINT13 \ 311 SAM_PINMUX(a, 13, a, periph) 312 313 /* pa13c_sercom2_pad1 */ 314 #define PA13C_SERCOM2_PAD1 \ 315 SAM_PINMUX(a, 13, c, periph) 316 317 /* pa13d_sercom4_pad1 */ 318 #define PA13D_SERCOM4_PAD1 \ 319 SAM_PINMUX(a, 13, d, periph) 320 321 /* pa13e_tcc2_wo1 */ 322 #define PA13E_TCC2_WO1 \ 323 SAM_PINMUX(a, 13, e, periph) 324 325 /* pa13f_tcc0_wo7 */ 326 #define PA13F_TCC0_WO7 \ 327 SAM_PINMUX(a, 13, f, periph) 328 329 /* pa13h_ac_cmp1 */ 330 #define PA13H_AC_CMP1 \ 331 SAM_PINMUX(a, 13, h, periph) 332 333 /* pa14_gpio */ 334 #define PA14_GPIO \ 335 SAM_PINMUX(a, 14, gpio, gpio) 336 337 /* pa14a_eic_extint14 */ 338 #define PA14A_EIC_EXTINT14 \ 339 SAM_PINMUX(a, 14, a, periph) 340 341 /* pa14c_sercom2_pad2 */ 342 #define PA14C_SERCOM2_PAD2 \ 343 SAM_PINMUX(a, 14, c, periph) 344 345 /* pa14d_sercom4_pad2 */ 346 #define PA14D_SERCOM4_PAD2 \ 347 SAM_PINMUX(a, 14, d, periph) 348 349 /* pa14e_tc4_wo0 */ 350 #define PA14E_TC4_WO0 \ 351 SAM_PINMUX(a, 14, e, periph) 352 353 /* pa14f_tcc0_wo4 */ 354 #define PA14F_TCC0_WO4 \ 355 SAM_PINMUX(a, 14, f, periph) 356 357 /* pa14h_gclk_io0 */ 358 #define PA14H_GCLK_IO0 \ 359 SAM_PINMUX(a, 14, h, periph) 360 361 /* pa15_gpio */ 362 #define PA15_GPIO \ 363 SAM_PINMUX(a, 15, gpio, gpio) 364 365 /* pa15a_eic_extint15 */ 366 #define PA15A_EIC_EXTINT15 \ 367 SAM_PINMUX(a, 15, a, periph) 368 369 /* pa15c_sercom2_pad3 */ 370 #define PA15C_SERCOM2_PAD3 \ 371 SAM_PINMUX(a, 15, c, periph) 372 373 /* pa15d_sercom4_pad3 */ 374 #define PA15D_SERCOM4_PAD3 \ 375 SAM_PINMUX(a, 15, d, periph) 376 377 /* pa15e_tc4_wo1 */ 378 #define PA15E_TC4_WO1 \ 379 SAM_PINMUX(a, 15, e, periph) 380 381 /* pa15f_tcc0_wo5 */ 382 #define PA15F_TCC0_WO5 \ 383 SAM_PINMUX(a, 15, f, periph) 384 385 /* pa15h_gclk_io1 */ 386 #define PA15H_GCLK_IO1 \ 387 SAM_PINMUX(a, 15, h, periph) 388 389 /* pa16_gpio */ 390 #define PA16_GPIO \ 391 SAM_PINMUX(a, 16, gpio, gpio) 392 393 /* pa16a_eic_extint0 */ 394 #define PA16A_EIC_EXTINT0 \ 395 SAM_PINMUX(a, 16, a, periph) 396 397 /* pa16b_ptc_x4 */ 398 #define PA16B_PTC_X4 \ 399 SAM_PINMUX(a, 16, b, periph) 400 401 /* pa16c_sercom1_pad0 */ 402 #define PA16C_SERCOM1_PAD0 \ 403 SAM_PINMUX(a, 16, c, periph) 404 405 /* pa16d_sercom3_pad0 */ 406 #define PA16D_SERCOM3_PAD0 \ 407 SAM_PINMUX(a, 16, d, periph) 408 409 /* pa16e_tcc2_wo0 */ 410 #define PA16E_TCC2_WO0 \ 411 SAM_PINMUX(a, 16, e, periph) 412 413 /* pa16f_tcc0_wo6 */ 414 #define PA16F_TCC0_WO6 \ 415 SAM_PINMUX(a, 16, f, periph) 416 417 /* pa16h_gclk_io2 */ 418 #define PA16H_GCLK_IO2 \ 419 SAM_PINMUX(a, 16, h, periph) 420 421 /* pa17_gpio */ 422 #define PA17_GPIO \ 423 SAM_PINMUX(a, 17, gpio, gpio) 424 425 /* pa17a_eic_extint1 */ 426 #define PA17A_EIC_EXTINT1 \ 427 SAM_PINMUX(a, 17, a, periph) 428 429 /* pa17b_ptc_x5 */ 430 #define PA17B_PTC_X5 \ 431 SAM_PINMUX(a, 17, b, periph) 432 433 /* pa17c_sercom1_pad1 */ 434 #define PA17C_SERCOM1_PAD1 \ 435 SAM_PINMUX(a, 17, c, periph) 436 437 /* pa17d_sercom3_pad1 */ 438 #define PA17D_SERCOM3_PAD1 \ 439 SAM_PINMUX(a, 17, d, periph) 440 441 /* pa17e_tcc2_wo1 */ 442 #define PA17E_TCC2_WO1 \ 443 SAM_PINMUX(a, 17, e, periph) 444 445 /* pa17f_tcc0_wo1 */ 446 #define PA17F_TCC0_WO1 \ 447 SAM_PINMUX(a, 17, f, periph) 448 449 /* pa17h_gclk_io3 */ 450 #define PA17H_GCLK_IO3 \ 451 SAM_PINMUX(a, 17, h, periph) 452 453 /* pa18_gpio */ 454 #define PA18_GPIO \ 455 SAM_PINMUX(a, 18, gpio, gpio) 456 457 /* pa18a_eic_extint2 */ 458 #define PA18A_EIC_EXTINT2 \ 459 SAM_PINMUX(a, 18, a, periph) 460 461 /* pa18b_ptc_x6 */ 462 #define PA18B_PTC_X6 \ 463 SAM_PINMUX(a, 18, b, periph) 464 465 /* pa18c_sercom1_pad2 */ 466 #define PA18C_SERCOM1_PAD2 \ 467 SAM_PINMUX(a, 18, c, periph) 468 469 /* pa18d_sercom3_pad2 */ 470 #define PA18D_SERCOM3_PAD2 \ 471 SAM_PINMUX(a, 18, d, periph) 472 473 /* pa18e_tc4_wo0 */ 474 #define PA18E_TC4_WO0 \ 475 SAM_PINMUX(a, 18, e, periph) 476 477 /* pa18f_tcc0_wo2 */ 478 #define PA18F_TCC0_WO2 \ 479 SAM_PINMUX(a, 18, f, periph) 480 481 /* pa18h_ac_cmp0 */ 482 #define PA18H_AC_CMP0 \ 483 SAM_PINMUX(a, 18, h, periph) 484 485 /* pa19_gpio */ 486 #define PA19_GPIO \ 487 SAM_PINMUX(a, 19, gpio, gpio) 488 489 /* pa19a_eic_extint3 */ 490 #define PA19A_EIC_EXTINT3 \ 491 SAM_PINMUX(a, 19, a, periph) 492 493 /* pa19b_ptc_x7 */ 494 #define PA19B_PTC_X7 \ 495 SAM_PINMUX(a, 19, b, periph) 496 497 /* pa19c_sercom1_pad3 */ 498 #define PA19C_SERCOM1_PAD3 \ 499 SAM_PINMUX(a, 19, c, periph) 500 501 /* pa19d_sercom3_pad3 */ 502 #define PA19D_SERCOM3_PAD3 \ 503 SAM_PINMUX(a, 19, d, periph) 504 505 /* pa19e_tc4_wo1 */ 506 #define PA19E_TC4_WO1 \ 507 SAM_PINMUX(a, 19, e, periph) 508 509 /* pa19f_tcc0_wo3 */ 510 #define PA19F_TCC0_WO3 \ 511 SAM_PINMUX(a, 19, f, periph) 512 513 /* pa19h_ac_cmp1 */ 514 #define PA19H_AC_CMP1 \ 515 SAM_PINMUX(a, 19, h, periph) 516 517 /* pa22_gpio */ 518 #define PA22_GPIO \ 519 SAM_PINMUX(a, 22, gpio, gpio) 520 521 /* pa22a_eic_extint6 */ 522 #define PA22A_EIC_EXTINT6 \ 523 SAM_PINMUX(a, 22, a, periph) 524 525 /* pa22b_ptc_x10 */ 526 #define PA22B_PTC_X10 \ 527 SAM_PINMUX(a, 22, b, periph) 528 529 /* pa22c_sercom3_pad0 */ 530 #define PA22C_SERCOM3_PAD0 \ 531 SAM_PINMUX(a, 22, c, periph) 532 533 /* pa22d_sercom5_pad0 */ 534 #define PA22D_SERCOM5_PAD0 \ 535 SAM_PINMUX(a, 22, d, periph) 536 537 /* pa22e_tc0_wo0 */ 538 #define PA22E_TC0_WO0 \ 539 SAM_PINMUX(a, 22, e, periph) 540 541 /* pa22f_tcc0_wo4 */ 542 #define PA22F_TCC0_WO4 \ 543 SAM_PINMUX(a, 22, f, periph) 544 545 /* pa22h_gclk_io6 */ 546 #define PA22H_GCLK_IO6 \ 547 SAM_PINMUX(a, 22, h, periph) 548 549 /* pa23_gpio */ 550 #define PA23_GPIO \ 551 SAM_PINMUX(a, 23, gpio, gpio) 552 553 /* pa23a_eic_extint7 */ 554 #define PA23A_EIC_EXTINT7 \ 555 SAM_PINMUX(a, 23, a, periph) 556 557 /* pa23b_ptc_x11 */ 558 #define PA23B_PTC_X11 \ 559 SAM_PINMUX(a, 23, b, periph) 560 561 /* pa23c_sercom3_pad1 */ 562 #define PA23C_SERCOM3_PAD1 \ 563 SAM_PINMUX(a, 23, c, periph) 564 565 /* pa23d_sercom5_pad1 */ 566 #define PA23D_SERCOM5_PAD1 \ 567 SAM_PINMUX(a, 23, d, periph) 568 569 /* pa23e_tc0_wo1 */ 570 #define PA23E_TC0_WO1 \ 571 SAM_PINMUX(a, 23, e, periph) 572 573 /* pa23f_tcc0_wo5 */ 574 #define PA23F_TCC0_WO5 \ 575 SAM_PINMUX(a, 23, f, periph) 576 577 /* pa23h_gclk_io7 */ 578 #define PA23H_GCLK_IO7 \ 579 SAM_PINMUX(a, 23, h, periph) 580 581 /* pa24_gpio */ 582 #define PA24_GPIO \ 583 SAM_PINMUX(a, 24, gpio, gpio) 584 585 /* pa24a_eic_extint12 */ 586 #define PA24A_EIC_EXTINT12 \ 587 SAM_PINMUX(a, 24, a, periph) 588 589 /* pa24c_sercom3_pad2 */ 590 #define PA24C_SERCOM3_PAD2 \ 591 SAM_PINMUX(a, 24, c, periph) 592 593 /* pa24d_sercom5_pad2 */ 594 #define PA24D_SERCOM5_PAD2 \ 595 SAM_PINMUX(a, 24, d, periph) 596 597 /* pa24e_tc1_wo0 */ 598 #define PA24E_TC1_WO0 \ 599 SAM_PINMUX(a, 24, e, periph) 600 601 /* pa24f_tcc1_wo2 */ 602 #define PA24F_TCC1_WO2 \ 603 SAM_PINMUX(a, 24, f, periph) 604 605 /* pa25_gpio */ 606 #define PA25_GPIO \ 607 SAM_PINMUX(a, 25, gpio, gpio) 608 609 /* pa25a_eic_extint13 */ 610 #define PA25A_EIC_EXTINT13 \ 611 SAM_PINMUX(a, 25, a, periph) 612 613 /* pa25c_sercom3_pad3 */ 614 #define PA25C_SERCOM3_PAD3 \ 615 SAM_PINMUX(a, 25, c, periph) 616 617 /* pa25d_sercom5_pad3 */ 618 #define PA25D_SERCOM5_PAD3 \ 619 SAM_PINMUX(a, 25, d, periph) 620 621 /* pa25e_tc1_wo1 */ 622 #define PA25E_TC1_WO1 \ 623 SAM_PINMUX(a, 25, e, periph) 624 625 /* pa25f_tcc1_wo3 */ 626 #define PA25F_TCC1_WO3 \ 627 SAM_PINMUX(a, 25, f, periph) 628 629 /* pa27_gpio */ 630 #define PA27_GPIO \ 631 SAM_PINMUX(a, 27, gpio, gpio) 632 633 /* pa27a_eic_extint15 */ 634 #define PA27A_EIC_EXTINT15 \ 635 SAM_PINMUX(a, 27, a, periph) 636 637 /* pa27h_gclk_io0 */ 638 #define PA27H_GCLK_IO0 \ 639 SAM_PINMUX(a, 27, h, periph) 640 641 /* pa28_gpio */ 642 #define PA28_GPIO \ 643 SAM_PINMUX(a, 28, gpio, gpio) 644 645 /* pa28a_eic_extint8 */ 646 #define PA28A_EIC_EXTINT8 \ 647 SAM_PINMUX(a, 28, a, periph) 648 649 /* pa28h_gclk_io0 */ 650 #define PA28H_GCLK_IO0 \ 651 SAM_PINMUX(a, 28, h, periph) 652 653 /* pa30_gpio */ 654 #define PA30_GPIO \ 655 SAM_PINMUX(a, 30, gpio, gpio) 656 657 /* pa30a_eic_extint10 */ 658 #define PA30A_EIC_EXTINT10 \ 659 SAM_PINMUX(a, 30, a, periph) 660 661 /* pa30d_sercom1_pad2 */ 662 #define PA30D_SERCOM1_PAD2 \ 663 SAM_PINMUX(a, 30, d, periph) 664 665 /* pa30e_tcc1_wo0 */ 666 #define PA30E_TCC1_WO0 \ 667 SAM_PINMUX(a, 30, e, periph) 668 669 /* pa30h_gclk_io0 */ 670 #define PA30H_GCLK_IO0 \ 671 SAM_PINMUX(a, 30, h, periph) 672 673 /* pa31_gpio */ 674 #define PA31_GPIO \ 675 SAM_PINMUX(a, 31, gpio, gpio) 676 677 /* pa31a_eic_extint11 */ 678 #define PA31A_EIC_EXTINT11 \ 679 SAM_PINMUX(a, 31, a, periph) 680 681 /* pa31d_sercom1_pad3 */ 682 #define PA31D_SERCOM1_PAD3 \ 683 SAM_PINMUX(a, 31, d, periph) 684 685 /* pa31e_tcc1_wo1 */ 686 #define PA31E_TCC1_WO1 \ 687 SAM_PINMUX(a, 31, e, periph) 688 689 /* pb0_gpio */ 690 #define PB0_GPIO \ 691 SAM_PINMUX(b, 0, gpio, gpio) 692 693 /* pb0a_eic_extint0 */ 694 #define PB0A_EIC_EXTINT0 \ 695 SAM_PINMUX(b, 0, a, periph) 696 697 /* pb0b_adc_ain8 */ 698 #define PB0B_ADC_AIN8 \ 699 SAM_PINMUX(b, 0, b, periph) 700 701 /* pb0d_sercom5_pad2 */ 702 #define PB0D_SERCOM5_PAD2 \ 703 SAM_PINMUX(b, 0, d, periph) 704 705 /* pb0e_tcc3_wo0 */ 706 #define PB0E_TCC3_WO0 \ 707 SAM_PINMUX(b, 0, e, periph) 708 709 /* pb2_gpio */ 710 #define PB2_GPIO \ 711 SAM_PINMUX(b, 2, gpio, gpio) 712 713 /* pb2a_eic_extint2 */ 714 #define PB2A_EIC_EXTINT2 \ 715 SAM_PINMUX(b, 2, a, periph) 716 717 /* pb2b_adc_ain10 */ 718 #define PB2B_ADC_AIN10 \ 719 SAM_PINMUX(b, 2, b, periph) 720 721 /* pb2d_sercom5_pad0 */ 722 #define PB2D_SERCOM5_PAD0 \ 723 SAM_PINMUX(b, 2, d, periph) 724 725 /* pb2e_tc2_wo0 */ 726 #define PB2E_TC2_WO0 \ 727 SAM_PINMUX(b, 2, e, periph) 728 729 /* pb3_gpio */ 730 #define PB3_GPIO \ 731 SAM_PINMUX(b, 3, gpio, gpio) 732 733 /* pb3a_eic_extint3 */ 734 #define PB3A_EIC_EXTINT3 \ 735 SAM_PINMUX(b, 3, a, periph) 736 737 /* pb3b_adc_ain11 */ 738 #define PB3B_ADC_AIN11 \ 739 SAM_PINMUX(b, 3, b, periph) 740 741 /* pb3d_sercom5_pad1 */ 742 #define PB3D_SERCOM5_PAD1 \ 743 SAM_PINMUX(b, 3, d, periph) 744 745 /* pb3e_tc2_wo1 */ 746 #define PB3E_TC2_WO1 \ 747 SAM_PINMUX(b, 3, e, periph) 748 749 /* pb15_gpio */ 750 #define PB15_GPIO \ 751 SAM_PINMUX(b, 15, gpio, gpio) 752 753 /* pb15a_eic_extint15 */ 754 #define PB15A_EIC_EXTINT15 \ 755 SAM_PINMUX(b, 15, a, periph) 756 757 /* pb15b_ptc_x15 */ 758 #define PB15B_PTC_X15 \ 759 SAM_PINMUX(b, 15, b, periph) 760 761 /* pb15c_sercom4_pad3 */ 762 #define PB15C_SERCOM4_PAD3 \ 763 SAM_PINMUX(b, 15, c, periph) 764 765 /* pb15e_tcc0_wo1 */ 766 #define PB15E_TCC0_WO1 \ 767 SAM_PINMUX(b, 15, e, periph) 768 769 /* pb15h_gclk_io1 */ 770 #define PB15H_GCLK_IO1 \ 771 SAM_PINMUX(b, 15, h, periph) 772 773 /* pb16_gpio */ 774 #define PB16_GPIO \ 775 SAM_PINMUX(b, 16, gpio, gpio) 776 777 /* pb16a_eic_extint0 */ 778 #define PB16A_EIC_EXTINT0 \ 779 SAM_PINMUX(b, 16, a, periph) 780 781 /* pb16c_sercom5_pad0 */ 782 #define PB16C_SERCOM5_PAD0 \ 783 SAM_PINMUX(b, 16, c, periph) 784 785 /* pb16e_tcc2_wo0 */ 786 #define PB16E_TCC2_WO0 \ 787 SAM_PINMUX(b, 16, e, periph) 788 789 /* pb16f_tcc0_wo4 */ 790 #define PB16F_TCC0_WO4 \ 791 SAM_PINMUX(b, 16, f, periph) 792 793 /* pb16h_gclk_io2 */ 794 #define PB16H_GCLK_IO2 \ 795 SAM_PINMUX(b, 16, h, periph) 796 797 /* pb17_gpio */ 798 #define PB17_GPIO \ 799 SAM_PINMUX(b, 17, gpio, gpio) 800 801 /* pb17a_eic_extint1 */ 802 #define PB17A_EIC_EXTINT1 \ 803 SAM_PINMUX(b, 17, a, periph) 804 805 /* pb17c_sercom5_pad1 */ 806 #define PB17C_SERCOM5_PAD1 \ 807 SAM_PINMUX(b, 17, c, periph) 808 809 /* pb17e_tcc2_wo1 */ 810 #define PB17E_TCC2_WO1 \ 811 SAM_PINMUX(b, 17, e, periph) 812 813 /* pb17f_tcc0_wo5 */ 814 #define PB17F_TCC0_WO5 \ 815 SAM_PINMUX(b, 17, f, periph) 816 817 /* pb17h_gclk_io3 */ 818 #define PB17H_GCLK_IO3 \ 819 SAM_PINMUX(b, 17, h, periph) 820 821 /* pb22_gpio */ 822 #define PB22_GPIO \ 823 SAM_PINMUX(b, 22, gpio, gpio) 824 825 /* pb22a_eic_extint6 */ 826 #define PB22A_EIC_EXTINT6 \ 827 SAM_PINMUX(b, 22, a, periph) 828 829 /* pb22d_sercom5_pad2 */ 830 #define PB22D_SERCOM5_PAD2 \ 831 SAM_PINMUX(b, 22, d, periph) 832 833 /* pb22e_tc3_wo0 */ 834 #define PB22E_TC3_WO0 \ 835 SAM_PINMUX(b, 22, e, periph) 836 837 /* pb22h_gclk_io0 */ 838 #define PB22H_GCLK_IO0 \ 839 SAM_PINMUX(b, 22, h, periph) 840 841 /* pb23_gpio */ 842 #define PB23_GPIO \ 843 SAM_PINMUX(b, 23, gpio, gpio) 844 845 /* pb23a_eic_extint7 */ 846 #define PB23A_EIC_EXTINT7 \ 847 SAM_PINMUX(b, 23, a, periph) 848 849 /* pb23d_sercom5_pad3 */ 850 #define PB23D_SERCOM5_PAD3 \ 851 SAM_PINMUX(b, 23, d, periph) 852 853 /* pb23e_tc3_wo1 */ 854 #define PB23E_TC3_WO1 \ 855 SAM_PINMUX(b, 23, e, periph) 856 857 /* pb23h_gclk_io1 */ 858 #define PB23H_GCLK_IO1 \ 859 SAM_PINMUX(b, 23, h, periph) 860 861 /* pb30_gpio */ 862 #define PB30_GPIO \ 863 SAM_PINMUX(b, 30, gpio, gpio) 864 865 /* pb30a_eic_extint14 */ 866 #define PB30A_EIC_EXTINT14 \ 867 SAM_PINMUX(b, 30, a, periph) 868 869 /* pb30d_sercom5_pad0 */ 870 #define PB30D_SERCOM5_PAD0 \ 871 SAM_PINMUX(b, 30, d, periph) 872 873 /* pb30e_tcc0_wo0 */ 874 #define PB30E_TCC0_WO0 \ 875 SAM_PINMUX(b, 30, e, periph) 876 877 /* pb30f_sercom4_pad2 */ 878 #define PB30F_SERCOM4_PAD2 \ 879 SAM_PINMUX(b, 30, f, periph) 880 881 /* pb31_gpio */ 882 #define PB31_GPIO \ 883 SAM_PINMUX(b, 31, gpio, gpio) 884 885 /* pb31a_eic_extint15 */ 886 #define PB31A_EIC_EXTINT15 \ 887 SAM_PINMUX(b, 31, a, periph) 888 889 /* pb31d_sercom5_pad1 */ 890 #define PB31D_SERCOM5_PAD1 \ 891 SAM_PINMUX(b, 31, d, periph) 892 893 /* pb31e_tcc0_wo1 */ 894 #define PB31E_TCC0_WO1 \ 895 SAM_PINMUX(b, 31, e, periph) 896 897 /* pb31f_sercom4_pad1 */ 898 #define PB31F_SERCOM4_PAD1 \ 899 SAM_PINMUX(b, 31, f, periph) 900 901 /* pc18_gpio */ 902 #define PC18_GPIO \ 903 SAM_PINMUX(c, 18, gpio, gpio) 904 905 /* pc18f_sercom4_pad3 */ 906 #define PC18F_SERCOM4_PAD3 \ 907 SAM_PINMUX(c, 18, f, periph) 908 909 /* pc19_gpio */ 910 #define PC19_GPIO \ 911 SAM_PINMUX(c, 19, gpio, gpio) 912 913 /* pc19f_sercom4_pad0 */ 914 #define PC19F_SERCOM4_PAD0 \ 915 SAM_PINMUX(c, 19, f, periph) 916
