1 /* 2 * Autogenerated file 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #include <dt-bindings/pinctrl/atmel_sam_pinctrl.h> 8 9 /* pa0_gpio */ 10 #define PA0_GPIO \ 11 SAM_PINMUX(a, 0, gpio, gpio) 12 13 /* pa0a_eic_extint0 */ 14 #define PA0A_EIC_EXTINT0 \ 15 SAM_PINMUX(a, 0, a, periph) 16 17 /* pa0d_sercom1_pad0 */ 18 #define PA0D_SERCOM1_PAD0 \ 19 SAM_PINMUX(a, 0, d, periph) 20 21 /* pa0e_tc2_wo0 */ 22 #define PA0E_TC2_WO0 \ 23 SAM_PINMUX(a, 0, e, periph) 24 25 /* pa0h_ac_cmp2 */ 26 #define PA0H_AC_CMP2 \ 27 SAM_PINMUX(a, 0, h, periph) 28 29 /* pa1_gpio */ 30 #define PA1_GPIO \ 31 SAM_PINMUX(a, 1, gpio, gpio) 32 33 /* pa1a_eic_extint1 */ 34 #define PA1A_EIC_EXTINT1 \ 35 SAM_PINMUX(a, 1, a, periph) 36 37 /* pa1d_sercom1_pad1 */ 38 #define PA1D_SERCOM1_PAD1 \ 39 SAM_PINMUX(a, 1, d, periph) 40 41 /* pa1e_tc2_wo1 */ 42 #define PA1E_TC2_WO1 \ 43 SAM_PINMUX(a, 1, e, periph) 44 45 /* pa1h_ac_cmp3 */ 46 #define PA1H_AC_CMP3 \ 47 SAM_PINMUX(a, 1, h, periph) 48 49 /* pa2_gpio */ 50 #define PA2_GPIO \ 51 SAM_PINMUX(a, 2, gpio, gpio) 52 53 /* pa2a_eic_extint2 */ 54 #define PA2A_EIC_EXTINT2 \ 55 SAM_PINMUX(a, 2, a, periph) 56 57 /* pa2b_adc0_ain0 */ 58 #define PA2B_ADC0_AIN0 \ 59 SAM_PINMUX(a, 2, b, periph) 60 61 /* pa2b_ac_ain4 */ 62 #define PA2B_AC_AIN4 \ 63 SAM_PINMUX(a, 2, b, periph) 64 65 /* pa2b_ptc_y0 */ 66 #define PA2B_PTC_Y0 \ 67 SAM_PINMUX(a, 2, b, periph) 68 69 /* pa3_gpio */ 70 #define PA3_GPIO \ 71 SAM_PINMUX(a, 3, gpio, gpio) 72 73 /* pa3a_eic_extint3 */ 74 #define PA3A_EIC_EXTINT3 \ 75 SAM_PINMUX(a, 3, a, periph) 76 77 /* pa3b_anaref_vrefa */ 78 #define PA3B_ANAREF_VREFA \ 79 SAM_PINMUX(a, 3, b, periph) 80 81 /* pa3b_adc0_ain5 */ 82 #define PA3B_ADC0_AIN5 \ 83 SAM_PINMUX(a, 3, b, periph) 84 85 /* pa3b_ac_ain4 */ 86 #define PA3B_AC_AIN4 \ 87 SAM_PINMUX(a, 3, b, periph) 88 89 /* pa3b_ptc_y1 */ 90 #define PA3B_PTC_Y1 \ 91 SAM_PINMUX(a, 3, b, periph) 92 93 /* pa4_gpio */ 94 #define PA4_GPIO \ 95 SAM_PINMUX(a, 4, gpio, gpio) 96 97 /* pa4a_eic_extint4 */ 98 #define PA4A_EIC_EXTINT4 \ 99 SAM_PINMUX(a, 4, a, periph) 100 101 /* pa4b_anaref_vrefb */ 102 #define PA4B_ANAREF_VREFB \ 103 SAM_PINMUX(a, 4, b, periph) 104 105 /* pa4b_adc0_ain4 */ 106 #define PA4B_ADC0_AIN4 \ 107 SAM_PINMUX(a, 4, b, periph) 108 109 /* pa4b_ac_ain0 */ 110 #define PA4B_AC_AIN0 \ 111 SAM_PINMUX(a, 4, b, periph) 112 113 /* pa4b_ptc_y2 */ 114 #define PA4B_PTC_Y2 \ 115 SAM_PINMUX(a, 4, b, periph) 116 117 /* pa4d_sercom0_pad0 */ 118 #define PA4D_SERCOM0_PAD0 \ 119 SAM_PINMUX(a, 4, d, periph) 120 121 /* pa4e_tc0_wo0 */ 122 #define PA4E_TC0_WO0 \ 123 SAM_PINMUX(a, 4, e, periph) 124 125 /* pa5_gpio */ 126 #define PA5_GPIO \ 127 SAM_PINMUX(a, 5, gpio, gpio) 128 129 /* pa5a_eic_extint5 */ 130 #define PA5A_EIC_EXTINT5 \ 131 SAM_PINMUX(a, 5, a, periph) 132 133 /* pa5b_adc0_ain5 */ 134 #define PA5B_ADC0_AIN5 \ 135 SAM_PINMUX(a, 5, b, periph) 136 137 /* pa5b_ac_ain1 */ 138 #define PA5B_AC_AIN1 \ 139 SAM_PINMUX(a, 5, b, periph) 140 141 /* pa5b_ptc_y3 */ 142 #define PA5B_PTC_Y3 \ 143 SAM_PINMUX(a, 5, b, periph) 144 145 /* pa5d_sercom0_pad1 */ 146 #define PA5D_SERCOM0_PAD1 \ 147 SAM_PINMUX(a, 5, d, periph) 148 149 /* pa5e_tc0_wo1 */ 150 #define PA5E_TC0_WO1 \ 151 SAM_PINMUX(a, 5, e, periph) 152 153 /* pa6_gpio */ 154 #define PA6_GPIO \ 155 SAM_PINMUX(a, 6, gpio, gpio) 156 157 /* pa6a_eic_extint6 */ 158 #define PA6A_EIC_EXTINT6 \ 159 SAM_PINMUX(a, 6, a, periph) 160 161 /* pa6b_adc0_ain6 */ 162 #define PA6B_ADC0_AIN6 \ 163 SAM_PINMUX(a, 6, b, periph) 164 165 /* pa6b_ac_ain2 */ 166 #define PA6B_AC_AIN2 \ 167 SAM_PINMUX(a, 6, b, periph) 168 169 /* pa6b_ptc_y4 */ 170 #define PA6B_PTC_Y4 \ 171 SAM_PINMUX(a, 6, b, periph) 172 173 /* pa6d_sercom0_pad2 */ 174 #define PA6D_SERCOM0_PAD2 \ 175 SAM_PINMUX(a, 6, d, periph) 176 177 /* pa6e_tcc1_wo0 */ 178 #define PA6E_TCC1_WO0 \ 179 SAM_PINMUX(a, 6, e, periph) 180 181 /* pa7_gpio */ 182 #define PA7_GPIO \ 183 SAM_PINMUX(a, 7, gpio, gpio) 184 185 /* pa7a_eic_extint7 */ 186 #define PA7A_EIC_EXTINT7 \ 187 SAM_PINMUX(a, 7, a, periph) 188 189 /* pa7b_adc0_ain7 */ 190 #define PA7B_ADC0_AIN7 \ 191 SAM_PINMUX(a, 7, b, periph) 192 193 /* pa7b_ac_ain3 */ 194 #define PA7B_AC_AIN3 \ 195 SAM_PINMUX(a, 7, b, periph) 196 197 /* pa7b_ptc_y5 */ 198 #define PA7B_PTC_Y5 \ 199 SAM_PINMUX(a, 7, b, periph) 200 201 /* pa7d_sercom0_pad3 */ 202 #define PA7D_SERCOM0_PAD3 \ 203 SAM_PINMUX(a, 7, d, periph) 204 205 /* pa7e_tcc1_wo1 */ 206 #define PA7E_TCC1_WO1 \ 207 SAM_PINMUX(a, 7, e, periph) 208 209 /* pa8_gpio */ 210 #define PA8_GPIO \ 211 SAM_PINMUX(a, 8, gpio, gpio) 212 213 /* pa8a_eic_nmi */ 214 #define PA8A_EIC_NMI \ 215 SAM_PINMUX(a, 8, a, periph) 216 217 /* pa8b_ptc_xy16 */ 218 #define PA8B_PTC_XY16 \ 219 SAM_PINMUX(a, 8, b, periph) 220 221 /* pa8c_sercom0_pad0 */ 222 #define PA8C_SERCOM0_PAD0 \ 223 SAM_PINMUX(a, 8, c, periph) 224 225 /* pa8d_sercom2_pad0 */ 226 #define PA8D_SERCOM2_PAD0 \ 227 SAM_PINMUX(a, 8, d, periph) 228 229 /* pa8e_tc0_wo0 */ 230 #define PA8E_TC0_WO0 \ 231 SAM_PINMUX(a, 8, e, periph) 232 233 /* pa8f_tcc0_wo0 */ 234 #define PA8F_TCC0_WO0 \ 235 SAM_PINMUX(a, 8, f, periph) 236 237 /* pa9_gpio */ 238 #define PA9_GPIO \ 239 SAM_PINMUX(a, 9, gpio, gpio) 240 241 /* pa9a_eic_extint9 */ 242 #define PA9A_EIC_EXTINT9 \ 243 SAM_PINMUX(a, 9, a, periph) 244 245 /* pa9b_ptc_x1 */ 246 #define PA9B_PTC_X1 \ 247 SAM_PINMUX(a, 9, b, periph) 248 249 /* pa9c_sercom0_pad1 */ 250 #define PA9C_SERCOM0_PAD1 \ 251 SAM_PINMUX(a, 9, c, periph) 252 253 /* pa9d_sercom2_pad1 */ 254 #define PA9D_SERCOM2_PAD1 \ 255 SAM_PINMUX(a, 9, d, periph) 256 257 /* pa9e_tc0_wo1 */ 258 #define PA9E_TC0_WO1 \ 259 SAM_PINMUX(a, 9, e, periph) 260 261 /* pa9f_tcc0_wo1 */ 262 #define PA9F_TCC0_WO1 \ 263 SAM_PINMUX(a, 9, f, periph) 264 265 /* pa10_gpio */ 266 #define PA10_GPIO \ 267 SAM_PINMUX(a, 10, gpio, gpio) 268 269 /* pa10a_eic_extint10 */ 270 #define PA10A_EIC_EXTINT10 \ 271 SAM_PINMUX(a, 10, a, periph) 272 273 /* pa10b_ptc_x2 */ 274 #define PA10B_PTC_X2 \ 275 SAM_PINMUX(a, 10, b, periph) 276 277 /* pa10c_sercom0_pad2 */ 278 #define PA10C_SERCOM0_PAD2 \ 279 SAM_PINMUX(a, 10, c, periph) 280 281 /* pa10d_sercom2_pad2 */ 282 #define PA10D_SERCOM2_PAD2 \ 283 SAM_PINMUX(a, 10, d, periph) 284 285 /* pa10e_tc1_wo0 */ 286 #define PA10E_TC1_WO0 \ 287 SAM_PINMUX(a, 10, e, periph) 288 289 /* pa10f_tcc0_wo2 */ 290 #define PA10F_TCC0_WO2 \ 291 SAM_PINMUX(a, 10, f, periph) 292 293 /* pa10h_gclk_io4 */ 294 #define PA10H_GCLK_IO4 \ 295 SAM_PINMUX(a, 10, h, periph) 296 297 /* pa11_gpio */ 298 #define PA11_GPIO \ 299 SAM_PINMUX(a, 11, gpio, gpio) 300 301 /* pa11a_eic_extint11 */ 302 #define PA11A_EIC_EXTINT11 \ 303 SAM_PINMUX(a, 11, a, periph) 304 305 /* pa11b_ptc_x3 */ 306 #define PA11B_PTC_X3 \ 307 SAM_PINMUX(a, 11, b, periph) 308 309 /* pa11c_sercom0_pad3 */ 310 #define PA11C_SERCOM0_PAD3 \ 311 SAM_PINMUX(a, 11, c, periph) 312 313 /* pa11d_sercom2_pad3 */ 314 #define PA11D_SERCOM2_PAD3 \ 315 SAM_PINMUX(a, 11, d, periph) 316 317 /* pa11e_tc1_wo1 */ 318 #define PA11E_TC1_WO1 \ 319 SAM_PINMUX(a, 11, e, periph) 320 321 /* pa11f_tcc0_wo3 */ 322 #define PA11F_TCC0_WO3 \ 323 SAM_PINMUX(a, 11, f, periph) 324 325 /* pa11h_gclk_io5 */ 326 #define PA11H_GCLK_IO5 \ 327 SAM_PINMUX(a, 11, h, periph) 328 329 /* pa12_gpio */ 330 #define PA12_GPIO \ 331 SAM_PINMUX(a, 12, gpio, gpio) 332 333 /* pa12a_eic_extint12 */ 334 #define PA12A_EIC_EXTINT12 \ 335 SAM_PINMUX(a, 12, a, periph) 336 337 /* pa12c_sercom2_pad0 */ 338 #define PA12C_SERCOM2_PAD0 \ 339 SAM_PINMUX(a, 12, c, periph) 340 341 /* pa12d_sercom4_pad0 */ 342 #define PA12D_SERCOM4_PAD0 \ 343 SAM_PINMUX(a, 12, d, periph) 344 345 /* pa12e_tcc2_wo0 */ 346 #define PA12E_TCC2_WO0 \ 347 SAM_PINMUX(a, 12, e, periph) 348 349 /* pa12f_tcc0_wo6 */ 350 #define PA12F_TCC0_WO6 \ 351 SAM_PINMUX(a, 12, f, periph) 352 353 /* pa12h_ac_cmp0 */ 354 #define PA12H_AC_CMP0 \ 355 SAM_PINMUX(a, 12, h, periph) 356 357 /* pa13_gpio */ 358 #define PA13_GPIO \ 359 SAM_PINMUX(a, 13, gpio, gpio) 360 361 /* pa13a_eic_extint13 */ 362 #define PA13A_EIC_EXTINT13 \ 363 SAM_PINMUX(a, 13, a, periph) 364 365 /* pa13c_sercom2_pad1 */ 366 #define PA13C_SERCOM2_PAD1 \ 367 SAM_PINMUX(a, 13, c, periph) 368 369 /* pa13d_sercom4_pad1 */ 370 #define PA13D_SERCOM4_PAD1 \ 371 SAM_PINMUX(a, 13, d, periph) 372 373 /* pa13e_tcc2_wo1 */ 374 #define PA13E_TCC2_WO1 \ 375 SAM_PINMUX(a, 13, e, periph) 376 377 /* pa13f_tcc0_wo7 */ 378 #define PA13F_TCC0_WO7 \ 379 SAM_PINMUX(a, 13, f, periph) 380 381 /* pa13h_ac_cmp1 */ 382 #define PA13H_AC_CMP1 \ 383 SAM_PINMUX(a, 13, h, periph) 384 385 /* pa14_gpio */ 386 #define PA14_GPIO \ 387 SAM_PINMUX(a, 14, gpio, gpio) 388 389 /* pa14a_eic_extint14 */ 390 #define PA14A_EIC_EXTINT14 \ 391 SAM_PINMUX(a, 14, a, periph) 392 393 /* pa14c_sercom2_pad2 */ 394 #define PA14C_SERCOM2_PAD2 \ 395 SAM_PINMUX(a, 14, c, periph) 396 397 /* pa14d_sercom4_pad2 */ 398 #define PA14D_SERCOM4_PAD2 \ 399 SAM_PINMUX(a, 14, d, periph) 400 401 /* pa14e_tc3_wo0 */ 402 #define PA14E_TC3_WO0 \ 403 SAM_PINMUX(a, 14, e, periph) 404 405 /* pa14h_gclk_io0 */ 406 #define PA14H_GCLK_IO0 \ 407 SAM_PINMUX(a, 14, h, periph) 408 409 /* pa15_gpio */ 410 #define PA15_GPIO \ 411 SAM_PINMUX(a, 15, gpio, gpio) 412 413 /* pa15a_eic_extint15 */ 414 #define PA15A_EIC_EXTINT15 \ 415 SAM_PINMUX(a, 15, a, periph) 416 417 /* pa15c_sercom2_pad3 */ 418 #define PA15C_SERCOM2_PAD3 \ 419 SAM_PINMUX(a, 15, c, periph) 420 421 /* pa15d_sercom4_pad3 */ 422 #define PA15D_SERCOM4_PAD3 \ 423 SAM_PINMUX(a, 15, d, periph) 424 425 /* pa15e_tc3_wo1 */ 426 #define PA15E_TC3_WO1 \ 427 SAM_PINMUX(a, 15, e, periph) 428 429 /* pa15h_gclk_io1 */ 430 #define PA15H_GCLK_IO1 \ 431 SAM_PINMUX(a, 15, h, periph) 432 433 /* pa16_gpio */ 434 #define PA16_GPIO \ 435 SAM_PINMUX(a, 16, gpio, gpio) 436 437 /* pa16a_eic_extint0 */ 438 #define PA16A_EIC_EXTINT0 \ 439 SAM_PINMUX(a, 16, a, periph) 440 441 /* pa16b_ptc_x4 */ 442 #define PA16B_PTC_X4 \ 443 SAM_PINMUX(a, 16, b, periph) 444 445 /* pa16c_sercom1_pad0 */ 446 #define PA16C_SERCOM1_PAD0 \ 447 SAM_PINMUX(a, 16, c, periph) 448 449 /* pa16d_sercom3_pad0 */ 450 #define PA16D_SERCOM3_PAD0 \ 451 SAM_PINMUX(a, 16, d, periph) 452 453 /* pa16e_tcc2_wo0 */ 454 #define PA16E_TCC2_WO0 \ 455 SAM_PINMUX(a, 16, e, periph) 456 457 /* pa16f_tcc1_wo6 */ 458 #define PA16F_TCC1_WO6 \ 459 SAM_PINMUX(a, 16, f, periph) 460 461 /* pa16h_gclk_io2 */ 462 #define PA16H_GCLK_IO2 \ 463 SAM_PINMUX(a, 16, h, periph) 464 465 /* pa17_gpio */ 466 #define PA17_GPIO \ 467 SAM_PINMUX(a, 17, gpio, gpio) 468 469 /* pa17a_eic_extint1 */ 470 #define PA17A_EIC_EXTINT1 \ 471 SAM_PINMUX(a, 17, a, periph) 472 473 /* pa17b_ptc_x5 */ 474 #define PA17B_PTC_X5 \ 475 SAM_PINMUX(a, 17, b, periph) 476 477 /* pa17c_sercom1_pad1 */ 478 #define PA17C_SERCOM1_PAD1 \ 479 SAM_PINMUX(a, 17, c, periph) 480 481 /* pa17d_sercom3_pad1 */ 482 #define PA17D_SERCOM3_PAD1 \ 483 SAM_PINMUX(a, 17, d, periph) 484 485 /* pa17e_tcc2_wo1 */ 486 #define PA17E_TCC2_WO1 \ 487 SAM_PINMUX(a, 17, e, periph) 488 489 /* pa17f_tcc1_wo7 */ 490 #define PA17F_TCC1_WO7 \ 491 SAM_PINMUX(a, 17, f, periph) 492 493 /* pa17h_gclk_io3 */ 494 #define PA17H_GCLK_IO3 \ 495 SAM_PINMUX(a, 17, h, periph) 496 497 /* pa18_gpio */ 498 #define PA18_GPIO \ 499 SAM_PINMUX(a, 18, gpio, gpio) 500 501 /* pa18a_eic_extint2 */ 502 #define PA18A_EIC_EXTINT2 \ 503 SAM_PINMUX(a, 18, a, periph) 504 505 /* pa18b_ptc_x6 */ 506 #define PA18B_PTC_X6 \ 507 SAM_PINMUX(a, 18, b, periph) 508 509 /* pa18c_sercom1_pad2 */ 510 #define PA18C_SERCOM1_PAD2 \ 511 SAM_PINMUX(a, 18, c, periph) 512 513 /* pa18d_sercom3_pad2 */ 514 #define PA18D_SERCOM3_PAD2 \ 515 SAM_PINMUX(a, 18, d, periph) 516 517 /* pa18e_tc3_wo0 */ 518 #define PA18E_TC3_WO0 \ 519 SAM_PINMUX(a, 18, e, periph) 520 521 /* pa18f_tcc1_wo2 */ 522 #define PA18F_TCC1_WO2 \ 523 SAM_PINMUX(a, 18, f, periph) 524 525 /* pa18h_ac_cmp0 */ 526 #define PA18H_AC_CMP0 \ 527 SAM_PINMUX(a, 18, h, periph) 528 529 /* pa19_gpio */ 530 #define PA19_GPIO \ 531 SAM_PINMUX(a, 19, gpio, gpio) 532 533 /* pa19a_eic_extint3 */ 534 #define PA19A_EIC_EXTINT3 \ 535 SAM_PINMUX(a, 19, a, periph) 536 537 /* pa19b_ptc_x7 */ 538 #define PA19B_PTC_X7 \ 539 SAM_PINMUX(a, 19, b, periph) 540 541 /* pa19c_sercom1_pad3 */ 542 #define PA19C_SERCOM1_PAD3 \ 543 SAM_PINMUX(a, 19, c, periph) 544 545 /* pa19d_sercom3_pad3 */ 546 #define PA19D_SERCOM3_PAD3 \ 547 SAM_PINMUX(a, 19, d, periph) 548 549 /* pa19e_tc3_wo1 */ 550 #define PA19E_TC3_WO1 \ 551 SAM_PINMUX(a, 19, e, periph) 552 553 /* pa19f_tcc1_wo3 */ 554 #define PA19F_TCC1_WO3 \ 555 SAM_PINMUX(a, 19, f, periph) 556 557 /* pa19h_ac_cmp1 */ 558 #define PA19H_AC_CMP1 \ 559 SAM_PINMUX(a, 19, h, periph) 560 561 /* pa20_gpio */ 562 #define PA20_GPIO \ 563 SAM_PINMUX(a, 20, gpio, gpio) 564 565 /* pa20a_eic_extint4 */ 566 #define PA20A_EIC_EXTINT4 \ 567 SAM_PINMUX(a, 20, a, periph) 568 569 /* pa20b_ptc_x8 */ 570 #define PA20B_PTC_X8 \ 571 SAM_PINMUX(a, 20, b, periph) 572 573 /* pa20c_sercom5_pad2 */ 574 #define PA20C_SERCOM5_PAD2 \ 575 SAM_PINMUX(a, 20, c, periph) 576 577 /* pa20d_sercom3_pad2 */ 578 #define PA20D_SERCOM3_PAD2 \ 579 SAM_PINMUX(a, 20, d, periph) 580 581 /* pa20e_tc7_wo0 */ 582 #define PA20E_TC7_WO0 \ 583 SAM_PINMUX(a, 20, e, periph) 584 585 /* pa20f_tcc2_wo0 */ 586 #define PA20F_TCC2_WO0 \ 587 SAM_PINMUX(a, 20, f, periph) 588 589 /* pa20h_gclk_io4 */ 590 #define PA20H_GCLK_IO4 \ 591 SAM_PINMUX(a, 20, h, periph) 592 593 /* pa21_gpio */ 594 #define PA21_GPIO \ 595 SAM_PINMUX(a, 21, gpio, gpio) 596 597 /* pa21a_eic_extint5 */ 598 #define PA21A_EIC_EXTINT5 \ 599 SAM_PINMUX(a, 21, a, periph) 600 601 /* pa21b_ptc_x9 */ 602 #define PA21B_PTC_X9 \ 603 SAM_PINMUX(a, 21, b, periph) 604 605 /* pa21c_sercom5_pad3 */ 606 #define PA21C_SERCOM5_PAD3 \ 607 SAM_PINMUX(a, 21, c, periph) 608 609 /* pa21d_sercom3_pad3 */ 610 #define PA21D_SERCOM3_PAD3 \ 611 SAM_PINMUX(a, 21, d, periph) 612 613 /* pa21e_tc7_wo1 */ 614 #define PA21E_TC7_WO1 \ 615 SAM_PINMUX(a, 21, e, periph) 616 617 /* pa21f_tcc2_wo1 */ 618 #define PA21F_TCC2_WO1 \ 619 SAM_PINMUX(a, 21, f, periph) 620 621 /* pa21h_gclk_io5 */ 622 #define PA21H_GCLK_IO5 \ 623 SAM_PINMUX(a, 21, h, periph) 624 625 /* pa22_gpio */ 626 #define PA22_GPIO \ 627 SAM_PINMUX(a, 22, gpio, gpio) 628 629 /* pa22a_eic_extint6 */ 630 #define PA22A_EIC_EXTINT6 \ 631 SAM_PINMUX(a, 22, a, periph) 632 633 /* pa22b_ptc_x10 */ 634 #define PA22B_PTC_X10 \ 635 SAM_PINMUX(a, 22, b, periph) 636 637 /* pa22c_sercom3_pad0 */ 638 #define PA22C_SERCOM3_PAD0 \ 639 SAM_PINMUX(a, 22, c, periph) 640 641 /* pa22d_sercom5_pad0 */ 642 #define PA22D_SERCOM5_PAD0 \ 643 SAM_PINMUX(a, 22, d, periph) 644 645 /* pa22e_tc4_wo0 */ 646 #define PA22E_TC4_WO0 \ 647 SAM_PINMUX(a, 22, e, periph) 648 649 /* pa22f_tcc1_wo0 */ 650 #define PA22F_TCC1_WO0 \ 651 SAM_PINMUX(a, 22, f, periph) 652 653 /* pa22h_gclk_io6 */ 654 #define PA22H_GCLK_IO6 \ 655 SAM_PINMUX(a, 22, h, periph) 656 657 /* pa23_gpio */ 658 #define PA23_GPIO \ 659 SAM_PINMUX(a, 23, gpio, gpio) 660 661 /* pa23a_eic_extint7 */ 662 #define PA23A_EIC_EXTINT7 \ 663 SAM_PINMUX(a, 23, a, periph) 664 665 /* pa23b_ptc_x11 */ 666 #define PA23B_PTC_X11 \ 667 SAM_PINMUX(a, 23, b, periph) 668 669 /* pa23c_sercom3_pad1 */ 670 #define PA23C_SERCOM3_PAD1 \ 671 SAM_PINMUX(a, 23, c, periph) 672 673 /* pa23d_sercom5_pad1 */ 674 #define PA23D_SERCOM5_PAD1 \ 675 SAM_PINMUX(a, 23, d, periph) 676 677 /* pa23e_tc4_wo1 */ 678 #define PA23E_TC4_WO1 \ 679 SAM_PINMUX(a, 23, e, periph) 680 681 /* pa23f_tcc1_wo1 */ 682 #define PA23F_TCC1_WO1 \ 683 SAM_PINMUX(a, 23, f, periph) 684 685 /* pa23h_gclk_io7 */ 686 #define PA23H_GCLK_IO7 \ 687 SAM_PINMUX(a, 23, h, periph) 688 689 /* pa24_gpio */ 690 #define PA24_GPIO \ 691 SAM_PINMUX(a, 24, gpio, gpio) 692 693 /* pa24a_eic_extint12 */ 694 #define PA24A_EIC_EXTINT12 \ 695 SAM_PINMUX(a, 24, a, periph) 696 697 /* pa24c_sercom3_pad2 */ 698 #define PA24C_SERCOM3_PAD2 \ 699 SAM_PINMUX(a, 24, c, periph) 700 701 /* pa24d_sercom5_pad2 */ 702 #define PA24D_SERCOM5_PAD2 \ 703 SAM_PINMUX(a, 24, d, periph) 704 705 /* pa24e_tc5_wo0 */ 706 #define PA24E_TC5_WO0 \ 707 SAM_PINMUX(a, 24, e, periph) 708 709 /* pa24f_tcc2_wo0 */ 710 #define PA24F_TCC2_WO0 \ 711 SAM_PINMUX(a, 24, f, periph) 712 713 /* pa24h_ac_cmp2 */ 714 #define PA24H_AC_CMP2 \ 715 SAM_PINMUX(a, 24, h, periph) 716 717 /* pa25_gpio */ 718 #define PA25_GPIO \ 719 SAM_PINMUX(a, 25, gpio, gpio) 720 721 /* pa25a_eic_extint13 */ 722 #define PA25A_EIC_EXTINT13 \ 723 SAM_PINMUX(a, 25, a, periph) 724 725 /* pa25c_sercom3_pad3 */ 726 #define PA25C_SERCOM3_PAD3 \ 727 SAM_PINMUX(a, 25, c, periph) 728 729 /* pa25d_sercom5_pad3 */ 730 #define PA25D_SERCOM5_PAD3 \ 731 SAM_PINMUX(a, 25, d, periph) 732 733 /* pa25e_tc5_wo1 */ 734 #define PA25E_TC5_WO1 \ 735 SAM_PINMUX(a, 25, e, periph) 736 737 /* pa25f_tcc2_wo1 */ 738 #define PA25F_TCC2_WO1 \ 739 SAM_PINMUX(a, 25, f, periph) 740 741 /* pa25h_ac_cmp3 */ 742 #define PA25H_AC_CMP3 \ 743 SAM_PINMUX(a, 25, h, periph) 744 745 /* pa27_gpio */ 746 #define PA27_GPIO \ 747 SAM_PINMUX(a, 27, gpio, gpio) 748 749 /* pa27a_eic_extint15 */ 750 #define PA27A_EIC_EXTINT15 \ 751 SAM_PINMUX(a, 27, a, periph) 752 753 /* pa27h_gclk_io0 */ 754 #define PA27H_GCLK_IO0 \ 755 SAM_PINMUX(a, 27, h, periph) 756 757 /* pa28_gpio */ 758 #define PA28_GPIO \ 759 SAM_PINMUX(a, 28, gpio, gpio) 760 761 /* pa28a_eic_extint8 */ 762 #define PA28A_EIC_EXTINT8 \ 763 SAM_PINMUX(a, 28, a, periph) 764 765 /* pa28h_gclk_io0 */ 766 #define PA28H_GCLK_IO0 \ 767 SAM_PINMUX(a, 28, h, periph) 768 769 /* pa30_gpio */ 770 #define PA30_GPIO \ 771 SAM_PINMUX(a, 30, gpio, gpio) 772 773 /* pa30a_eic_extint10 */ 774 #define PA30A_EIC_EXTINT10 \ 775 SAM_PINMUX(a, 30, a, periph) 776 777 /* pa30d_sercom1_pad2 */ 778 #define PA30D_SERCOM1_PAD2 \ 779 SAM_PINMUX(a, 30, d, periph) 780 781 /* pa30e_tc1_wo0 */ 782 #define PA30E_TC1_WO0 \ 783 SAM_PINMUX(a, 30, e, periph) 784 785 /* pa30g_swd_clk */ 786 #define PA30G_SWD_CLK \ 787 SAM_PINMUX(a, 30, g, periph) 788 789 /* pa30h_gclk_io0 */ 790 #define PA30H_GCLK_IO0 \ 791 SAM_PINMUX(a, 30, h, periph) 792 793 /* pa31_gpio */ 794 #define PA31_GPIO \ 795 SAM_PINMUX(a, 31, gpio, gpio) 796 797 /* pa31a_eic_extint11 */ 798 #define PA31A_EIC_EXTINT11 \ 799 SAM_PINMUX(a, 31, a, periph) 800 801 /* pa31d_sercom1_pad3 */ 802 #define PA31D_SERCOM1_PAD3 \ 803 SAM_PINMUX(a, 31, d, periph) 804 805 /* pa31e_tc1_wo1 */ 806 #define PA31E_TC1_WO1 \ 807 SAM_PINMUX(a, 31, e, periph) 808 809 /* pa31g_swd_io */ 810 #define PA31G_SWD_IO \ 811 SAM_PINMUX(a, 31, g, periph) 812 813 /* pb0_gpio */ 814 #define PB0_GPIO \ 815 SAM_PINMUX(b, 0, gpio, gpio) 816 817 /* pb0a_eic_extint0 */ 818 #define PB0A_EIC_EXTINT0 \ 819 SAM_PINMUX(b, 0, a, periph) 820 821 /* pb0b_ptc_y6 */ 822 #define PB0B_PTC_Y6 \ 823 SAM_PINMUX(b, 0, b, periph) 824 825 /* pb0d_sercom5_pad2 */ 826 #define PB0D_SERCOM5_PAD2 \ 827 SAM_PINMUX(b, 0, d, periph) 828 829 /* pb0e_tc7_wo0 */ 830 #define PB0E_TC7_WO0 \ 831 SAM_PINMUX(b, 0, e, periph) 832 833 /* pb1_gpio */ 834 #define PB1_GPIO \ 835 SAM_PINMUX(b, 1, gpio, gpio) 836 837 /* pb1a_eic_extint1 */ 838 #define PB1A_EIC_EXTINT1 \ 839 SAM_PINMUX(b, 1, a, periph) 840 841 /* pb1b_ptc_y7 */ 842 #define PB1B_PTC_Y7 \ 843 SAM_PINMUX(b, 1, b, periph) 844 845 /* pb1d_sercom5_pad3 */ 846 #define PB1D_SERCOM5_PAD3 \ 847 SAM_PINMUX(b, 1, d, periph) 848 849 /* pb1e_tc7_wo1 */ 850 #define PB1E_TC7_WO1 \ 851 SAM_PINMUX(b, 1, e, periph) 852 853 /* pb2_gpio */ 854 #define PB2_GPIO \ 855 SAM_PINMUX(b, 2, gpio, gpio) 856 857 /* pb2a_eic_extint2 */ 858 #define PB2A_EIC_EXTINT2 \ 859 SAM_PINMUX(b, 2, a, periph) 860 861 /* pb2b_ptc_y8 */ 862 #define PB2B_PTC_Y8 \ 863 SAM_PINMUX(b, 2, b, periph) 864 865 /* pb2d_sercom5_pad0 */ 866 #define PB2D_SERCOM5_PAD0 \ 867 SAM_PINMUX(b, 2, d, periph) 868 869 /* pb2e_tc6_wo0 */ 870 #define PB2E_TC6_WO0 \ 871 SAM_PINMUX(b, 2, e, periph) 872 873 /* pb3_gpio */ 874 #define PB3_GPIO \ 875 SAM_PINMUX(b, 3, gpio, gpio) 876 877 /* pb3a_eic_extint3 */ 878 #define PB3A_EIC_EXTINT3 \ 879 SAM_PINMUX(b, 3, a, periph) 880 881 /* pb3b_ptc_y9 */ 882 #define PB3B_PTC_Y9 \ 883 SAM_PINMUX(b, 3, b, periph) 884 885 /* pb3d_sercom5_pad1 */ 886 #define PB3D_SERCOM5_PAD1 \ 887 SAM_PINMUX(b, 3, d, periph) 888 889 /* pb3e_tc6_wo1 */ 890 #define PB3E_TC6_WO1 \ 891 SAM_PINMUX(b, 3, e, periph) 892 893 /* pb4_gpio */ 894 #define PB4_GPIO \ 895 SAM_PINMUX(b, 4, gpio, gpio) 896 897 /* pb4a_eic_extint4 */ 898 #define PB4A_EIC_EXTINT4 \ 899 SAM_PINMUX(b, 4, a, periph) 900 901 /* pb4b_adc0_ain6 */ 902 #define PB4B_ADC0_AIN6 \ 903 SAM_PINMUX(b, 4, b, periph) 904 905 /* pb4b_ptc_y10 */ 906 #define PB4B_PTC_Y10 \ 907 SAM_PINMUX(b, 4, b, periph) 908 909 /* pb5_gpio */ 910 #define PB5_GPIO \ 911 SAM_PINMUX(b, 5, gpio, gpio) 912 913 /* pb5a_eic_extint5 */ 914 #define PB5A_EIC_EXTINT5 \ 915 SAM_PINMUX(b, 5, a, periph) 916 917 /* pb5b_adc0_ain7 */ 918 #define PB5B_ADC0_AIN7 \ 919 SAM_PINMUX(b, 5, b, periph) 920 921 /* pb5b_ac_ain6 */ 922 #define PB5B_AC_AIN6 \ 923 SAM_PINMUX(b, 5, b, periph) 924 925 /* pb5b_ptc_y11 */ 926 #define PB5B_PTC_Y11 \ 927 SAM_PINMUX(b, 5, b, periph) 928 929 /* pb6_gpio */ 930 #define PB6_GPIO \ 931 SAM_PINMUX(b, 6, gpio, gpio) 932 933 /* pb6a_eic_extint6 */ 934 #define PB6A_EIC_EXTINT6 \ 935 SAM_PINMUX(b, 6, a, periph) 936 937 /* pb6b_adc0_ain8 */ 938 #define PB6B_ADC0_AIN8 \ 939 SAM_PINMUX(b, 6, b, periph) 940 941 /* pb6b_ac_ain7 */ 942 #define PB6B_AC_AIN7 \ 943 SAM_PINMUX(b, 6, b, periph) 944 945 /* pb6b_ptc_y12 */ 946 #define PB6B_PTC_Y12 \ 947 SAM_PINMUX(b, 6, b, periph) 948 949 /* pb6c_sercom7_pad1 */ 950 #define PB6C_SERCOM7_PAD1 \ 951 SAM_PINMUX(b, 6, c, periph) 952 953 /* pb7_gpio */ 954 #define PB7_GPIO \ 955 SAM_PINMUX(b, 7, gpio, gpio) 956 957 /* pb7a_eic_extint7 */ 958 #define PB7A_EIC_EXTINT7 \ 959 SAM_PINMUX(b, 7, a, periph) 960 961 /* pb7b_adc0_ain9 */ 962 #define PB7B_ADC0_AIN9 \ 963 SAM_PINMUX(b, 7, b, periph) 964 965 /* pb7b_ptc_y13 */ 966 #define PB7B_PTC_Y13 \ 967 SAM_PINMUX(b, 7, b, periph) 968 969 /* pb7c_sercom7_pad3 */ 970 #define PB7C_SERCOM7_PAD3 \ 971 SAM_PINMUX(b, 7, c, periph) 972 973 /* pb7d_sercom7_pad2 */ 974 #define PB7D_SERCOM7_PAD2 \ 975 SAM_PINMUX(b, 7, d, periph) 976 977 /* pb8_gpio */ 978 #define PB8_GPIO \ 979 SAM_PINMUX(b, 8, gpio, gpio) 980 981 /* pb8a_eic_extint8 */ 982 #define PB8A_EIC_EXTINT8 \ 983 SAM_PINMUX(b, 8, a, periph) 984 985 /* pb8b_adc0_ain2 */ 986 #define PB8B_ADC0_AIN2 \ 987 SAM_PINMUX(b, 8, b, periph) 988 989 /* pb8b_ptc_y14 */ 990 #define PB8B_PTC_Y14 \ 991 SAM_PINMUX(b, 8, b, periph) 992 993 /* pb8c_sercom7_pad2 */ 994 #define PB8C_SERCOM7_PAD2 \ 995 SAM_PINMUX(b, 8, c, periph) 996 997 /* pb8d_sercom7_pad3 */ 998 #define PB8D_SERCOM7_PAD3 \ 999 SAM_PINMUX(b, 8, d, periph) 1000 1001 /* pb8e_tc4_wo0 */ 1002 #define PB8E_TC4_WO0 \ 1003 SAM_PINMUX(b, 8, e, periph) 1004 1005 /* pb9_gpio */ 1006 #define PB9_GPIO \ 1007 SAM_PINMUX(b, 9, gpio, gpio) 1008 1009 /* pb9a_eic_extint9 */ 1010 #define PB9A_EIC_EXTINT9 \ 1011 SAM_PINMUX(b, 9, a, periph) 1012 1013 /* pb9b_adc0_ain3 */ 1014 #define PB9B_ADC0_AIN3 \ 1015 SAM_PINMUX(b, 9, b, periph) 1016 1017 /* pb9b_ptc_y15 */ 1018 #define PB9B_PTC_Y15 \ 1019 SAM_PINMUX(b, 9, b, periph) 1020 1021 /* pb9d_sercom4_pad1 */ 1022 #define PB9D_SERCOM4_PAD1 \ 1023 SAM_PINMUX(b, 9, d, periph) 1024 1025 /* pb9e_tc4_wo1 */ 1026 #define PB9E_TC4_WO1 \ 1027 SAM_PINMUX(b, 9, e, periph) 1028 1029 /* pb10_gpio */ 1030 #define PB10_GPIO \ 1031 SAM_PINMUX(b, 10, gpio, gpio) 1032 1033 /* pb10a_eic_extint10 */ 1034 #define PB10A_EIC_EXTINT10 \ 1035 SAM_PINMUX(b, 10, a, periph) 1036 1037 /* pb10d_sercom4_pad2 */ 1038 #define PB10D_SERCOM4_PAD2 \ 1039 SAM_PINMUX(b, 10, d, periph) 1040 1041 /* pb10e_tc5_wo0 */ 1042 #define PB10E_TC5_WO0 \ 1043 SAM_PINMUX(b, 10, e, periph) 1044 1045 /* pb10f_tcc0_wo4 */ 1046 #define PB10F_TCC0_WO4 \ 1047 SAM_PINMUX(b, 10, f, periph) 1048 1049 /* pb10h_gclk_io4 */ 1050 #define PB10H_GCLK_IO4 \ 1051 SAM_PINMUX(b, 10, h, periph) 1052 1053 /* pb11_gpio */ 1054 #define PB11_GPIO \ 1055 SAM_PINMUX(b, 11, gpio, gpio) 1056 1057 /* pb11a_eic_extint11 */ 1058 #define PB11A_EIC_EXTINT11 \ 1059 SAM_PINMUX(b, 11, a, periph) 1060 1061 /* pb11d_sercom4_pad3 */ 1062 #define PB11D_SERCOM4_PAD3 \ 1063 SAM_PINMUX(b, 11, d, periph) 1064 1065 /* pb11e_tc5_wo1 */ 1066 #define PB11E_TC5_WO1 \ 1067 SAM_PINMUX(b, 11, e, periph) 1068 1069 /* pb11f_tcc0_wo5 */ 1070 #define PB11F_TCC0_WO5 \ 1071 SAM_PINMUX(b, 11, f, periph) 1072 1073 /* pb11h_gclk_io5 */ 1074 #define PB11H_GCLK_IO5 \ 1075 SAM_PINMUX(b, 11, h, periph) 1076 1077 /* pb12_gpio */ 1078 #define PB12_GPIO \ 1079 SAM_PINMUX(b, 12, gpio, gpio) 1080 1081 /* pb12a_eic_extint12 */ 1082 #define PB12A_EIC_EXTINT12 \ 1083 SAM_PINMUX(b, 12, a, periph) 1084 1085 /* pb12b_ptc_x12 */ 1086 #define PB12B_PTC_X12 \ 1087 SAM_PINMUX(b, 12, b, periph) 1088 1089 /* pb12c_sercom4_pad0 */ 1090 #define PB12C_SERCOM4_PAD0 \ 1091 SAM_PINMUX(b, 12, c, periph) 1092 1093 /* pb12e_tc4_wo0 */ 1094 #define PB12E_TC4_WO0 \ 1095 SAM_PINMUX(b, 12, e, periph) 1096 1097 /* pb12f_tcc0_wo6 */ 1098 #define PB12F_TCC0_WO6 \ 1099 SAM_PINMUX(b, 12, f, periph) 1100 1101 /* pb12h_gclk_io6 */ 1102 #define PB12H_GCLK_IO6 \ 1103 SAM_PINMUX(b, 12, h, periph) 1104 1105 /* pb13_gpio */ 1106 #define PB13_GPIO \ 1107 SAM_PINMUX(b, 13, gpio, gpio) 1108 1109 /* pb13a_eic_extint13 */ 1110 #define PB13A_EIC_EXTINT13 \ 1111 SAM_PINMUX(b, 13, a, periph) 1112 1113 /* pb13b_ptc_x13 */ 1114 #define PB13B_PTC_X13 \ 1115 SAM_PINMUX(b, 13, b, periph) 1116 1117 /* pb13c_sercom4_pad1 */ 1118 #define PB13C_SERCOM4_PAD1 \ 1119 SAM_PINMUX(b, 13, c, periph) 1120 1121 /* pb13e_tc4_wo1 */ 1122 #define PB13E_TC4_WO1 \ 1123 SAM_PINMUX(b, 13, e, periph) 1124 1125 /* pb13f_tcc0_wo7 */ 1126 #define PB13F_TCC0_WO7 \ 1127 SAM_PINMUX(b, 13, f, periph) 1128 1129 /* pb13h_gclk_io7 */ 1130 #define PB13H_GCLK_IO7 \ 1131 SAM_PINMUX(b, 13, h, periph) 1132 1133 /* pb14_gpio */ 1134 #define PB14_GPIO \ 1135 SAM_PINMUX(b, 14, gpio, gpio) 1136 1137 /* pb14a_eic_extint14 */ 1138 #define PB14A_EIC_EXTINT14 \ 1139 SAM_PINMUX(b, 14, a, periph) 1140 1141 /* pb14b_ptc_x14 */ 1142 #define PB14B_PTC_X14 \ 1143 SAM_PINMUX(b, 14, b, periph) 1144 1145 /* pb14c_sercom4_pad2 */ 1146 #define PB14C_SERCOM4_PAD2 \ 1147 SAM_PINMUX(b, 14, c, periph) 1148 1149 /* pb14e_tc5_wo0 */ 1150 #define PB14E_TC5_WO0 \ 1151 SAM_PINMUX(b, 14, e, periph) 1152 1153 /* pb14h_gclk_io0 */ 1154 #define PB14H_GCLK_IO0 \ 1155 SAM_PINMUX(b, 14, h, periph) 1156 1157 /* pb15_gpio */ 1158 #define PB15_GPIO \ 1159 SAM_PINMUX(b, 15, gpio, gpio) 1160 1161 /* pb15a_eic_extint15 */ 1162 #define PB15A_EIC_EXTINT15 \ 1163 SAM_PINMUX(b, 15, a, periph) 1164 1165 /* pb15b_ptc_x15 */ 1166 #define PB15B_PTC_X15 \ 1167 SAM_PINMUX(b, 15, b, periph) 1168 1169 /* pb15c_sercom4_pad3 */ 1170 #define PB15C_SERCOM4_PAD3 \ 1171 SAM_PINMUX(b, 15, c, periph) 1172 1173 /* pb15e_tc5_wo1 */ 1174 #define PB15E_TC5_WO1 \ 1175 SAM_PINMUX(b, 15, e, periph) 1176 1177 /* pb15h_gclk_io1 */ 1178 #define PB15H_GCLK_IO1 \ 1179 SAM_PINMUX(b, 15, h, periph) 1180 1181 /* pb16_gpio */ 1182 #define PB16_GPIO \ 1183 SAM_PINMUX(b, 16, gpio, gpio) 1184 1185 /* pb16a_eic_extint0 */ 1186 #define PB16A_EIC_EXTINT0 \ 1187 SAM_PINMUX(b, 16, a, periph) 1188 1189 /* pb16c_sercom5_pad0 */ 1190 #define PB16C_SERCOM5_PAD0 \ 1191 SAM_PINMUX(b, 16, c, periph) 1192 1193 /* pb16e_tc6_wo0 */ 1194 #define PB16E_TC6_WO0 \ 1195 SAM_PINMUX(b, 16, e, periph) 1196 1197 /* pb16h_gclk_io2 */ 1198 #define PB16H_GCLK_IO2 \ 1199 SAM_PINMUX(b, 16, h, periph) 1200 1201 /* pb17_gpio */ 1202 #define PB17_GPIO \ 1203 SAM_PINMUX(b, 17, gpio, gpio) 1204 1205 /* pb17a_eic_extint1 */ 1206 #define PB17A_EIC_EXTINT1 \ 1207 SAM_PINMUX(b, 17, a, periph) 1208 1209 /* pb17c_sercom5_pad1 */ 1210 #define PB17C_SERCOM5_PAD1 \ 1211 SAM_PINMUX(b, 17, c, periph) 1212 1213 /* pb17e_tc6_wo1 */ 1214 #define PB17E_TC6_WO1 \ 1215 SAM_PINMUX(b, 17, e, periph) 1216 1217 /* pb17h_gclk_io3 */ 1218 #define PB17H_GCLK_IO3 \ 1219 SAM_PINMUX(b, 17, h, periph) 1220 1221 /* pb18_gpio */ 1222 #define PB18_GPIO \ 1223 SAM_PINMUX(b, 18, gpio, gpio) 1224 1225 /* pb18a_eic_extint2 */ 1226 #define PB18A_EIC_EXTINT2 \ 1227 SAM_PINMUX(b, 18, a, periph) 1228 1229 /* pb18c_sercom5_pad2 */ 1230 #define PB18C_SERCOM5_PAD2 \ 1231 SAM_PINMUX(b, 18, c, periph) 1232 1233 /* pb18d_sercom3_pad2 */ 1234 #define PB18D_SERCOM3_PAD2 \ 1235 SAM_PINMUX(b, 18, d, periph) 1236 1237 /* pb18h_gclk_io4 */ 1238 #define PB18H_GCLK_IO4 \ 1239 SAM_PINMUX(b, 18, h, periph) 1240 1241 /* pb19_gpio */ 1242 #define PB19_GPIO \ 1243 SAM_PINMUX(b, 19, gpio, gpio) 1244 1245 /* pb19a_eic_extint3 */ 1246 #define PB19A_EIC_EXTINT3 \ 1247 SAM_PINMUX(b, 19, a, periph) 1248 1249 /* pb19c_sercom5_pad3 */ 1250 #define PB19C_SERCOM5_PAD3 \ 1251 SAM_PINMUX(b, 19, c, periph) 1252 1253 /* pb19d_sercom3_pad3 */ 1254 #define PB19D_SERCOM3_PAD3 \ 1255 SAM_PINMUX(b, 19, d, periph) 1256 1257 /* pb19h_gclk_io5 */ 1258 #define PB19H_GCLK_IO5 \ 1259 SAM_PINMUX(b, 19, h, periph) 1260 1261 /* pb20_gpio */ 1262 #define PB20_GPIO \ 1263 SAM_PINMUX(b, 20, gpio, gpio) 1264 1265 /* pb20a_eic_extint4 */ 1266 #define PB20A_EIC_EXTINT4 \ 1267 SAM_PINMUX(b, 20, a, periph) 1268 1269 /* pb20c_sercom3_pad0 */ 1270 #define PB20C_SERCOM3_PAD0 \ 1271 SAM_PINMUX(b, 20, c, periph) 1272 1273 /* pb20d_sercom2_pad0 */ 1274 #define PB20D_SERCOM2_PAD0 \ 1275 SAM_PINMUX(b, 20, d, periph) 1276 1277 /* pb20h_gclk_io6 */ 1278 #define PB20H_GCLK_IO6 \ 1279 SAM_PINMUX(b, 20, h, periph) 1280 1281 /* pb21_gpio */ 1282 #define PB21_GPIO \ 1283 SAM_PINMUX(b, 21, gpio, gpio) 1284 1285 /* pb21a_eic_extint5 */ 1286 #define PB21A_EIC_EXTINT5 \ 1287 SAM_PINMUX(b, 21, a, periph) 1288 1289 /* pb21c_sercom3_pad1 */ 1290 #define PB21C_SERCOM3_PAD1 \ 1291 SAM_PINMUX(b, 21, c, periph) 1292 1293 /* pb21d_sercom2_pad2 */ 1294 #define PB21D_SERCOM2_PAD2 \ 1295 SAM_PINMUX(b, 21, d, periph) 1296 1297 /* pb21h_gclk_io7 */ 1298 #define PB21H_GCLK_IO7 \ 1299 SAM_PINMUX(b, 21, h, periph) 1300 1301 /* pb22_gpio */ 1302 #define PB22_GPIO \ 1303 SAM_PINMUX(b, 22, gpio, gpio) 1304 1305 /* pb22a_eic_extint6 */ 1306 #define PB22A_EIC_EXTINT6 \ 1307 SAM_PINMUX(b, 22, a, periph) 1308 1309 /* pb22c_sercom0_pad2 */ 1310 #define PB22C_SERCOM0_PAD2 \ 1311 SAM_PINMUX(b, 22, c, periph) 1312 1313 /* pb22d_sercom5_pad2 */ 1314 #define PB22D_SERCOM5_PAD2 \ 1315 SAM_PINMUX(b, 22, d, periph) 1316 1317 /* pb22e_tc7_wo0 */ 1318 #define PB22E_TC7_WO0 \ 1319 SAM_PINMUX(b, 22, e, periph) 1320 1321 /* pb22f_tcc1_wo2 */ 1322 #define PB22F_TCC1_WO2 \ 1323 SAM_PINMUX(b, 22, f, periph) 1324 1325 /* pb22h_gclk_io0 */ 1326 #define PB22H_GCLK_IO0 \ 1327 SAM_PINMUX(b, 22, h, periph) 1328 1329 /* pb23_gpio */ 1330 #define PB23_GPIO \ 1331 SAM_PINMUX(b, 23, gpio, gpio) 1332 1333 /* pb23a_eic_extint7 */ 1334 #define PB23A_EIC_EXTINT7 \ 1335 SAM_PINMUX(b, 23, a, periph) 1336 1337 /* pb23c_sercom0_pad3 */ 1338 #define PB23C_SERCOM0_PAD3 \ 1339 SAM_PINMUX(b, 23, c, periph) 1340 1341 /* pb23d_sercom5_pad3 */ 1342 #define PB23D_SERCOM5_PAD3 \ 1343 SAM_PINMUX(b, 23, d, periph) 1344 1345 /* pb23e_tc7_wo1 */ 1346 #define PB23E_TC7_WO1 \ 1347 SAM_PINMUX(b, 23, e, periph) 1348 1349 /* pb23f_tcc1_wo3 */ 1350 #define PB23F_TCC1_WO3 \ 1351 SAM_PINMUX(b, 23, f, periph) 1352 1353 /* pb23h_gclk_io1 */ 1354 #define PB23H_GCLK_IO1 \ 1355 SAM_PINMUX(b, 23, h, periph) 1356 1357 /* pb24_gpio */ 1358 #define PB24_GPIO \ 1359 SAM_PINMUX(b, 24, gpio, gpio) 1360 1361 /* pb24a_eic_extint7 */ 1362 #define PB24A_EIC_EXTINT7 \ 1363 SAM_PINMUX(b, 24, a, periph) 1364 1365 /* pb24c_sercom0_pad0 */ 1366 #define PB24C_SERCOM0_PAD0 \ 1367 SAM_PINMUX(b, 24, c, periph) 1368 1369 /* pb24d_sercom4_pad0 */ 1370 #define PB24D_SERCOM4_PAD0 \ 1371 SAM_PINMUX(b, 24, d, periph) 1372 1373 /* pb24h_ac_cmp0 */ 1374 #define PB24H_AC_CMP0 \ 1375 SAM_PINMUX(b, 24, h, periph) 1376 1377 /* pb25_gpio */ 1378 #define PB25_GPIO \ 1379 SAM_PINMUX(b, 25, gpio, gpio) 1380 1381 /* pb25a_eic_extint8 */ 1382 #define PB25A_EIC_EXTINT8 \ 1383 SAM_PINMUX(b, 25, a, periph) 1384 1385 /* pb25c_sercom0_pad1 */ 1386 #define PB25C_SERCOM0_PAD1 \ 1387 SAM_PINMUX(b, 25, c, periph) 1388 1389 /* pb25d_sercom4_pad1 */ 1390 #define PB25D_SERCOM4_PAD1 \ 1391 SAM_PINMUX(b, 25, d, periph) 1392 1393 /* pb25h_ac_cmp1 */ 1394 #define PB25H_AC_CMP1 \ 1395 SAM_PINMUX(b, 25, h, periph) 1396 1397 /* pb30_gpio */ 1398 #define PB30_GPIO \ 1399 SAM_PINMUX(b, 30, gpio, gpio) 1400 1401 /* pb30a_eic_extint14 */ 1402 #define PB30A_EIC_EXTINT14 \ 1403 SAM_PINMUX(b, 30, a, periph) 1404 1405 /* pb30d_sercom5_pad0 */ 1406 #define PB30D_SERCOM5_PAD0 \ 1407 SAM_PINMUX(b, 30, d, periph) 1408 1409 /* pb30e_tc0_wo0 */ 1410 #define PB30E_TC0_WO0 \ 1411 SAM_PINMUX(b, 30, e, periph) 1412 1413 /* pb30h_ac_cmp2 */ 1414 #define PB30H_AC_CMP2 \ 1415 SAM_PINMUX(b, 30, h, periph) 1416 1417 /* pb31_gpio */ 1418 #define PB31_GPIO \ 1419 SAM_PINMUX(b, 31, gpio, gpio) 1420 1421 /* pb31a_eic_extint15 */ 1422 #define PB31A_EIC_EXTINT15 \ 1423 SAM_PINMUX(b, 31, a, periph) 1424 1425 /* pb31d_sercom5_pad1 */ 1426 #define PB31D_SERCOM5_PAD1 \ 1427 SAM_PINMUX(b, 31, d, periph) 1428 1429 /* pb31e_tc0_wo1 */ 1430 #define PB31E_TC0_WO1 \ 1431 SAM_PINMUX(b, 31, e, periph) 1432 1433 /* pb31h_ac_cmp3 */ 1434 #define PB31H_AC_CMP3 \ 1435 SAM_PINMUX(b, 31, h, periph) 1436 1437 /* pc0_gpio */ 1438 #define PC0_GPIO \ 1439 SAM_PINMUX(c, 0, gpio, gpio) 1440 1441 /* pc0a_eic_extint8 */ 1442 #define PC0A_EIC_EXTINT8 \ 1443 SAM_PINMUX(c, 0, a, periph) 1444 1445 /* pc0b_adc0_ain8 */ 1446 #define PC0B_ADC0_AIN8 \ 1447 SAM_PINMUX(c, 0, b, periph) 1448 1449 /* pc1_gpio */ 1450 #define PC1_GPIO \ 1451 SAM_PINMUX(c, 1, gpio, gpio) 1452 1453 /* pc1a_eic_extint9 */ 1454 #define PC1A_EIC_EXTINT9 \ 1455 SAM_PINMUX(c, 1, a, periph) 1456 1457 /* pc1b_adc0_ain9 */ 1458 #define PC1B_ADC0_AIN9 \ 1459 SAM_PINMUX(c, 1, b, periph) 1460 1461 /* pc2_gpio */ 1462 #define PC2_GPIO \ 1463 SAM_PINMUX(c, 2, gpio, gpio) 1464 1465 /* pc2a_eic_extint10 */ 1466 #define PC2A_EIC_EXTINT10 \ 1467 SAM_PINMUX(c, 2, a, periph) 1468 1469 /* pc2b_adc0_ain10 */ 1470 #define PC2B_ADC0_AIN10 \ 1471 SAM_PINMUX(c, 2, b, periph) 1472 1473 /* pc3_gpio */ 1474 #define PC3_GPIO \ 1475 SAM_PINMUX(c, 3, gpio, gpio) 1476 1477 /* pc3a_eic_extint11 */ 1478 #define PC3A_EIC_EXTINT11 \ 1479 SAM_PINMUX(c, 3, a, periph) 1480 1481 /* pc3b_adc0_ain11 */ 1482 #define PC3B_ADC0_AIN11 \ 1483 SAM_PINMUX(c, 3, b, periph) 1484 1485 /* pc3c_sercom7_pad0 */ 1486 #define PC3C_SERCOM7_PAD0 \ 1487 SAM_PINMUX(c, 3, c, periph) 1488 1489 /* pc3f_tcc2_wo0 */ 1490 #define PC3F_TCC2_WO0 \ 1491 SAM_PINMUX(c, 3, f, periph) 1492 1493 /* pc5_gpio */ 1494 #define PC5_GPIO \ 1495 SAM_PINMUX(c, 5, gpio, gpio) 1496 1497 /* pc5a_eic_extint13 */ 1498 #define PC5A_EIC_EXTINT13 \ 1499 SAM_PINMUX(c, 5, a, periph) 1500 1501 /* pc5c_sercom6_pad3 */ 1502 #define PC5C_SERCOM6_PAD3 \ 1503 SAM_PINMUX(c, 5, c, periph) 1504 1505 /* pc5f_tcc2_wo1 */ 1506 #define PC5F_TCC2_WO1 \ 1507 SAM_PINMUX(c, 5, f, periph) 1508 1509 /* pc6_gpio */ 1510 #define PC6_GPIO \ 1511 SAM_PINMUX(c, 6, gpio, gpio) 1512 1513 /* pc6a_eic_extint14 */ 1514 #define PC6A_EIC_EXTINT14 \ 1515 SAM_PINMUX(c, 6, a, periph) 1516 1517 /* pc6c_sercom6_pad0 */ 1518 #define PC6C_SERCOM6_PAD0 \ 1519 SAM_PINMUX(c, 6, c, periph) 1520 1521 /* pc7_gpio */ 1522 #define PC7_GPIO \ 1523 SAM_PINMUX(c, 7, gpio, gpio) 1524 1525 /* pc7a_eic_extint15 */ 1526 #define PC7A_EIC_EXTINT15 \ 1527 SAM_PINMUX(c, 7, a, periph) 1528 1529 /* pc7c_sercom6_pad1 */ 1530 #define PC7C_SERCOM6_PAD1 \ 1531 SAM_PINMUX(c, 7, c, periph) 1532 1533 /* pc8_gpio */ 1534 #define PC8_GPIO \ 1535 SAM_PINMUX(c, 8, gpio, gpio) 1536 1537 /* pc8a_eic_extint0 */ 1538 #define PC8A_EIC_EXTINT0 \ 1539 SAM_PINMUX(c, 8, a, periph) 1540 1541 /* pc8c_sercom6_pad0 */ 1542 #define PC8C_SERCOM6_PAD0 \ 1543 SAM_PINMUX(c, 8, c, periph) 1544 1545 /* pc8d_sercom7_pad0 */ 1546 #define PC8D_SERCOM7_PAD0 \ 1547 SAM_PINMUX(c, 8, d, periph) 1548 1549 /* pc9_gpio */ 1550 #define PC9_GPIO \ 1551 SAM_PINMUX(c, 9, gpio, gpio) 1552 1553 /* pc9a_eic_extint1 */ 1554 #define PC9A_EIC_EXTINT1 \ 1555 SAM_PINMUX(c, 9, a, periph) 1556 1557 /* pc9c_sercom6_pad1 */ 1558 #define PC9C_SERCOM6_PAD1 \ 1559 SAM_PINMUX(c, 9, c, periph) 1560 1561 /* pc9d_sercom7_pad1 */ 1562 #define PC9D_SERCOM7_PAD1 \ 1563 SAM_PINMUX(c, 9, d, periph) 1564 1565 /* pc10_gpio */ 1566 #define PC10_GPIO \ 1567 SAM_PINMUX(c, 10, gpio, gpio) 1568 1569 /* pc10a_eic_extint2 */ 1570 #define PC10A_EIC_EXTINT2 \ 1571 SAM_PINMUX(c, 10, a, periph) 1572 1573 /* pc10c_sercom6_pad2 */ 1574 #define PC10C_SERCOM6_PAD2 \ 1575 SAM_PINMUX(c, 10, c, periph) 1576 1577 /* pc10d_sercom7_pad2 */ 1578 #define PC10D_SERCOM7_PAD2 \ 1579 SAM_PINMUX(c, 10, d, periph) 1580 1581 /* pc11_gpio */ 1582 #define PC11_GPIO \ 1583 SAM_PINMUX(c, 11, gpio, gpio) 1584 1585 /* pc11a_eic_extint3 */ 1586 #define PC11A_EIC_EXTINT3 \ 1587 SAM_PINMUX(c, 11, a, periph) 1588 1589 /* pc11c_sercom6_pad3 */ 1590 #define PC11C_SERCOM6_PAD3 \ 1591 SAM_PINMUX(c, 11, c, periph) 1592 1593 /* pc11d_sercom7_pad3 */ 1594 #define PC11D_SERCOM7_PAD3 \ 1595 SAM_PINMUX(c, 11, d, periph) 1596 1597 /* pc12_gpio */ 1598 #define PC12_GPIO \ 1599 SAM_PINMUX(c, 12, gpio, gpio) 1600 1601 /* pc12a_eic_extint4 */ 1602 #define PC12A_EIC_EXTINT4 \ 1603 SAM_PINMUX(c, 12, a, periph) 1604 1605 /* pc12c_sercom7_pad0 */ 1606 #define PC12C_SERCOM7_PAD0 \ 1607 SAM_PINMUX(c, 12, c, periph) 1608 1609 /* pc13_gpio */ 1610 #define PC13_GPIO \ 1611 SAM_PINMUX(c, 13, gpio, gpio) 1612 1613 /* pc13a_eic_extint5 */ 1614 #define PC13A_EIC_EXTINT5 \ 1615 SAM_PINMUX(c, 13, a, periph) 1616 1617 /* pc13c_sercom7_pad1 */ 1618 #define PC13C_SERCOM7_PAD1 \ 1619 SAM_PINMUX(c, 13, c, periph) 1620 1621 /* pc14_gpio */ 1622 #define PC14_GPIO \ 1623 SAM_PINMUX(c, 14, gpio, gpio) 1624 1625 /* pc14a_eic_extint6 */ 1626 #define PC14A_EIC_EXTINT6 \ 1627 SAM_PINMUX(c, 14, a, periph) 1628 1629 /* pc14c_sercom7_pad2 */ 1630 #define PC14C_SERCOM7_PAD2 \ 1631 SAM_PINMUX(c, 14, c, periph) 1632 1633 /* pc15_gpio */ 1634 #define PC15_GPIO \ 1635 SAM_PINMUX(c, 15, gpio, gpio) 1636 1637 /* pc15a_eic_extint7 */ 1638 #define PC15A_EIC_EXTINT7 \ 1639 SAM_PINMUX(c, 15, a, periph) 1640 1641 /* pc15c_sercom7_pad3 */ 1642 #define PC15C_SERCOM7_PAD3 \ 1643 SAM_PINMUX(c, 15, c, periph) 1644 1645 /* pc16_gpio */ 1646 #define PC16_GPIO \ 1647 SAM_PINMUX(c, 16, gpio, gpio) 1648 1649 /* pc16a_eic_extint8 */ 1650 #define PC16A_EIC_EXTINT8 \ 1651 SAM_PINMUX(c, 16, a, periph) 1652 1653 /* pc16c_sercom6_pad0 */ 1654 #define PC16C_SERCOM6_PAD0 \ 1655 SAM_PINMUX(c, 16, c, periph) 1656 1657 /* pc17_gpio */ 1658 #define PC17_GPIO \ 1659 SAM_PINMUX(c, 17, gpio, gpio) 1660 1661 /* pc17a_eic_extint9 */ 1662 #define PC17A_EIC_EXTINT9 \ 1663 SAM_PINMUX(c, 17, a, periph) 1664 1665 /* pc17c_sercom6_pad1 */ 1666 #define PC17C_SERCOM6_PAD1 \ 1667 SAM_PINMUX(c, 17, c, periph) 1668 1669 /* pc18_gpio */ 1670 #define PC18_GPIO \ 1671 SAM_PINMUX(c, 18, gpio, gpio) 1672 1673 /* pc18a_eic_extint10 */ 1674 #define PC18A_EIC_EXTINT10 \ 1675 SAM_PINMUX(c, 18, a, periph) 1676 1677 /* pc18c_sercom6_pad2 */ 1678 #define PC18C_SERCOM6_PAD2 \ 1679 SAM_PINMUX(c, 18, c, periph) 1680 1681 /* pc19_gpio */ 1682 #define PC19_GPIO \ 1683 SAM_PINMUX(c, 19, gpio, gpio) 1684 1685 /* pc19a_eic_extint11 */ 1686 #define PC19A_EIC_EXTINT11 \ 1687 SAM_PINMUX(c, 19, a, periph) 1688 1689 /* pc19c_sercom6_pad3 */ 1690 #define PC19C_SERCOM6_PAD3 \ 1691 SAM_PINMUX(c, 19, c, periph) 1692 1693 /* pc20_gpio */ 1694 #define PC20_GPIO \ 1695 SAM_PINMUX(c, 20, gpio, gpio) 1696 1697 /* pc20a_eic_extint12 */ 1698 #define PC20A_EIC_EXTINT12 \ 1699 SAM_PINMUX(c, 20, a, periph) 1700 1701 /* pc21_gpio */ 1702 #define PC21_GPIO \ 1703 SAM_PINMUX(c, 21, gpio, gpio) 1704 1705 /* pc21a_eic_extint13 */ 1706 #define PC21A_EIC_EXTINT13 \ 1707 SAM_PINMUX(c, 21, a, periph) 1708 1709 /* pc24_gpio */ 1710 #define PC24_GPIO \ 1711 SAM_PINMUX(c, 24, gpio, gpio) 1712 1713 /* pc24a_eic_extint0 */ 1714 #define PC24A_EIC_EXTINT0 \ 1715 SAM_PINMUX(c, 24, a, periph) 1716 1717 /* pc24c_sercom0_pad2 */ 1718 #define PC24C_SERCOM0_PAD2 \ 1719 SAM_PINMUX(c, 24, c, periph) 1720 1721 /* pc24d_sercom4_pad2 */ 1722 #define PC24D_SERCOM4_PAD2 \ 1723 SAM_PINMUX(c, 24, d, periph) 1724 1725 /* pc25_gpio */ 1726 #define PC25_GPIO \ 1727 SAM_PINMUX(c, 25, gpio, gpio) 1728 1729 /* pc25a_eic_extint1 */ 1730 #define PC25A_EIC_EXTINT1 \ 1731 SAM_PINMUX(c, 25, a, periph) 1732 1733 /* pc25c_sercom0_pad3 */ 1734 #define PC25C_SERCOM0_PAD3 \ 1735 SAM_PINMUX(c, 25, c, periph) 1736 1737 /* pc25d_sercom4_pad3 */ 1738 #define PC25D_SERCOM4_PAD3 \ 1739 SAM_PINMUX(c, 25, d, periph) 1740 1741 /* pc26_gpio */ 1742 #define PC26_GPIO \ 1743 SAM_PINMUX(c, 26, gpio, gpio) 1744 1745 /* pc26a_eic_extint2 */ 1746 #define PC26A_EIC_EXTINT2 \ 1747 SAM_PINMUX(c, 26, a, periph) 1748 1749 /* pc27_gpio */ 1750 #define PC27_GPIO \ 1751 SAM_PINMUX(c, 27, gpio, gpio) 1752 1753 /* pc27a_eic_extint3 */ 1754 #define PC27A_EIC_EXTINT3 \ 1755 SAM_PINMUX(c, 27, a, periph) 1756 1757 /* pc27d_sercom1_pad0 */ 1758 #define PC27D_SERCOM1_PAD0 \ 1759 SAM_PINMUX(c, 27, d, periph) 1760 1761 /* pc28_gpio */ 1762 #define PC28_GPIO \ 1763 SAM_PINMUX(c, 28, gpio, gpio) 1764 1765 /* pc28a_eic_extint4 */ 1766 #define PC28A_EIC_EXTINT4 \ 1767 SAM_PINMUX(c, 28, a, periph) 1768 1769 /* pc28d_sercom1_pad1 */ 1770 #define PC28D_SERCOM1_PAD1 \ 1771 SAM_PINMUX(c, 28, d, periph) 1772
