1 /* 2 * Autogenerated file 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #include <dt-bindings/pinctrl/atmel_sam_pinctrl.h> 8 9 /* pa0_gpio */ 10 #define PA0_GPIO \ 11 SAM_PINMUX(a, 0, gpio, gpio) 12 13 /* pa0a_eic_extint0 */ 14 #define PA0A_EIC_EXTINT0 \ 15 SAM_PINMUX(a, 0, a, periph) 16 17 /* pa0d_sercom1_pad0 */ 18 #define PA0D_SERCOM1_PAD0 \ 19 SAM_PINMUX(a, 0, d, periph) 20 21 /* pa0e_tc2_wo0 */ 22 #define PA0E_TC2_WO0 \ 23 SAM_PINMUX(a, 0, e, periph) 24 25 /* pa0h_ac_cmp2 */ 26 #define PA0H_AC_CMP2 \ 27 SAM_PINMUX(a, 0, h, periph) 28 29 /* pa1_gpio */ 30 #define PA1_GPIO \ 31 SAM_PINMUX(a, 1, gpio, gpio) 32 33 /* pa1a_eic_extint1 */ 34 #define PA1A_EIC_EXTINT1 \ 35 SAM_PINMUX(a, 1, a, periph) 36 37 /* pa1d_sercom1_pad1 */ 38 #define PA1D_SERCOM1_PAD1 \ 39 SAM_PINMUX(a, 1, d, periph) 40 41 /* pa1e_tc2_wo1 */ 42 #define PA1E_TC2_WO1 \ 43 SAM_PINMUX(a, 1, e, periph) 44 45 /* pa1h_ac_cmp3 */ 46 #define PA1H_AC_CMP3 \ 47 SAM_PINMUX(a, 1, h, periph) 48 49 /* pa2_gpio */ 50 #define PA2_GPIO \ 51 SAM_PINMUX(a, 2, gpio, gpio) 52 53 /* pa2a_eic_extint2 */ 54 #define PA2A_EIC_EXTINT2 \ 55 SAM_PINMUX(a, 2, a, periph) 56 57 /* pa2b_adc0_ain0 */ 58 #define PA2B_ADC0_AIN0 \ 59 SAM_PINMUX(a, 2, b, periph) 60 61 /* pa2b_ac_ain4 */ 62 #define PA2B_AC_AIN4 \ 63 SAM_PINMUX(a, 2, b, periph) 64 65 /* pa2b_ptc_y0 */ 66 #define PA2B_PTC_Y0 \ 67 SAM_PINMUX(a, 2, b, periph) 68 69 /* pa3_gpio */ 70 #define PA3_GPIO \ 71 SAM_PINMUX(a, 3, gpio, gpio) 72 73 /* pa3a_eic_extint3 */ 74 #define PA3A_EIC_EXTINT3 \ 75 SAM_PINMUX(a, 3, a, periph) 76 77 /* pa3b_anaref_vrefa */ 78 #define PA3B_ANAREF_VREFA \ 79 SAM_PINMUX(a, 3, b, periph) 80 81 /* pa3b_adc0_ain5 */ 82 #define PA3B_ADC0_AIN5 \ 83 SAM_PINMUX(a, 3, b, periph) 84 85 /* pa3b_ac_ain4 */ 86 #define PA3B_AC_AIN4 \ 87 SAM_PINMUX(a, 3, b, periph) 88 89 /* pa3b_ptc_y1 */ 90 #define PA3B_PTC_Y1 \ 91 SAM_PINMUX(a, 3, b, periph) 92 93 /* pa4_gpio */ 94 #define PA4_GPIO \ 95 SAM_PINMUX(a, 4, gpio, gpio) 96 97 /* pa4a_eic_extint4 */ 98 #define PA4A_EIC_EXTINT4 \ 99 SAM_PINMUX(a, 4, a, periph) 100 101 /* pa4b_anaref_vrefb */ 102 #define PA4B_ANAREF_VREFB \ 103 SAM_PINMUX(a, 4, b, periph) 104 105 /* pa4b_adc0_ain4 */ 106 #define PA4B_ADC0_AIN4 \ 107 SAM_PINMUX(a, 4, b, periph) 108 109 /* pa4b_ac_ain0 */ 110 #define PA4B_AC_AIN0 \ 111 SAM_PINMUX(a, 4, b, periph) 112 113 /* pa4b_ptc_y2 */ 114 #define PA4B_PTC_Y2 \ 115 SAM_PINMUX(a, 4, b, periph) 116 117 /* pa4d_sercom0_pad0 */ 118 #define PA4D_SERCOM0_PAD0 \ 119 SAM_PINMUX(a, 4, d, periph) 120 121 /* pa4e_tcc0_wo0 */ 122 #define PA4E_TCC0_WO0 \ 123 SAM_PINMUX(a, 4, e, periph) 124 125 /* pa5_gpio */ 126 #define PA5_GPIO \ 127 SAM_PINMUX(a, 5, gpio, gpio) 128 129 /* pa5a_eic_extint5 */ 130 #define PA5A_EIC_EXTINT5 \ 131 SAM_PINMUX(a, 5, a, periph) 132 133 /* pa5b_adc0_ain5 */ 134 #define PA5B_ADC0_AIN5 \ 135 SAM_PINMUX(a, 5, b, periph) 136 137 /* pa5b_ac_ain1 */ 138 #define PA5B_AC_AIN1 \ 139 SAM_PINMUX(a, 5, b, periph) 140 141 /* pa5b_ptc_y3 */ 142 #define PA5B_PTC_Y3 \ 143 SAM_PINMUX(a, 5, b, periph) 144 145 /* pa5d_sercom0_pad1 */ 146 #define PA5D_SERCOM0_PAD1 \ 147 SAM_PINMUX(a, 5, d, periph) 148 149 /* pa5e_tcc0_wo1 */ 150 #define PA5E_TCC0_WO1 \ 151 SAM_PINMUX(a, 5, e, periph) 152 153 /* pa6_gpio */ 154 #define PA6_GPIO \ 155 SAM_PINMUX(a, 6, gpio, gpio) 156 157 /* pa6a_eic_extint6 */ 158 #define PA6A_EIC_EXTINT6 \ 159 SAM_PINMUX(a, 6, a, periph) 160 161 /* pa6b_adc0_ain6 */ 162 #define PA6B_ADC0_AIN6 \ 163 SAM_PINMUX(a, 6, b, periph) 164 165 /* pa6b_ac_ain2 */ 166 #define PA6B_AC_AIN2 \ 167 SAM_PINMUX(a, 6, b, periph) 168 169 /* pa6b_ptc_y4 */ 170 #define PA6B_PTC_Y4 \ 171 SAM_PINMUX(a, 6, b, periph) 172 173 /* pa6d_sercom0_pad2 */ 174 #define PA6D_SERCOM0_PAD2 \ 175 SAM_PINMUX(a, 6, d, periph) 176 177 /* pa6e_tcc1_wo0 */ 178 #define PA6E_TCC1_WO0 \ 179 SAM_PINMUX(a, 6, e, periph) 180 181 /* pa7_gpio */ 182 #define PA7_GPIO \ 183 SAM_PINMUX(a, 7, gpio, gpio) 184 185 /* pa7a_eic_extint7 */ 186 #define PA7A_EIC_EXTINT7 \ 187 SAM_PINMUX(a, 7, a, periph) 188 189 /* pa7b_adc0_ain7 */ 190 #define PA7B_ADC0_AIN7 \ 191 SAM_PINMUX(a, 7, b, periph) 192 193 /* pa7b_ac_ain3 */ 194 #define PA7B_AC_AIN3 \ 195 SAM_PINMUX(a, 7, b, periph) 196 197 /* pa7b_ptc_y5 */ 198 #define PA7B_PTC_Y5 \ 199 SAM_PINMUX(a, 7, b, periph) 200 201 /* pa7d_sercom0_pad3 */ 202 #define PA7D_SERCOM0_PAD3 \ 203 SAM_PINMUX(a, 7, d, periph) 204 205 /* pa7e_tcc1_wo1 */ 206 #define PA7E_TCC1_WO1 \ 207 SAM_PINMUX(a, 7, e, periph) 208 209 /* pa8_gpio */ 210 #define PA8_GPIO \ 211 SAM_PINMUX(a, 8, gpio, gpio) 212 213 /* pa8a_eic_nmi */ 214 #define PA8A_EIC_NMI \ 215 SAM_PINMUX(a, 8, a, periph) 216 217 /* pa8b_adc0_ain8 */ 218 #define PA8B_ADC0_AIN8 \ 219 SAM_PINMUX(a, 8, b, periph) 220 221 /* pa8b_ptc_xy16 */ 222 #define PA8B_PTC_XY16 \ 223 SAM_PINMUX(a, 8, b, periph) 224 225 /* pa8c_sercom0_pad0 */ 226 #define PA8C_SERCOM0_PAD0 \ 227 SAM_PINMUX(a, 8, c, periph) 228 229 /* pa8d_sercom2_pad0 */ 230 #define PA8D_SERCOM2_PAD0 \ 231 SAM_PINMUX(a, 8, d, periph) 232 233 /* pa8e_tcc0_wo0 */ 234 #define PA8E_TCC0_WO0 \ 235 SAM_PINMUX(a, 8, e, periph) 236 237 /* pa8f_tcc1_wo2 */ 238 #define PA8F_TCC1_WO2 \ 239 SAM_PINMUX(a, 8, f, periph) 240 241 /* pa9_gpio */ 242 #define PA9_GPIO \ 243 SAM_PINMUX(a, 9, gpio, gpio) 244 245 /* pa9a_eic_extint9 */ 246 #define PA9A_EIC_EXTINT9 \ 247 SAM_PINMUX(a, 9, a, periph) 248 249 /* pa9b_adc0_ain9 */ 250 #define PA9B_ADC0_AIN9 \ 251 SAM_PINMUX(a, 9, b, periph) 252 253 /* pa9b_ptc_x1 */ 254 #define PA9B_PTC_X1 \ 255 SAM_PINMUX(a, 9, b, periph) 256 257 /* pa9c_sercom0_pad1 */ 258 #define PA9C_SERCOM0_PAD1 \ 259 SAM_PINMUX(a, 9, c, periph) 260 261 /* pa9d_sercom2_pad1 */ 262 #define PA9D_SERCOM2_PAD1 \ 263 SAM_PINMUX(a, 9, d, periph) 264 265 /* pa9e_tcc0_wo1 */ 266 #define PA9E_TCC0_WO1 \ 267 SAM_PINMUX(a, 9, e, periph) 268 269 /* pa9f_tcc1_wo3 */ 270 #define PA9F_TCC1_WO3 \ 271 SAM_PINMUX(a, 9, f, periph) 272 273 /* pa10_gpio */ 274 #define PA10_GPIO \ 275 SAM_PINMUX(a, 10, gpio, gpio) 276 277 /* pa10a_eic_extint10 */ 278 #define PA10A_EIC_EXTINT10 \ 279 SAM_PINMUX(a, 10, a, periph) 280 281 /* pa10b_adc0_ain10 */ 282 #define PA10B_ADC0_AIN10 \ 283 SAM_PINMUX(a, 10, b, periph) 284 285 /* pa10b_ptc_x2 */ 286 #define PA10B_PTC_X2 \ 287 SAM_PINMUX(a, 10, b, periph) 288 289 /* pa10c_sercom0_pad2 */ 290 #define PA10C_SERCOM0_PAD2 \ 291 SAM_PINMUX(a, 10, c, periph) 292 293 /* pa10d_sercom2_pad2 */ 294 #define PA10D_SERCOM2_PAD2 \ 295 SAM_PINMUX(a, 10, d, periph) 296 297 /* pa10e_tcc1_wo0 */ 298 #define PA10E_TCC1_WO0 \ 299 SAM_PINMUX(a, 10, e, periph) 300 301 /* pa10f_tcc0_wo2 */ 302 #define PA10F_TCC0_WO2 \ 303 SAM_PINMUX(a, 10, f, periph) 304 305 /* pa10h_gclk_io4 */ 306 #define PA10H_GCLK_IO4 \ 307 SAM_PINMUX(a, 10, h, periph) 308 309 /* pa11_gpio */ 310 #define PA11_GPIO \ 311 SAM_PINMUX(a, 11, gpio, gpio) 312 313 /* pa11a_eic_extint11 */ 314 #define PA11A_EIC_EXTINT11 \ 315 SAM_PINMUX(a, 11, a, periph) 316 317 /* pa11b_adc0_ain11 */ 318 #define PA11B_ADC0_AIN11 \ 319 SAM_PINMUX(a, 11, b, periph) 320 321 /* pa11b_ptc_x3 */ 322 #define PA11B_PTC_X3 \ 323 SAM_PINMUX(a, 11, b, periph) 324 325 /* pa11c_sercom0_pad3 */ 326 #define PA11C_SERCOM0_PAD3 \ 327 SAM_PINMUX(a, 11, c, periph) 328 329 /* pa11d_sercom2_pad3 */ 330 #define PA11D_SERCOM2_PAD3 \ 331 SAM_PINMUX(a, 11, d, periph) 332 333 /* pa11e_tcc1_wo1 */ 334 #define PA11E_TCC1_WO1 \ 335 SAM_PINMUX(a, 11, e, periph) 336 337 /* pa11f_tcc0_wo3 */ 338 #define PA11F_TCC0_WO3 \ 339 SAM_PINMUX(a, 11, f, periph) 340 341 /* pa11h_gclk_io5 */ 342 #define PA11H_GCLK_IO5 \ 343 SAM_PINMUX(a, 11, h, periph) 344 345 /* pa14_gpio */ 346 #define PA14_GPIO \ 347 SAM_PINMUX(a, 14, gpio, gpio) 348 349 /* pa14a_eic_extint14 */ 350 #define PA14A_EIC_EXTINT14 \ 351 SAM_PINMUX(a, 14, a, periph) 352 353 /* pa14c_sercom2_pad2 */ 354 #define PA14C_SERCOM2_PAD2 \ 355 SAM_PINMUX(a, 14, c, periph) 356 357 /* pa14d_sercom4_pad2 */ 358 #define PA14D_SERCOM4_PAD2 \ 359 SAM_PINMUX(a, 14, d, periph) 360 361 /* pa14e_tc4_wo0 */ 362 #define PA14E_TC4_WO0 \ 363 SAM_PINMUX(a, 14, e, periph) 364 365 /* pa14f_tcc0_wo4 */ 366 #define PA14F_TCC0_WO4 \ 367 SAM_PINMUX(a, 14, f, periph) 368 369 /* pa14h_gclk_io0 */ 370 #define PA14H_GCLK_IO0 \ 371 SAM_PINMUX(a, 14, h, periph) 372 373 /* pa15_gpio */ 374 #define PA15_GPIO \ 375 SAM_PINMUX(a, 15, gpio, gpio) 376 377 /* pa15a_eic_extint15 */ 378 #define PA15A_EIC_EXTINT15 \ 379 SAM_PINMUX(a, 15, a, periph) 380 381 /* pa15c_sercom2_pad3 */ 382 #define PA15C_SERCOM2_PAD3 \ 383 SAM_PINMUX(a, 15, c, periph) 384 385 /* pa15d_sercom4_pad3 */ 386 #define PA15D_SERCOM4_PAD3 \ 387 SAM_PINMUX(a, 15, d, periph) 388 389 /* pa15e_tc4_wo1 */ 390 #define PA15E_TC4_WO1 \ 391 SAM_PINMUX(a, 15, e, periph) 392 393 /* pa15f_tcc0_wo5 */ 394 #define PA15F_TCC0_WO5 \ 395 SAM_PINMUX(a, 15, f, periph) 396 397 /* pa15h_gclk_io1 */ 398 #define PA15H_GCLK_IO1 \ 399 SAM_PINMUX(a, 15, h, periph) 400 401 /* pa16_gpio */ 402 #define PA16_GPIO \ 403 SAM_PINMUX(a, 16, gpio, gpio) 404 405 /* pa16a_eic_extint0 */ 406 #define PA16A_EIC_EXTINT0 \ 407 SAM_PINMUX(a, 16, a, periph) 408 409 /* pa16b_ptc_x4 */ 410 #define PA16B_PTC_X4 \ 411 SAM_PINMUX(a, 16, b, periph) 412 413 /* pa16c_sercom1_pad0 */ 414 #define PA16C_SERCOM1_PAD0 \ 415 SAM_PINMUX(a, 16, c, periph) 416 417 /* pa16d_sercom3_pad0 */ 418 #define PA16D_SERCOM3_PAD0 \ 419 SAM_PINMUX(a, 16, d, periph) 420 421 /* pa16e_tcc2_wo0 */ 422 #define PA16E_TCC2_WO0 \ 423 SAM_PINMUX(a, 16, e, periph) 424 425 /* pa16f_tcc0_wo6 */ 426 #define PA16F_TCC0_WO6 \ 427 SAM_PINMUX(a, 16, f, periph) 428 429 /* pa16h_gclk_io2 */ 430 #define PA16H_GCLK_IO2 \ 431 SAM_PINMUX(a, 16, h, periph) 432 433 /* pa17_gpio */ 434 #define PA17_GPIO \ 435 SAM_PINMUX(a, 17, gpio, gpio) 436 437 /* pa17a_eic_extint1 */ 438 #define PA17A_EIC_EXTINT1 \ 439 SAM_PINMUX(a, 17, a, periph) 440 441 /* pa17b_ptc_x5 */ 442 #define PA17B_PTC_X5 \ 443 SAM_PINMUX(a, 17, b, periph) 444 445 /* pa17c_sercom1_pad1 */ 446 #define PA17C_SERCOM1_PAD1 \ 447 SAM_PINMUX(a, 17, c, periph) 448 449 /* pa17d_sercom3_pad1 */ 450 #define PA17D_SERCOM3_PAD1 \ 451 SAM_PINMUX(a, 17, d, periph) 452 453 /* pa17e_tcc2_wo1 */ 454 #define PA17E_TCC2_WO1 \ 455 SAM_PINMUX(a, 17, e, periph) 456 457 /* pa17f_tcc0_wo7 */ 458 #define PA17F_TCC0_WO7 \ 459 SAM_PINMUX(a, 17, f, periph) 460 461 /* pa17h_gclk_io3 */ 462 #define PA17H_GCLK_IO3 \ 463 SAM_PINMUX(a, 17, h, periph) 464 465 /* pa18_gpio */ 466 #define PA18_GPIO \ 467 SAM_PINMUX(a, 18, gpio, gpio) 468 469 /* pa18a_eic_extint2 */ 470 #define PA18A_EIC_EXTINT2 \ 471 SAM_PINMUX(a, 18, a, periph) 472 473 /* pa18b_ptc_x6 */ 474 #define PA18B_PTC_X6 \ 475 SAM_PINMUX(a, 18, b, periph) 476 477 /* pa18c_sercom1_pad2 */ 478 #define PA18C_SERCOM1_PAD2 \ 479 SAM_PINMUX(a, 18, c, periph) 480 481 /* pa18d_sercom3_pad2 */ 482 #define PA18D_SERCOM3_PAD2 \ 483 SAM_PINMUX(a, 18, d, periph) 484 485 /* pa18e_tc4_wo0 */ 486 #define PA18E_TC4_WO0 \ 487 SAM_PINMUX(a, 18, e, periph) 488 489 /* pa18f_tcc0_wo2 */ 490 #define PA18F_TCC0_WO2 \ 491 SAM_PINMUX(a, 18, f, periph) 492 493 /* pa18h_ac_cmp0 */ 494 #define PA18H_AC_CMP0 \ 495 SAM_PINMUX(a, 18, h, periph) 496 497 /* pa19_gpio */ 498 #define PA19_GPIO \ 499 SAM_PINMUX(a, 19, gpio, gpio) 500 501 /* pa19a_eic_extint3 */ 502 #define PA19A_EIC_EXTINT3 \ 503 SAM_PINMUX(a, 19, a, periph) 504 505 /* pa19b_ptc_x7 */ 506 #define PA19B_PTC_X7 \ 507 SAM_PINMUX(a, 19, b, periph) 508 509 /* pa19c_sercom1_pad3 */ 510 #define PA19C_SERCOM1_PAD3 \ 511 SAM_PINMUX(a, 19, c, periph) 512 513 /* pa19d_sercom3_pad3 */ 514 #define PA19D_SERCOM3_PAD3 \ 515 SAM_PINMUX(a, 19, d, periph) 516 517 /* pa19e_tc4_wo1 */ 518 #define PA19E_TC4_WO1 \ 519 SAM_PINMUX(a, 19, e, periph) 520 521 /* pa19f_tcc0_wo3 */ 522 #define PA19F_TCC0_WO3 \ 523 SAM_PINMUX(a, 19, f, periph) 524 525 /* pa19h_ac_cmp1 */ 526 #define PA19H_AC_CMP1 \ 527 SAM_PINMUX(a, 19, h, periph) 528 529 /* pa22_gpio */ 530 #define PA22_GPIO \ 531 SAM_PINMUX(a, 22, gpio, gpio) 532 533 /* pa22a_eic_extint6 */ 534 #define PA22A_EIC_EXTINT6 \ 535 SAM_PINMUX(a, 22, a, periph) 536 537 /* pa22b_ptc_x10 */ 538 #define PA22B_PTC_X10 \ 539 SAM_PINMUX(a, 22, b, periph) 540 541 /* pa22c_sercom3_pad0 */ 542 #define PA22C_SERCOM3_PAD0 \ 543 SAM_PINMUX(a, 22, c, periph) 544 545 /* pa22d_sercom5_pad0 */ 546 #define PA22D_SERCOM5_PAD0 \ 547 SAM_PINMUX(a, 22, d, periph) 548 549 /* pa22e_tc0_wo0 */ 550 #define PA22E_TC0_WO0 \ 551 SAM_PINMUX(a, 22, e, periph) 552 553 /* pa22f_tcc0_wo4 */ 554 #define PA22F_TCC0_WO4 \ 555 SAM_PINMUX(a, 22, f, periph) 556 557 /* pa22h_gclk_io6 */ 558 #define PA22H_GCLK_IO6 \ 559 SAM_PINMUX(a, 22, h, periph) 560 561 /* pa23_gpio */ 562 #define PA23_GPIO \ 563 SAM_PINMUX(a, 23, gpio, gpio) 564 565 /* pa23a_eic_extint7 */ 566 #define PA23A_EIC_EXTINT7 \ 567 SAM_PINMUX(a, 23, a, periph) 568 569 /* pa23b_ptc_x11 */ 570 #define PA23B_PTC_X11 \ 571 SAM_PINMUX(a, 23, b, periph) 572 573 /* pa23c_sercom3_pad1 */ 574 #define PA23C_SERCOM3_PAD1 \ 575 SAM_PINMUX(a, 23, c, periph) 576 577 /* pa23d_sercom5_pad1 */ 578 #define PA23D_SERCOM5_PAD1 \ 579 SAM_PINMUX(a, 23, d, periph) 580 581 /* pa23e_tc0_wo1 */ 582 #define PA23E_TC0_WO1 \ 583 SAM_PINMUX(a, 23, e, periph) 584 585 /* pa23f_tcc0_wo5 */ 586 #define PA23F_TCC0_WO5 \ 587 SAM_PINMUX(a, 23, f, periph) 588 589 /* pa23h_gclk_io7 */ 590 #define PA23H_GCLK_IO7 \ 591 SAM_PINMUX(a, 23, h, periph) 592 593 /* pa24_gpio */ 594 #define PA24_GPIO \ 595 SAM_PINMUX(a, 24, gpio, gpio) 596 597 /* pa24a_eic_extint12 */ 598 #define PA24A_EIC_EXTINT12 \ 599 SAM_PINMUX(a, 24, a, periph) 600 601 /* pa24c_sercom3_pad2 */ 602 #define PA24C_SERCOM3_PAD2 \ 603 SAM_PINMUX(a, 24, c, periph) 604 605 /* pa24d_sercom5_pad2 */ 606 #define PA24D_SERCOM5_PAD2 \ 607 SAM_PINMUX(a, 24, d, periph) 608 609 /* pa24e_tc1_wo0 */ 610 #define PA24E_TC1_WO0 \ 611 SAM_PINMUX(a, 24, e, periph) 612 613 /* pa24f_tcc1_wo2 */ 614 #define PA24F_TCC1_WO2 \ 615 SAM_PINMUX(a, 24, f, periph) 616 617 /* pa24h_ac_cmp2 */ 618 #define PA24H_AC_CMP2 \ 619 SAM_PINMUX(a, 24, h, periph) 620 621 /* pa25_gpio */ 622 #define PA25_GPIO \ 623 SAM_PINMUX(a, 25, gpio, gpio) 624 625 /* pa25a_eic_extint13 */ 626 #define PA25A_EIC_EXTINT13 \ 627 SAM_PINMUX(a, 25, a, periph) 628 629 /* pa25c_sercom3_pad3 */ 630 #define PA25C_SERCOM3_PAD3 \ 631 SAM_PINMUX(a, 25, c, periph) 632 633 /* pa25d_sercom5_pad3 */ 634 #define PA25D_SERCOM5_PAD3 \ 635 SAM_PINMUX(a, 25, d, periph) 636 637 /* pa25e_tc1_wo1 */ 638 #define PA25E_TC1_WO1 \ 639 SAM_PINMUX(a, 25, e, periph) 640 641 /* pa25f_tcc1_wo3 */ 642 #define PA25F_TCC1_WO3 \ 643 SAM_PINMUX(a, 25, f, periph) 644 645 /* pa25h_ac_cmp3 */ 646 #define PA25H_AC_CMP3 \ 647 SAM_PINMUX(a, 25, h, periph) 648 649 /* pa27_gpio */ 650 #define PA27_GPIO \ 651 SAM_PINMUX(a, 27, gpio, gpio) 652 653 /* pa27a_eic_extint15 */ 654 #define PA27A_EIC_EXTINT15 \ 655 SAM_PINMUX(a, 27, a, periph) 656 657 /* pa27h_gclk_io0 */ 658 #define PA27H_GCLK_IO0 \ 659 SAM_PINMUX(a, 27, h, periph) 660 661 /* pa28_gpio */ 662 #define PA28_GPIO \ 663 SAM_PINMUX(a, 28, gpio, gpio) 664 665 /* pa28a_eic_extint8 */ 666 #define PA28A_EIC_EXTINT8 \ 667 SAM_PINMUX(a, 28, a, periph) 668 669 /* pa28h_gclk_io0 */ 670 #define PA28H_GCLK_IO0 \ 671 SAM_PINMUX(a, 28, h, periph) 672 673 /* pa30_gpio */ 674 #define PA30_GPIO \ 675 SAM_PINMUX(a, 30, gpio, gpio) 676 677 /* pa30a_eic_extint10 */ 678 #define PA30A_EIC_EXTINT10 \ 679 SAM_PINMUX(a, 30, a, periph) 680 681 /* pa30d_sercom1_pad2 */ 682 #define PA30D_SERCOM1_PAD2 \ 683 SAM_PINMUX(a, 30, d, periph) 684 685 /* pa30e_tcc1_wo0 */ 686 #define PA30E_TCC1_WO0 \ 687 SAM_PINMUX(a, 30, e, periph) 688 689 /* pa30g_swd_clk */ 690 #define PA30G_SWD_CLK \ 691 SAM_PINMUX(a, 30, g, periph) 692 693 /* pa30h_gclk_io0 */ 694 #define PA30H_GCLK_IO0 \ 695 SAM_PINMUX(a, 30, h, periph) 696 697 /* pa31_gpio */ 698 #define PA31_GPIO \ 699 SAM_PINMUX(a, 31, gpio, gpio) 700 701 /* pa31a_eic_extint11 */ 702 #define PA31A_EIC_EXTINT11 \ 703 SAM_PINMUX(a, 31, a, periph) 704 705 /* pa31d_sercom1_pad3 */ 706 #define PA31D_SERCOM1_PAD3 \ 707 SAM_PINMUX(a, 31, d, periph) 708 709 /* pa31e_tcc1_wo1 */ 710 #define PA31E_TCC1_WO1 \ 711 SAM_PINMUX(a, 31, e, periph) 712 713 /* pa31g_swd_io */ 714 #define PA31G_SWD_IO \ 715 SAM_PINMUX(a, 31, g, periph) 716
