1 /* 2 * Autogenerated file 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #include <dt-bindings/pinctrl/atmel_sam_pinctrl.h> 8 9 /* pa0_gpio */ 10 #define PA0_GPIO \ 11 SAM_PINMUX(a, 0, gpio, gpio) 12 13 /* pa1_gpio */ 14 #define PA1_GPIO \ 15 SAM_PINMUX(a, 1, gpio, gpio) 16 17 /* pa2_gpio */ 18 #define PA2_GPIO \ 19 SAM_PINMUX(a, 2, gpio, gpio) 20 21 /* pa2a_scif_gclk0 */ 22 #define PA2A_SCIF_GCLK0 \ 23 SAM_PINMUX(a, 2, a, periph) 24 25 /* pa2b_spi_npcs0 */ 26 #define PA2B_SPI_NPCS0 \ 27 SAM_PINMUX(a, 2, b, periph) 28 29 /* pa2g_catb_dis */ 30 #define PA2G_CATB_DIS \ 31 SAM_PINMUX(a, 2, g, periph) 32 33 /* pa3_gpio */ 34 #define PA3_GPIO \ 35 SAM_PINMUX(a, 3, gpio, gpio) 36 37 /* pa3b_spi_miso */ 38 #define PA3B_SPI_MISO \ 39 SAM_PINMUX(a, 3, b, periph) 40 41 /* pa4_gpio */ 42 #define PA4_GPIO \ 43 SAM_PINMUX(a, 4, gpio, gpio) 44 45 /* pa4a_adcife_ad0 */ 46 #define PA4A_ADCIFE_AD0 \ 47 SAM_PINMUX(a, 4, a, periph) 48 49 /* pa4b_usart0_clk */ 50 #define PA4B_USART0_CLK \ 51 SAM_PINMUX(a, 4, b, periph) 52 53 /* pa4c_eic_extint2 */ 54 #define PA4C_EIC_EXTINT2 \ 55 SAM_PINMUX(a, 4, c, periph) 56 57 /* pa4d_gloc_in1 */ 58 #define PA4D_GLOC_IN1 \ 59 SAM_PINMUX(a, 4, d, periph) 60 61 /* pa4g_catb_sense0 */ 62 #define PA4G_CATB_SENSE0 \ 63 SAM_PINMUX(a, 4, g, periph) 64 65 /* pa5_gpio */ 66 #define PA5_GPIO \ 67 SAM_PINMUX(a, 5, gpio, gpio) 68 69 /* pa5a_adcife_ad1 */ 70 #define PA5A_ADCIFE_AD1 \ 71 SAM_PINMUX(a, 5, a, periph) 72 73 /* pa5b_usart0_rxd */ 74 #define PA5B_USART0_RXD \ 75 SAM_PINMUX(a, 5, b, periph) 76 77 /* pa5c_eic_extint3 */ 78 #define PA5C_EIC_EXTINT3 \ 79 SAM_PINMUX(a, 5, c, periph) 80 81 /* pa5d_gloc_in2 */ 82 #define PA5D_GLOC_IN2 \ 83 SAM_PINMUX(a, 5, d, periph) 84 85 /* pa5e_adcife_trigger */ 86 #define PA5E_ADCIFE_TRIGGER \ 87 SAM_PINMUX(a, 5, e, periph) 88 89 /* pa5g_catb_sense1 */ 90 #define PA5G_CATB_SENSE1 \ 91 SAM_PINMUX(a, 5, g, periph) 92 93 /* pa6_gpio */ 94 #define PA6_GPIO \ 95 SAM_PINMUX(a, 6, gpio, gpio) 96 97 /* pa6a_dacc_vout */ 98 #define PA6A_DACC_VOUT \ 99 SAM_PINMUX(a, 6, a, periph) 100 101 /* pa6b_usart0_rts */ 102 #define PA6B_USART0_RTS \ 103 SAM_PINMUX(a, 6, b, periph) 104 105 /* pa6c_eic_extint1 */ 106 #define PA6C_EIC_EXTINT1 \ 107 SAM_PINMUX(a, 6, c, periph) 108 109 /* pa6d_gloc_in0 */ 110 #define PA6D_GLOC_IN0 \ 111 SAM_PINMUX(a, 6, d, periph) 112 113 /* pa6e_acifc_acan0 */ 114 #define PA6E_ACIFC_ACAN0 \ 115 SAM_PINMUX(a, 6, e, periph) 116 117 /* pa6g_catb_sense2 */ 118 #define PA6G_CATB_SENSE2 \ 119 SAM_PINMUX(a, 6, g, periph) 120 121 /* pa7_gpio */ 122 #define PA7_GPIO \ 123 SAM_PINMUX(a, 7, gpio, gpio) 124 125 /* pa7a_adcife_ad2 */ 126 #define PA7A_ADCIFE_AD2 \ 127 SAM_PINMUX(a, 7, a, periph) 128 129 /* pa7b_usart0_txd */ 130 #define PA7B_USART0_TXD \ 131 SAM_PINMUX(a, 7, b, periph) 132 133 /* pa7c_eic_extint4 */ 134 #define PA7C_EIC_EXTINT4 \ 135 SAM_PINMUX(a, 7, c, periph) 136 137 /* pa7d_gloc_in3 */ 138 #define PA7D_GLOC_IN3 \ 139 SAM_PINMUX(a, 7, d, periph) 140 141 /* pa7e_acifc_acap0 */ 142 #define PA7E_ACIFC_ACAP0 \ 143 SAM_PINMUX(a, 7, e, periph) 144 145 /* pa7g_catb_sense3 */ 146 #define PA7G_CATB_SENSE3 \ 147 SAM_PINMUX(a, 7, g, periph) 148 149 /* pa8_gpio */ 150 #define PA8_GPIO \ 151 SAM_PINMUX(a, 8, gpio, gpio) 152 153 /* pa8a_usart0_rts */ 154 #define PA8A_USART0_RTS \ 155 SAM_PINMUX(a, 8, a, periph) 156 157 /* pa8b_tc0_a0 */ 158 #define PA8B_TC0_A0 \ 159 SAM_PINMUX(a, 8, b, periph) 160 161 /* pa8c_pevc_evt0 */ 162 #define PA8C_PEVC_EVT0 \ 163 SAM_PINMUX(a, 8, c, periph) 164 165 /* pa8d_gloc_out0 */ 166 #define PA8D_GLOC_OUT0 \ 167 SAM_PINMUX(a, 8, d, periph) 168 169 /* pa8g_catb_sense4 */ 170 #define PA8G_CATB_SENSE4 \ 171 SAM_PINMUX(a, 8, g, periph) 172 173 /* pa9_gpio */ 174 #define PA9_GPIO \ 175 SAM_PINMUX(a, 9, gpio, gpio) 176 177 /* pa9a_usart0_cts */ 178 #define PA9A_USART0_CTS \ 179 SAM_PINMUX(a, 9, a, periph) 180 181 /* pa9b_tc0_b0 */ 182 #define PA9B_TC0_B0 \ 183 SAM_PINMUX(a, 9, b, periph) 184 185 /* pa9c_pevc_evt1 */ 186 #define PA9C_PEVC_EVT1 \ 187 SAM_PINMUX(a, 9, c, periph) 188 189 /* pa9d_parc_pcdata0 */ 190 #define PA9D_PARC_PCDATA0 \ 191 SAM_PINMUX(a, 9, d, periph) 192 193 /* pa9g_catb_sense5 */ 194 #define PA9G_CATB_SENSE5 \ 195 SAM_PINMUX(a, 9, g, periph) 196 197 /* pa10_gpio */ 198 #define PA10_GPIO \ 199 SAM_PINMUX(a, 10, gpio, gpio) 200 201 /* pa10a_usart0_clk */ 202 #define PA10A_USART0_CLK \ 203 SAM_PINMUX(a, 10, a, periph) 204 205 /* pa10b_tc0_a1 */ 206 #define PA10B_TC0_A1 \ 207 SAM_PINMUX(a, 10, b, periph) 208 209 /* pa10c_pevc_evt2 */ 210 #define PA10C_PEVC_EVT2 \ 211 SAM_PINMUX(a, 10, c, periph) 212 213 /* pa10d_parc_pcdata1 */ 214 #define PA10D_PARC_PCDATA1 \ 215 SAM_PINMUX(a, 10, d, periph) 216 217 /* pa10g_catb_sense6 */ 218 #define PA10G_CATB_SENSE6 \ 219 SAM_PINMUX(a, 10, g, periph) 220 221 /* pa11_gpio */ 222 #define PA11_GPIO \ 223 SAM_PINMUX(a, 11, gpio, gpio) 224 225 /* pa11a_usart0_rxd */ 226 #define PA11A_USART0_RXD \ 227 SAM_PINMUX(a, 11, a, periph) 228 229 /* pa11b_tc0_b1 */ 230 #define PA11B_TC0_B1 \ 231 SAM_PINMUX(a, 11, b, periph) 232 233 /* pa11c_pevc_evt3 */ 234 #define PA11C_PEVC_EVT3 \ 235 SAM_PINMUX(a, 11, c, periph) 236 237 /* pa11d_parc_pcdata2 */ 238 #define PA11D_PARC_PCDATA2 \ 239 SAM_PINMUX(a, 11, d, periph) 240 241 /* pa11g_catb_sense7 */ 242 #define PA11G_CATB_SENSE7 \ 243 SAM_PINMUX(a, 11, g, periph) 244 245 /* pa12_gpio */ 246 #define PA12_GPIO \ 247 SAM_PINMUX(a, 12, gpio, gpio) 248 249 /* pa12a_usart0_txd */ 250 #define PA12A_USART0_TXD \ 251 SAM_PINMUX(a, 12, a, periph) 252 253 /* pa12b_tc0_a2 */ 254 #define PA12B_TC0_A2 \ 255 SAM_PINMUX(a, 12, b, periph) 256 257 /* pa12d_parc_pcdata3 */ 258 #define PA12D_PARC_PCDATA3 \ 259 SAM_PINMUX(a, 12, d, periph) 260 261 /* pa12g_catb_dis */ 262 #define PA12G_CATB_DIS \ 263 SAM_PINMUX(a, 12, g, periph) 264 265 /* pa13_gpio */ 266 #define PA13_GPIO \ 267 SAM_PINMUX(a, 13, gpio, gpio) 268 269 /* pa13a_usart1_rts */ 270 #define PA13A_USART1_RTS \ 271 SAM_PINMUX(a, 13, a, periph) 272 273 /* pa13b_tc0_b2 */ 274 #define PA13B_TC0_B2 \ 275 SAM_PINMUX(a, 13, b, periph) 276 277 /* pa13c_spi_npcs1 */ 278 #define PA13C_SPI_NPCS1 \ 279 SAM_PINMUX(a, 13, c, periph) 280 281 /* pa13d_parc_pcdata4 */ 282 #define PA13D_PARC_PCDATA4 \ 283 SAM_PINMUX(a, 13, d, periph) 284 285 /* pa13g_catb_sense8 */ 286 #define PA13G_CATB_SENSE8 \ 287 SAM_PINMUX(a, 13, g, periph) 288 289 /* pa14_gpio */ 290 #define PA14_GPIO \ 291 SAM_PINMUX(a, 14, gpio, gpio) 292 293 /* pa14a_usart1_clk */ 294 #define PA14A_USART1_CLK \ 295 SAM_PINMUX(a, 14, a, periph) 296 297 /* pa14b_tc0_clk0 */ 298 #define PA14B_TC0_CLK0 \ 299 SAM_PINMUX(a, 14, b, periph) 300 301 /* pa14c_spi_npcs2 */ 302 #define PA14C_SPI_NPCS2 \ 303 SAM_PINMUX(a, 14, c, periph) 304 305 /* pa14d_parc_pcdata5 */ 306 #define PA14D_PARC_PCDATA5 \ 307 SAM_PINMUX(a, 14, d, periph) 308 309 /* pa14g_catb_sense9 */ 310 #define PA14G_CATB_SENSE9 \ 311 SAM_PINMUX(a, 14, g, periph) 312 313 /* pa15_gpio */ 314 #define PA15_GPIO \ 315 SAM_PINMUX(a, 15, gpio, gpio) 316 317 /* pa15a_usart1_rxd */ 318 #define PA15A_USART1_RXD \ 319 SAM_PINMUX(a, 15, a, periph) 320 321 /* pa15b_tc0_clk1 */ 322 #define PA15B_TC0_CLK1 \ 323 SAM_PINMUX(a, 15, b, periph) 324 325 /* pa15c_spi_npcs3 */ 326 #define PA15C_SPI_NPCS3 \ 327 SAM_PINMUX(a, 15, c, periph) 328 329 /* pa15d_parc_pcdata6 */ 330 #define PA15D_PARC_PCDATA6 \ 331 SAM_PINMUX(a, 15, d, periph) 332 333 /* pa15g_catb_sense10 */ 334 #define PA15G_CATB_SENSE10 \ 335 SAM_PINMUX(a, 15, g, periph) 336 337 /* pa16_gpio */ 338 #define PA16_GPIO \ 339 SAM_PINMUX(a, 16, gpio, gpio) 340 341 /* pa16a_usart1_txd */ 342 #define PA16A_USART1_TXD \ 343 SAM_PINMUX(a, 16, a, periph) 344 345 /* pa16b_tc0_clk2 */ 346 #define PA16B_TC0_CLK2 \ 347 SAM_PINMUX(a, 16, b, periph) 348 349 /* pa16c_eic_extint1 */ 350 #define PA16C_EIC_EXTINT1 \ 351 SAM_PINMUX(a, 16, c, periph) 352 353 /* pa16d_parc_pcdata7 */ 354 #define PA16D_PARC_PCDATA7 \ 355 SAM_PINMUX(a, 16, d, periph) 356 357 /* pa16g_catb_sense11 */ 358 #define PA16G_CATB_SENSE11 \ 359 SAM_PINMUX(a, 16, g, periph) 360 361 /* pa17_gpio */ 362 #define PA17_GPIO \ 363 SAM_PINMUX(a, 17, gpio, gpio) 364 365 /* pa17a_usart2_rts */ 366 #define PA17A_USART2_RTS \ 367 SAM_PINMUX(a, 17, a, periph) 368 369 /* pa17b_abdacb_dac0 */ 370 #define PA17B_ABDACB_DAC0 \ 371 SAM_PINMUX(a, 17, b, periph) 372 373 /* pa17c_eic_extint2 */ 374 #define PA17C_EIC_EXTINT2 \ 375 SAM_PINMUX(a, 17, c, periph) 376 377 /* pa17d_parc_pcck */ 378 #define PA17D_PARC_PCCK \ 379 SAM_PINMUX(a, 17, d, periph) 380 381 /* pa17g_catb_sense12 */ 382 #define PA17G_CATB_SENSE12 \ 383 SAM_PINMUX(a, 17, g, periph) 384 385 /* pa18_gpio */ 386 #define PA18_GPIO \ 387 SAM_PINMUX(a, 18, gpio, gpio) 388 389 /* pa18a_usart2_clk */ 390 #define PA18A_USART2_CLK \ 391 SAM_PINMUX(a, 18, a, periph) 392 393 /* pa18b_abdacb_dacn0 */ 394 #define PA18B_ABDACB_DACN0 \ 395 SAM_PINMUX(a, 18, b, periph) 396 397 /* pa18c_eic_extint3 */ 398 #define PA18C_EIC_EXTINT3 \ 399 SAM_PINMUX(a, 18, c, periph) 400 401 /* pa18d_parc_pcen1 */ 402 #define PA18D_PARC_PCEN1 \ 403 SAM_PINMUX(a, 18, d, periph) 404 405 /* pa18g_catb_sense13 */ 406 #define PA18G_CATB_SENSE13 \ 407 SAM_PINMUX(a, 18, g, periph) 408 409 /* pa19_gpio */ 410 #define PA19_GPIO \ 411 SAM_PINMUX(a, 19, gpio, gpio) 412 413 /* pa19a_usart2_rxd */ 414 #define PA19A_USART2_RXD \ 415 SAM_PINMUX(a, 19, a, periph) 416 417 /* pa19b_abdacb_dac1 */ 418 #define PA19B_ABDACB_DAC1 \ 419 SAM_PINMUX(a, 19, b, periph) 420 421 /* pa19c_eic_extint4 */ 422 #define PA19C_EIC_EXTINT4 \ 423 SAM_PINMUX(a, 19, c, periph) 424 425 /* pa19d_parc_pcen2 */ 426 #define PA19D_PARC_PCEN2 \ 427 SAM_PINMUX(a, 19, d, periph) 428 429 /* pa19e_scif_gclk0 */ 430 #define PA19E_SCIF_GCLK0 \ 431 SAM_PINMUX(a, 19, e, periph) 432 433 /* pa19g_catb_sense14 */ 434 #define PA19G_CATB_SENSE14 \ 435 SAM_PINMUX(a, 19, g, periph) 436 437 /* pa20_gpio */ 438 #define PA20_GPIO \ 439 SAM_PINMUX(a, 20, gpio, gpio) 440 441 /* pa20a_usart2_txd */ 442 #define PA20A_USART2_TXD \ 443 SAM_PINMUX(a, 20, a, periph) 444 445 /* pa20b_abdacb_dacn1 */ 446 #define PA20B_ABDACB_DACN1 \ 447 SAM_PINMUX(a, 20, b, periph) 448 449 /* pa20c_eic_extint5 */ 450 #define PA20C_EIC_EXTINT5 \ 451 SAM_PINMUX(a, 20, c, periph) 452 453 /* pa20d_gcloc_in0 */ 454 #define PA20D_GCLOC_IN0 \ 455 SAM_PINMUX(a, 20, d, periph) 456 457 /* pa20e_scif_gclk1 */ 458 #define PA20E_SCIF_GCLK1 \ 459 SAM_PINMUX(a, 20, e, periph) 460 461 /* pa20g_catb_sense15 */ 462 #define PA20G_CATB_SENSE15 \ 463 SAM_PINMUX(a, 20, g, periph) 464 465 /* pa21_gpio */ 466 #define PA21_GPIO \ 467 SAM_PINMUX(a, 21, gpio, gpio) 468 469 /* pa21a_spi_miso */ 470 #define PA21A_SPI_MISO \ 471 SAM_PINMUX(a, 21, a, periph) 472 473 /* pa21b_usart1_cts */ 474 #define PA21B_USART1_CTS \ 475 SAM_PINMUX(a, 21, b, periph) 476 477 /* pa21c_eic_extint6 */ 478 #define PA21C_EIC_EXTINT6 \ 479 SAM_PINMUX(a, 21, c, periph) 480 481 /* pa21d_gcloc_in1 */ 482 #define PA21D_GCLOC_IN1 \ 483 SAM_PINMUX(a, 21, d, periph) 484 485 /* pa21e_twim2_twd */ 486 #define PA21E_TWIM2_TWD \ 487 SAM_PINMUX(a, 21, e, periph) 488 489 /* pa21g_catb_sense16 */ 490 #define PA21G_CATB_SENSE16 \ 491 SAM_PINMUX(a, 21, g, periph) 492 493 /* pa22_gpio */ 494 #define PA22_GPIO \ 495 SAM_PINMUX(a, 22, gpio, gpio) 496 497 /* pa22a_spi_mosi */ 498 #define PA22A_SPI_MOSI \ 499 SAM_PINMUX(a, 22, a, periph) 500 501 /* pa22b_usart2_cts */ 502 #define PA22B_USART2_CTS \ 503 SAM_PINMUX(a, 22, b, periph) 504 505 /* pa22c_eic_extint7 */ 506 #define PA22C_EIC_EXTINT7 \ 507 SAM_PINMUX(a, 22, c, periph) 508 509 /* pa22d_gcloc_in2 */ 510 #define PA22D_GCLOC_IN2 \ 511 SAM_PINMUX(a, 22, d, periph) 512 513 /* pa22e_twim2_twck */ 514 #define PA22E_TWIM2_TWCK \ 515 SAM_PINMUX(a, 22, e, periph) 516 517 /* pa22g_catb_sense17 */ 518 #define PA22G_CATB_SENSE17 \ 519 SAM_PINMUX(a, 22, g, periph) 520 521 /* pa23_gpio */ 522 #define PA23_GPIO \ 523 SAM_PINMUX(a, 23, gpio, gpio) 524 525 /* pa23a_spi_sck */ 526 #define PA23A_SPI_SCK \ 527 SAM_PINMUX(a, 23, a, periph) 528 529 /* pa23b_twims0_twd */ 530 #define PA23B_TWIMS0_TWD \ 531 SAM_PINMUX(a, 23, b, periph) 532 533 /* pa23c_eic_extint8 */ 534 #define PA23C_EIC_EXTINT8 \ 535 SAM_PINMUX(a, 23, c, periph) 536 537 /* pa23d_gcloc_in3 */ 538 #define PA23D_GCLOC_IN3 \ 539 SAM_PINMUX(a, 23, d, periph) 540 541 /* pa23e_scif_glck_in0 */ 542 #define PA23E_SCIF_GLCK_IN0 \ 543 SAM_PINMUX(a, 23, e, periph) 544 545 /* pa23g_catb_dis */ 546 #define PA23G_CATB_DIS \ 547 SAM_PINMUX(a, 23, g, periph) 548 549 /* pa24_gpio */ 550 #define PA24_GPIO \ 551 SAM_PINMUX(a, 24, gpio, gpio) 552 553 /* pa24a_spi_npcs0 */ 554 #define PA24A_SPI_NPCS0 \ 555 SAM_PINMUX(a, 24, a, periph) 556 557 /* pa24b_twims0_twck */ 558 #define PA24B_TWIMS0_TWCK \ 559 SAM_PINMUX(a, 24, b, periph) 560 561 /* pa24d_gcloc_out0 */ 562 #define PA24D_GCLOC_OUT0 \ 563 SAM_PINMUX(a, 24, d, periph) 564 565 /* pa24e_scif_glck_in1 */ 566 #define PA24E_SCIF_GLCK_IN1 \ 567 SAM_PINMUX(a, 24, e, periph) 568 569 /* pa24g_catb_sense18 */ 570 #define PA24G_CATB_SENSE18 \ 571 SAM_PINMUX(a, 24, g, periph) 572 573 /* pa25_gpio */ 574 #define PA25_GPIO \ 575 SAM_PINMUX(a, 25, gpio, gpio) 576 577 /* pa25b_usart2_rxd */ 578 #define PA25B_USART2_RXD \ 579 SAM_PINMUX(a, 25, b, periph) 580 581 /* pa25g_catb_sense19 */ 582 #define PA25G_CATB_SENSE19 \ 583 SAM_PINMUX(a, 25, g, periph) 584 585 /* pa26_gpio */ 586 #define PA26_GPIO \ 587 SAM_PINMUX(a, 26, gpio, gpio) 588 589 /* pa26b_usart2_txd */ 590 #define PA26B_USART2_TXD \ 591 SAM_PINMUX(a, 26, b, periph) 592 593 /* pa26g_catb_sense20 */ 594 #define PA26G_CATB_SENSE20 \ 595 SAM_PINMUX(a, 26, g, periph) 596 597 /* pa27_gpio */ 598 #define PA27_GPIO \ 599 SAM_PINMUX(a, 27, gpio, gpio) 600 601 /* pa27a_spi_miso */ 602 #define PA27A_SPI_MISO \ 603 SAM_PINMUX(a, 27, a, periph) 604 605 /* pa27b_iisc_isck */ 606 #define PA27B_IISC_ISCK \ 607 SAM_PINMUX(a, 27, b, periph) 608 609 /* pa27c_abdacb_dac0 */ 610 #define PA27C_ABDACB_DAC0 \ 611 SAM_PINMUX(a, 27, c, periph) 612 613 /* pa27d_gloc_in4 */ 614 #define PA27D_GLOC_IN4 \ 615 SAM_PINMUX(a, 27, d, periph) 616 617 /* pa27e_usart3_rts */ 618 #define PA27E_USART3_RTS \ 619 SAM_PINMUX(a, 27, e, periph) 620 621 /* pa27g_catb_sense0 */ 622 #define PA27G_CATB_SENSE0 \ 623 SAM_PINMUX(a, 27, g, periph) 624 625 /* pa28_gpio */ 626 #define PA28_GPIO \ 627 SAM_PINMUX(a, 28, gpio, gpio) 628 629 /* pa28a_spi_mosi */ 630 #define PA28A_SPI_MOSI \ 631 SAM_PINMUX(a, 28, a, periph) 632 633 /* pa28b_iisc_isdi */ 634 #define PA28B_IISC_ISDI \ 635 SAM_PINMUX(a, 28, b, periph) 636 637 /* pa28c_abdacb_dacn0 */ 638 #define PA28C_ABDACB_DACN0 \ 639 SAM_PINMUX(a, 28, c, periph) 640 641 /* pa28d_gloc_in5 */ 642 #define PA28D_GLOC_IN5 \ 643 SAM_PINMUX(a, 28, d, periph) 644 645 /* pa28e_usart3_cts */ 646 #define PA28E_USART3_CTS \ 647 SAM_PINMUX(a, 28, e, periph) 648 649 /* pa28g_catb_sense1 */ 650 #define PA28G_CATB_SENSE1 \ 651 SAM_PINMUX(a, 28, g, periph) 652 653 /* pa29_gpio */ 654 #define PA29_GPIO \ 655 SAM_PINMUX(a, 29, gpio, gpio) 656 657 /* pa29a_spi_sck */ 658 #define PA29A_SPI_SCK \ 659 SAM_PINMUX(a, 29, a, periph) 660 661 /* pa29b_iisc_iws */ 662 #define PA29B_IISC_IWS \ 663 SAM_PINMUX(a, 29, b, periph) 664 665 /* pa29c_abdacb_dac1 */ 666 #define PA29C_ABDACB_DAC1 \ 667 SAM_PINMUX(a, 29, c, periph) 668 669 /* pa29d_gloc_in6 */ 670 #define PA29D_GLOC_IN6 \ 671 SAM_PINMUX(a, 29, d, periph) 672 673 /* pa29e_usart3_clk */ 674 #define PA29E_USART3_CLK \ 675 SAM_PINMUX(a, 29, e, periph) 676 677 /* pa29g_catb_sense2 */ 678 #define PA29G_CATB_SENSE2 \ 679 SAM_PINMUX(a, 29, g, periph) 680 681 /* pa30_gpio */ 682 #define PA30_GPIO \ 683 SAM_PINMUX(a, 30, gpio, gpio) 684 685 /* pa30a_spi_npcs0 */ 686 #define PA30A_SPI_NPCS0 \ 687 SAM_PINMUX(a, 30, a, periph) 688 689 /* pa30b_iisc_isdo */ 690 #define PA30B_IISC_ISDO \ 691 SAM_PINMUX(a, 30, b, periph) 692 693 /* pa30c_abdacb_dacn1 */ 694 #define PA30C_ABDACB_DACN1 \ 695 SAM_PINMUX(a, 30, c, periph) 696 697 /* pa30d_gloc_in7 */ 698 #define PA30D_GLOC_IN7 \ 699 SAM_PINMUX(a, 30, d, periph) 700 701 /* pa30e_usart3_rxd */ 702 #define PA30E_USART3_RXD \ 703 SAM_PINMUX(a, 30, e, periph) 704 705 /* pa30g_catb_sense3 */ 706 #define PA30G_CATB_SENSE3 \ 707 SAM_PINMUX(a, 30, g, periph) 708 709 /* pa31_gpio */ 710 #define PA31_GPIO \ 711 SAM_PINMUX(a, 31, gpio, gpio) 712 713 /* pa31a_spi_npcs1 */ 714 #define PA31A_SPI_NPCS1 \ 715 SAM_PINMUX(a, 31, a, periph) 716 717 /* pa31b_iisc_imck */ 718 #define PA31B_IISC_IMCK \ 719 SAM_PINMUX(a, 31, b, periph) 720 721 /* pa31c_abdacb_clk */ 722 #define PA31C_ABDACB_CLK \ 723 SAM_PINMUX(a, 31, c, periph) 724 725 /* pa31d_gloc_out1 */ 726 #define PA31D_GLOC_OUT1 \ 727 SAM_PINMUX(a, 31, d, periph) 728 729 /* pa31e_usart3_txd */ 730 #define PA31E_USART3_TXD \ 731 SAM_PINMUX(a, 31, e, periph) 732 733 /* pa31g_catb_dis */ 734 #define PA31G_CATB_DIS \ 735 SAM_PINMUX(a, 31, g, periph) 736 737 /* pb0_gpio */ 738 #define PB0_GPIO \ 739 SAM_PINMUX(b, 0, gpio, gpio) 740 741 /* pb0a_twims1_twd */ 742 #define PB0A_TWIMS1_TWD \ 743 SAM_PINMUX(b, 0, a, periph) 744 745 /* pb0b_usart0_rxd */ 746 #define PB0B_USART0_RXD \ 747 SAM_PINMUX(b, 0, b, periph) 748 749 /* pb0g_catb_sense21 */ 750 #define PB0G_CATB_SENSE21 \ 751 SAM_PINMUX(b, 0, g, periph) 752 753 /* pb1_gpio */ 754 #define PB1_GPIO \ 755 SAM_PINMUX(b, 1, gpio, gpio) 756 757 /* pb1a_twims1_twck */ 758 #define PB1A_TWIMS1_TWCK \ 759 SAM_PINMUX(b, 1, a, periph) 760 761 /* pb1b_usart0_txd */ 762 #define PB1B_USART0_TXD \ 763 SAM_PINMUX(b, 1, b, periph) 764 765 /* pb1c_eic_extint0 */ 766 #define PB1C_EIC_EXTINT0 \ 767 SAM_PINMUX(b, 1, c, periph) 768 769 /* pb1g_catb_sense22 */ 770 #define PB1G_CATB_SENSE22 \ 771 SAM_PINMUX(b, 1, g, periph) 772 773 /* pb2_gpio */ 774 #define PB2_GPIO \ 775 SAM_PINMUX(b, 2, gpio, gpio) 776 777 /* pb2a_adcife_ad3 */ 778 #define PB2A_ADCIFE_AD3 \ 779 SAM_PINMUX(b, 2, a, periph) 780 781 /* pb2b_usart1_rts */ 782 #define PB2B_USART1_RTS \ 783 SAM_PINMUX(b, 2, b, periph) 784 785 /* pb2c_abdacb_dac0 */ 786 #define PB2C_ABDACB_DAC0 \ 787 SAM_PINMUX(b, 2, c, periph) 788 789 /* pb2d_iisc_isck */ 790 #define PB2D_IISC_ISCK \ 791 SAM_PINMUX(b, 2, d, periph) 792 793 /* pb2e_acifc_acbn0 */ 794 #define PB2E_ACIFC_ACBN0 \ 795 SAM_PINMUX(b, 2, e, periph) 796 797 /* pb2g_catb_sense23 */ 798 #define PB2G_CATB_SENSE23 \ 799 SAM_PINMUX(b, 2, g, periph) 800 801 /* pb3_gpio */ 802 #define PB3_GPIO \ 803 SAM_PINMUX(b, 3, gpio, gpio) 804 805 /* pb3a_adcife_ad4 */ 806 #define PB3A_ADCIFE_AD4 \ 807 SAM_PINMUX(b, 3, a, periph) 808 809 /* pb3b_usart1_clk */ 810 #define PB3B_USART1_CLK \ 811 SAM_PINMUX(b, 3, b, periph) 812 813 /* pb3c_abdacb_dacn0 */ 814 #define PB3C_ABDACB_DACN0 \ 815 SAM_PINMUX(b, 3, c, periph) 816 817 /* pb3d_iisc_isdi */ 818 #define PB3D_IISC_ISDI \ 819 SAM_PINMUX(b, 3, d, periph) 820 821 /* pb3e_acifc_acbp0 */ 822 #define PB3E_ACIFC_ACBP0 \ 823 SAM_PINMUX(b, 3, e, periph) 824 825 /* pb3g_catb_dis */ 826 #define PB3G_CATB_DIS \ 827 SAM_PINMUX(b, 3, g, periph) 828 829 /* pb4_gpio */ 830 #define PB4_GPIO \ 831 SAM_PINMUX(b, 4, gpio, gpio) 832 833 /* pb4a_adcife_ad5 */ 834 #define PB4A_ADCIFE_AD5 \ 835 SAM_PINMUX(b, 4, a, periph) 836 837 /* pb4b_usart1_rxd */ 838 #define PB4B_USART1_RXD \ 839 SAM_PINMUX(b, 4, b, periph) 840 841 /* pb4c_abdacb_dac1 */ 842 #define PB4C_ABDACB_DAC1 \ 843 SAM_PINMUX(b, 4, c, periph) 844 845 /* pb4d_iisc_isdo */ 846 #define PB4D_IISC_ISDO \ 847 SAM_PINMUX(b, 4, d, periph) 848 849 /* pb4e_dacc_ext_trig0 */ 850 #define PB4E_DACC_EXT_TRIG0 \ 851 SAM_PINMUX(b, 4, e, periph) 852 853 /* pb4g_catb_sense24 */ 854 #define PB4G_CATB_SENSE24 \ 855 SAM_PINMUX(b, 4, g, periph) 856 857 /* pb5_gpio */ 858 #define PB5_GPIO \ 859 SAM_PINMUX(b, 5, gpio, gpio) 860 861 /* pb5a_adcife_ad6 */ 862 #define PB5A_ADCIFE_AD6 \ 863 SAM_PINMUX(b, 5, a, periph) 864 865 /* pb5b_usart1_txd */ 866 #define PB5B_USART1_TXD \ 867 SAM_PINMUX(b, 5, b, periph) 868 869 /* pb5c_abdacb_dacn1 */ 870 #define PB5C_ABDACB_DACN1 \ 871 SAM_PINMUX(b, 5, c, periph) 872 873 /* pb5d_iisc_imck */ 874 #define PB5D_IISC_IMCK \ 875 SAM_PINMUX(b, 5, d, periph) 876 877 /* pb5g_catb_sense25 */ 878 #define PB5G_CATB_SENSE25 \ 879 SAM_PINMUX(b, 5, g, periph) 880 881 /* pb6_gpio */ 882 #define PB6_GPIO \ 883 SAM_PINMUX(b, 6, gpio, gpio) 884 885 /* pb6a_usart3_rts */ 886 #define PB6A_USART3_RTS \ 887 SAM_PINMUX(b, 6, a, periph) 888 889 /* pb6c_gloc_in4 */ 890 #define PB6C_GLOC_IN4 \ 891 SAM_PINMUX(b, 6, c, periph) 892 893 /* pb6d_iisc_iws */ 894 #define PB6D_IISC_IWS \ 895 SAM_PINMUX(b, 6, d, periph) 896 897 /* pb6g_catb_sense26 */ 898 #define PB6G_CATB_SENSE26 \ 899 SAM_PINMUX(b, 6, g, periph) 900 901 /* pb7_gpio */ 902 #define PB7_GPIO \ 903 SAM_PINMUX(b, 7, gpio, gpio) 904 905 /* pb7a_usart3_cts */ 906 #define PB7A_USART3_CTS \ 907 SAM_PINMUX(b, 7, a, periph) 908 909 /* pb7c_gloc_in5 */ 910 #define PB7C_GLOC_IN5 \ 911 SAM_PINMUX(b, 7, c, periph) 912 913 /* pb7d_tc0_a0 */ 914 #define PB7D_TC0_A0 \ 915 SAM_PINMUX(b, 7, d, periph) 916 917 /* pb7g_catb_sense27 */ 918 #define PB7G_CATB_SENSE27 \ 919 SAM_PINMUX(b, 7, g, periph) 920 921 /* pb8_gpio */ 922 #define PB8_GPIO \ 923 SAM_PINMUX(b, 8, gpio, gpio) 924 925 /* pb8a_usart3_clk */ 926 #define PB8A_USART3_CLK \ 927 SAM_PINMUX(b, 8, a, periph) 928 929 /* pb8c_gloc_in6 */ 930 #define PB8C_GLOC_IN6 \ 931 SAM_PINMUX(b, 8, c, periph) 932 933 /* pb8d_tc0_b0 */ 934 #define PB8D_TC0_B0 \ 935 SAM_PINMUX(b, 8, d, periph) 936 937 /* pb8g_catb_sense28 */ 938 #define PB8G_CATB_SENSE28 \ 939 SAM_PINMUX(b, 8, g, periph) 940 941 /* pb9_gpio */ 942 #define PB9_GPIO \ 943 SAM_PINMUX(b, 9, gpio, gpio) 944 945 /* pb9a_usart3_rxd */ 946 #define PB9A_USART3_RXD \ 947 SAM_PINMUX(b, 9, a, periph) 948 949 /* pb9b_pevd_evt2 */ 950 #define PB9B_PEVD_EVT2 \ 951 SAM_PINMUX(b, 9, b, periph) 952 953 /* pb9c_gloc_in7 */ 954 #define PB9C_GLOC_IN7 \ 955 SAM_PINMUX(b, 9, c, periph) 956 957 /* pb9d_tc0_a1 */ 958 #define PB9D_TC0_A1 \ 959 SAM_PINMUX(b, 9, d, periph) 960 961 /* pb9g_catb_sense29 */ 962 #define PB9G_CATB_SENSE29 \ 963 SAM_PINMUX(b, 9, g, periph) 964 965 /* pb10_gpio */ 966 #define PB10_GPIO \ 967 SAM_PINMUX(b, 10, gpio, gpio) 968 969 /* pb10a_usart3_txd */ 970 #define PB10A_USART3_TXD \ 971 SAM_PINMUX(b, 10, a, periph) 972 973 /* pb10b_pevd_evt3 */ 974 #define PB10B_PEVD_EVT3 \ 975 SAM_PINMUX(b, 10, b, periph) 976 977 /* pb10c_gloc_out1 */ 978 #define PB10C_GLOC_OUT1 \ 979 SAM_PINMUX(b, 10, c, periph) 980 981 /* pb10d_tc0_b1 */ 982 #define PB10D_TC0_B1 \ 983 SAM_PINMUX(b, 10, d, periph) 984 985 /* pb10e_scif_gclk0 */ 986 #define PB10E_SCIF_GCLK0 \ 987 SAM_PINMUX(b, 10, e, periph) 988 989 /* pb10g_catb_sense30 */ 990 #define PB10G_CATB_SENSE30 \ 991 SAM_PINMUX(b, 10, g, periph) 992 993 /* pb11_gpio */ 994 #define PB11_GPIO \ 995 SAM_PINMUX(b, 11, gpio, gpio) 996 997 /* pb11a_usart0_cts */ 998 #define PB11A_USART0_CTS \ 999 SAM_PINMUX(b, 11, a, periph) 1000 1001 /* pb11b_spi_npcs2 */ 1002 #define PB11B_SPI_NPCS2 \ 1003 SAM_PINMUX(b, 11, b, periph) 1004 1005 /* pb11d_tc0_a2 */ 1006 #define PB11D_TC0_A2 \ 1007 SAM_PINMUX(b, 11, d, periph) 1008 1009 /* pb11e_scif_gclk1 */ 1010 #define PB11E_SCIF_GCLK1 \ 1011 SAM_PINMUX(b, 11, e, periph) 1012 1013 /* pb11g_catb_sense31 */ 1014 #define PB11G_CATB_SENSE31 \ 1015 SAM_PINMUX(b, 11, g, periph) 1016 1017 /* pb12_gpio */ 1018 #define PB12_GPIO \ 1019 SAM_PINMUX(b, 12, gpio, gpio) 1020 1021 /* pb12a_usart0_rts */ 1022 #define PB12A_USART0_RTS \ 1023 SAM_PINMUX(b, 12, a, periph) 1024 1025 /* pb12b_spi_npcs3 */ 1026 #define PB12B_SPI_NPCS3 \ 1027 SAM_PINMUX(b, 12, b, periph) 1028 1029 /* pb12c_pevc_evt0 */ 1030 #define PB12C_PEVC_EVT0 \ 1031 SAM_PINMUX(b, 12, c, periph) 1032 1033 /* pb12d_tc0_b2 */ 1034 #define PB12D_TC0_B2 \ 1035 SAM_PINMUX(b, 12, d, periph) 1036 1037 /* pb12e_scif_gclk2 */ 1038 #define PB12E_SCIF_GCLK2 \ 1039 SAM_PINMUX(b, 12, e, periph) 1040 1041 /* pb12g_catb_dis */ 1042 #define PB12G_CATB_DIS \ 1043 SAM_PINMUX(b, 12, g, periph) 1044 1045 /* pb13_gpio */ 1046 #define PB13_GPIO \ 1047 SAM_PINMUX(b, 13, gpio, gpio) 1048 1049 /* pb13a_usart0_clk */ 1050 #define PB13A_USART0_CLK \ 1051 SAM_PINMUX(b, 13, a, periph) 1052 1053 /* pb13b_spi_npcs1 */ 1054 #define PB13B_SPI_NPCS1 \ 1055 SAM_PINMUX(b, 13, b, periph) 1056 1057 /* pb13c_pevc_evt1 */ 1058 #define PB13C_PEVC_EVT1 \ 1059 SAM_PINMUX(b, 13, c, periph) 1060 1061 /* pb13d_tc0_clk0 */ 1062 #define PB13D_TC0_CLK0 \ 1063 SAM_PINMUX(b, 13, d, periph) 1064 1065 /* pb13e_scif_gclk3 */ 1066 #define PB13E_SCIF_GCLK3 \ 1067 SAM_PINMUX(b, 13, e, periph) 1068 1069 /* pb13g_catb_sense0 */ 1070 #define PB13G_CATB_SENSE0 \ 1071 SAM_PINMUX(b, 13, g, periph) 1072 1073 /* pb14_gpio */ 1074 #define PB14_GPIO \ 1075 SAM_PINMUX(b, 14, gpio, gpio) 1076 1077 /* pb14a_usart0_rxd */ 1078 #define PB14A_USART0_RXD \ 1079 SAM_PINMUX(b, 14, a, periph) 1080 1081 /* pb14b_spi_miso */ 1082 #define PB14B_SPI_MISO \ 1083 SAM_PINMUX(b, 14, b, periph) 1084 1085 /* pb14c_twim3_twd */ 1086 #define PB14C_TWIM3_TWD \ 1087 SAM_PINMUX(b, 14, c, periph) 1088 1089 /* pb14d_tc0_clk1 */ 1090 #define PB14D_TC0_CLK1 \ 1091 SAM_PINMUX(b, 14, d, periph) 1092 1093 /* pb14e_scif_gclk_in0 */ 1094 #define PB14E_SCIF_GCLK_IN0 \ 1095 SAM_PINMUX(b, 14, e, periph) 1096 1097 /* pb14g_catb_sense1 */ 1098 #define PB14G_CATB_SENSE1 \ 1099 SAM_PINMUX(b, 14, g, periph) 1100 1101 /* pb15_gpio */ 1102 #define PB15_GPIO \ 1103 SAM_PINMUX(b, 15, gpio, gpio) 1104 1105 /* pb15a_usart0_txd */ 1106 #define PB15A_USART0_TXD \ 1107 SAM_PINMUX(b, 15, a, periph) 1108 1109 /* pb15b_spi_mosi */ 1110 #define PB15B_SPI_MOSI \ 1111 SAM_PINMUX(b, 15, b, periph) 1112 1113 /* pb15c_twim3_twck */ 1114 #define PB15C_TWIM3_TWCK \ 1115 SAM_PINMUX(b, 15, c, periph) 1116 1117 /* pb15d_tc0_clk2 */ 1118 #define PB15D_TC0_CLK2 \ 1119 SAM_PINMUX(b, 15, d, periph) 1120 1121 /* pb15e_scif_gclk_in1 */ 1122 #define PB15E_SCIF_GCLK_IN1 \ 1123 SAM_PINMUX(b, 15, e, periph) 1124 1125 /* pb15g_catb_sense2 */ 1126 #define PB15G_CATB_SENSE2 \ 1127 SAM_PINMUX(b, 15, g, periph) 1128 1129 /* pc0_gpio */ 1130 #define PC0_GPIO \ 1131 SAM_PINMUX(c, 0, gpio, gpio) 1132 1133 /* pc0a_spi_npcs2 */ 1134 #define PC0A_SPI_NPCS2 \ 1135 SAM_PINMUX(c, 0, a, periph) 1136 1137 /* pc0b_usart0_clk */ 1138 #define PC0B_USART0_CLK \ 1139 SAM_PINMUX(c, 0, b, periph) 1140 1141 /* pc0d_tc1_a0 */ 1142 #define PC0D_TC1_A0 \ 1143 SAM_PINMUX(c, 0, d, periph) 1144 1145 /* pc0g_catb_sense3 */ 1146 #define PC0G_CATB_SENSE3 \ 1147 SAM_PINMUX(c, 0, g, periph) 1148 1149 /* pc1_gpio */ 1150 #define PC1_GPIO \ 1151 SAM_PINMUX(c, 1, gpio, gpio) 1152 1153 /* pc1a_spi_npcs3 */ 1154 #define PC1A_SPI_NPCS3 \ 1155 SAM_PINMUX(c, 1, a, periph) 1156 1157 /* pc1b_usart0_rts */ 1158 #define PC1B_USART0_RTS \ 1159 SAM_PINMUX(c, 1, b, periph) 1160 1161 /* pc1d_tc1_b0 */ 1162 #define PC1D_TC1_B0 \ 1163 SAM_PINMUX(c, 1, d, periph) 1164 1165 /* pc1g_catb_sense4 */ 1166 #define PC1G_CATB_SENSE4 \ 1167 SAM_PINMUX(c, 1, g, periph) 1168 1169 /* pc2_gpio */ 1170 #define PC2_GPIO \ 1171 SAM_PINMUX(c, 2, gpio, gpio) 1172 1173 /* pc2a_spi_npcs1 */ 1174 #define PC2A_SPI_NPCS1 \ 1175 SAM_PINMUX(c, 2, a, periph) 1176 1177 /* pc2b_usart0_cts */ 1178 #define PC2B_USART0_CTS \ 1179 SAM_PINMUX(c, 2, b, periph) 1180 1181 /* pc2c_usart0_rxd */ 1182 #define PC2C_USART0_RXD \ 1183 SAM_PINMUX(c, 2, c, periph) 1184 1185 /* pc2d_tc1_a1 */ 1186 #define PC2D_TC1_A1 \ 1187 SAM_PINMUX(c, 2, d, periph) 1188 1189 /* pc2g_catb_sense5 */ 1190 #define PC2G_CATB_SENSE5 \ 1191 SAM_PINMUX(c, 2, g, periph) 1192 1193 /* pc3_gpio */ 1194 #define PC3_GPIO \ 1195 SAM_PINMUX(c, 3, gpio, gpio) 1196 1197 /* pc3a_spi_npcs0 */ 1198 #define PC3A_SPI_NPCS0 \ 1199 SAM_PINMUX(c, 3, a, periph) 1200 1201 /* pc3b_eic_extint5 */ 1202 #define PC3B_EIC_EXTINT5 \ 1203 SAM_PINMUX(c, 3, b, periph) 1204 1205 /* pc3c_usart0_txd */ 1206 #define PC3C_USART0_TXD \ 1207 SAM_PINMUX(c, 3, c, periph) 1208 1209 /* pc3d_tc1_b1 */ 1210 #define PC3D_TC1_B1 \ 1211 SAM_PINMUX(c, 3, d, periph) 1212 1213 /* pc3g_catb_sense6 */ 1214 #define PC3G_CATB_SENSE6 \ 1215 SAM_PINMUX(c, 3, g, periph) 1216 1217 /* pc4_gpio */ 1218 #define PC4_GPIO \ 1219 SAM_PINMUX(c, 4, gpio, gpio) 1220 1221 /* pc4a_spi_miso */ 1222 #define PC4A_SPI_MISO \ 1223 SAM_PINMUX(c, 4, a, periph) 1224 1225 /* pc4b_eic_extint6 */ 1226 #define PC4B_EIC_EXTINT6 \ 1227 SAM_PINMUX(c, 4, b, periph) 1228 1229 /* pc4d_tc1_a2 */ 1230 #define PC4D_TC1_A2 \ 1231 SAM_PINMUX(c, 4, d, periph) 1232 1233 /* pc4g_catb_sense7 */ 1234 #define PC4G_CATB_SENSE7 \ 1235 SAM_PINMUX(c, 4, g, periph) 1236 1237 /* pc5_gpio */ 1238 #define PC5_GPIO \ 1239 SAM_PINMUX(c, 5, gpio, gpio) 1240 1241 /* pc5a_spi_mosi */ 1242 #define PC5A_SPI_MOSI \ 1243 SAM_PINMUX(c, 5, a, periph) 1244 1245 /* pc5b_eic_extint7 */ 1246 #define PC5B_EIC_EXTINT7 \ 1247 SAM_PINMUX(c, 5, b, periph) 1248 1249 /* pc5d_tc1_b2 */ 1250 #define PC5D_TC1_B2 \ 1251 SAM_PINMUX(c, 5, d, periph) 1252 1253 /* pc5g_catb_dis */ 1254 #define PC5G_CATB_DIS \ 1255 SAM_PINMUX(c, 5, g, periph) 1256 1257 /* pc6_gpio */ 1258 #define PC6_GPIO \ 1259 SAM_PINMUX(c, 6, gpio, gpio) 1260 1261 /* pc6a_spi_sck */ 1262 #define PC6A_SPI_SCK \ 1263 SAM_PINMUX(c, 6, a, periph) 1264 1265 /* pc6b_eic_extint8 */ 1266 #define PC6B_EIC_EXTINT8 \ 1267 SAM_PINMUX(c, 6, b, periph) 1268 1269 /* pc6d_tc1_clk0 */ 1270 #define PC6D_TC1_CLK0 \ 1271 SAM_PINMUX(c, 6, d, periph) 1272 1273 /* pc6g_catb_sense8 */ 1274 #define PC6G_CATB_SENSE8 \ 1275 SAM_PINMUX(c, 6, g, periph) 1276 1277 /* pc7_gpio */ 1278 #define PC7_GPIO \ 1279 SAM_PINMUX(c, 7, gpio, gpio) 1280 1281 /* pc7a_adcife_ad7 */ 1282 #define PC7A_ADCIFE_AD7 \ 1283 SAM_PINMUX(c, 7, a, periph) 1284 1285 /* pc7b_usart2_rts */ 1286 #define PC7B_USART2_RTS \ 1287 SAM_PINMUX(c, 7, b, periph) 1288 1289 /* pc7c_pevc_evt0 */ 1290 #define PC7C_PEVC_EVT0 \ 1291 SAM_PINMUX(c, 7, c, periph) 1292 1293 /* pc7d_tc1_clk1 */ 1294 #define PC7D_TC1_CLK1 \ 1295 SAM_PINMUX(c, 7, d, periph) 1296 1297 /* pc7g_catb_sense9 */ 1298 #define PC7G_CATB_SENSE9 \ 1299 SAM_PINMUX(c, 7, g, periph) 1300 1301 /* pc8_gpio */ 1302 #define PC8_GPIO \ 1303 SAM_PINMUX(c, 8, gpio, gpio) 1304 1305 /* pc8a_adcife_ad8 */ 1306 #define PC8A_ADCIFE_AD8 \ 1307 SAM_PINMUX(c, 8, a, periph) 1308 1309 /* pc8b_usart2_clk */ 1310 #define PC8B_USART2_CLK \ 1311 SAM_PINMUX(c, 8, b, periph) 1312 1313 /* pc8c_pevc_evt1 */ 1314 #define PC8C_PEVC_EVT1 \ 1315 SAM_PINMUX(c, 8, c, periph) 1316 1317 /* pc8d_tc1_clk2 */ 1318 #define PC8D_TC1_CLK2 \ 1319 SAM_PINMUX(c, 8, d, periph) 1320 1321 /* pc8e_usart2_cts */ 1322 #define PC8E_USART2_CTS \ 1323 SAM_PINMUX(c, 8, e, periph) 1324 1325 /* pc8g_catb_sense10 */ 1326 #define PC8G_CATB_SENSE10 \ 1327 SAM_PINMUX(c, 8, g, periph) 1328 1329 /* pc9_gpio */ 1330 #define PC9_GPIO \ 1331 SAM_PINMUX(c, 9, gpio, gpio) 1332 1333 /* pc9a_adcife_ad9 */ 1334 #define PC9A_ADCIFE_AD9 \ 1335 SAM_PINMUX(c, 9, a, periph) 1336 1337 /* pc9b_usart3_rxd */ 1338 #define PC9B_USART3_RXD \ 1339 SAM_PINMUX(c, 9, b, periph) 1340 1341 /* pc9c_abdacb_dac0 */ 1342 #define PC9C_ABDACB_DAC0 \ 1343 SAM_PINMUX(c, 9, c, periph) 1344 1345 /* pc9d_iisc_isck */ 1346 #define PC9D_IISC_ISCK \ 1347 SAM_PINMUX(c, 9, d, periph) 1348 1349 /* pc9e_acifc_acan1 */ 1350 #define PC9E_ACIFC_ACAN1 \ 1351 SAM_PINMUX(c, 9, e, periph) 1352 1353 /* pc9g_catb_sense11 */ 1354 #define PC9G_CATB_SENSE11 \ 1355 SAM_PINMUX(c, 9, g, periph) 1356 1357 /* pc10_gpio */ 1358 #define PC10_GPIO \ 1359 SAM_PINMUX(c, 10, gpio, gpio) 1360 1361 /* pc10a_adcife_ad10 */ 1362 #define PC10A_ADCIFE_AD10 \ 1363 SAM_PINMUX(c, 10, a, periph) 1364 1365 /* pc10b_usart3_txd */ 1366 #define PC10B_USART3_TXD \ 1367 SAM_PINMUX(c, 10, b, periph) 1368 1369 /* pc10c_abdacb_dacn0 */ 1370 #define PC10C_ABDACB_DACN0 \ 1371 SAM_PINMUX(c, 10, c, periph) 1372 1373 /* pc10d_iisc_isdi */ 1374 #define PC10D_IISC_ISDI \ 1375 SAM_PINMUX(c, 10, d, periph) 1376 1377 /* pc10e_acifc_acap1 */ 1378 #define PC10E_ACIFC_ACAP1 \ 1379 SAM_PINMUX(c, 10, e, periph) 1380 1381 /* pc10g_catb_sense12 */ 1382 #define PC10G_CATB_SENSE12 \ 1383 SAM_PINMUX(c, 10, g, periph) 1384 1385 /* pc11_gpio */ 1386 #define PC11_GPIO \ 1387 SAM_PINMUX(c, 11, gpio, gpio) 1388 1389 /* pc11a_adcife_ad11 */ 1390 #define PC11A_ADCIFE_AD11 \ 1391 SAM_PINMUX(c, 11, a, periph) 1392 1393 /* pc11b_usart2_rxd */ 1394 #define PC11B_USART2_RXD \ 1395 SAM_PINMUX(c, 11, b, periph) 1396 1397 /* pc11c_pevc_evt2 */ 1398 #define PC11C_PEVC_EVT2 \ 1399 SAM_PINMUX(c, 11, c, periph) 1400 1401 /* pc11g_catb_sense13 */ 1402 #define PC11G_CATB_SENSE13 \ 1403 SAM_PINMUX(c, 11, g, periph) 1404 1405 /* pc12_gpio */ 1406 #define PC12_GPIO \ 1407 SAM_PINMUX(c, 12, gpio, gpio) 1408 1409 /* pc12a_adcife_ad12 */ 1410 #define PC12A_ADCIFE_AD12 \ 1411 SAM_PINMUX(c, 12, a, periph) 1412 1413 /* pc12b_usart2_txd */ 1414 #define PC12B_USART2_TXD \ 1415 SAM_PINMUX(c, 12, b, periph) 1416 1417 /* pc12c_abdacb_clk */ 1418 #define PC12C_ABDACB_CLK \ 1419 SAM_PINMUX(c, 12, c, periph) 1420 1421 /* pc12d_iisc_iws */ 1422 #define PC12D_IISC_IWS \ 1423 SAM_PINMUX(c, 12, d, periph) 1424 1425 /* pc12g_catb_sense14 */ 1426 #define PC12G_CATB_SENSE14 \ 1427 SAM_PINMUX(c, 12, g, periph) 1428 1429 /* pc13_gpio */ 1430 #define PC13_GPIO \ 1431 SAM_PINMUX(c, 13, gpio, gpio) 1432 1433 /* pc13a_adcife_ad13 */ 1434 #define PC13A_ADCIFE_AD13 \ 1435 SAM_PINMUX(c, 13, a, periph) 1436 1437 /* pc13b_usart3_rts */ 1438 #define PC13B_USART3_RTS \ 1439 SAM_PINMUX(c, 13, b, periph) 1440 1441 /* pc13c_abdacb_dac1 */ 1442 #define PC13C_ABDACB_DAC1 \ 1443 SAM_PINMUX(c, 13, c, periph) 1444 1445 /* pc13d_iisc_isdo */ 1446 #define PC13D_IISC_ISDO \ 1447 SAM_PINMUX(c, 13, d, periph) 1448 1449 /* pc13e_acifc_acbn1 */ 1450 #define PC13E_ACIFC_ACBN1 \ 1451 SAM_PINMUX(c, 13, e, periph) 1452 1453 /* pc13g_catb_sense15 */ 1454 #define PC13G_CATB_SENSE15 \ 1455 SAM_PINMUX(c, 13, g, periph) 1456 1457 /* pc14_gpio */ 1458 #define PC14_GPIO \ 1459 SAM_PINMUX(c, 14, gpio, gpio) 1460 1461 /* pc14a_adcife_ad14 */ 1462 #define PC14A_ADCIFE_AD14 \ 1463 SAM_PINMUX(c, 14, a, periph) 1464 1465 /* pc14b_usart3_clk */ 1466 #define PC14B_USART3_CLK \ 1467 SAM_PINMUX(c, 14, b, periph) 1468 1469 /* pc14c_abdacb_dacn1 */ 1470 #define PC14C_ABDACB_DACN1 \ 1471 SAM_PINMUX(c, 14, c, periph) 1472 1473 /* pc14d_iisc_imck */ 1474 #define PC14D_IISC_IMCK \ 1475 SAM_PINMUX(c, 14, d, periph) 1476 1477 /* pc14e_acifc_acbp1 */ 1478 #define PC14E_ACIFC_ACBP1 \ 1479 SAM_PINMUX(c, 14, e, periph) 1480 1481 /* pc14g_catb_dis */ 1482 #define PC14G_CATB_DIS \ 1483 SAM_PINMUX(c, 14, g, periph) 1484 1485 /* pc15_gpio */ 1486 #define PC15_GPIO \ 1487 SAM_PINMUX(c, 15, gpio, gpio) 1488 1489 /* pc15a_tc1_a0 */ 1490 #define PC15A_TC1_A0 \ 1491 SAM_PINMUX(c, 15, a, periph) 1492 1493 /* pc15d_gloc_in4 */ 1494 #define PC15D_GLOC_IN4 \ 1495 SAM_PINMUX(c, 15, d, periph) 1496 1497 /* pc15g_catb_sense16 */ 1498 #define PC15G_CATB_SENSE16 \ 1499 SAM_PINMUX(c, 15, g, periph) 1500 1501 /* pc16_gpio */ 1502 #define PC16_GPIO \ 1503 SAM_PINMUX(c, 16, gpio, gpio) 1504 1505 /* pc16a_tc1_b0 */ 1506 #define PC16A_TC1_B0 \ 1507 SAM_PINMUX(c, 16, a, periph) 1508 1509 /* pc16d_gloc_in5 */ 1510 #define PC16D_GLOC_IN5 \ 1511 SAM_PINMUX(c, 16, d, periph) 1512 1513 /* pc16g_catb_sense17 */ 1514 #define PC16G_CATB_SENSE17 \ 1515 SAM_PINMUX(c, 16, g, periph) 1516 1517 /* pc17_gpio */ 1518 #define PC17_GPIO \ 1519 SAM_PINMUX(c, 17, gpio, gpio) 1520 1521 /* pc17a_tc1_a1 */ 1522 #define PC17A_TC1_A1 \ 1523 SAM_PINMUX(c, 17, a, periph) 1524 1525 /* pc17d_gloc_in6 */ 1526 #define PC17D_GLOC_IN6 \ 1527 SAM_PINMUX(c, 17, d, periph) 1528 1529 /* pc17g_catb_sense18 */ 1530 #define PC17G_CATB_SENSE18 \ 1531 SAM_PINMUX(c, 17, g, periph) 1532 1533 /* pc18_gpio */ 1534 #define PC18_GPIO \ 1535 SAM_PINMUX(c, 18, gpio, gpio) 1536 1537 /* pc18a_tc1_b1 */ 1538 #define PC18A_TC1_B1 \ 1539 SAM_PINMUX(c, 18, a, periph) 1540 1541 /* pc18d_gloc_in7 */ 1542 #define PC18D_GLOC_IN7 \ 1543 SAM_PINMUX(c, 18, d, periph) 1544 1545 /* pc18g_catb_sense19 */ 1546 #define PC18G_CATB_SENSE19 \ 1547 SAM_PINMUX(c, 18, g, periph) 1548 1549 /* pc19_gpio */ 1550 #define PC19_GPIO \ 1551 SAM_PINMUX(c, 19, gpio, gpio) 1552 1553 /* pc19a_tc1_a2 */ 1554 #define PC19A_TC1_A2 \ 1555 SAM_PINMUX(c, 19, a, periph) 1556 1557 /* pc19d_gloc_out1 */ 1558 #define PC19D_GLOC_OUT1 \ 1559 SAM_PINMUX(c, 19, d, periph) 1560 1561 /* pc19g_catb_sense20 */ 1562 #define PC19G_CATB_SENSE20 \ 1563 SAM_PINMUX(c, 19, g, periph) 1564 1565 /* pc20_gpio */ 1566 #define PC20_GPIO \ 1567 SAM_PINMUX(c, 20, gpio, gpio) 1568 1569 /* pc20a_tc1_b2 */ 1570 #define PC20A_TC1_B2 \ 1571 SAM_PINMUX(c, 20, a, periph) 1572 1573 /* pc20g_catb_sense21 */ 1574 #define PC20G_CATB_SENSE21 \ 1575 SAM_PINMUX(c, 20, g, periph) 1576 1577 /* pc21_gpio */ 1578 #define PC21_GPIO \ 1579 SAM_PINMUX(c, 21, gpio, gpio) 1580 1581 /* pc21a_tc1_clk0 */ 1582 #define PC21A_TC1_CLK0 \ 1583 SAM_PINMUX(c, 21, a, periph) 1584 1585 /* pc21d_parc_pcck */ 1586 #define PC21D_PARC_PCCK \ 1587 SAM_PINMUX(c, 21, d, periph) 1588 1589 /* pc21g_catb_sense22 */ 1590 #define PC21G_CATB_SENSE22 \ 1591 SAM_PINMUX(c, 21, g, periph) 1592 1593 /* pc22_gpio */ 1594 #define PC22_GPIO \ 1595 SAM_PINMUX(c, 22, gpio, gpio) 1596 1597 /* pc22a_tc1_clk1 */ 1598 #define PC22A_TC1_CLK1 \ 1599 SAM_PINMUX(c, 22, a, periph) 1600 1601 /* pc22d_parc_pcen1 */ 1602 #define PC22D_PARC_PCEN1 \ 1603 SAM_PINMUX(c, 22, d, periph) 1604 1605 /* pc22g_catb_sense23 */ 1606 #define PC22G_CATB_SENSE23 \ 1607 SAM_PINMUX(c, 22, g, periph) 1608 1609 /* pc23_gpio */ 1610 #define PC23_GPIO \ 1611 SAM_PINMUX(c, 23, gpio, gpio) 1612 1613 /* pc23a_tc1_clk2 */ 1614 #define PC23A_TC1_CLK2 \ 1615 SAM_PINMUX(c, 23, a, periph) 1616 1617 /* pc23d_parc_pcen2 */ 1618 #define PC23D_PARC_PCEN2 \ 1619 SAM_PINMUX(c, 23, d, periph) 1620 1621 /* pc23g_catb_dis */ 1622 #define PC23G_CATB_DIS \ 1623 SAM_PINMUX(c, 23, g, periph) 1624 1625 /* pc24_gpio */ 1626 #define PC24_GPIO \ 1627 SAM_PINMUX(c, 24, gpio, gpio) 1628 1629 /* pc24a_usart1_rts */ 1630 #define PC24A_USART1_RTS \ 1631 SAM_PINMUX(c, 24, a, periph) 1632 1633 /* pc24b_eic_extint1 */ 1634 #define PC24B_EIC_EXTINT1 \ 1635 SAM_PINMUX(c, 24, b, periph) 1636 1637 /* pc24c_pevc_evt0 */ 1638 #define PC24C_PEVC_EVT0 \ 1639 SAM_PINMUX(c, 24, c, periph) 1640 1641 /* pc24d_parc_pcdata0 */ 1642 #define PC24D_PARC_PCDATA0 \ 1643 SAM_PINMUX(c, 24, d, periph) 1644 1645 /* pc24g_catb_sense24 */ 1646 #define PC24G_CATB_SENSE24 \ 1647 SAM_PINMUX(c, 24, g, periph) 1648 1649 /* pc25_gpio */ 1650 #define PC25_GPIO \ 1651 SAM_PINMUX(c, 25, gpio, gpio) 1652 1653 /* pc25a_usart1_clk */ 1654 #define PC25A_USART1_CLK \ 1655 SAM_PINMUX(c, 25, a, periph) 1656 1657 /* pc25b_eic_extint2 */ 1658 #define PC25B_EIC_EXTINT2 \ 1659 SAM_PINMUX(c, 25, b, periph) 1660 1661 /* pc25c_pevc_evt1 */ 1662 #define PC25C_PEVC_EVT1 \ 1663 SAM_PINMUX(c, 25, c, periph) 1664 1665 /* pc25d_parc_pcdata1 */ 1666 #define PC25D_PARC_PCDATA1 \ 1667 SAM_PINMUX(c, 25, d, periph) 1668 1669 /* pc25g_catb_sense25 */ 1670 #define PC25G_CATB_SENSE25 \ 1671 SAM_PINMUX(c, 25, g, periph) 1672 1673 /* pc26_gpio */ 1674 #define PC26_GPIO \ 1675 SAM_PINMUX(c, 26, gpio, gpio) 1676 1677 /* pc26a_usart1_rxd */ 1678 #define PC26A_USART1_RXD \ 1679 SAM_PINMUX(c, 26, a, periph) 1680 1681 /* pc26b_eic_extint3 */ 1682 #define PC26B_EIC_EXTINT3 \ 1683 SAM_PINMUX(c, 26, b, periph) 1684 1685 /* pc26c_pevc_evt2 */ 1686 #define PC26C_PEVC_EVT2 \ 1687 SAM_PINMUX(c, 26, c, periph) 1688 1689 /* pc26d_parc_pcdata2 */ 1690 #define PC26D_PARC_PCDATA2 \ 1691 SAM_PINMUX(c, 26, d, periph) 1692 1693 /* pc26e_scif_glkc0 */ 1694 #define PC26E_SCIF_GLKC0 \ 1695 SAM_PINMUX(c, 26, e, periph) 1696 1697 /* pc26g_catb_sense26 */ 1698 #define PC26G_CATB_SENSE26 \ 1699 SAM_PINMUX(c, 26, g, periph) 1700 1701 /* pc27_gpio */ 1702 #define PC27_GPIO \ 1703 SAM_PINMUX(c, 27, gpio, gpio) 1704 1705 /* pc27a_usart1_txd */ 1706 #define PC27A_USART1_TXD \ 1707 SAM_PINMUX(c, 27, a, periph) 1708 1709 /* pc27b_eic_extint4 */ 1710 #define PC27B_EIC_EXTINT4 \ 1711 SAM_PINMUX(c, 27, b, periph) 1712 1713 /* pc27c_pevc_evt3 */ 1714 #define PC27C_PEVC_EVT3 \ 1715 SAM_PINMUX(c, 27, c, periph) 1716 1717 /* pc27d_parc_pcdata3 */ 1718 #define PC27D_PARC_PCDATA3 \ 1719 SAM_PINMUX(c, 27, d, periph) 1720 1721 /* pc27e_scif_gclk1 */ 1722 #define PC27E_SCIF_GCLK1 \ 1723 SAM_PINMUX(c, 27, e, periph) 1724 1725 /* pc27g_catb_sense27 */ 1726 #define PC27G_CATB_SENSE27 \ 1727 SAM_PINMUX(c, 27, g, periph) 1728 1729 /* pc28_gpio */ 1730 #define PC28_GPIO \ 1731 SAM_PINMUX(c, 28, gpio, gpio) 1732 1733 /* pc28a_usart3_rxd */ 1734 #define PC28A_USART3_RXD \ 1735 SAM_PINMUX(c, 28, a, periph) 1736 1737 /* pc28b_spi_miso */ 1738 #define PC28B_SPI_MISO \ 1739 SAM_PINMUX(c, 28, b, periph) 1740 1741 /* pc28c_gloc_in4 */ 1742 #define PC28C_GLOC_IN4 \ 1743 SAM_PINMUX(c, 28, c, periph) 1744 1745 /* pc28d_parc_pcdata4 */ 1746 #define PC28D_PARC_PCDATA4 \ 1747 SAM_PINMUX(c, 28, d, periph) 1748 1749 /* pc28e_scif_gclk2 */ 1750 #define PC28E_SCIF_GCLK2 \ 1751 SAM_PINMUX(c, 28, e, periph) 1752 1753 /* pc28g_catb_sense28 */ 1754 #define PC28G_CATB_SENSE28 \ 1755 SAM_PINMUX(c, 28, g, periph) 1756 1757 /* pc29_gpio */ 1758 #define PC29_GPIO \ 1759 SAM_PINMUX(c, 29, gpio, gpio) 1760 1761 /* pc29a_usart3_txd */ 1762 #define PC29A_USART3_TXD \ 1763 SAM_PINMUX(c, 29, a, periph) 1764 1765 /* pc29b_spi_mosi */ 1766 #define PC29B_SPI_MOSI \ 1767 SAM_PINMUX(c, 29, b, periph) 1768 1769 /* pc29c_gloc_in5 */ 1770 #define PC29C_GLOC_IN5 \ 1771 SAM_PINMUX(c, 29, c, periph) 1772 1773 /* pc29d_parc_pcdata5 */ 1774 #define PC29D_PARC_PCDATA5 \ 1775 SAM_PINMUX(c, 29, d, periph) 1776 1777 /* pc29e_scif_gclk3 */ 1778 #define PC29E_SCIF_GCLK3 \ 1779 SAM_PINMUX(c, 29, e, periph) 1780 1781 /* pc29g_catb_sense29 */ 1782 #define PC29G_CATB_SENSE29 \ 1783 SAM_PINMUX(c, 29, g, periph) 1784 1785 /* pc30_gpio */ 1786 #define PC30_GPIO \ 1787 SAM_PINMUX(c, 30, gpio, gpio) 1788 1789 /* pc30a_usart3_rts */ 1790 #define PC30A_USART3_RTS \ 1791 SAM_PINMUX(c, 30, a, periph) 1792 1793 /* pc30b_spi_sck */ 1794 #define PC30B_SPI_SCK \ 1795 SAM_PINMUX(c, 30, b, periph) 1796 1797 /* pc30c_gloc_in6 */ 1798 #define PC30C_GLOC_IN6 \ 1799 SAM_PINMUX(c, 30, c, periph) 1800 1801 /* pc30d_parc_pcdata6 */ 1802 #define PC30D_PARC_PCDATA6 \ 1803 SAM_PINMUX(c, 30, d, periph) 1804 1805 /* pc30e_scif_gclk_in0 */ 1806 #define PC30E_SCIF_GCLK_IN0 \ 1807 SAM_PINMUX(c, 30, e, periph) 1808 1809 /* pc30g_catb_sense30 */ 1810 #define PC30G_CATB_SENSE30 \ 1811 SAM_PINMUX(c, 30, g, periph) 1812 1813 /* pc31_gpio */ 1814 #define PC31_GPIO \ 1815 SAM_PINMUX(c, 31, gpio, gpio) 1816 1817 /* pc31a_usart3_clk */ 1818 #define PC31A_USART3_CLK \ 1819 SAM_PINMUX(c, 31, a, periph) 1820 1821 /* pc31b_spi_npcs0 */ 1822 #define PC31B_SPI_NPCS0 \ 1823 SAM_PINMUX(c, 31, b, periph) 1824 1825 /* pc31c_gloc_out1 */ 1826 #define PC31C_GLOC_OUT1 \ 1827 SAM_PINMUX(c, 31, c, periph) 1828 1829 /* pc31d_parc_pcdata7 */ 1830 #define PC31D_PARC_PCDATA7 \ 1831 SAM_PINMUX(c, 31, d, periph) 1832 1833 /* pc31e_scif_gclk_in1 */ 1834 #define PC31E_SCIF_GCLK_IN1 \ 1835 SAM_PINMUX(c, 31, e, periph) 1836 1837 /* pc31g_catb_sense31 */ 1838 #define PC31G_CATB_SENSE31 \ 1839 SAM_PINMUX(c, 31, g, periph) 1840
