1 /** 2 * \file 3 * 4 * \brief Instance description for TCC2 5 * 6 * Copyright (c) 2018 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAMR35_TCC2_INSTANCE_ 31 #define _SAMR35_TCC2_INSTANCE_ 32 33 /* ========== Register definition for TCC2 peripheral ========== */ 34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 35 #define REG_TCC2_CTRLA (0x42001C00) /**< \brief (TCC2) Control A */ 36 #define REG_TCC2_CTRLBCLR (0x42001C04) /**< \brief (TCC2) Control B Clear */ 37 #define REG_TCC2_CTRLBSET (0x42001C05) /**< \brief (TCC2) Control B Set */ 38 #define REG_TCC2_SYNCBUSY (0x42001C08) /**< \brief (TCC2) Synchronization Busy */ 39 #define REG_TCC2_FCTRLA (0x42001C0C) /**< \brief (TCC2) Recoverable Fault A Configuration */ 40 #define REG_TCC2_FCTRLB (0x42001C10) /**< \brief (TCC2) Recoverable Fault B Configuration */ 41 #define REG_TCC2_DRVCTRL (0x42001C18) /**< \brief (TCC2) Driver Control */ 42 #define REG_TCC2_DBGCTRL (0x42001C1E) /**< \brief (TCC2) Debug Control */ 43 #define REG_TCC2_EVCTRL (0x42001C20) /**< \brief (TCC2) Event Control */ 44 #define REG_TCC2_INTENCLR (0x42001C24) /**< \brief (TCC2) Interrupt Enable Clear */ 45 #define REG_TCC2_INTENSET (0x42001C28) /**< \brief (TCC2) Interrupt Enable Set */ 46 #define REG_TCC2_INTFLAG (0x42001C2C) /**< \brief (TCC2) Interrupt Flag Status and Clear */ 47 #define REG_TCC2_STATUS (0x42001C30) /**< \brief (TCC2) Status */ 48 #define REG_TCC2_COUNT (0x42001C34) /**< \brief (TCC2) Count */ 49 #define REG_TCC2_WAVE (0x42001C3C) /**< \brief (TCC2) Waveform Control */ 50 #define REG_TCC2_PER (0x42001C40) /**< \brief (TCC2) Period */ 51 #define REG_TCC2_CC0 (0x42001C44) /**< \brief (TCC2) Compare and Capture 0 */ 52 #define REG_TCC2_CC1 (0x42001C48) /**< \brief (TCC2) Compare and Capture 1 */ 53 #define REG_TCC2_PERBUF (0x42001C6C) /**< \brief (TCC2) Period Buffer */ 54 #define REG_TCC2_CCBUF0 (0x42001C70) /**< \brief (TCC2) Compare and Capture Buffer 0 */ 55 #define REG_TCC2_CCBUF1 (0x42001C74) /**< \brief (TCC2) Compare and Capture Buffer 1 */ 56 #else 57 #define REG_TCC2_CTRLA (*(RwReg *)0x42001C00UL) /**< \brief (TCC2) Control A */ 58 #define REG_TCC2_CTRLBCLR (*(RwReg8 *)0x42001C04UL) /**< \brief (TCC2) Control B Clear */ 59 #define REG_TCC2_CTRLBSET (*(RwReg8 *)0x42001C05UL) /**< \brief (TCC2) Control B Set */ 60 #define REG_TCC2_SYNCBUSY (*(RoReg *)0x42001C08UL) /**< \brief (TCC2) Synchronization Busy */ 61 #define REG_TCC2_FCTRLA (*(RwReg *)0x42001C0CUL) /**< \brief (TCC2) Recoverable Fault A Configuration */ 62 #define REG_TCC2_FCTRLB (*(RwReg *)0x42001C10UL) /**< \brief (TCC2) Recoverable Fault B Configuration */ 63 #define REG_TCC2_DRVCTRL (*(RwReg *)0x42001C18UL) /**< \brief (TCC2) Driver Control */ 64 #define REG_TCC2_DBGCTRL (*(RwReg8 *)0x42001C1EUL) /**< \brief (TCC2) Debug Control */ 65 #define REG_TCC2_EVCTRL (*(RwReg *)0x42001C20UL) /**< \brief (TCC2) Event Control */ 66 #define REG_TCC2_INTENCLR (*(RwReg *)0x42001C24UL) /**< \brief (TCC2) Interrupt Enable Clear */ 67 #define REG_TCC2_INTENSET (*(RwReg *)0x42001C28UL) /**< \brief (TCC2) Interrupt Enable Set */ 68 #define REG_TCC2_INTFLAG (*(RwReg *)0x42001C2CUL) /**< \brief (TCC2) Interrupt Flag Status and Clear */ 69 #define REG_TCC2_STATUS (*(RwReg *)0x42001C30UL) /**< \brief (TCC2) Status */ 70 #define REG_TCC2_COUNT (*(RwReg *)0x42001C34UL) /**< \brief (TCC2) Count */ 71 #define REG_TCC2_WAVE (*(RwReg *)0x42001C3CUL) /**< \brief (TCC2) Waveform Control */ 72 #define REG_TCC2_PER (*(RwReg *)0x42001C40UL) /**< \brief (TCC2) Period */ 73 #define REG_TCC2_CC0 (*(RwReg *)0x42001C44UL) /**< \brief (TCC2) Compare and Capture 0 */ 74 #define REG_TCC2_CC1 (*(RwReg *)0x42001C48UL) /**< \brief (TCC2) Compare and Capture 1 */ 75 #define REG_TCC2_PERBUF (*(RwReg *)0x42001C6CUL) /**< \brief (TCC2) Period Buffer */ 76 #define REG_TCC2_CCBUF0 (*(RwReg *)0x42001C70UL) /**< \brief (TCC2) Compare and Capture Buffer 0 */ 77 #define REG_TCC2_CCBUF1 (*(RwReg *)0x42001C74UL) /**< \brief (TCC2) Compare and Capture Buffer 1 */ 78 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 79 80 /* ========== Instance parameters for TCC2 peripheral ========== */ 81 #define TCC2_CC_NUM 2 // Number of Compare/Capture units 82 #define TCC2_DITHERING 0 // Dithering feature implemented 83 #define TCC2_DMAC_ID_MC_0 20 84 #define TCC2_DMAC_ID_MC_1 21 85 #define TCC2_DMAC_ID_MC_LSB 20 86 #define TCC2_DMAC_ID_MC_MSB 21 87 #define TCC2_DMAC_ID_MC_SIZE 2 88 #define TCC2_DMAC_ID_OVF 19 // DMA overflow/underflow/retrigger trigger 89 #define TCC2_DTI 0 // Dead-Time-Insertion feature implemented 90 #define TCC2_EXT 0 // Coding of implemented extended features 91 #define TCC2_GCLK_ID 26 // Index of Generic Clock 92 #define TCC2_OTMX 0 // Output Matrix feature implemented 93 #define TCC2_OW_NUM 2 // Number of Output Waveforms 94 #define TCC2_PG 0 // Pattern Generation feature implemented 95 #define TCC2_SIZE 16 96 #define TCC2_SWAP 0 // DTI outputs swap feature implemented 97 #define TCC2_TYPE 0 // TCC type 0 : NA, 1 : Master, 2 : Slave 98 99 #endif /* _SAMR35_TCC2_INSTANCE_ */ 100
