1 /** 2 * \file 3 * 4 * \brief Instance description for TCC0 5 * 6 * Copyright (c) 2018 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAMR35_TCC0_INSTANCE_ 31 #define _SAMR35_TCC0_INSTANCE_ 32 33 /* ========== Register definition for TCC0 peripheral ========== */ 34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 35 #define REG_TCC0_CTRLA (0x42001400) /**< \brief (TCC0) Control A */ 36 #define REG_TCC0_CTRLBCLR (0x42001404) /**< \brief (TCC0) Control B Clear */ 37 #define REG_TCC0_CTRLBSET (0x42001405) /**< \brief (TCC0) Control B Set */ 38 #define REG_TCC0_SYNCBUSY (0x42001408) /**< \brief (TCC0) Synchronization Busy */ 39 #define REG_TCC0_FCTRLA (0x4200140C) /**< \brief (TCC0) Recoverable Fault A Configuration */ 40 #define REG_TCC0_FCTRLB (0x42001410) /**< \brief (TCC0) Recoverable Fault B Configuration */ 41 #define REG_TCC0_WEXCTRL (0x42001414) /**< \brief (TCC0) Waveform Extension Configuration */ 42 #define REG_TCC0_DRVCTRL (0x42001418) /**< \brief (TCC0) Driver Control */ 43 #define REG_TCC0_DBGCTRL (0x4200141E) /**< \brief (TCC0) Debug Control */ 44 #define REG_TCC0_EVCTRL (0x42001420) /**< \brief (TCC0) Event Control */ 45 #define REG_TCC0_INTENCLR (0x42001424) /**< \brief (TCC0) Interrupt Enable Clear */ 46 #define REG_TCC0_INTENSET (0x42001428) /**< \brief (TCC0) Interrupt Enable Set */ 47 #define REG_TCC0_INTFLAG (0x4200142C) /**< \brief (TCC0) Interrupt Flag Status and Clear */ 48 #define REG_TCC0_STATUS (0x42001430) /**< \brief (TCC0) Status */ 49 #define REG_TCC0_COUNT (0x42001434) /**< \brief (TCC0) Count */ 50 #define REG_TCC0_PATT (0x42001438) /**< \brief (TCC0) Pattern */ 51 #define REG_TCC0_WAVE (0x4200143C) /**< \brief (TCC0) Waveform Control */ 52 #define REG_TCC0_PER (0x42001440) /**< \brief (TCC0) Period */ 53 #define REG_TCC0_CC0 (0x42001444) /**< \brief (TCC0) Compare and Capture 0 */ 54 #define REG_TCC0_CC1 (0x42001448) /**< \brief (TCC0) Compare and Capture 1 */ 55 #define REG_TCC0_CC2 (0x4200144C) /**< \brief (TCC0) Compare and Capture 2 */ 56 #define REG_TCC0_CC3 (0x42001450) /**< \brief (TCC0) Compare and Capture 3 */ 57 #define REG_TCC0_PATTBUF (0x42001464) /**< \brief (TCC0) Pattern Buffer */ 58 #define REG_TCC0_PERBUF (0x4200146C) /**< \brief (TCC0) Period Buffer */ 59 #define REG_TCC0_CCBUF0 (0x42001470) /**< \brief (TCC0) Compare and Capture Buffer 0 */ 60 #define REG_TCC0_CCBUF1 (0x42001474) /**< \brief (TCC0) Compare and Capture Buffer 1 */ 61 #define REG_TCC0_CCBUF2 (0x42001478) /**< \brief (TCC0) Compare and Capture Buffer 2 */ 62 #define REG_TCC0_CCBUF3 (0x4200147C) /**< \brief (TCC0) Compare and Capture Buffer 3 */ 63 #else 64 #define REG_TCC0_CTRLA (*(RwReg *)0x42001400UL) /**< \brief (TCC0) Control A */ 65 #define REG_TCC0_CTRLBCLR (*(RwReg8 *)0x42001404UL) /**< \brief (TCC0) Control B Clear */ 66 #define REG_TCC0_CTRLBSET (*(RwReg8 *)0x42001405UL) /**< \brief (TCC0) Control B Set */ 67 #define REG_TCC0_SYNCBUSY (*(RoReg *)0x42001408UL) /**< \brief (TCC0) Synchronization Busy */ 68 #define REG_TCC0_FCTRLA (*(RwReg *)0x4200140CUL) /**< \brief (TCC0) Recoverable Fault A Configuration */ 69 #define REG_TCC0_FCTRLB (*(RwReg *)0x42001410UL) /**< \brief (TCC0) Recoverable Fault B Configuration */ 70 #define REG_TCC0_WEXCTRL (*(RwReg *)0x42001414UL) /**< \brief (TCC0) Waveform Extension Configuration */ 71 #define REG_TCC0_DRVCTRL (*(RwReg *)0x42001418UL) /**< \brief (TCC0) Driver Control */ 72 #define REG_TCC0_DBGCTRL (*(RwReg8 *)0x4200141EUL) /**< \brief (TCC0) Debug Control */ 73 #define REG_TCC0_EVCTRL (*(RwReg *)0x42001420UL) /**< \brief (TCC0) Event Control */ 74 #define REG_TCC0_INTENCLR (*(RwReg *)0x42001424UL) /**< \brief (TCC0) Interrupt Enable Clear */ 75 #define REG_TCC0_INTENSET (*(RwReg *)0x42001428UL) /**< \brief (TCC0) Interrupt Enable Set */ 76 #define REG_TCC0_INTFLAG (*(RwReg *)0x4200142CUL) /**< \brief (TCC0) Interrupt Flag Status and Clear */ 77 #define REG_TCC0_STATUS (*(RwReg *)0x42001430UL) /**< \brief (TCC0) Status */ 78 #define REG_TCC0_COUNT (*(RwReg *)0x42001434UL) /**< \brief (TCC0) Count */ 79 #define REG_TCC0_PATT (*(RwReg16*)0x42001438UL) /**< \brief (TCC0) Pattern */ 80 #define REG_TCC0_WAVE (*(RwReg *)0x4200143CUL) /**< \brief (TCC0) Waveform Control */ 81 #define REG_TCC0_PER (*(RwReg *)0x42001440UL) /**< \brief (TCC0) Period */ 82 #define REG_TCC0_CC0 (*(RwReg *)0x42001444UL) /**< \brief (TCC0) Compare and Capture 0 */ 83 #define REG_TCC0_CC1 (*(RwReg *)0x42001448UL) /**< \brief (TCC0) Compare and Capture 1 */ 84 #define REG_TCC0_CC2 (*(RwReg *)0x4200144CUL) /**< \brief (TCC0) Compare and Capture 2 */ 85 #define REG_TCC0_CC3 (*(RwReg *)0x42001450UL) /**< \brief (TCC0) Compare and Capture 3 */ 86 #define REG_TCC0_PATTBUF (*(RwReg16*)0x42001464UL) /**< \brief (TCC0) Pattern Buffer */ 87 #define REG_TCC0_PERBUF (*(RwReg *)0x4200146CUL) /**< \brief (TCC0) Period Buffer */ 88 #define REG_TCC0_CCBUF0 (*(RwReg *)0x42001470UL) /**< \brief (TCC0) Compare and Capture Buffer 0 */ 89 #define REG_TCC0_CCBUF1 (*(RwReg *)0x42001474UL) /**< \brief (TCC0) Compare and Capture Buffer 1 */ 90 #define REG_TCC0_CCBUF2 (*(RwReg *)0x42001478UL) /**< \brief (TCC0) Compare and Capture Buffer 2 */ 91 #define REG_TCC0_CCBUF3 (*(RwReg *)0x4200147CUL) /**< \brief (TCC0) Compare and Capture Buffer 3 */ 92 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 93 94 /* ========== Instance parameters for TCC0 peripheral ========== */ 95 #define TCC0_CC_NUM 4 // Number of Compare/Capture units 96 #define TCC0_DITHERING 1 // Dithering feature implemented 97 #define TCC0_DMAC_ID_MC_0 12 98 #define TCC0_DMAC_ID_MC_1 13 99 #define TCC0_DMAC_ID_MC_2 14 100 #define TCC0_DMAC_ID_MC_3 15 101 #define TCC0_DMAC_ID_MC_LSB 12 102 #define TCC0_DMAC_ID_MC_MSB 15 103 #define TCC0_DMAC_ID_MC_SIZE 4 104 #define TCC0_DMAC_ID_OVF 11 // DMA overflow/underflow/retrigger trigger 105 #define TCC0_DTI 1 // Dead-Time-Insertion feature implemented 106 #define TCC0_EXT 31 // Coding of implemented extended features 107 #define TCC0_GCLK_ID 25 // Index of Generic Clock 108 #define TCC0_OTMX 1 // Output Matrix feature implemented 109 #define TCC0_OW_NUM 8 // Number of Output Waveforms 110 #define TCC0_PG 1 // Pattern Generation feature implemented 111 #define TCC0_SIZE 24 112 #define TCC0_SWAP 1 // DTI outputs swap feature implemented 113 #define TCC0_TYPE 1 // TCC type 0 : NA, 1 : Master, 2 : Slave 114 115 #endif /* _SAMR35_TCC0_INSTANCE_ */ 116
