1 /** 2 * \file 3 * 4 * \brief Component description for PM 5 * 6 * Copyright (c) 2018 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAMR35_PM_COMPONENT_ 31 #define _SAMR35_PM_COMPONENT_ 32 33 /* ========================================================================== */ 34 /** SOFTWARE API DEFINITION FOR PM */ 35 /* ========================================================================== */ 36 /** \addtogroup SAMR35_PM Power Manager */ 37 /*@{*/ 38 39 #define PM_U2240 40 #define REV_PM 0x102 41 42 /* -------- PM_CTRLA : (PM Offset: 0x00) (R/W 8) Control A -------- */ 43 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 44 typedef union { 45 struct { 46 uint8_t :2; /*!< bit: 0.. 1 Reserved */ 47 uint8_t IORET:1; /*!< bit: 2 I/O Retention */ 48 uint8_t :5; /*!< bit: 3.. 7 Reserved */ 49 } bit; /*!< Structure used for bit access */ 50 uint8_t reg; /*!< Type used for register access */ 51 } PM_CTRLA_Type; 52 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 53 54 #define PM_CTRLA_OFFSET 0x00 /**< \brief (PM_CTRLA offset) Control A */ 55 #define PM_CTRLA_RESETVALUE _U_(0x00) /**< \brief (PM_CTRLA reset_value) Control A */ 56 57 #define PM_CTRLA_IORET_Pos 2 /**< \brief (PM_CTRLA) I/O Retention */ 58 #define PM_CTRLA_IORET (_U_(0x1) << PM_CTRLA_IORET_Pos) 59 #define PM_CTRLA_MASK _U_(0x04) /**< \brief (PM_CTRLA) MASK Register */ 60 61 /* -------- PM_SLEEPCFG : (PM Offset: 0x01) (R/W 8) Sleep Configuration -------- */ 62 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 63 typedef union { 64 struct { 65 uint8_t SLEEPMODE:3; /*!< bit: 0.. 2 Sleep Mode */ 66 uint8_t :5; /*!< bit: 3.. 7 Reserved */ 67 } bit; /*!< Structure used for bit access */ 68 uint8_t reg; /*!< Type used for register access */ 69 } PM_SLEEPCFG_Type; 70 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 71 72 #define PM_SLEEPCFG_OFFSET 0x01 /**< \brief (PM_SLEEPCFG offset) Sleep Configuration */ 73 #define PM_SLEEPCFG_RESETVALUE _U_(0x02) /**< \brief (PM_SLEEPCFG reset_value) Sleep Configuration */ 74 75 #define PM_SLEEPCFG_SLEEPMODE_Pos 0 /**< \brief (PM_SLEEPCFG) Sleep Mode */ 76 #define PM_SLEEPCFG_SLEEPMODE_Msk (_U_(0x7) << PM_SLEEPCFG_SLEEPMODE_Pos) 77 #define PM_SLEEPCFG_SLEEPMODE(value) (PM_SLEEPCFG_SLEEPMODE_Msk & ((value) << PM_SLEEPCFG_SLEEPMODE_Pos)) 78 #define PM_SLEEPCFG_SLEEPMODE_IDLE_Val _U_(0x2) /**< \brief (PM_SLEEPCFG) CPU, AHBx, and APBx clocks are OFF */ 79 #define PM_SLEEPCFG_SLEEPMODE_STANDBY_Val _U_(0x4) /**< \brief (PM_SLEEPCFG) All Clocks are OFF */ 80 #define PM_SLEEPCFG_SLEEPMODE_BACKUP_Val _U_(0x5) /**< \brief (PM_SLEEPCFG) Only Backup domain is powered ON */ 81 #define PM_SLEEPCFG_SLEEPMODE_OFF_Val _U_(0x6) /**< \brief (PM_SLEEPCFG) All power domains are powered OFF */ 82 #define PM_SLEEPCFG_SLEEPMODE_IDLE (PM_SLEEPCFG_SLEEPMODE_IDLE_Val << PM_SLEEPCFG_SLEEPMODE_Pos) 83 #define PM_SLEEPCFG_SLEEPMODE_STANDBY (PM_SLEEPCFG_SLEEPMODE_STANDBY_Val << PM_SLEEPCFG_SLEEPMODE_Pos) 84 #define PM_SLEEPCFG_SLEEPMODE_BACKUP (PM_SLEEPCFG_SLEEPMODE_BACKUP_Val << PM_SLEEPCFG_SLEEPMODE_Pos) 85 #define PM_SLEEPCFG_SLEEPMODE_OFF (PM_SLEEPCFG_SLEEPMODE_OFF_Val << PM_SLEEPCFG_SLEEPMODE_Pos) 86 #define PM_SLEEPCFG_MASK _U_(0x07) /**< \brief (PM_SLEEPCFG) MASK Register */ 87 88 /* -------- PM_PLCFG : (PM Offset: 0x02) (R/W 8) Performance Level Configuration -------- */ 89 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 90 typedef union { 91 struct { 92 uint8_t PLSEL:2; /*!< bit: 0.. 1 Performance Level Select */ 93 uint8_t :5; /*!< bit: 2.. 6 Reserved */ 94 uint8_t PLDIS:1; /*!< bit: 7 Performance Level Disable */ 95 } bit; /*!< Structure used for bit access */ 96 uint8_t reg; /*!< Type used for register access */ 97 } PM_PLCFG_Type; 98 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 99 100 #define PM_PLCFG_OFFSET 0x02 /**< \brief (PM_PLCFG offset) Performance Level Configuration */ 101 #define PM_PLCFG_RESETVALUE _U_(0x00) /**< \brief (PM_PLCFG reset_value) Performance Level Configuration */ 102 103 #define PM_PLCFG_PLSEL_Pos 0 /**< \brief (PM_PLCFG) Performance Level Select */ 104 #define PM_PLCFG_PLSEL_Msk (_U_(0x3) << PM_PLCFG_PLSEL_Pos) 105 #define PM_PLCFG_PLSEL(value) (PM_PLCFG_PLSEL_Msk & ((value) << PM_PLCFG_PLSEL_Pos)) 106 #define PM_PLCFG_PLSEL_PL0_Val _U_(0x0) /**< \brief (PM_PLCFG) Performance Level 0 */ 107 #define PM_PLCFG_PLSEL_PL1_Val _U_(0x1) /**< \brief (PM_PLCFG) Performance Level 1 */ 108 #define PM_PLCFG_PLSEL_PL2_Val _U_(0x2) /**< \brief (PM_PLCFG) Performance Level 2 */ 109 #define PM_PLCFG_PLSEL_PL0 (PM_PLCFG_PLSEL_PL0_Val << PM_PLCFG_PLSEL_Pos) 110 #define PM_PLCFG_PLSEL_PL1 (PM_PLCFG_PLSEL_PL1_Val << PM_PLCFG_PLSEL_Pos) 111 #define PM_PLCFG_PLSEL_PL2 (PM_PLCFG_PLSEL_PL2_Val << PM_PLCFG_PLSEL_Pos) 112 #define PM_PLCFG_PLDIS_Pos 7 /**< \brief (PM_PLCFG) Performance Level Disable */ 113 #define PM_PLCFG_PLDIS (_U_(0x1) << PM_PLCFG_PLDIS_Pos) 114 #define PM_PLCFG_MASK _U_(0x83) /**< \brief (PM_PLCFG) MASK Register */ 115 116 /* -------- PM_INTENCLR : (PM Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ 117 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 118 typedef union { 119 struct { 120 uint8_t PLRDY:1; /*!< bit: 0 Performance Level Interrupt Enable */ 121 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 122 } bit; /*!< Structure used for bit access */ 123 uint8_t reg; /*!< Type used for register access */ 124 } PM_INTENCLR_Type; 125 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 126 127 #define PM_INTENCLR_OFFSET 0x04 /**< \brief (PM_INTENCLR offset) Interrupt Enable Clear */ 128 #define PM_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (PM_INTENCLR reset_value) Interrupt Enable Clear */ 129 130 #define PM_INTENCLR_PLRDY_Pos 0 /**< \brief (PM_INTENCLR) Performance Level Interrupt Enable */ 131 #define PM_INTENCLR_PLRDY (_U_(0x1) << PM_INTENCLR_PLRDY_Pos) 132 #define PM_INTENCLR_MASK _U_(0x01) /**< \brief (PM_INTENCLR) MASK Register */ 133 134 /* -------- PM_INTENSET : (PM Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ 135 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 136 typedef union { 137 struct { 138 uint8_t PLRDY:1; /*!< bit: 0 Performance Level Ready interrupt Enable */ 139 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 140 } bit; /*!< Structure used for bit access */ 141 uint8_t reg; /*!< Type used for register access */ 142 } PM_INTENSET_Type; 143 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 144 145 #define PM_INTENSET_OFFSET 0x05 /**< \brief (PM_INTENSET offset) Interrupt Enable Set */ 146 #define PM_INTENSET_RESETVALUE _U_(0x00) /**< \brief (PM_INTENSET reset_value) Interrupt Enable Set */ 147 148 #define PM_INTENSET_PLRDY_Pos 0 /**< \brief (PM_INTENSET) Performance Level Ready interrupt Enable */ 149 #define PM_INTENSET_PLRDY (_U_(0x1) << PM_INTENSET_PLRDY_Pos) 150 #define PM_INTENSET_MASK _U_(0x01) /**< \brief (PM_INTENSET) MASK Register */ 151 152 /* -------- PM_INTFLAG : (PM Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ 153 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 154 typedef union { // __I to avoid read-modify-write on write-to-clear register 155 struct { 156 __I uint8_t PLRDY:1; /*!< bit: 0 Performance Level Ready */ 157 __I uint8_t :7; /*!< bit: 1.. 7 Reserved */ 158 } bit; /*!< Structure used for bit access */ 159 uint8_t reg; /*!< Type used for register access */ 160 } PM_INTFLAG_Type; 161 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 162 163 #define PM_INTFLAG_OFFSET 0x06 /**< \brief (PM_INTFLAG offset) Interrupt Flag Status and Clear */ 164 #define PM_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (PM_INTFLAG reset_value) Interrupt Flag Status and Clear */ 165 166 #define PM_INTFLAG_PLRDY_Pos 0 /**< \brief (PM_INTFLAG) Performance Level Ready */ 167 #define PM_INTFLAG_PLRDY (_U_(0x1) << PM_INTFLAG_PLRDY_Pos) 168 #define PM_INTFLAG_MASK _U_(0x01) /**< \brief (PM_INTFLAG) MASK Register */ 169 170 /* -------- PM_STDBYCFG : (PM Offset: 0x08) (R/W 16) Standby Configuration -------- */ 171 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 172 typedef union { 173 struct { 174 uint16_t PDCFG:2; /*!< bit: 0.. 1 Power Domain Configuration */ 175 uint16_t :2; /*!< bit: 2.. 3 Reserved */ 176 uint16_t DPGPD0:1; /*!< bit: 4 Dynamic Power Gating for PD0 */ 177 uint16_t DPGPD1:1; /*!< bit: 5 Dynamic Power Gating for PD1 */ 178 uint16_t VREGSMOD:2; /*!< bit: 6.. 7 Voltage Regulator Standby mode */ 179 uint16_t LINKPD:2; /*!< bit: 8.. 9 Linked Power Domain */ 180 uint16_t BBIASHS:2; /*!< bit: 10..11 Back Bias for HMCRAMCHS */ 181 uint16_t BBIASLP:2; /*!< bit: 12..13 Back Bias for HMCRAMCLP */ 182 uint16_t BBIASPP:2; /*!< bit: 14..15 Back Bias for PicoPram */ 183 } bit; /*!< Structure used for bit access */ 184 uint16_t reg; /*!< Type used for register access */ 185 } PM_STDBYCFG_Type; 186 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 187 188 #define PM_STDBYCFG_OFFSET 0x08 /**< \brief (PM_STDBYCFG offset) Standby Configuration */ 189 #define PM_STDBYCFG_RESETVALUE _U_(0x0000) /**< \brief (PM_STDBYCFG reset_value) Standby Configuration */ 190 191 #define PM_STDBYCFG_PDCFG_Pos 0 /**< \brief (PM_STDBYCFG) Power Domain Configuration */ 192 #define PM_STDBYCFG_PDCFG_Msk (_U_(0x3) << PM_STDBYCFG_PDCFG_Pos) 193 #define PM_STDBYCFG_PDCFG(value) (PM_STDBYCFG_PDCFG_Msk & ((value) << PM_STDBYCFG_PDCFG_Pos)) 194 #define PM_STDBYCFG_PDCFG_DEFAULT_Val _U_(0x0) /**< \brief (PM_STDBYCFG) All power domains switching is handled by hardware. */ 195 #define PM_STDBYCFG_PDCFG_PD0_Val _U_(0x1) /**< \brief (PM_STDBYCFG) PD0 is forced ACTIVE. PD1 and PD2 power domains switching is handled by hardware. */ 196 #define PM_STDBYCFG_PDCFG_PD01_Val _U_(0x2) /**< \brief (PM_STDBYCFG) PD0 and PD1 are forced ACTIVE. PD2 power domain switching is handled by hardware. */ 197 #define PM_STDBYCFG_PDCFG_PD012_Val _U_(0x3) /**< \brief (PM_STDBYCFG) All power domains are forced ACTIVE. */ 198 #define PM_STDBYCFG_PDCFG_DEFAULT (PM_STDBYCFG_PDCFG_DEFAULT_Val << PM_STDBYCFG_PDCFG_Pos) 199 #define PM_STDBYCFG_PDCFG_PD0 (PM_STDBYCFG_PDCFG_PD0_Val << PM_STDBYCFG_PDCFG_Pos) 200 #define PM_STDBYCFG_PDCFG_PD01 (PM_STDBYCFG_PDCFG_PD01_Val << PM_STDBYCFG_PDCFG_Pos) 201 #define PM_STDBYCFG_PDCFG_PD012 (PM_STDBYCFG_PDCFG_PD012_Val << PM_STDBYCFG_PDCFG_Pos) 202 #define PM_STDBYCFG_DPGPD0_Pos 4 /**< \brief (PM_STDBYCFG) Dynamic Power Gating for PD0 */ 203 #define PM_STDBYCFG_DPGPD0 (_U_(0x1) << PM_STDBYCFG_DPGPD0_Pos) 204 #define PM_STDBYCFG_DPGPD1_Pos 5 /**< \brief (PM_STDBYCFG) Dynamic Power Gating for PD1 */ 205 #define PM_STDBYCFG_DPGPD1 (_U_(0x1) << PM_STDBYCFG_DPGPD1_Pos) 206 #define PM_STDBYCFG_VREGSMOD_Pos 6 /**< \brief (PM_STDBYCFG) Voltage Regulator Standby mode */ 207 #define PM_STDBYCFG_VREGSMOD_Msk (_U_(0x3) << PM_STDBYCFG_VREGSMOD_Pos) 208 #define PM_STDBYCFG_VREGSMOD(value) (PM_STDBYCFG_VREGSMOD_Msk & ((value) << PM_STDBYCFG_VREGSMOD_Pos)) 209 #define PM_STDBYCFG_VREGSMOD_AUTO_Val _U_(0x0) /**< \brief (PM_STDBYCFG) Automatic mode */ 210 #define PM_STDBYCFG_VREGSMOD_PERFORMANCE_Val _U_(0x1) /**< \brief (PM_STDBYCFG) Performance oriented */ 211 #define PM_STDBYCFG_VREGSMOD_LP_Val _U_(0x2) /**< \brief (PM_STDBYCFG) Low Power oriented */ 212 #define PM_STDBYCFG_VREGSMOD_AUTO (PM_STDBYCFG_VREGSMOD_AUTO_Val << PM_STDBYCFG_VREGSMOD_Pos) 213 #define PM_STDBYCFG_VREGSMOD_PERFORMANCE (PM_STDBYCFG_VREGSMOD_PERFORMANCE_Val << PM_STDBYCFG_VREGSMOD_Pos) 214 #define PM_STDBYCFG_VREGSMOD_LP (PM_STDBYCFG_VREGSMOD_LP_Val << PM_STDBYCFG_VREGSMOD_Pos) 215 #define PM_STDBYCFG_LINKPD_Pos 8 /**< \brief (PM_STDBYCFG) Linked Power Domain */ 216 #define PM_STDBYCFG_LINKPD_Msk (_U_(0x3) << PM_STDBYCFG_LINKPD_Pos) 217 #define PM_STDBYCFG_LINKPD(value) (PM_STDBYCFG_LINKPD_Msk & ((value) << PM_STDBYCFG_LINKPD_Pos)) 218 #define PM_STDBYCFG_LINKPD_DEFAULT_Val _U_(0x0) /**< \brief (PM_STDBYCFG) Power domains are not linked */ 219 #define PM_STDBYCFG_LINKPD_PD01_Val _U_(0x1) /**< \brief (PM_STDBYCFG) PD0 and PD1 power domains are linked */ 220 #define PM_STDBYCFG_LINKPD_PD12_Val _U_(0x2) /**< \brief (PM_STDBYCFG) PD1 and PD2 power domains are linked */ 221 #define PM_STDBYCFG_LINKPD_PD012_Val _U_(0x3) /**< \brief (PM_STDBYCFG) All power domains are linked */ 222 #define PM_STDBYCFG_LINKPD_DEFAULT (PM_STDBYCFG_LINKPD_DEFAULT_Val << PM_STDBYCFG_LINKPD_Pos) 223 #define PM_STDBYCFG_LINKPD_PD01 (PM_STDBYCFG_LINKPD_PD01_Val << PM_STDBYCFG_LINKPD_Pos) 224 #define PM_STDBYCFG_LINKPD_PD12 (PM_STDBYCFG_LINKPD_PD12_Val << PM_STDBYCFG_LINKPD_Pos) 225 #define PM_STDBYCFG_LINKPD_PD012 (PM_STDBYCFG_LINKPD_PD012_Val << PM_STDBYCFG_LINKPD_Pos) 226 #define PM_STDBYCFG_BBIASHS_Pos 10 /**< \brief (PM_STDBYCFG) Back Bias for HMCRAMCHS */ 227 #define PM_STDBYCFG_BBIASHS_Msk (_U_(0x3) << PM_STDBYCFG_BBIASHS_Pos) 228 #define PM_STDBYCFG_BBIASHS(value) (PM_STDBYCFG_BBIASHS_Msk & ((value) << PM_STDBYCFG_BBIASHS_Pos)) 229 #define PM_STDBYCFG_BBIASLP_Pos 12 /**< \brief (PM_STDBYCFG) Back Bias for HMCRAMCLP */ 230 #define PM_STDBYCFG_BBIASLP_Msk (_U_(0x3) << PM_STDBYCFG_BBIASLP_Pos) 231 #define PM_STDBYCFG_BBIASLP(value) (PM_STDBYCFG_BBIASLP_Msk & ((value) << PM_STDBYCFG_BBIASLP_Pos)) 232 #define PM_STDBYCFG_BBIASPP_Pos 14 /**< \brief (PM_STDBYCFG) Back Bias for PicoPram */ 233 #define PM_STDBYCFG_BBIASPP_Msk (_U_(0x3) << PM_STDBYCFG_BBIASPP_Pos) 234 #define PM_STDBYCFG_BBIASPP(value) (PM_STDBYCFG_BBIASPP_Msk & ((value) << PM_STDBYCFG_BBIASPP_Pos)) 235 #define PM_STDBYCFG_MASK _U_(0xFFF3) /**< \brief (PM_STDBYCFG) MASK Register */ 236 237 /* -------- PM_PWSAKDLY : (PM Offset: 0x0C) (R/W 8) Power Switch Acknowledge Delay -------- */ 238 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 239 typedef union { 240 struct { 241 uint8_t DLYVAL:7; /*!< bit: 0.. 6 Delay Value */ 242 uint8_t IGNACK:1; /*!< bit: 7 Ignore Acknowledge */ 243 } bit; /*!< Structure used for bit access */ 244 uint8_t reg; /*!< Type used for register access */ 245 } PM_PWSAKDLY_Type; 246 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 247 248 #define PM_PWSAKDLY_OFFSET 0x0C /**< \brief (PM_PWSAKDLY offset) Power Switch Acknowledge Delay */ 249 #define PM_PWSAKDLY_RESETVALUE _U_(0x00) /**< \brief (PM_PWSAKDLY reset_value) Power Switch Acknowledge Delay */ 250 251 #define PM_PWSAKDLY_DLYVAL_Pos 0 /**< \brief (PM_PWSAKDLY) Delay Value */ 252 #define PM_PWSAKDLY_DLYVAL_Msk (_U_(0x7F) << PM_PWSAKDLY_DLYVAL_Pos) 253 #define PM_PWSAKDLY_DLYVAL(value) (PM_PWSAKDLY_DLYVAL_Msk & ((value) << PM_PWSAKDLY_DLYVAL_Pos)) 254 #define PM_PWSAKDLY_IGNACK_Pos 7 /**< \brief (PM_PWSAKDLY) Ignore Acknowledge */ 255 #define PM_PWSAKDLY_IGNACK (_U_(0x1) << PM_PWSAKDLY_IGNACK_Pos) 256 #define PM_PWSAKDLY_MASK _U_(0xFF) /**< \brief (PM_PWSAKDLY) MASK Register */ 257 258 /** \brief PM hardware registers */ 259 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 260 typedef struct { 261 __IO PM_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ 262 __IO PM_SLEEPCFG_Type SLEEPCFG; /**< \brief Offset: 0x01 (R/W 8) Sleep Configuration */ 263 __IO PM_PLCFG_Type PLCFG; /**< \brief Offset: 0x02 (R/W 8) Performance Level Configuration */ 264 RoReg8 Reserved1[0x1]; 265 __IO PM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */ 266 __IO PM_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */ 267 __IO PM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ 268 RoReg8 Reserved2[0x1]; 269 __IO PM_STDBYCFG_Type STDBYCFG; /**< \brief Offset: 0x08 (R/W 16) Standby Configuration */ 270 RoReg8 Reserved3[0x2]; 271 __IO PM_PWSAKDLY_Type PWSAKDLY; /**< \brief Offset: 0x0C (R/W 8) Power Switch Acknowledge Delay */ 272 } Pm; 273 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 274 275 /*@}*/ 276 277 #endif /* _SAMR35_PM_COMPONENT_ */ 278
