1 /** 2 * \file 3 * 4 * \brief Instance description for DAC 5 * 6 * Copyright (c) 2018 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAMR34_DAC_INSTANCE_ 31 #define _SAMR34_DAC_INSTANCE_ 32 33 /* ========== Register definition for DAC peripheral ========== */ 34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 35 #define REG_DAC_CTRLA (0x42003000) /**< \brief (DAC) Control A */ 36 #define REG_DAC_CTRLB (0x42003001) /**< \brief (DAC) Control B */ 37 #define REG_DAC_EVCTRL (0x42003002) /**< \brief (DAC) Event Control */ 38 #define REG_DAC_INTENCLR (0x42003004) /**< \brief (DAC) Interrupt Enable Clear */ 39 #define REG_DAC_INTENSET (0x42003005) /**< \brief (DAC) Interrupt Enable Set */ 40 #define REG_DAC_INTFLAG (0x42003006) /**< \brief (DAC) Interrupt Flag Status and Clear */ 41 #define REG_DAC_STATUS (0x42003007) /**< \brief (DAC) Status */ 42 #define REG_DAC_SYNCBUSY (0x42003008) /**< \brief (DAC) Synchronization Busy */ 43 #define REG_DAC_DACCTRL0 (0x4200300C) /**< \brief (DAC) DAC 0 Control */ 44 #define REG_DAC_DACCTRL1 (0x4200300E) /**< \brief (DAC) DAC 1 Control */ 45 #define REG_DAC_DATA0 (0x42003010) /**< \brief (DAC) DAC 0 Data */ 46 #define REG_DAC_DATA1 (0x42003012) /**< \brief (DAC) DAC 1 Data */ 47 #define REG_DAC_DATABUF0 (0x42003014) /**< \brief (DAC) DAC 0 Data Buffer */ 48 #define REG_DAC_DATABUF1 (0x42003016) /**< \brief (DAC) DAC 1 Data Buffer */ 49 #define REG_DAC_DBGCTRL (0x42003018) /**< \brief (DAC) Debug Control */ 50 #else 51 #define REG_DAC_CTRLA (*(RwReg8 *)0x42003000UL) /**< \brief (DAC) Control A */ 52 #define REG_DAC_CTRLB (*(RwReg8 *)0x42003001UL) /**< \brief (DAC) Control B */ 53 #define REG_DAC_EVCTRL (*(RwReg8 *)0x42003002UL) /**< \brief (DAC) Event Control */ 54 #define REG_DAC_INTENCLR (*(RwReg8 *)0x42003004UL) /**< \brief (DAC) Interrupt Enable Clear */ 55 #define REG_DAC_INTENSET (*(RwReg8 *)0x42003005UL) /**< \brief (DAC) Interrupt Enable Set */ 56 #define REG_DAC_INTFLAG (*(RwReg8 *)0x42003006UL) /**< \brief (DAC) Interrupt Flag Status and Clear */ 57 #define REG_DAC_STATUS (*(RoReg8 *)0x42003007UL) /**< \brief (DAC) Status */ 58 #define REG_DAC_SYNCBUSY (*(RoReg *)0x42003008UL) /**< \brief (DAC) Synchronization Busy */ 59 #define REG_DAC_DACCTRL0 (*(RwReg16*)0x4200300CUL) /**< \brief (DAC) DAC 0 Control */ 60 #define REG_DAC_DACCTRL1 (*(RwReg16*)0x4200300EUL) /**< \brief (DAC) DAC 1 Control */ 61 #define REG_DAC_DATA0 (*(WoReg16*)0x42003010UL) /**< \brief (DAC) DAC 0 Data */ 62 #define REG_DAC_DATA1 (*(WoReg16*)0x42003012UL) /**< \brief (DAC) DAC 1 Data */ 63 #define REG_DAC_DATABUF0 (*(WoReg16*)0x42003014UL) /**< \brief (DAC) DAC 0 Data Buffer */ 64 #define REG_DAC_DATABUF1 (*(WoReg16*)0x42003016UL) /**< \brief (DAC) DAC 1 Data Buffer */ 65 #define REG_DAC_DBGCTRL (*(RwReg8 *)0x42003018UL) /**< \brief (DAC) Debug Control */ 66 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 67 68 /* ========== Instance parameters for DAC peripheral ========== */ 69 #define DAC_DAC_NUM 2 // Number of DACs 70 #define DAC_DATA_SIZE 12 // Number of bits in data 71 #define DAC_DMAC_ID_EMPTY_0 38 72 #define DAC_DMAC_ID_EMPTY_1 39 73 #define DAC_DMAC_ID_EMPTY_LSB 38 74 #define DAC_DMAC_ID_EMPTY_MSB 39 75 #define DAC_DMAC_ID_EMPTY_SIZE 2 76 #define DAC_GCLK_ID 32 // Index of Generic Clock 77 78 #endif /* _SAMR34_DAC_INSTANCE_ */ 79
