1 /** 2 * \file 3 * 4 * \brief Component description for AES 5 * 6 * Copyright (c) 2018 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAMR34_AES_COMPONENT_ 31 #define _SAMR34_AES_COMPONENT_ 32 33 /* ========================================================================== */ 34 /** SOFTWARE API DEFINITION FOR AES */ 35 /* ========================================================================== */ 36 /** \addtogroup SAMR34_AES Advanced Encryption Standard */ 37 /*@{*/ 38 39 #define AES_U2238 40 #define REV_AES 0x200 41 42 /* -------- AES_CTRLA : (AES Offset: 0x00) (R/W 32) Control A -------- */ 43 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 44 typedef union { 45 struct { 46 uint32_t SWRST:1; /*!< bit: 0 Software Reset */ 47 uint32_t ENABLE:1; /*!< bit: 1 Enable */ 48 uint32_t AESMODE:3; /*!< bit: 2.. 4 AES Modes of operation */ 49 uint32_t CFBS:3; /*!< bit: 5.. 7 CFB Types */ 50 uint32_t KEYSIZE:2; /*!< bit: 8.. 9 Keysize */ 51 uint32_t CIPHER:1; /*!< bit: 10 Cipher mode */ 52 uint32_t STARTMODE:1; /*!< bit: 11 Start mode */ 53 uint32_t LOD:1; /*!< bit: 12 LOD Enable */ 54 uint32_t KEYGEN:1; /*!< bit: 13 Last key generation */ 55 uint32_t XORKEY:1; /*!< bit: 14 Xor Key operation */ 56 uint32_t :1; /*!< bit: 15 Reserved */ 57 uint32_t CTYPE:4; /*!< bit: 16..19 Counter measure types */ 58 uint32_t :12; /*!< bit: 20..31 Reserved */ 59 } bit; /*!< Structure used for bit access */ 60 uint32_t reg; /*!< Type used for register access */ 61 } AES_CTRLA_Type; 62 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 63 64 #define AES_CTRLA_OFFSET 0x00 /**< \brief (AES_CTRLA offset) Control A */ 65 #define AES_CTRLA_RESETVALUE _U_(0x00000000) /**< \brief (AES_CTRLA reset_value) Control A */ 66 67 #define AES_CTRLA_SWRST_Pos 0 /**< \brief (AES_CTRLA) Software Reset */ 68 #define AES_CTRLA_SWRST (_U_(0x1) << AES_CTRLA_SWRST_Pos) 69 #define AES_CTRLA_ENABLE_Pos 1 /**< \brief (AES_CTRLA) Enable */ 70 #define AES_CTRLA_ENABLE (_U_(0x1) << AES_CTRLA_ENABLE_Pos) 71 #define AES_CTRLA_AESMODE_Pos 2 /**< \brief (AES_CTRLA) AES Modes of operation */ 72 #define AES_CTRLA_AESMODE_Msk (_U_(0x7) << AES_CTRLA_AESMODE_Pos) 73 #define AES_CTRLA_AESMODE(value) (AES_CTRLA_AESMODE_Msk & ((value) << AES_CTRLA_AESMODE_Pos)) 74 #define AES_CTRLA_CFBS_Pos 5 /**< \brief (AES_CTRLA) CFB Types */ 75 #define AES_CTRLA_CFBS_Msk (_U_(0x7) << AES_CTRLA_CFBS_Pos) 76 #define AES_CTRLA_CFBS(value) (AES_CTRLA_CFBS_Msk & ((value) << AES_CTRLA_CFBS_Pos)) 77 #define AES_CTRLA_KEYSIZE_Pos 8 /**< \brief (AES_CTRLA) Keysize */ 78 #define AES_CTRLA_KEYSIZE_Msk (_U_(0x3) << AES_CTRLA_KEYSIZE_Pos) 79 #define AES_CTRLA_KEYSIZE(value) (AES_CTRLA_KEYSIZE_Msk & ((value) << AES_CTRLA_KEYSIZE_Pos)) 80 #define AES_CTRLA_CIPHER_Pos 10 /**< \brief (AES_CTRLA) Cipher mode */ 81 #define AES_CTRLA_CIPHER (_U_(0x1) << AES_CTRLA_CIPHER_Pos) 82 #define AES_CTRLA_STARTMODE_Pos 11 /**< \brief (AES_CTRLA) Start mode */ 83 #define AES_CTRLA_STARTMODE (_U_(0x1) << AES_CTRLA_STARTMODE_Pos) 84 #define AES_CTRLA_LOD_Pos 12 /**< \brief (AES_CTRLA) LOD Enable */ 85 #define AES_CTRLA_LOD (_U_(0x1) << AES_CTRLA_LOD_Pos) 86 #define AES_CTRLA_KEYGEN_Pos 13 /**< \brief (AES_CTRLA) Last key generation */ 87 #define AES_CTRLA_KEYGEN (_U_(0x1) << AES_CTRLA_KEYGEN_Pos) 88 #define AES_CTRLA_XORKEY_Pos 14 /**< \brief (AES_CTRLA) Xor Key operation */ 89 #define AES_CTRLA_XORKEY (_U_(0x1) << AES_CTRLA_XORKEY_Pos) 90 #define AES_CTRLA_CTYPE_Pos 16 /**< \brief (AES_CTRLA) Counter measure types */ 91 #define AES_CTRLA_CTYPE_Msk (_U_(0xF) << AES_CTRLA_CTYPE_Pos) 92 #define AES_CTRLA_CTYPE(value) (AES_CTRLA_CTYPE_Msk & ((value) << AES_CTRLA_CTYPE_Pos)) 93 #define AES_CTRLA_MASK _U_(0x000F7FFF) /**< \brief (AES_CTRLA) MASK Register */ 94 95 /* -------- AES_CTRLB : (AES Offset: 0x04) (R/W 8) Control B -------- */ 96 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 97 typedef union { 98 struct { 99 uint8_t START:1; /*!< bit: 0 Manual Start */ 100 uint8_t NEWMSG:1; /*!< bit: 1 New message */ 101 uint8_t EOM:1; /*!< bit: 2 End of message */ 102 uint8_t GFMUL:1; /*!< bit: 3 GF Multiplication */ 103 uint8_t :4; /*!< bit: 4.. 7 Reserved */ 104 } bit; /*!< Structure used for bit access */ 105 uint8_t reg; /*!< Type used for register access */ 106 } AES_CTRLB_Type; 107 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 108 109 #define AES_CTRLB_OFFSET 0x04 /**< \brief (AES_CTRLB offset) Control B */ 110 #define AES_CTRLB_RESETVALUE _U_(0x00) /**< \brief (AES_CTRLB reset_value) Control B */ 111 112 #define AES_CTRLB_START_Pos 0 /**< \brief (AES_CTRLB) Manual Start */ 113 #define AES_CTRLB_START (_U_(0x1) << AES_CTRLB_START_Pos) 114 #define AES_CTRLB_NEWMSG_Pos 1 /**< \brief (AES_CTRLB) New message */ 115 #define AES_CTRLB_NEWMSG (_U_(0x1) << AES_CTRLB_NEWMSG_Pos) 116 #define AES_CTRLB_EOM_Pos 2 /**< \brief (AES_CTRLB) End of message */ 117 #define AES_CTRLB_EOM (_U_(0x1) << AES_CTRLB_EOM_Pos) 118 #define AES_CTRLB_GFMUL_Pos 3 /**< \brief (AES_CTRLB) GF Multiplication */ 119 #define AES_CTRLB_GFMUL (_U_(0x1) << AES_CTRLB_GFMUL_Pos) 120 #define AES_CTRLB_MASK _U_(0x0F) /**< \brief (AES_CTRLB) MASK Register */ 121 122 /* -------- AES_INTENCLR : (AES Offset: 0x05) (R/W 8) Interrupt Enable Clear -------- */ 123 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 124 typedef union { 125 struct { 126 uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete */ 127 uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete */ 128 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 129 } bit; /*!< Structure used for bit access */ 130 uint8_t reg; /*!< Type used for register access */ 131 } AES_INTENCLR_Type; 132 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 133 134 #define AES_INTENCLR_OFFSET 0x05 /**< \brief (AES_INTENCLR offset) Interrupt Enable Clear */ 135 #define AES_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (AES_INTENCLR reset_value) Interrupt Enable Clear */ 136 137 #define AES_INTENCLR_ENCCMP_Pos 0 /**< \brief (AES_INTENCLR) Encryption Complete */ 138 #define AES_INTENCLR_ENCCMP (_U_(0x1) << AES_INTENCLR_ENCCMP_Pos) 139 #define AES_INTENCLR_GFMCMP_Pos 1 /**< \brief (AES_INTENCLR) GF Multiplication Complete */ 140 #define AES_INTENCLR_GFMCMP (_U_(0x1) << AES_INTENCLR_GFMCMP_Pos) 141 #define AES_INTENCLR_MASK _U_(0x03) /**< \brief (AES_INTENCLR) MASK Register */ 142 143 /* -------- AES_INTENSET : (AES Offset: 0x06) (R/W 8) Interrupt Enable Set -------- */ 144 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 145 typedef union { 146 struct { 147 uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete */ 148 uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete */ 149 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 150 } bit; /*!< Structure used for bit access */ 151 uint8_t reg; /*!< Type used for register access */ 152 } AES_INTENSET_Type; 153 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 154 155 #define AES_INTENSET_OFFSET 0x06 /**< \brief (AES_INTENSET offset) Interrupt Enable Set */ 156 #define AES_INTENSET_RESETVALUE _U_(0x00) /**< \brief (AES_INTENSET reset_value) Interrupt Enable Set */ 157 158 #define AES_INTENSET_ENCCMP_Pos 0 /**< \brief (AES_INTENSET) Encryption Complete */ 159 #define AES_INTENSET_ENCCMP (_U_(0x1) << AES_INTENSET_ENCCMP_Pos) 160 #define AES_INTENSET_GFMCMP_Pos 1 /**< \brief (AES_INTENSET) GF Multiplication Complete */ 161 #define AES_INTENSET_GFMCMP (_U_(0x1) << AES_INTENSET_GFMCMP_Pos) 162 #define AES_INTENSET_MASK _U_(0x03) /**< \brief (AES_INTENSET) MASK Register */ 163 164 /* -------- AES_INTFLAG : (AES Offset: 0x07) (R/W 8) Interrupt Flag Status -------- */ 165 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 166 typedef union { // __I to avoid read-modify-write on write-to-clear register 167 struct { 168 __I uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete */ 169 __I uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete */ 170 __I uint8_t :6; /*!< bit: 2.. 7 Reserved */ 171 } bit; /*!< Structure used for bit access */ 172 uint8_t reg; /*!< Type used for register access */ 173 } AES_INTFLAG_Type; 174 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 175 176 #define AES_INTFLAG_OFFSET 0x07 /**< \brief (AES_INTFLAG offset) Interrupt Flag Status */ 177 #define AES_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (AES_INTFLAG reset_value) Interrupt Flag Status */ 178 179 #define AES_INTFLAG_ENCCMP_Pos 0 /**< \brief (AES_INTFLAG) Encryption Complete */ 180 #define AES_INTFLAG_ENCCMP (_U_(0x1) << AES_INTFLAG_ENCCMP_Pos) 181 #define AES_INTFLAG_GFMCMP_Pos 1 /**< \brief (AES_INTFLAG) GF Multiplication Complete */ 182 #define AES_INTFLAG_GFMCMP (_U_(0x1) << AES_INTFLAG_GFMCMP_Pos) 183 #define AES_INTFLAG_MASK _U_(0x03) /**< \brief (AES_INTFLAG) MASK Register */ 184 185 /* -------- AES_DATABUFPTR : (AES Offset: 0x08) (R/W 8) Data buffer pointer -------- */ 186 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 187 typedef union { 188 struct { 189 uint8_t INDATAPTR:2; /*!< bit: 0.. 1 Input Data Pointer */ 190 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 191 } bit; /*!< Structure used for bit access */ 192 uint8_t reg; /*!< Type used for register access */ 193 } AES_DATABUFPTR_Type; 194 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 195 196 #define AES_DATABUFPTR_OFFSET 0x08 /**< \brief (AES_DATABUFPTR offset) Data buffer pointer */ 197 #define AES_DATABUFPTR_RESETVALUE _U_(0x00) /**< \brief (AES_DATABUFPTR reset_value) Data buffer pointer */ 198 199 #define AES_DATABUFPTR_INDATAPTR_Pos 0 /**< \brief (AES_DATABUFPTR) Input Data Pointer */ 200 #define AES_DATABUFPTR_INDATAPTR_Msk (_U_(0x3) << AES_DATABUFPTR_INDATAPTR_Pos) 201 #define AES_DATABUFPTR_INDATAPTR(value) (AES_DATABUFPTR_INDATAPTR_Msk & ((value) << AES_DATABUFPTR_INDATAPTR_Pos)) 202 #define AES_DATABUFPTR_MASK _U_(0x03) /**< \brief (AES_DATABUFPTR) MASK Register */ 203 204 /* -------- AES_DBGCTRL : (AES Offset: 0x09) ( /W 8) Debug control -------- */ 205 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 206 typedef union { 207 struct { 208 uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ 209 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 210 } bit; /*!< Structure used for bit access */ 211 uint8_t reg; /*!< Type used for register access */ 212 } AES_DBGCTRL_Type; 213 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 214 215 #define AES_DBGCTRL_OFFSET 0x09 /**< \brief (AES_DBGCTRL offset) Debug control */ 216 #define AES_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (AES_DBGCTRL reset_value) Debug control */ 217 218 #define AES_DBGCTRL_DBGRUN_Pos 0 /**< \brief (AES_DBGCTRL) Debug Run */ 219 #define AES_DBGCTRL_DBGRUN (_U_(0x1) << AES_DBGCTRL_DBGRUN_Pos) 220 #define AES_DBGCTRL_MASK _U_(0x01) /**< \brief (AES_DBGCTRL) MASK Register */ 221 222 /* -------- AES_KEYWORD : (AES Offset: 0x0C) ( /W 32) Keyword n -------- */ 223 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 224 typedef union { 225 uint32_t reg; /*!< Type used for register access */ 226 } AES_KEYWORD_Type; 227 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 228 229 #define AES_KEYWORD_OFFSET 0x0C /**< \brief (AES_KEYWORD offset) Keyword n */ 230 #define AES_KEYWORD_RESETVALUE _U_(0x00000000) /**< \brief (AES_KEYWORD reset_value) Keyword n */ 231 #define AES_KEYWORD_MASK _U_(0xFFFFFFFF) /**< \brief (AES_KEYWORD) MASK Register */ 232 233 /* -------- AES_INDATA : (AES Offset: 0x38) (R/W 32) Indata -------- */ 234 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 235 typedef union { 236 uint32_t reg; /*!< Type used for register access */ 237 } AES_INDATA_Type; 238 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 239 240 #define AES_INDATA_OFFSET 0x38 /**< \brief (AES_INDATA offset) Indata */ 241 #define AES_INDATA_RESETVALUE _U_(0x00000000) /**< \brief (AES_INDATA reset_value) Indata */ 242 #define AES_INDATA_MASK _U_(0xFFFFFFFF) /**< \brief (AES_INDATA) MASK Register */ 243 244 /* -------- AES_INTVECTV : (AES Offset: 0x3C) ( /W 32) Initialisation Vector n -------- */ 245 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 246 typedef union { 247 uint32_t reg; /*!< Type used for register access */ 248 } AES_INTVECTV_Type; 249 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 250 251 #define AES_INTVECTV_OFFSET 0x3C /**< \brief (AES_INTVECTV offset) Initialisation Vector n */ 252 #define AES_INTVECTV_RESETVALUE _U_(0x00000000) /**< \brief (AES_INTVECTV reset_value) Initialisation Vector n */ 253 #define AES_INTVECTV_MASK _U_(0xFFFFFFFF) /**< \brief (AES_INTVECTV) MASK Register */ 254 255 /* -------- AES_HASHKEY : (AES Offset: 0x5C) (R/W 32) Hash key n -------- */ 256 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 257 typedef union { 258 uint32_t reg; /*!< Type used for register access */ 259 } AES_HASHKEY_Type; 260 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 261 262 #define AES_HASHKEY_OFFSET 0x5C /**< \brief (AES_HASHKEY offset) Hash key n */ 263 #define AES_HASHKEY_RESETVALUE _U_(0x00000000) /**< \brief (AES_HASHKEY reset_value) Hash key n */ 264 #define AES_HASHKEY_MASK _U_(0xFFFFFFFF) /**< \brief (AES_HASHKEY) MASK Register */ 265 266 /* -------- AES_GHASH : (AES Offset: 0x6C) (R/W 32) Galois Hash n -------- */ 267 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 268 typedef union { 269 uint32_t reg; /*!< Type used for register access */ 270 } AES_GHASH_Type; 271 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 272 273 #define AES_GHASH_OFFSET 0x6C /**< \brief (AES_GHASH offset) Galois Hash n */ 274 #define AES_GHASH_RESETVALUE _U_(0x00000000) /**< \brief (AES_GHASH reset_value) Galois Hash n */ 275 #define AES_GHASH_MASK _U_(0xFFFFFFFF) /**< \brief (AES_GHASH) MASK Register */ 276 277 /* -------- AES_CIPLEN : (AES Offset: 0x80) (R/W 32) Cipher Length -------- */ 278 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 279 typedef union { 280 uint32_t reg; /*!< Type used for register access */ 281 } AES_CIPLEN_Type; 282 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 283 284 #define AES_CIPLEN_OFFSET 0x80 /**< \brief (AES_CIPLEN offset) Cipher Length */ 285 #define AES_CIPLEN_RESETVALUE _U_(0x00000000) /**< \brief (AES_CIPLEN reset_value) Cipher Length */ 286 #define AES_CIPLEN_MASK _U_(0xFFFFFFFF) /**< \brief (AES_CIPLEN) MASK Register */ 287 288 /* -------- AES_RANDSEED : (AES Offset: 0x84) (R/W 32) Random Seed -------- */ 289 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 290 typedef union { 291 uint32_t reg; /*!< Type used for register access */ 292 } AES_RANDSEED_Type; 293 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 294 295 #define AES_RANDSEED_OFFSET 0x84 /**< \brief (AES_RANDSEED offset) Random Seed */ 296 #define AES_RANDSEED_RESETVALUE _U_(0x00000000) /**< \brief (AES_RANDSEED reset_value) Random Seed */ 297 #define AES_RANDSEED_MASK _U_(0xFFFFFFFF) /**< \brief (AES_RANDSEED) MASK Register */ 298 299 /** \brief AES hardware registers */ 300 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 301 typedef struct { 302 __IO AES_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */ 303 __IO AES_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 8) Control B */ 304 __IO AES_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Clear */ 305 __IO AES_INTENSET_Type INTENSET; /**< \brief Offset: 0x06 (R/W 8) Interrupt Enable Set */ 306 __IO AES_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x07 (R/W 8) Interrupt Flag Status */ 307 __IO AES_DATABUFPTR_Type DATABUFPTR; /**< \brief Offset: 0x08 (R/W 8) Data buffer pointer */ 308 __O AES_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x09 ( /W 8) Debug control */ 309 RoReg8 Reserved1[0x2]; 310 __O AES_KEYWORD_Type KEYWORD[8]; /**< \brief Offset: 0x0C ( /W 32) Keyword n */ 311 RoReg8 Reserved2[0xC]; 312 __IO AES_INDATA_Type INDATA; /**< \brief Offset: 0x38 (R/W 32) Indata */ 313 __O AES_INTVECTV_Type INTVECTV[4]; /**< \brief Offset: 0x3C ( /W 32) Initialisation Vector n */ 314 RoReg8 Reserved3[0x10]; 315 __IO AES_HASHKEY_Type HASHKEY[4]; /**< \brief Offset: 0x5C (R/W 32) Hash key n */ 316 __IO AES_GHASH_Type GHASH[4]; /**< \brief Offset: 0x6C (R/W 32) Galois Hash n */ 317 RoReg8 Reserved4[0x4]; 318 __IO AES_CIPLEN_Type CIPLEN; /**< \brief Offset: 0x80 (R/W 32) Cipher Length */ 319 __IO AES_RANDSEED_Type RANDSEED; /**< \brief Offset: 0x84 (R/W 32) Random Seed */ 320 } Aes; 321 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 322 323 /*@}*/ 324 325 #endif /* _SAMR34_AES_COMPONENT_ */ 326
