1 /** 2 * \file 3 * 4 * \brief Component description for USB 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAMR21_USB_COMPONENT_ 30 #define _SAMR21_USB_COMPONENT_ 31 32 /* ========================================================================== */ 33 /** SOFTWARE API DEFINITION FOR USB */ 34 /* ========================================================================== */ 35 /** \addtogroup SAMR21_USB Universal Serial Bus */ 36 /*@{*/ 37 38 #define USB_U2222 39 #define REV_USB 0x101 40 41 /* -------- USB_CTRLA : (USB Offset: 0x000) (R/W 8) Control A -------- */ 42 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 43 typedef union { 44 struct { 45 uint8_t SWRST:1; /*!< bit: 0 Software Reset */ 46 uint8_t ENABLE:1; /*!< bit: 1 Enable */ 47 uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby Mode */ 48 uint8_t :4; /*!< bit: 3.. 6 Reserved */ 49 uint8_t MODE:1; /*!< bit: 7 Operating Mode */ 50 } bit; /*!< Structure used for bit access */ 51 uint8_t reg; /*!< Type used for register access */ 52 } USB_CTRLA_Type; 53 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 54 55 #define USB_CTRLA_OFFSET 0x000 /**< \brief (USB_CTRLA offset) Control A */ 56 #define USB_CTRLA_RESETVALUE _U_(0x00) /**< \brief (USB_CTRLA reset_value) Control A */ 57 58 #define USB_CTRLA_SWRST_Pos 0 /**< \brief (USB_CTRLA) Software Reset */ 59 #define USB_CTRLA_SWRST (_U_(0x1) << USB_CTRLA_SWRST_Pos) 60 #define USB_CTRLA_ENABLE_Pos 1 /**< \brief (USB_CTRLA) Enable */ 61 #define USB_CTRLA_ENABLE (_U_(0x1) << USB_CTRLA_ENABLE_Pos) 62 #define USB_CTRLA_RUNSTDBY_Pos 2 /**< \brief (USB_CTRLA) Run in Standby Mode */ 63 #define USB_CTRLA_RUNSTDBY (_U_(0x1) << USB_CTRLA_RUNSTDBY_Pos) 64 #define USB_CTRLA_MODE_Pos 7 /**< \brief (USB_CTRLA) Operating Mode */ 65 #define USB_CTRLA_MODE (_U_(0x1) << USB_CTRLA_MODE_Pos) 66 #define USB_CTRLA_MODE_DEVICE_Val _U_(0x0) /**< \brief (USB_CTRLA) Device Mode */ 67 #define USB_CTRLA_MODE_HOST_Val _U_(0x1) /**< \brief (USB_CTRLA) Host Mode */ 68 #define USB_CTRLA_MODE_DEVICE (USB_CTRLA_MODE_DEVICE_Val << USB_CTRLA_MODE_Pos) 69 #define USB_CTRLA_MODE_HOST (USB_CTRLA_MODE_HOST_Val << USB_CTRLA_MODE_Pos) 70 #define USB_CTRLA_MASK _U_(0x87) /**< \brief (USB_CTRLA) MASK Register */ 71 72 /* -------- USB_SYNCBUSY : (USB Offset: 0x002) (R/ 8) Synchronization Busy -------- */ 73 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 74 typedef union { 75 struct { 76 uint8_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ 77 uint8_t ENABLE:1; /*!< bit: 1 Enable Synchronization Busy */ 78 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 79 } bit; /*!< Structure used for bit access */ 80 uint8_t reg; /*!< Type used for register access */ 81 } USB_SYNCBUSY_Type; 82 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 83 84 #define USB_SYNCBUSY_OFFSET 0x002 /**< \brief (USB_SYNCBUSY offset) Synchronization Busy */ 85 #define USB_SYNCBUSY_RESETVALUE _U_(0x00) /**< \brief (USB_SYNCBUSY reset_value) Synchronization Busy */ 86 87 #define USB_SYNCBUSY_SWRST_Pos 0 /**< \brief (USB_SYNCBUSY) Software Reset Synchronization Busy */ 88 #define USB_SYNCBUSY_SWRST (_U_(0x1) << USB_SYNCBUSY_SWRST_Pos) 89 #define USB_SYNCBUSY_ENABLE_Pos 1 /**< \brief (USB_SYNCBUSY) Enable Synchronization Busy */ 90 #define USB_SYNCBUSY_ENABLE (_U_(0x1) << USB_SYNCBUSY_ENABLE_Pos) 91 #define USB_SYNCBUSY_MASK _U_(0x03) /**< \brief (USB_SYNCBUSY) MASK Register */ 92 93 /* -------- USB_QOSCTRL : (USB Offset: 0x003) (R/W 8) USB Quality Of Service -------- */ 94 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 95 typedef union { 96 struct { 97 uint8_t CQOS:2; /*!< bit: 0.. 1 Configuration Quality of Service */ 98 uint8_t DQOS:2; /*!< bit: 2.. 3 Data Quality of Service */ 99 uint8_t :4; /*!< bit: 4.. 7 Reserved */ 100 } bit; /*!< Structure used for bit access */ 101 uint8_t reg; /*!< Type used for register access */ 102 } USB_QOSCTRL_Type; 103 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 104 105 #define USB_QOSCTRL_OFFSET 0x003 /**< \brief (USB_QOSCTRL offset) USB Quality Of Service */ 106 #define USB_QOSCTRL_RESETVALUE _U_(0x05) /**< \brief (USB_QOSCTRL reset_value) USB Quality Of Service */ 107 108 #define USB_QOSCTRL_CQOS_Pos 0 /**< \brief (USB_QOSCTRL) Configuration Quality of Service */ 109 #define USB_QOSCTRL_CQOS_Msk (_U_(0x3) << USB_QOSCTRL_CQOS_Pos) 110 #define USB_QOSCTRL_CQOS(value) (USB_QOSCTRL_CQOS_Msk & ((value) << USB_QOSCTRL_CQOS_Pos)) 111 #define USB_QOSCTRL_CQOS_DISABLE_Val _U_(0x0) /**< \brief (USB_QOSCTRL) Background (no sensitive operation) */ 112 #define USB_QOSCTRL_CQOS_LOW_Val _U_(0x1) /**< \brief (USB_QOSCTRL) Sensitive Bandwidth */ 113 #define USB_QOSCTRL_CQOS_MEDIUM_Val _U_(0x2) /**< \brief (USB_QOSCTRL) Sensitive Latency */ 114 #define USB_QOSCTRL_CQOS_HIGH_Val _U_(0x3) /**< \brief (USB_QOSCTRL) Critical Latency */ 115 #define USB_QOSCTRL_CQOS_DISABLE (USB_QOSCTRL_CQOS_DISABLE_Val << USB_QOSCTRL_CQOS_Pos) 116 #define USB_QOSCTRL_CQOS_LOW (USB_QOSCTRL_CQOS_LOW_Val << USB_QOSCTRL_CQOS_Pos) 117 #define USB_QOSCTRL_CQOS_MEDIUM (USB_QOSCTRL_CQOS_MEDIUM_Val << USB_QOSCTRL_CQOS_Pos) 118 #define USB_QOSCTRL_CQOS_HIGH (USB_QOSCTRL_CQOS_HIGH_Val << USB_QOSCTRL_CQOS_Pos) 119 #define USB_QOSCTRL_DQOS_Pos 2 /**< \brief (USB_QOSCTRL) Data Quality of Service */ 120 #define USB_QOSCTRL_DQOS_Msk (_U_(0x3) << USB_QOSCTRL_DQOS_Pos) 121 #define USB_QOSCTRL_DQOS(value) (USB_QOSCTRL_DQOS_Msk & ((value) << USB_QOSCTRL_DQOS_Pos)) 122 #define USB_QOSCTRL_DQOS_DISABLE_Val _U_(0x0) /**< \brief (USB_QOSCTRL) Background (no sensitive operation) */ 123 #define USB_QOSCTRL_DQOS_LOW_Val _U_(0x1) /**< \brief (USB_QOSCTRL) Sensitive Bandwidth */ 124 #define USB_QOSCTRL_DQOS_MEDIUM_Val _U_(0x2) /**< \brief (USB_QOSCTRL) Sensitive Latency */ 125 #define USB_QOSCTRL_DQOS_HIGH_Val _U_(0x3) /**< \brief (USB_QOSCTRL) Critical Latency */ 126 #define USB_QOSCTRL_DQOS_DISABLE (USB_QOSCTRL_DQOS_DISABLE_Val << USB_QOSCTRL_DQOS_Pos) 127 #define USB_QOSCTRL_DQOS_LOW (USB_QOSCTRL_DQOS_LOW_Val << USB_QOSCTRL_DQOS_Pos) 128 #define USB_QOSCTRL_DQOS_MEDIUM (USB_QOSCTRL_DQOS_MEDIUM_Val << USB_QOSCTRL_DQOS_Pos) 129 #define USB_QOSCTRL_DQOS_HIGH (USB_QOSCTRL_DQOS_HIGH_Val << USB_QOSCTRL_DQOS_Pos) 130 #define USB_QOSCTRL_MASK _U_(0x0F) /**< \brief (USB_QOSCTRL) MASK Register */ 131 132 /* -------- USB_DEVICE_CTRLB : (USB Offset: 0x008) (R/W 16) DEVICE DEVICE Control B -------- */ 133 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 134 typedef union { 135 struct { 136 uint16_t DETACH:1; /*!< bit: 0 Detach */ 137 uint16_t UPRSM:1; /*!< bit: 1 Upstream Resume */ 138 uint16_t SPDCONF:2; /*!< bit: 2.. 3 Speed Configuration */ 139 uint16_t NREPLY:1; /*!< bit: 4 No Reply */ 140 uint16_t TSTJ:1; /*!< bit: 5 Test mode J */ 141 uint16_t TSTK:1; /*!< bit: 6 Test mode K */ 142 uint16_t TSTPCKT:1; /*!< bit: 7 Test packet mode */ 143 uint16_t OPMODE2:1; /*!< bit: 8 Specific Operational Mode */ 144 uint16_t GNAK:1; /*!< bit: 9 Global NAK */ 145 uint16_t LPMHDSK:2; /*!< bit: 10..11 Link Power Management Handshake */ 146 uint16_t :4; /*!< bit: 12..15 Reserved */ 147 } bit; /*!< Structure used for bit access */ 148 uint16_t reg; /*!< Type used for register access */ 149 } USB_DEVICE_CTRLB_Type; 150 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 151 152 #define USB_DEVICE_CTRLB_OFFSET 0x008 /**< \brief (USB_DEVICE_CTRLB offset) DEVICE Control B */ 153 #define USB_DEVICE_CTRLB_RESETVALUE _U_(0x0001) /**< \brief (USB_DEVICE_CTRLB reset_value) DEVICE Control B */ 154 155 #define USB_DEVICE_CTRLB_DETACH_Pos 0 /**< \brief (USB_DEVICE_CTRLB) Detach */ 156 #define USB_DEVICE_CTRLB_DETACH (_U_(0x1) << USB_DEVICE_CTRLB_DETACH_Pos) 157 #define USB_DEVICE_CTRLB_UPRSM_Pos 1 /**< \brief (USB_DEVICE_CTRLB) Upstream Resume */ 158 #define USB_DEVICE_CTRLB_UPRSM (_U_(0x1) << USB_DEVICE_CTRLB_UPRSM_Pos) 159 #define USB_DEVICE_CTRLB_SPDCONF_Pos 2 /**< \brief (USB_DEVICE_CTRLB) Speed Configuration */ 160 #define USB_DEVICE_CTRLB_SPDCONF_Msk (_U_(0x3) << USB_DEVICE_CTRLB_SPDCONF_Pos) 161 #define USB_DEVICE_CTRLB_SPDCONF(value) (USB_DEVICE_CTRLB_SPDCONF_Msk & ((value) << USB_DEVICE_CTRLB_SPDCONF_Pos)) 162 #define USB_DEVICE_CTRLB_SPDCONF_FS_Val _U_(0x0) /**< \brief (USB_DEVICE_CTRLB) FS : Full Speed */ 163 #define USB_DEVICE_CTRLB_SPDCONF_LS_Val _U_(0x1) /**< \brief (USB_DEVICE_CTRLB) LS : Low Speed */ 164 #define USB_DEVICE_CTRLB_SPDCONF_HS_Val _U_(0x2) /**< \brief (USB_DEVICE_CTRLB) HS : High Speed capable */ 165 #define USB_DEVICE_CTRLB_SPDCONF_HSTM_Val _U_(0x3) /**< \brief (USB_DEVICE_CTRLB) HSTM: High Speed Test Mode (force high-speed mode for test mode) */ 166 #define USB_DEVICE_CTRLB_SPDCONF_FS (USB_DEVICE_CTRLB_SPDCONF_FS_Val << USB_DEVICE_CTRLB_SPDCONF_Pos) 167 #define USB_DEVICE_CTRLB_SPDCONF_LS (USB_DEVICE_CTRLB_SPDCONF_LS_Val << USB_DEVICE_CTRLB_SPDCONF_Pos) 168 #define USB_DEVICE_CTRLB_SPDCONF_HS (USB_DEVICE_CTRLB_SPDCONF_HS_Val << USB_DEVICE_CTRLB_SPDCONF_Pos) 169 #define USB_DEVICE_CTRLB_SPDCONF_HSTM (USB_DEVICE_CTRLB_SPDCONF_HSTM_Val << USB_DEVICE_CTRLB_SPDCONF_Pos) 170 #define USB_DEVICE_CTRLB_NREPLY_Pos 4 /**< \brief (USB_DEVICE_CTRLB) No Reply */ 171 #define USB_DEVICE_CTRLB_NREPLY (_U_(0x1) << USB_DEVICE_CTRLB_NREPLY_Pos) 172 #define USB_DEVICE_CTRLB_TSTJ_Pos 5 /**< \brief (USB_DEVICE_CTRLB) Test mode J */ 173 #define USB_DEVICE_CTRLB_TSTJ (_U_(0x1) << USB_DEVICE_CTRLB_TSTJ_Pos) 174 #define USB_DEVICE_CTRLB_TSTK_Pos 6 /**< \brief (USB_DEVICE_CTRLB) Test mode K */ 175 #define USB_DEVICE_CTRLB_TSTK (_U_(0x1) << USB_DEVICE_CTRLB_TSTK_Pos) 176 #define USB_DEVICE_CTRLB_TSTPCKT_Pos 7 /**< \brief (USB_DEVICE_CTRLB) Test packet mode */ 177 #define USB_DEVICE_CTRLB_TSTPCKT (_U_(0x1) << USB_DEVICE_CTRLB_TSTPCKT_Pos) 178 #define USB_DEVICE_CTRLB_OPMODE2_Pos 8 /**< \brief (USB_DEVICE_CTRLB) Specific Operational Mode */ 179 #define USB_DEVICE_CTRLB_OPMODE2 (_U_(0x1) << USB_DEVICE_CTRLB_OPMODE2_Pos) 180 #define USB_DEVICE_CTRLB_GNAK_Pos 9 /**< \brief (USB_DEVICE_CTRLB) Global NAK */ 181 #define USB_DEVICE_CTRLB_GNAK (_U_(0x1) << USB_DEVICE_CTRLB_GNAK_Pos) 182 #define USB_DEVICE_CTRLB_LPMHDSK_Pos 10 /**< \brief (USB_DEVICE_CTRLB) Link Power Management Handshake */ 183 #define USB_DEVICE_CTRLB_LPMHDSK_Msk (_U_(0x3) << USB_DEVICE_CTRLB_LPMHDSK_Pos) 184 #define USB_DEVICE_CTRLB_LPMHDSK(value) (USB_DEVICE_CTRLB_LPMHDSK_Msk & ((value) << USB_DEVICE_CTRLB_LPMHDSK_Pos)) 185 #define USB_DEVICE_CTRLB_LPMHDSK_NO_Val _U_(0x0) /**< \brief (USB_DEVICE_CTRLB) No handshake. LPM is not supported */ 186 #define USB_DEVICE_CTRLB_LPMHDSK_ACK_Val _U_(0x1) /**< \brief (USB_DEVICE_CTRLB) ACK */ 187 #define USB_DEVICE_CTRLB_LPMHDSK_NYET_Val _U_(0x2) /**< \brief (USB_DEVICE_CTRLB) NYET */ 188 #define USB_DEVICE_CTRLB_LPMHDSK_STALL_Val _U_(0x3) /**< \brief (USB_DEVICE_CTRLB) STALL */ 189 #define USB_DEVICE_CTRLB_LPMHDSK_NO (USB_DEVICE_CTRLB_LPMHDSK_NO_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos) 190 #define USB_DEVICE_CTRLB_LPMHDSK_ACK (USB_DEVICE_CTRLB_LPMHDSK_ACK_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos) 191 #define USB_DEVICE_CTRLB_LPMHDSK_NYET (USB_DEVICE_CTRLB_LPMHDSK_NYET_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos) 192 #define USB_DEVICE_CTRLB_LPMHDSK_STALL (USB_DEVICE_CTRLB_LPMHDSK_STALL_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos) 193 #define USB_DEVICE_CTRLB_MASK _U_(0x0FFF) /**< \brief (USB_DEVICE_CTRLB) MASK Register */ 194 195 /* -------- USB_HOST_CTRLB : (USB Offset: 0x008) (R/W 16) HOST HOST Control B -------- */ 196 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 197 typedef union { 198 struct { 199 uint16_t :1; /*!< bit: 0 Reserved */ 200 uint16_t RESUME:1; /*!< bit: 1 Send USB Resume */ 201 uint16_t SPDCONF:2; /*!< bit: 2.. 3 Speed Configuration for Host */ 202 uint16_t :1; /*!< bit: 4 Reserved */ 203 uint16_t TSTJ:1; /*!< bit: 5 Test mode J */ 204 uint16_t TSTK:1; /*!< bit: 6 Test mode K */ 205 uint16_t :1; /*!< bit: 7 Reserved */ 206 uint16_t SOFE:1; /*!< bit: 8 Start of Frame Generation Enable */ 207 uint16_t BUSRESET:1; /*!< bit: 9 Send USB Reset */ 208 uint16_t VBUSOK:1; /*!< bit: 10 VBUS is OK */ 209 uint16_t L1RESUME:1; /*!< bit: 11 Send L1 Resume */ 210 uint16_t :4; /*!< bit: 12..15 Reserved */ 211 } bit; /*!< Structure used for bit access */ 212 uint16_t reg; /*!< Type used for register access */ 213 } USB_HOST_CTRLB_Type; 214 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 215 216 #define USB_HOST_CTRLB_OFFSET 0x008 /**< \brief (USB_HOST_CTRLB offset) HOST Control B */ 217 #define USB_HOST_CTRLB_RESETVALUE _U_(0x0000) /**< \brief (USB_HOST_CTRLB reset_value) HOST Control B */ 218 219 #define USB_HOST_CTRLB_RESUME_Pos 1 /**< \brief (USB_HOST_CTRLB) Send USB Resume */ 220 #define USB_HOST_CTRLB_RESUME (_U_(0x1) << USB_HOST_CTRLB_RESUME_Pos) 221 #define USB_HOST_CTRLB_SPDCONF_Pos 2 /**< \brief (USB_HOST_CTRLB) Speed Configuration for Host */ 222 #define USB_HOST_CTRLB_SPDCONF_Msk (_U_(0x3) << USB_HOST_CTRLB_SPDCONF_Pos) 223 #define USB_HOST_CTRLB_SPDCONF(value) (USB_HOST_CTRLB_SPDCONF_Msk & ((value) << USB_HOST_CTRLB_SPDCONF_Pos)) 224 #define USB_HOST_CTRLB_SPDCONF_NORMAL_Val _U_(0x0) /**< \brief (USB_HOST_CTRLB) Normal mode:the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable. */ 225 #define USB_HOST_CTRLB_SPDCONF_FS_Val _U_(0x3) /**< \brief (USB_HOST_CTRLB) Full-speed:the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only. */ 226 #define USB_HOST_CTRLB_SPDCONF_NORMAL (USB_HOST_CTRLB_SPDCONF_NORMAL_Val << USB_HOST_CTRLB_SPDCONF_Pos) 227 #define USB_HOST_CTRLB_SPDCONF_FS (USB_HOST_CTRLB_SPDCONF_FS_Val << USB_HOST_CTRLB_SPDCONF_Pos) 228 #define USB_HOST_CTRLB_TSTJ_Pos 5 /**< \brief (USB_HOST_CTRLB) Test mode J */ 229 #define USB_HOST_CTRLB_TSTJ (_U_(0x1) << USB_HOST_CTRLB_TSTJ_Pos) 230 #define USB_HOST_CTRLB_TSTK_Pos 6 /**< \brief (USB_HOST_CTRLB) Test mode K */ 231 #define USB_HOST_CTRLB_TSTK (_U_(0x1) << USB_HOST_CTRLB_TSTK_Pos) 232 #define USB_HOST_CTRLB_SOFE_Pos 8 /**< \brief (USB_HOST_CTRLB) Start of Frame Generation Enable */ 233 #define USB_HOST_CTRLB_SOFE (_U_(0x1) << USB_HOST_CTRLB_SOFE_Pos) 234 #define USB_HOST_CTRLB_BUSRESET_Pos 9 /**< \brief (USB_HOST_CTRLB) Send USB Reset */ 235 #define USB_HOST_CTRLB_BUSRESET (_U_(0x1) << USB_HOST_CTRLB_BUSRESET_Pos) 236 #define USB_HOST_CTRLB_VBUSOK_Pos 10 /**< \brief (USB_HOST_CTRLB) VBUS is OK */ 237 #define USB_HOST_CTRLB_VBUSOK (_U_(0x1) << USB_HOST_CTRLB_VBUSOK_Pos) 238 #define USB_HOST_CTRLB_L1RESUME_Pos 11 /**< \brief (USB_HOST_CTRLB) Send L1 Resume */ 239 #define USB_HOST_CTRLB_L1RESUME (_U_(0x1) << USB_HOST_CTRLB_L1RESUME_Pos) 240 #define USB_HOST_CTRLB_MASK _U_(0x0F6E) /**< \brief (USB_HOST_CTRLB) MASK Register */ 241 242 /* -------- USB_DEVICE_DADD : (USB Offset: 0x00A) (R/W 8) DEVICE DEVICE Device Address -------- */ 243 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 244 typedef union { 245 struct { 246 uint8_t DADD:7; /*!< bit: 0.. 6 Device Address */ 247 uint8_t ADDEN:1; /*!< bit: 7 Device Address Enable */ 248 } bit; /*!< Structure used for bit access */ 249 uint8_t reg; /*!< Type used for register access */ 250 } USB_DEVICE_DADD_Type; 251 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 252 253 #define USB_DEVICE_DADD_OFFSET 0x00A /**< \brief (USB_DEVICE_DADD offset) DEVICE Device Address */ 254 #define USB_DEVICE_DADD_RESETVALUE _U_(0x00) /**< \brief (USB_DEVICE_DADD reset_value) DEVICE Device Address */ 255 256 #define USB_DEVICE_DADD_DADD_Pos 0 /**< \brief (USB_DEVICE_DADD) Device Address */ 257 #define USB_DEVICE_DADD_DADD_Msk (_U_(0x7F) << USB_DEVICE_DADD_DADD_Pos) 258 #define USB_DEVICE_DADD_DADD(value) (USB_DEVICE_DADD_DADD_Msk & ((value) << USB_DEVICE_DADD_DADD_Pos)) 259 #define USB_DEVICE_DADD_ADDEN_Pos 7 /**< \brief (USB_DEVICE_DADD) Device Address Enable */ 260 #define USB_DEVICE_DADD_ADDEN (_U_(0x1) << USB_DEVICE_DADD_ADDEN_Pos) 261 #define USB_DEVICE_DADD_MASK _U_(0xFF) /**< \brief (USB_DEVICE_DADD) MASK Register */ 262 263 /* -------- USB_HOST_HSOFC : (USB Offset: 0x00A) (R/W 8) HOST HOST Host Start Of Frame Control -------- */ 264 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 265 typedef union { 266 struct { 267 uint8_t FLENC:4; /*!< bit: 0.. 3 Frame Length Control */ 268 uint8_t :3; /*!< bit: 4.. 6 Reserved */ 269 uint8_t FLENCE:1; /*!< bit: 7 Frame Length Control Enable */ 270 } bit; /*!< Structure used for bit access */ 271 uint8_t reg; /*!< Type used for register access */ 272 } USB_HOST_HSOFC_Type; 273 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 274 275 #define USB_HOST_HSOFC_OFFSET 0x00A /**< \brief (USB_HOST_HSOFC offset) HOST Host Start Of Frame Control */ 276 #define USB_HOST_HSOFC_RESETVALUE _U_(0x00) /**< \brief (USB_HOST_HSOFC reset_value) HOST Host Start Of Frame Control */ 277 278 #define USB_HOST_HSOFC_FLENC_Pos 0 /**< \brief (USB_HOST_HSOFC) Frame Length Control */ 279 #define USB_HOST_HSOFC_FLENC_Msk (_U_(0xF) << USB_HOST_HSOFC_FLENC_Pos) 280 #define USB_HOST_HSOFC_FLENC(value) (USB_HOST_HSOFC_FLENC_Msk & ((value) << USB_HOST_HSOFC_FLENC_Pos)) 281 #define USB_HOST_HSOFC_FLENCE_Pos 7 /**< \brief (USB_HOST_HSOFC) Frame Length Control Enable */ 282 #define USB_HOST_HSOFC_FLENCE (_U_(0x1) << USB_HOST_HSOFC_FLENCE_Pos) 283 #define USB_HOST_HSOFC_MASK _U_(0x8F) /**< \brief (USB_HOST_HSOFC) MASK Register */ 284 285 /* -------- USB_DEVICE_STATUS : (USB Offset: 0x00C) (R/ 8) DEVICE DEVICE Status -------- */ 286 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 287 typedef union { 288 struct { 289 uint8_t :2; /*!< bit: 0.. 1 Reserved */ 290 uint8_t SPEED:2; /*!< bit: 2.. 3 Speed Status */ 291 uint8_t :2; /*!< bit: 4.. 5 Reserved */ 292 uint8_t LINESTATE:2; /*!< bit: 6.. 7 USB Line State Status */ 293 } bit; /*!< Structure used for bit access */ 294 uint8_t reg; /*!< Type used for register access */ 295 } USB_DEVICE_STATUS_Type; 296 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 297 298 #define USB_DEVICE_STATUS_OFFSET 0x00C /**< \brief (USB_DEVICE_STATUS offset) DEVICE Status */ 299 #define USB_DEVICE_STATUS_RESETVALUE _U_(0x40) /**< \brief (USB_DEVICE_STATUS reset_value) DEVICE Status */ 300 301 #define USB_DEVICE_STATUS_SPEED_Pos 2 /**< \brief (USB_DEVICE_STATUS) Speed Status */ 302 #define USB_DEVICE_STATUS_SPEED_Msk (_U_(0x3) << USB_DEVICE_STATUS_SPEED_Pos) 303 #define USB_DEVICE_STATUS_SPEED(value) (USB_DEVICE_STATUS_SPEED_Msk & ((value) << USB_DEVICE_STATUS_SPEED_Pos)) 304 #define USB_DEVICE_STATUS_SPEED_FS_Val _U_(0x0) /**< \brief (USB_DEVICE_STATUS) Full-speed mode */ 305 #define USB_DEVICE_STATUS_SPEED_HS_Val _U_(0x1) /**< \brief (USB_DEVICE_STATUS) High-speed mode */ 306 #define USB_DEVICE_STATUS_SPEED_LS_Val _U_(0x2) /**< \brief (USB_DEVICE_STATUS) Low-speed mode */ 307 #define USB_DEVICE_STATUS_SPEED_FS (USB_DEVICE_STATUS_SPEED_FS_Val << USB_DEVICE_STATUS_SPEED_Pos) 308 #define USB_DEVICE_STATUS_SPEED_HS (USB_DEVICE_STATUS_SPEED_HS_Val << USB_DEVICE_STATUS_SPEED_Pos) 309 #define USB_DEVICE_STATUS_SPEED_LS (USB_DEVICE_STATUS_SPEED_LS_Val << USB_DEVICE_STATUS_SPEED_Pos) 310 #define USB_DEVICE_STATUS_LINESTATE_Pos 6 /**< \brief (USB_DEVICE_STATUS) USB Line State Status */ 311 #define USB_DEVICE_STATUS_LINESTATE_Msk (_U_(0x3) << USB_DEVICE_STATUS_LINESTATE_Pos) 312 #define USB_DEVICE_STATUS_LINESTATE(value) (USB_DEVICE_STATUS_LINESTATE_Msk & ((value) << USB_DEVICE_STATUS_LINESTATE_Pos)) 313 #define USB_DEVICE_STATUS_LINESTATE_0_Val _U_(0x0) /**< \brief (USB_DEVICE_STATUS) SE0/RESET */ 314 #define USB_DEVICE_STATUS_LINESTATE_1_Val _U_(0x1) /**< \brief (USB_DEVICE_STATUS) FS-J or LS-K State */ 315 #define USB_DEVICE_STATUS_LINESTATE_2_Val _U_(0x2) /**< \brief (USB_DEVICE_STATUS) FS-K or LS-J State */ 316 #define USB_DEVICE_STATUS_LINESTATE_0 (USB_DEVICE_STATUS_LINESTATE_0_Val << USB_DEVICE_STATUS_LINESTATE_Pos) 317 #define USB_DEVICE_STATUS_LINESTATE_1 (USB_DEVICE_STATUS_LINESTATE_1_Val << USB_DEVICE_STATUS_LINESTATE_Pos) 318 #define USB_DEVICE_STATUS_LINESTATE_2 (USB_DEVICE_STATUS_LINESTATE_2_Val << USB_DEVICE_STATUS_LINESTATE_Pos) 319 #define USB_DEVICE_STATUS_MASK _U_(0xCC) /**< \brief (USB_DEVICE_STATUS) MASK Register */ 320 321 /* -------- USB_HOST_STATUS : (USB Offset: 0x00C) (R/W 8) HOST HOST Status -------- */ 322 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 323 typedef union { 324 struct { 325 uint8_t :2; /*!< bit: 0.. 1 Reserved */ 326 uint8_t SPEED:2; /*!< bit: 2.. 3 Speed Status */ 327 uint8_t :2; /*!< bit: 4.. 5 Reserved */ 328 uint8_t LINESTATE:2; /*!< bit: 6.. 7 USB Line State Status */ 329 } bit; /*!< Structure used for bit access */ 330 uint8_t reg; /*!< Type used for register access */ 331 } USB_HOST_STATUS_Type; 332 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 333 334 #define USB_HOST_STATUS_OFFSET 0x00C /**< \brief (USB_HOST_STATUS offset) HOST Status */ 335 #define USB_HOST_STATUS_RESETVALUE _U_(0x00) /**< \brief (USB_HOST_STATUS reset_value) HOST Status */ 336 337 #define USB_HOST_STATUS_SPEED_Pos 2 /**< \brief (USB_HOST_STATUS) Speed Status */ 338 #define USB_HOST_STATUS_SPEED_Msk (_U_(0x3) << USB_HOST_STATUS_SPEED_Pos) 339 #define USB_HOST_STATUS_SPEED(value) (USB_HOST_STATUS_SPEED_Msk & ((value) << USB_HOST_STATUS_SPEED_Pos)) 340 #define USB_HOST_STATUS_LINESTATE_Pos 6 /**< \brief (USB_HOST_STATUS) USB Line State Status */ 341 #define USB_HOST_STATUS_LINESTATE_Msk (_U_(0x3) << USB_HOST_STATUS_LINESTATE_Pos) 342 #define USB_HOST_STATUS_LINESTATE(value) (USB_HOST_STATUS_LINESTATE_Msk & ((value) << USB_HOST_STATUS_LINESTATE_Pos)) 343 #define USB_HOST_STATUS_MASK _U_(0xCC) /**< \brief (USB_HOST_STATUS) MASK Register */ 344 345 /* -------- USB_FSMSTATUS : (USB Offset: 0x00D) (R/ 8) Finite State Machine Status -------- */ 346 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 347 typedef union { 348 struct { 349 uint8_t FSMSTATE:7; /*!< bit: 0.. 6 Fine State Machine Status */ 350 uint8_t :1; /*!< bit: 7 Reserved */ 351 } bit; /*!< Structure used for bit access */ 352 uint8_t reg; /*!< Type used for register access */ 353 } USB_FSMSTATUS_Type; 354 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 355 356 #define USB_FSMSTATUS_OFFSET 0x00D /**< \brief (USB_FSMSTATUS offset) Finite State Machine Status */ 357 #define USB_FSMSTATUS_RESETVALUE _U_(0x01) /**< \brief (USB_FSMSTATUS reset_value) Finite State Machine Status */ 358 359 #define USB_FSMSTATUS_FSMSTATE_Pos 0 /**< \brief (USB_FSMSTATUS) Fine State Machine Status */ 360 #define USB_FSMSTATUS_FSMSTATE_Msk (_U_(0x7F) << USB_FSMSTATUS_FSMSTATE_Pos) 361 #define USB_FSMSTATUS_FSMSTATE(value) (USB_FSMSTATUS_FSMSTATE_Msk & ((value) << USB_FSMSTATUS_FSMSTATE_Pos)) 362 #define USB_FSMSTATUS_FSMSTATE_OFF_Val _U_(0x1) /**< \brief (USB_FSMSTATUS) OFF (L3). It corresponds to the powered-off, disconnected, and disabled state */ 363 #define USB_FSMSTATUS_FSMSTATE_ON_Val _U_(0x2) /**< \brief (USB_FSMSTATUS) ON (L0). It corresponds to the Idle and Active states */ 364 #define USB_FSMSTATUS_FSMSTATE_SUSPEND_Val _U_(0x4) /**< \brief (USB_FSMSTATUS) SUSPEND (L2) */ 365 #define USB_FSMSTATUS_FSMSTATE_SLEEP_Val _U_(0x8) /**< \brief (USB_FSMSTATUS) SLEEP (L1) */ 366 #define USB_FSMSTATUS_FSMSTATE_DNRESUME_Val _U_(0x10) /**< \brief (USB_FSMSTATUS) DNRESUME. Down Stream Resume. */ 367 #define USB_FSMSTATUS_FSMSTATE_UPRESUME_Val _U_(0x20) /**< \brief (USB_FSMSTATUS) UPRESUME. Up Stream Resume. */ 368 #define USB_FSMSTATUS_FSMSTATE_RESET_Val _U_(0x40) /**< \brief (USB_FSMSTATUS) RESET. USB lines Reset. */ 369 #define USB_FSMSTATUS_FSMSTATE_OFF (USB_FSMSTATUS_FSMSTATE_OFF_Val << USB_FSMSTATUS_FSMSTATE_Pos) 370 #define USB_FSMSTATUS_FSMSTATE_ON (USB_FSMSTATUS_FSMSTATE_ON_Val << USB_FSMSTATUS_FSMSTATE_Pos) 371 #define USB_FSMSTATUS_FSMSTATE_SUSPEND (USB_FSMSTATUS_FSMSTATE_SUSPEND_Val << USB_FSMSTATUS_FSMSTATE_Pos) 372 #define USB_FSMSTATUS_FSMSTATE_SLEEP (USB_FSMSTATUS_FSMSTATE_SLEEP_Val << USB_FSMSTATUS_FSMSTATE_Pos) 373 #define USB_FSMSTATUS_FSMSTATE_DNRESUME (USB_FSMSTATUS_FSMSTATE_DNRESUME_Val << USB_FSMSTATUS_FSMSTATE_Pos) 374 #define USB_FSMSTATUS_FSMSTATE_UPRESUME (USB_FSMSTATUS_FSMSTATE_UPRESUME_Val << USB_FSMSTATUS_FSMSTATE_Pos) 375 #define USB_FSMSTATUS_FSMSTATE_RESET (USB_FSMSTATUS_FSMSTATE_RESET_Val << USB_FSMSTATUS_FSMSTATE_Pos) 376 #define USB_FSMSTATUS_MASK _U_(0x7F) /**< \brief (USB_FSMSTATUS) MASK Register */ 377 378 /* -------- USB_DEVICE_FNUM : (USB Offset: 0x010) (R/ 16) DEVICE DEVICE Device Frame Number -------- */ 379 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 380 typedef union { 381 struct { 382 uint16_t MFNUM:3; /*!< bit: 0.. 2 Micro Frame Number */ 383 uint16_t FNUM:11; /*!< bit: 3..13 Frame Number */ 384 uint16_t :1; /*!< bit: 14 Reserved */ 385 uint16_t FNCERR:1; /*!< bit: 15 Frame Number CRC Error */ 386 } bit; /*!< Structure used for bit access */ 387 uint16_t reg; /*!< Type used for register access */ 388 } USB_DEVICE_FNUM_Type; 389 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 390 391 #define USB_DEVICE_FNUM_OFFSET 0x010 /**< \brief (USB_DEVICE_FNUM offset) DEVICE Device Frame Number */ 392 #define USB_DEVICE_FNUM_RESETVALUE _U_(0x0000) /**< \brief (USB_DEVICE_FNUM reset_value) DEVICE Device Frame Number */ 393 394 #define USB_DEVICE_FNUM_MFNUM_Pos 0 /**< \brief (USB_DEVICE_FNUM) Micro Frame Number */ 395 #define USB_DEVICE_FNUM_MFNUM_Msk (_U_(0x7) << USB_DEVICE_FNUM_MFNUM_Pos) 396 #define USB_DEVICE_FNUM_MFNUM(value) (USB_DEVICE_FNUM_MFNUM_Msk & ((value) << USB_DEVICE_FNUM_MFNUM_Pos)) 397 #define USB_DEVICE_FNUM_FNUM_Pos 3 /**< \brief (USB_DEVICE_FNUM) Frame Number */ 398 #define USB_DEVICE_FNUM_FNUM_Msk (_U_(0x7FF) << USB_DEVICE_FNUM_FNUM_Pos) 399 #define USB_DEVICE_FNUM_FNUM(value) (USB_DEVICE_FNUM_FNUM_Msk & ((value) << USB_DEVICE_FNUM_FNUM_Pos)) 400 #define USB_DEVICE_FNUM_FNCERR_Pos 15 /**< \brief (USB_DEVICE_FNUM) Frame Number CRC Error */ 401 #define USB_DEVICE_FNUM_FNCERR (_U_(0x1) << USB_DEVICE_FNUM_FNCERR_Pos) 402 #define USB_DEVICE_FNUM_MASK _U_(0xBFFF) /**< \brief (USB_DEVICE_FNUM) MASK Register */ 403 404 /* -------- USB_HOST_FNUM : (USB Offset: 0x010) (R/W 16) HOST HOST Host Frame Number -------- */ 405 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 406 typedef union { 407 struct { 408 uint16_t MFNUM:3; /*!< bit: 0.. 2 Micro Frame Number */ 409 uint16_t FNUM:11; /*!< bit: 3..13 Frame Number */ 410 uint16_t :2; /*!< bit: 14..15 Reserved */ 411 } bit; /*!< Structure used for bit access */ 412 uint16_t reg; /*!< Type used for register access */ 413 } USB_HOST_FNUM_Type; 414 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 415 416 #define USB_HOST_FNUM_OFFSET 0x010 /**< \brief (USB_HOST_FNUM offset) HOST Host Frame Number */ 417 #define USB_HOST_FNUM_RESETVALUE _U_(0x0000) /**< \brief (USB_HOST_FNUM reset_value) HOST Host Frame Number */ 418 419 #define USB_HOST_FNUM_MFNUM_Pos 0 /**< \brief (USB_HOST_FNUM) Micro Frame Number */ 420 #define USB_HOST_FNUM_MFNUM_Msk (_U_(0x7) << USB_HOST_FNUM_MFNUM_Pos) 421 #define USB_HOST_FNUM_MFNUM(value) (USB_HOST_FNUM_MFNUM_Msk & ((value) << USB_HOST_FNUM_MFNUM_Pos)) 422 #define USB_HOST_FNUM_FNUM_Pos 3 /**< \brief (USB_HOST_FNUM) Frame Number */ 423 #define USB_HOST_FNUM_FNUM_Msk (_U_(0x7FF) << USB_HOST_FNUM_FNUM_Pos) 424 #define USB_HOST_FNUM_FNUM(value) (USB_HOST_FNUM_FNUM_Msk & ((value) << USB_HOST_FNUM_FNUM_Pos)) 425 #define USB_HOST_FNUM_MASK _U_(0x3FFF) /**< \brief (USB_HOST_FNUM) MASK Register */ 426 427 /* -------- USB_HOST_FLENHIGH : (USB Offset: 0x012) (R/ 8) HOST HOST Host Frame Length -------- */ 428 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 429 typedef union { 430 struct { 431 uint8_t FLENHIGH:8; /*!< bit: 0.. 7 Frame Length */ 432 } bit; /*!< Structure used for bit access */ 433 uint8_t reg; /*!< Type used for register access */ 434 } USB_HOST_FLENHIGH_Type; 435 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 436 437 #define USB_HOST_FLENHIGH_OFFSET 0x012 /**< \brief (USB_HOST_FLENHIGH offset) HOST Host Frame Length */ 438 #define USB_HOST_FLENHIGH_RESETVALUE _U_(0x00) /**< \brief (USB_HOST_FLENHIGH reset_value) HOST Host Frame Length */ 439 440 #define USB_HOST_FLENHIGH_FLENHIGH_Pos 0 /**< \brief (USB_HOST_FLENHIGH) Frame Length */ 441 #define USB_HOST_FLENHIGH_FLENHIGH_Msk (_U_(0xFF) << USB_HOST_FLENHIGH_FLENHIGH_Pos) 442 #define USB_HOST_FLENHIGH_FLENHIGH(value) (USB_HOST_FLENHIGH_FLENHIGH_Msk & ((value) << USB_HOST_FLENHIGH_FLENHIGH_Pos)) 443 #define USB_HOST_FLENHIGH_MASK _U_(0xFF) /**< \brief (USB_HOST_FLENHIGH) MASK Register */ 444 445 /* -------- USB_DEVICE_INTENCLR : (USB Offset: 0x014) (R/W 16) DEVICE DEVICE Device Interrupt Enable Clear -------- */ 446 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 447 typedef union { 448 struct { 449 uint16_t SUSPEND:1; /*!< bit: 0 Suspend Interrupt Enable */ 450 uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame Interrupt Enable in High Speed Mode */ 451 uint16_t SOF:1; /*!< bit: 2 Start Of Frame Interrupt Enable */ 452 uint16_t EORST:1; /*!< bit: 3 End of Reset Interrupt Enable */ 453 uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */ 454 uint16_t EORSM:1; /*!< bit: 5 End Of Resume Interrupt Enable */ 455 uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume Interrupt Enable */ 456 uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */ 457 uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet Interrupt Enable */ 458 uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend Interrupt Enable */ 459 uint16_t :6; /*!< bit: 10..15 Reserved */ 460 } bit; /*!< Structure used for bit access */ 461 uint16_t reg; /*!< Type used for register access */ 462 } USB_DEVICE_INTENCLR_Type; 463 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 464 465 #define USB_DEVICE_INTENCLR_OFFSET 0x014 /**< \brief (USB_DEVICE_INTENCLR offset) DEVICE Device Interrupt Enable Clear */ 466 #define USB_DEVICE_INTENCLR_RESETVALUE _U_(0x0000) /**< \brief (USB_DEVICE_INTENCLR reset_value) DEVICE Device Interrupt Enable Clear */ 467 468 #define USB_DEVICE_INTENCLR_SUSPEND_Pos 0 /**< \brief (USB_DEVICE_INTENCLR) Suspend Interrupt Enable */ 469 #define USB_DEVICE_INTENCLR_SUSPEND (_U_(0x1) << USB_DEVICE_INTENCLR_SUSPEND_Pos) 470 #define USB_DEVICE_INTENCLR_MSOF_Pos 1 /**< \brief (USB_DEVICE_INTENCLR) Micro Start of Frame Interrupt Enable in High Speed Mode */ 471 #define USB_DEVICE_INTENCLR_MSOF (_U_(0x1) << USB_DEVICE_INTENCLR_MSOF_Pos) 472 #define USB_DEVICE_INTENCLR_SOF_Pos 2 /**< \brief (USB_DEVICE_INTENCLR) Start Of Frame Interrupt Enable */ 473 #define USB_DEVICE_INTENCLR_SOF (_U_(0x1) << USB_DEVICE_INTENCLR_SOF_Pos) 474 #define USB_DEVICE_INTENCLR_EORST_Pos 3 /**< \brief (USB_DEVICE_INTENCLR) End of Reset Interrupt Enable */ 475 #define USB_DEVICE_INTENCLR_EORST (_U_(0x1) << USB_DEVICE_INTENCLR_EORST_Pos) 476 #define USB_DEVICE_INTENCLR_WAKEUP_Pos 4 /**< \brief (USB_DEVICE_INTENCLR) Wake Up Interrupt Enable */ 477 #define USB_DEVICE_INTENCLR_WAKEUP (_U_(0x1) << USB_DEVICE_INTENCLR_WAKEUP_Pos) 478 #define USB_DEVICE_INTENCLR_EORSM_Pos 5 /**< \brief (USB_DEVICE_INTENCLR) End Of Resume Interrupt Enable */ 479 #define USB_DEVICE_INTENCLR_EORSM (_U_(0x1) << USB_DEVICE_INTENCLR_EORSM_Pos) 480 #define USB_DEVICE_INTENCLR_UPRSM_Pos 6 /**< \brief (USB_DEVICE_INTENCLR) Upstream Resume Interrupt Enable */ 481 #define USB_DEVICE_INTENCLR_UPRSM (_U_(0x1) << USB_DEVICE_INTENCLR_UPRSM_Pos) 482 #define USB_DEVICE_INTENCLR_RAMACER_Pos 7 /**< \brief (USB_DEVICE_INTENCLR) Ram Access Interrupt Enable */ 483 #define USB_DEVICE_INTENCLR_RAMACER (_U_(0x1) << USB_DEVICE_INTENCLR_RAMACER_Pos) 484 #define USB_DEVICE_INTENCLR_LPMNYET_Pos 8 /**< \brief (USB_DEVICE_INTENCLR) Link Power Management Not Yet Interrupt Enable */ 485 #define USB_DEVICE_INTENCLR_LPMNYET (_U_(0x1) << USB_DEVICE_INTENCLR_LPMNYET_Pos) 486 #define USB_DEVICE_INTENCLR_LPMSUSP_Pos 9 /**< \brief (USB_DEVICE_INTENCLR) Link Power Management Suspend Interrupt Enable */ 487 #define USB_DEVICE_INTENCLR_LPMSUSP (_U_(0x1) << USB_DEVICE_INTENCLR_LPMSUSP_Pos) 488 #define USB_DEVICE_INTENCLR_MASK _U_(0x03FF) /**< \brief (USB_DEVICE_INTENCLR) MASK Register */ 489 490 /* -------- USB_HOST_INTENCLR : (USB Offset: 0x014) (R/W 16) HOST HOST Host Interrupt Enable Clear -------- */ 491 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 492 typedef union { 493 struct { 494 uint16_t :2; /*!< bit: 0.. 1 Reserved */ 495 uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame Interrupt Disable */ 496 uint16_t RST:1; /*!< bit: 3 BUS Reset Interrupt Disable */ 497 uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Disable */ 498 uint16_t DNRSM:1; /*!< bit: 5 DownStream to Device Interrupt Disable */ 499 uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume from Device Interrupt Disable */ 500 uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Disable */ 501 uint16_t DCONN:1; /*!< bit: 8 Device Connection Interrupt Disable */ 502 uint16_t DDISC:1; /*!< bit: 9 Device Disconnection Interrupt Disable */ 503 uint16_t :6; /*!< bit: 10..15 Reserved */ 504 } bit; /*!< Structure used for bit access */ 505 uint16_t reg; /*!< Type used for register access */ 506 } USB_HOST_INTENCLR_Type; 507 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 508 509 #define USB_HOST_INTENCLR_OFFSET 0x014 /**< \brief (USB_HOST_INTENCLR offset) HOST Host Interrupt Enable Clear */ 510 #define USB_HOST_INTENCLR_RESETVALUE _U_(0x0000) /**< \brief (USB_HOST_INTENCLR reset_value) HOST Host Interrupt Enable Clear */ 511 512 #define USB_HOST_INTENCLR_HSOF_Pos 2 /**< \brief (USB_HOST_INTENCLR) Host Start Of Frame Interrupt Disable */ 513 #define USB_HOST_INTENCLR_HSOF (_U_(0x1) << USB_HOST_INTENCLR_HSOF_Pos) 514 #define USB_HOST_INTENCLR_RST_Pos 3 /**< \brief (USB_HOST_INTENCLR) BUS Reset Interrupt Disable */ 515 #define USB_HOST_INTENCLR_RST (_U_(0x1) << USB_HOST_INTENCLR_RST_Pos) 516 #define USB_HOST_INTENCLR_WAKEUP_Pos 4 /**< \brief (USB_HOST_INTENCLR) Wake Up Interrupt Disable */ 517 #define USB_HOST_INTENCLR_WAKEUP (_U_(0x1) << USB_HOST_INTENCLR_WAKEUP_Pos) 518 #define USB_HOST_INTENCLR_DNRSM_Pos 5 /**< \brief (USB_HOST_INTENCLR) DownStream to Device Interrupt Disable */ 519 #define USB_HOST_INTENCLR_DNRSM (_U_(0x1) << USB_HOST_INTENCLR_DNRSM_Pos) 520 #define USB_HOST_INTENCLR_UPRSM_Pos 6 /**< \brief (USB_HOST_INTENCLR) Upstream Resume from Device Interrupt Disable */ 521 #define USB_HOST_INTENCLR_UPRSM (_U_(0x1) << USB_HOST_INTENCLR_UPRSM_Pos) 522 #define USB_HOST_INTENCLR_RAMACER_Pos 7 /**< \brief (USB_HOST_INTENCLR) Ram Access Interrupt Disable */ 523 #define USB_HOST_INTENCLR_RAMACER (_U_(0x1) << USB_HOST_INTENCLR_RAMACER_Pos) 524 #define USB_HOST_INTENCLR_DCONN_Pos 8 /**< \brief (USB_HOST_INTENCLR) Device Connection Interrupt Disable */ 525 #define USB_HOST_INTENCLR_DCONN (_U_(0x1) << USB_HOST_INTENCLR_DCONN_Pos) 526 #define USB_HOST_INTENCLR_DDISC_Pos 9 /**< \brief (USB_HOST_INTENCLR) Device Disconnection Interrupt Disable */ 527 #define USB_HOST_INTENCLR_DDISC (_U_(0x1) << USB_HOST_INTENCLR_DDISC_Pos) 528 #define USB_HOST_INTENCLR_MASK _U_(0x03FC) /**< \brief (USB_HOST_INTENCLR) MASK Register */ 529 530 /* -------- USB_DEVICE_INTENSET : (USB Offset: 0x018) (R/W 16) DEVICE DEVICE Device Interrupt Enable Set -------- */ 531 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 532 typedef union { 533 struct { 534 uint16_t SUSPEND:1; /*!< bit: 0 Suspend Interrupt Enable */ 535 uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame Interrupt Enable in High Speed Mode */ 536 uint16_t SOF:1; /*!< bit: 2 Start Of Frame Interrupt Enable */ 537 uint16_t EORST:1; /*!< bit: 3 End of Reset Interrupt Enable */ 538 uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */ 539 uint16_t EORSM:1; /*!< bit: 5 End Of Resume Interrupt Enable */ 540 uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume Interrupt Enable */ 541 uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */ 542 uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet Interrupt Enable */ 543 uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend Interrupt Enable */ 544 uint16_t :6; /*!< bit: 10..15 Reserved */ 545 } bit; /*!< Structure used for bit access */ 546 uint16_t reg; /*!< Type used for register access */ 547 } USB_DEVICE_INTENSET_Type; 548 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 549 550 #define USB_DEVICE_INTENSET_OFFSET 0x018 /**< \brief (USB_DEVICE_INTENSET offset) DEVICE Device Interrupt Enable Set */ 551 #define USB_DEVICE_INTENSET_RESETVALUE _U_(0x0000) /**< \brief (USB_DEVICE_INTENSET reset_value) DEVICE Device Interrupt Enable Set */ 552 553 #define USB_DEVICE_INTENSET_SUSPEND_Pos 0 /**< \brief (USB_DEVICE_INTENSET) Suspend Interrupt Enable */ 554 #define USB_DEVICE_INTENSET_SUSPEND (_U_(0x1) << USB_DEVICE_INTENSET_SUSPEND_Pos) 555 #define USB_DEVICE_INTENSET_MSOF_Pos 1 /**< \brief (USB_DEVICE_INTENSET) Micro Start of Frame Interrupt Enable in High Speed Mode */ 556 #define USB_DEVICE_INTENSET_MSOF (_U_(0x1) << USB_DEVICE_INTENSET_MSOF_Pos) 557 #define USB_DEVICE_INTENSET_SOF_Pos 2 /**< \brief (USB_DEVICE_INTENSET) Start Of Frame Interrupt Enable */ 558 #define USB_DEVICE_INTENSET_SOF (_U_(0x1) << USB_DEVICE_INTENSET_SOF_Pos) 559 #define USB_DEVICE_INTENSET_EORST_Pos 3 /**< \brief (USB_DEVICE_INTENSET) End of Reset Interrupt Enable */ 560 #define USB_DEVICE_INTENSET_EORST (_U_(0x1) << USB_DEVICE_INTENSET_EORST_Pos) 561 #define USB_DEVICE_INTENSET_WAKEUP_Pos 4 /**< \brief (USB_DEVICE_INTENSET) Wake Up Interrupt Enable */ 562 #define USB_DEVICE_INTENSET_WAKEUP (_U_(0x1) << USB_DEVICE_INTENSET_WAKEUP_Pos) 563 #define USB_DEVICE_INTENSET_EORSM_Pos 5 /**< \brief (USB_DEVICE_INTENSET) End Of Resume Interrupt Enable */ 564 #define USB_DEVICE_INTENSET_EORSM (_U_(0x1) << USB_DEVICE_INTENSET_EORSM_Pos) 565 #define USB_DEVICE_INTENSET_UPRSM_Pos 6 /**< \brief (USB_DEVICE_INTENSET) Upstream Resume Interrupt Enable */ 566 #define USB_DEVICE_INTENSET_UPRSM (_U_(0x1) << USB_DEVICE_INTENSET_UPRSM_Pos) 567 #define USB_DEVICE_INTENSET_RAMACER_Pos 7 /**< \brief (USB_DEVICE_INTENSET) Ram Access Interrupt Enable */ 568 #define USB_DEVICE_INTENSET_RAMACER (_U_(0x1) << USB_DEVICE_INTENSET_RAMACER_Pos) 569 #define USB_DEVICE_INTENSET_LPMNYET_Pos 8 /**< \brief (USB_DEVICE_INTENSET) Link Power Management Not Yet Interrupt Enable */ 570 #define USB_DEVICE_INTENSET_LPMNYET (_U_(0x1) << USB_DEVICE_INTENSET_LPMNYET_Pos) 571 #define USB_DEVICE_INTENSET_LPMSUSP_Pos 9 /**< \brief (USB_DEVICE_INTENSET) Link Power Management Suspend Interrupt Enable */ 572 #define USB_DEVICE_INTENSET_LPMSUSP (_U_(0x1) << USB_DEVICE_INTENSET_LPMSUSP_Pos) 573 #define USB_DEVICE_INTENSET_MASK _U_(0x03FF) /**< \brief (USB_DEVICE_INTENSET) MASK Register */ 574 575 /* -------- USB_HOST_INTENSET : (USB Offset: 0x018) (R/W 16) HOST HOST Host Interrupt Enable Set -------- */ 576 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 577 typedef union { 578 struct { 579 uint16_t :2; /*!< bit: 0.. 1 Reserved */ 580 uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame Interrupt Enable */ 581 uint16_t RST:1; /*!< bit: 3 Bus Reset Interrupt Enable */ 582 uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */ 583 uint16_t DNRSM:1; /*!< bit: 5 DownStream to the Device Interrupt Enable */ 584 uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume fromthe device Interrupt Enable */ 585 uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */ 586 uint16_t DCONN:1; /*!< bit: 8 Link Power Management Interrupt Enable */ 587 uint16_t DDISC:1; /*!< bit: 9 Device Disconnection Interrupt Enable */ 588 uint16_t :6; /*!< bit: 10..15 Reserved */ 589 } bit; /*!< Structure used for bit access */ 590 uint16_t reg; /*!< Type used for register access */ 591 } USB_HOST_INTENSET_Type; 592 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 593 594 #define USB_HOST_INTENSET_OFFSET 0x018 /**< \brief (USB_HOST_INTENSET offset) HOST Host Interrupt Enable Set */ 595 #define USB_HOST_INTENSET_RESETVALUE _U_(0x0000) /**< \brief (USB_HOST_INTENSET reset_value) HOST Host Interrupt Enable Set */ 596 597 #define USB_HOST_INTENSET_HSOF_Pos 2 /**< \brief (USB_HOST_INTENSET) Host Start Of Frame Interrupt Enable */ 598 #define USB_HOST_INTENSET_HSOF (_U_(0x1) << USB_HOST_INTENSET_HSOF_Pos) 599 #define USB_HOST_INTENSET_RST_Pos 3 /**< \brief (USB_HOST_INTENSET) Bus Reset Interrupt Enable */ 600 #define USB_HOST_INTENSET_RST (_U_(0x1) << USB_HOST_INTENSET_RST_Pos) 601 #define USB_HOST_INTENSET_WAKEUP_Pos 4 /**< \brief (USB_HOST_INTENSET) Wake Up Interrupt Enable */ 602 #define USB_HOST_INTENSET_WAKEUP (_U_(0x1) << USB_HOST_INTENSET_WAKEUP_Pos) 603 #define USB_HOST_INTENSET_DNRSM_Pos 5 /**< \brief (USB_HOST_INTENSET) DownStream to the Device Interrupt Enable */ 604 #define USB_HOST_INTENSET_DNRSM (_U_(0x1) << USB_HOST_INTENSET_DNRSM_Pos) 605 #define USB_HOST_INTENSET_UPRSM_Pos 6 /**< \brief (USB_HOST_INTENSET) Upstream Resume fromthe device Interrupt Enable */ 606 #define USB_HOST_INTENSET_UPRSM (_U_(0x1) << USB_HOST_INTENSET_UPRSM_Pos) 607 #define USB_HOST_INTENSET_RAMACER_Pos 7 /**< \brief (USB_HOST_INTENSET) Ram Access Interrupt Enable */ 608 #define USB_HOST_INTENSET_RAMACER (_U_(0x1) << USB_HOST_INTENSET_RAMACER_Pos) 609 #define USB_HOST_INTENSET_DCONN_Pos 8 /**< \brief (USB_HOST_INTENSET) Link Power Management Interrupt Enable */ 610 #define USB_HOST_INTENSET_DCONN (_U_(0x1) << USB_HOST_INTENSET_DCONN_Pos) 611 #define USB_HOST_INTENSET_DDISC_Pos 9 /**< \brief (USB_HOST_INTENSET) Device Disconnection Interrupt Enable */ 612 #define USB_HOST_INTENSET_DDISC (_U_(0x1) << USB_HOST_INTENSET_DDISC_Pos) 613 #define USB_HOST_INTENSET_MASK _U_(0x03FC) /**< \brief (USB_HOST_INTENSET) MASK Register */ 614 615 /* -------- USB_DEVICE_INTFLAG : (USB Offset: 0x01C) (R/W 16) DEVICE DEVICE Device Interrupt Flag -------- */ 616 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 617 typedef union { // __I to avoid read-modify-write on write-to-clear register 618 struct { 619 __I uint16_t SUSPEND:1; /*!< bit: 0 Suspend */ 620 __I uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame in High Speed Mode */ 621 __I uint16_t SOF:1; /*!< bit: 2 Start Of Frame */ 622 __I uint16_t EORST:1; /*!< bit: 3 End of Reset */ 623 __I uint16_t WAKEUP:1; /*!< bit: 4 Wake Up */ 624 __I uint16_t EORSM:1; /*!< bit: 5 End Of Resume */ 625 __I uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume */ 626 __I uint16_t RAMACER:1; /*!< bit: 7 Ram Access */ 627 __I uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet */ 628 __I uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend */ 629 __I uint16_t :6; /*!< bit: 10..15 Reserved */ 630 } bit; /*!< Structure used for bit access */ 631 uint16_t reg; /*!< Type used for register access */ 632 } USB_DEVICE_INTFLAG_Type; 633 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 634 635 #define USB_DEVICE_INTFLAG_OFFSET 0x01C /**< \brief (USB_DEVICE_INTFLAG offset) DEVICE Device Interrupt Flag */ 636 #define USB_DEVICE_INTFLAG_RESETVALUE _U_(0x0000) /**< \brief (USB_DEVICE_INTFLAG reset_value) DEVICE Device Interrupt Flag */ 637 638 #define USB_DEVICE_INTFLAG_SUSPEND_Pos 0 /**< \brief (USB_DEVICE_INTFLAG) Suspend */ 639 #define USB_DEVICE_INTFLAG_SUSPEND (_U_(0x1) << USB_DEVICE_INTFLAG_SUSPEND_Pos) 640 #define USB_DEVICE_INTFLAG_MSOF_Pos 1 /**< \brief (USB_DEVICE_INTFLAG) Micro Start of Frame in High Speed Mode */ 641 #define USB_DEVICE_INTFLAG_MSOF (_U_(0x1) << USB_DEVICE_INTFLAG_MSOF_Pos) 642 #define USB_DEVICE_INTFLAG_SOF_Pos 2 /**< \brief (USB_DEVICE_INTFLAG) Start Of Frame */ 643 #define USB_DEVICE_INTFLAG_SOF (_U_(0x1) << USB_DEVICE_INTFLAG_SOF_Pos) 644 #define USB_DEVICE_INTFLAG_EORST_Pos 3 /**< \brief (USB_DEVICE_INTFLAG) End of Reset */ 645 #define USB_DEVICE_INTFLAG_EORST (_U_(0x1) << USB_DEVICE_INTFLAG_EORST_Pos) 646 #define USB_DEVICE_INTFLAG_WAKEUP_Pos 4 /**< \brief (USB_DEVICE_INTFLAG) Wake Up */ 647 #define USB_DEVICE_INTFLAG_WAKEUP (_U_(0x1) << USB_DEVICE_INTFLAG_WAKEUP_Pos) 648 #define USB_DEVICE_INTFLAG_EORSM_Pos 5 /**< \brief (USB_DEVICE_INTFLAG) End Of Resume */ 649 #define USB_DEVICE_INTFLAG_EORSM (_U_(0x1) << USB_DEVICE_INTFLAG_EORSM_Pos) 650 #define USB_DEVICE_INTFLAG_UPRSM_Pos 6 /**< \brief (USB_DEVICE_INTFLAG) Upstream Resume */ 651 #define USB_DEVICE_INTFLAG_UPRSM (_U_(0x1) << USB_DEVICE_INTFLAG_UPRSM_Pos) 652 #define USB_DEVICE_INTFLAG_RAMACER_Pos 7 /**< \brief (USB_DEVICE_INTFLAG) Ram Access */ 653 #define USB_DEVICE_INTFLAG_RAMACER (_U_(0x1) << USB_DEVICE_INTFLAG_RAMACER_Pos) 654 #define USB_DEVICE_INTFLAG_LPMNYET_Pos 8 /**< \brief (USB_DEVICE_INTFLAG) Link Power Management Not Yet */ 655 #define USB_DEVICE_INTFLAG_LPMNYET (_U_(0x1) << USB_DEVICE_INTFLAG_LPMNYET_Pos) 656 #define USB_DEVICE_INTFLAG_LPMSUSP_Pos 9 /**< \brief (USB_DEVICE_INTFLAG) Link Power Management Suspend */ 657 #define USB_DEVICE_INTFLAG_LPMSUSP (_U_(0x1) << USB_DEVICE_INTFLAG_LPMSUSP_Pos) 658 #define USB_DEVICE_INTFLAG_MASK _U_(0x03FF) /**< \brief (USB_DEVICE_INTFLAG) MASK Register */ 659 660 /* -------- USB_HOST_INTFLAG : (USB Offset: 0x01C) (R/W 16) HOST HOST Host Interrupt Flag -------- */ 661 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 662 typedef union { // __I to avoid read-modify-write on write-to-clear register 663 struct { 664 __I uint16_t :2; /*!< bit: 0.. 1 Reserved */ 665 __I uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame */ 666 __I uint16_t RST:1; /*!< bit: 3 Bus Reset */ 667 __I uint16_t WAKEUP:1; /*!< bit: 4 Wake Up */ 668 __I uint16_t DNRSM:1; /*!< bit: 5 Downstream */ 669 __I uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume from the Device */ 670 __I uint16_t RAMACER:1; /*!< bit: 7 Ram Access */ 671 __I uint16_t DCONN:1; /*!< bit: 8 Device Connection */ 672 __I uint16_t DDISC:1; /*!< bit: 9 Device Disconnection */ 673 __I uint16_t :6; /*!< bit: 10..15 Reserved */ 674 } bit; /*!< Structure used for bit access */ 675 uint16_t reg; /*!< Type used for register access */ 676 } USB_HOST_INTFLAG_Type; 677 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 678 679 #define USB_HOST_INTFLAG_OFFSET 0x01C /**< \brief (USB_HOST_INTFLAG offset) HOST Host Interrupt Flag */ 680 #define USB_HOST_INTFLAG_RESETVALUE _U_(0x0000) /**< \brief (USB_HOST_INTFLAG reset_value) HOST Host Interrupt Flag */ 681 682 #define USB_HOST_INTFLAG_HSOF_Pos 2 /**< \brief (USB_HOST_INTFLAG) Host Start Of Frame */ 683 #define USB_HOST_INTFLAG_HSOF (_U_(0x1) << USB_HOST_INTFLAG_HSOF_Pos) 684 #define USB_HOST_INTFLAG_RST_Pos 3 /**< \brief (USB_HOST_INTFLAG) Bus Reset */ 685 #define USB_HOST_INTFLAG_RST (_U_(0x1) << USB_HOST_INTFLAG_RST_Pos) 686 #define USB_HOST_INTFLAG_WAKEUP_Pos 4 /**< \brief (USB_HOST_INTFLAG) Wake Up */ 687 #define USB_HOST_INTFLAG_WAKEUP (_U_(0x1) << USB_HOST_INTFLAG_WAKEUP_Pos) 688 #define USB_HOST_INTFLAG_DNRSM_Pos 5 /**< \brief (USB_HOST_INTFLAG) Downstream */ 689 #define USB_HOST_INTFLAG_DNRSM (_U_(0x1) << USB_HOST_INTFLAG_DNRSM_Pos) 690 #define USB_HOST_INTFLAG_UPRSM_Pos 6 /**< \brief (USB_HOST_INTFLAG) Upstream Resume from the Device */ 691 #define USB_HOST_INTFLAG_UPRSM (_U_(0x1) << USB_HOST_INTFLAG_UPRSM_Pos) 692 #define USB_HOST_INTFLAG_RAMACER_Pos 7 /**< \brief (USB_HOST_INTFLAG) Ram Access */ 693 #define USB_HOST_INTFLAG_RAMACER (_U_(0x1) << USB_HOST_INTFLAG_RAMACER_Pos) 694 #define USB_HOST_INTFLAG_DCONN_Pos 8 /**< \brief (USB_HOST_INTFLAG) Device Connection */ 695 #define USB_HOST_INTFLAG_DCONN (_U_(0x1) << USB_HOST_INTFLAG_DCONN_Pos) 696 #define USB_HOST_INTFLAG_DDISC_Pos 9 /**< \brief (USB_HOST_INTFLAG) Device Disconnection */ 697 #define USB_HOST_INTFLAG_DDISC (_U_(0x1) << USB_HOST_INTFLAG_DDISC_Pos) 698 #define USB_HOST_INTFLAG_MASK _U_(0x03FC) /**< \brief (USB_HOST_INTFLAG) MASK Register */ 699 700 /* -------- USB_DEVICE_EPINTSMRY : (USB Offset: 0x020) (R/ 16) DEVICE DEVICE End Point Interrupt Summary -------- */ 701 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 702 typedef union { 703 struct { 704 uint16_t EPINT0:1; /*!< bit: 0 End Point 0 Interrupt */ 705 uint16_t EPINT1:1; /*!< bit: 1 End Point 1 Interrupt */ 706 uint16_t EPINT2:1; /*!< bit: 2 End Point 2 Interrupt */ 707 uint16_t EPINT3:1; /*!< bit: 3 End Point 3 Interrupt */ 708 uint16_t EPINT4:1; /*!< bit: 4 End Point 4 Interrupt */ 709 uint16_t EPINT5:1; /*!< bit: 5 End Point 5 Interrupt */ 710 uint16_t EPINT6:1; /*!< bit: 6 End Point 6 Interrupt */ 711 uint16_t EPINT7:1; /*!< bit: 7 End Point 7 Interrupt */ 712 uint16_t :8; /*!< bit: 8..15 Reserved */ 713 } bit; /*!< Structure used for bit access */ 714 struct { 715 uint16_t EPINT:8; /*!< bit: 0.. 7 End Point x Interrupt */ 716 uint16_t :8; /*!< bit: 8..15 Reserved */ 717 } vec; /*!< Structure used for vec access */ 718 uint16_t reg; /*!< Type used for register access */ 719 } USB_DEVICE_EPINTSMRY_Type; 720 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 721 722 #define USB_DEVICE_EPINTSMRY_OFFSET 0x020 /**< \brief (USB_DEVICE_EPINTSMRY offset) DEVICE End Point Interrupt Summary */ 723 #define USB_DEVICE_EPINTSMRY_RESETVALUE _U_(0x0000) /**< \brief (USB_DEVICE_EPINTSMRY reset_value) DEVICE End Point Interrupt Summary */ 724 725 #define USB_DEVICE_EPINTSMRY_EPINT0_Pos 0 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 0 Interrupt */ 726 #define USB_DEVICE_EPINTSMRY_EPINT0 (1 << USB_DEVICE_EPINTSMRY_EPINT0_Pos) 727 #define USB_DEVICE_EPINTSMRY_EPINT1_Pos 1 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 1 Interrupt */ 728 #define USB_DEVICE_EPINTSMRY_EPINT1 (1 << USB_DEVICE_EPINTSMRY_EPINT1_Pos) 729 #define USB_DEVICE_EPINTSMRY_EPINT2_Pos 2 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 2 Interrupt */ 730 #define USB_DEVICE_EPINTSMRY_EPINT2 (1 << USB_DEVICE_EPINTSMRY_EPINT2_Pos) 731 #define USB_DEVICE_EPINTSMRY_EPINT3_Pos 3 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 3 Interrupt */ 732 #define USB_DEVICE_EPINTSMRY_EPINT3 (1 << USB_DEVICE_EPINTSMRY_EPINT3_Pos) 733 #define USB_DEVICE_EPINTSMRY_EPINT4_Pos 4 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 4 Interrupt */ 734 #define USB_DEVICE_EPINTSMRY_EPINT4 (1 << USB_DEVICE_EPINTSMRY_EPINT4_Pos) 735 #define USB_DEVICE_EPINTSMRY_EPINT5_Pos 5 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 5 Interrupt */ 736 #define USB_DEVICE_EPINTSMRY_EPINT5 (1 << USB_DEVICE_EPINTSMRY_EPINT5_Pos) 737 #define USB_DEVICE_EPINTSMRY_EPINT6_Pos 6 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 6 Interrupt */ 738 #define USB_DEVICE_EPINTSMRY_EPINT6 (1 << USB_DEVICE_EPINTSMRY_EPINT6_Pos) 739 #define USB_DEVICE_EPINTSMRY_EPINT7_Pos 7 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 7 Interrupt */ 740 #define USB_DEVICE_EPINTSMRY_EPINT7 (1 << USB_DEVICE_EPINTSMRY_EPINT7_Pos) 741 #define USB_DEVICE_EPINTSMRY_EPINT_Pos 0 /**< \brief (USB_DEVICE_EPINTSMRY) End Point x Interrupt */ 742 #define USB_DEVICE_EPINTSMRY_EPINT_Msk (_U_(0xFF) << USB_DEVICE_EPINTSMRY_EPINT_Pos) 743 #define USB_DEVICE_EPINTSMRY_EPINT(value) (USB_DEVICE_EPINTSMRY_EPINT_Msk & ((value) << USB_DEVICE_EPINTSMRY_EPINT_Pos)) 744 #define USB_DEVICE_EPINTSMRY_MASK _U_(0x00FF) /**< \brief (USB_DEVICE_EPINTSMRY) MASK Register */ 745 746 /* -------- USB_HOST_PINTSMRY : (USB Offset: 0x020) (R/ 16) HOST HOST Pipe Interrupt Summary -------- */ 747 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 748 typedef union { 749 struct { 750 uint16_t EPINT0:1; /*!< bit: 0 Pipe 0 Interrupt */ 751 uint16_t EPINT1:1; /*!< bit: 1 Pipe 1 Interrupt */ 752 uint16_t EPINT2:1; /*!< bit: 2 Pipe 2 Interrupt */ 753 uint16_t EPINT3:1; /*!< bit: 3 Pipe 3 Interrupt */ 754 uint16_t EPINT4:1; /*!< bit: 4 Pipe 4 Interrupt */ 755 uint16_t EPINT5:1; /*!< bit: 5 Pipe 5 Interrupt */ 756 uint16_t EPINT6:1; /*!< bit: 6 Pipe 6 Interrupt */ 757 uint16_t EPINT7:1; /*!< bit: 7 Pipe 7 Interrupt */ 758 uint16_t :8; /*!< bit: 8..15 Reserved */ 759 } bit; /*!< Structure used for bit access */ 760 struct { 761 uint16_t EPINT:8; /*!< bit: 0.. 7 Pipe x Interrupt */ 762 uint16_t :8; /*!< bit: 8..15 Reserved */ 763 } vec; /*!< Structure used for vec access */ 764 uint16_t reg; /*!< Type used for register access */ 765 } USB_HOST_PINTSMRY_Type; 766 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 767 768 #define USB_HOST_PINTSMRY_OFFSET 0x020 /**< \brief (USB_HOST_PINTSMRY offset) HOST Pipe Interrupt Summary */ 769 #define USB_HOST_PINTSMRY_RESETVALUE _U_(0x0000) /**< \brief (USB_HOST_PINTSMRY reset_value) HOST Pipe Interrupt Summary */ 770 771 #define USB_HOST_PINTSMRY_EPINT0_Pos 0 /**< \brief (USB_HOST_PINTSMRY) Pipe 0 Interrupt */ 772 #define USB_HOST_PINTSMRY_EPINT0 (1 << USB_HOST_PINTSMRY_EPINT0_Pos) 773 #define USB_HOST_PINTSMRY_EPINT1_Pos 1 /**< \brief (USB_HOST_PINTSMRY) Pipe 1 Interrupt */ 774 #define USB_HOST_PINTSMRY_EPINT1 (1 << USB_HOST_PINTSMRY_EPINT1_Pos) 775 #define USB_HOST_PINTSMRY_EPINT2_Pos 2 /**< \brief (USB_HOST_PINTSMRY) Pipe 2 Interrupt */ 776 #define USB_HOST_PINTSMRY_EPINT2 (1 << USB_HOST_PINTSMRY_EPINT2_Pos) 777 #define USB_HOST_PINTSMRY_EPINT3_Pos 3 /**< \brief (USB_HOST_PINTSMRY) Pipe 3 Interrupt */ 778 #define USB_HOST_PINTSMRY_EPINT3 (1 << USB_HOST_PINTSMRY_EPINT3_Pos) 779 #define USB_HOST_PINTSMRY_EPINT4_Pos 4 /**< \brief (USB_HOST_PINTSMRY) Pipe 4 Interrupt */ 780 #define USB_HOST_PINTSMRY_EPINT4 (1 << USB_HOST_PINTSMRY_EPINT4_Pos) 781 #define USB_HOST_PINTSMRY_EPINT5_Pos 5 /**< \brief (USB_HOST_PINTSMRY) Pipe 5 Interrupt */ 782 #define USB_HOST_PINTSMRY_EPINT5 (1 << USB_HOST_PINTSMRY_EPINT5_Pos) 783 #define USB_HOST_PINTSMRY_EPINT6_Pos 6 /**< \brief (USB_HOST_PINTSMRY) Pipe 6 Interrupt */ 784 #define USB_HOST_PINTSMRY_EPINT6 (1 << USB_HOST_PINTSMRY_EPINT6_Pos) 785 #define USB_HOST_PINTSMRY_EPINT7_Pos 7 /**< \brief (USB_HOST_PINTSMRY) Pipe 7 Interrupt */ 786 #define USB_HOST_PINTSMRY_EPINT7 (1 << USB_HOST_PINTSMRY_EPINT7_Pos) 787 #define USB_HOST_PINTSMRY_EPINT_Pos 0 /**< \brief (USB_HOST_PINTSMRY) Pipe x Interrupt */ 788 #define USB_HOST_PINTSMRY_EPINT_Msk (_U_(0xFF) << USB_HOST_PINTSMRY_EPINT_Pos) 789 #define USB_HOST_PINTSMRY_EPINT(value) (USB_HOST_PINTSMRY_EPINT_Msk & ((value) << USB_HOST_PINTSMRY_EPINT_Pos)) 790 #define USB_HOST_PINTSMRY_MASK _U_(0x00FF) /**< \brief (USB_HOST_PINTSMRY) MASK Register */ 791 792 /* -------- USB_DESCADD : (USB Offset: 0x024) (R/W 32) Descriptor Address -------- */ 793 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 794 typedef union { 795 struct { 796 uint32_t DESCADD:32; /*!< bit: 0..31 Descriptor Address Value */ 797 } bit; /*!< Structure used for bit access */ 798 uint32_t reg; /*!< Type used for register access */ 799 } USB_DESCADD_Type; 800 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 801 802 #define USB_DESCADD_OFFSET 0x024 /**< \brief (USB_DESCADD offset) Descriptor Address */ 803 #define USB_DESCADD_RESETVALUE _U_(0x00000000) /**< \brief (USB_DESCADD reset_value) Descriptor Address */ 804 805 #define USB_DESCADD_DESCADD_Pos 0 /**< \brief (USB_DESCADD) Descriptor Address Value */ 806 #define USB_DESCADD_DESCADD_Msk (_U_(0xFFFFFFFF) << USB_DESCADD_DESCADD_Pos) 807 #define USB_DESCADD_DESCADD(value) (USB_DESCADD_DESCADD_Msk & ((value) << USB_DESCADD_DESCADD_Pos)) 808 #define USB_DESCADD_MASK _U_(0xFFFFFFFF) /**< \brief (USB_DESCADD) MASK Register */ 809 810 /* -------- USB_PADCAL : (USB Offset: 0x028) (R/W 16) USB PAD Calibration -------- */ 811 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 812 typedef union { 813 struct { 814 uint16_t TRANSP:5; /*!< bit: 0.. 4 USB Pad Transp calibration */ 815 uint16_t :1; /*!< bit: 5 Reserved */ 816 uint16_t TRANSN:5; /*!< bit: 6..10 USB Pad Transn calibration */ 817 uint16_t :1; /*!< bit: 11 Reserved */ 818 uint16_t TRIM:3; /*!< bit: 12..14 USB Pad Trim calibration */ 819 uint16_t :1; /*!< bit: 15 Reserved */ 820 } bit; /*!< Structure used for bit access */ 821 uint16_t reg; /*!< Type used for register access */ 822 } USB_PADCAL_Type; 823 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 824 825 #define USB_PADCAL_OFFSET 0x028 /**< \brief (USB_PADCAL offset) USB PAD Calibration */ 826 #define USB_PADCAL_RESETVALUE _U_(0x0000) /**< \brief (USB_PADCAL reset_value) USB PAD Calibration */ 827 828 #define USB_PADCAL_TRANSP_Pos 0 /**< \brief (USB_PADCAL) USB Pad Transp calibration */ 829 #define USB_PADCAL_TRANSP_Msk (_U_(0x1F) << USB_PADCAL_TRANSP_Pos) 830 #define USB_PADCAL_TRANSP(value) (USB_PADCAL_TRANSP_Msk & ((value) << USB_PADCAL_TRANSP_Pos)) 831 #define USB_PADCAL_TRANSN_Pos 6 /**< \brief (USB_PADCAL) USB Pad Transn calibration */ 832 #define USB_PADCAL_TRANSN_Msk (_U_(0x1F) << USB_PADCAL_TRANSN_Pos) 833 #define USB_PADCAL_TRANSN(value) (USB_PADCAL_TRANSN_Msk & ((value) << USB_PADCAL_TRANSN_Pos)) 834 #define USB_PADCAL_TRIM_Pos 12 /**< \brief (USB_PADCAL) USB Pad Trim calibration */ 835 #define USB_PADCAL_TRIM_Msk (_U_(0x7) << USB_PADCAL_TRIM_Pos) 836 #define USB_PADCAL_TRIM(value) (USB_PADCAL_TRIM_Msk & ((value) << USB_PADCAL_TRIM_Pos)) 837 #define USB_PADCAL_MASK _U_(0x77DF) /**< \brief (USB_PADCAL) MASK Register */ 838 839 /* -------- USB_DEVICE_EPCFG : (USB Offset: 0x100) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Configuration -------- */ 840 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 841 typedef union { 842 struct { 843 uint8_t EPTYPE0:3; /*!< bit: 0.. 2 End Point Type0 */ 844 uint8_t :1; /*!< bit: 3 Reserved */ 845 uint8_t EPTYPE1:3; /*!< bit: 4.. 6 End Point Type1 */ 846 uint8_t NYETDIS:1; /*!< bit: 7 NYET Token Disable */ 847 } bit; /*!< Structure used for bit access */ 848 uint8_t reg; /*!< Type used for register access */ 849 } USB_DEVICE_EPCFG_Type; 850 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 851 852 #define USB_DEVICE_EPCFG_OFFSET 0x100 /**< \brief (USB_DEVICE_EPCFG offset) DEVICE_ENDPOINT End Point Configuration */ 853 #define USB_DEVICE_EPCFG_RESETVALUE _U_(0x00) /**< \brief (USB_DEVICE_EPCFG reset_value) DEVICE_ENDPOINT End Point Configuration */ 854 855 #define USB_DEVICE_EPCFG_EPTYPE0_Pos 0 /**< \brief (USB_DEVICE_EPCFG) End Point Type0 */ 856 #define USB_DEVICE_EPCFG_EPTYPE0_Msk (_U_(0x7) << USB_DEVICE_EPCFG_EPTYPE0_Pos) 857 #define USB_DEVICE_EPCFG_EPTYPE0(value) (USB_DEVICE_EPCFG_EPTYPE0_Msk & ((value) << USB_DEVICE_EPCFG_EPTYPE0_Pos)) 858 #define USB_DEVICE_EPCFG_EPTYPE1_Pos 4 /**< \brief (USB_DEVICE_EPCFG) End Point Type1 */ 859 #define USB_DEVICE_EPCFG_EPTYPE1_Msk (_U_(0x7) << USB_DEVICE_EPCFG_EPTYPE1_Pos) 860 #define USB_DEVICE_EPCFG_EPTYPE1(value) (USB_DEVICE_EPCFG_EPTYPE1_Msk & ((value) << USB_DEVICE_EPCFG_EPTYPE1_Pos)) 861 #define USB_DEVICE_EPCFG_NYETDIS_Pos 7 /**< \brief (USB_DEVICE_EPCFG) NYET Token Disable */ 862 #define USB_DEVICE_EPCFG_NYETDIS (_U_(0x1) << USB_DEVICE_EPCFG_NYETDIS_Pos) 863 #define USB_DEVICE_EPCFG_MASK _U_(0xF7) /**< \brief (USB_DEVICE_EPCFG) MASK Register */ 864 865 /* -------- USB_HOST_PCFG : (USB Offset: 0x100) (R/W 8) HOST HOST_PIPE End Point Configuration -------- */ 866 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 867 typedef union { 868 struct { 869 uint8_t PTOKEN:2; /*!< bit: 0.. 1 Pipe Token */ 870 uint8_t BK:1; /*!< bit: 2 Pipe Bank */ 871 uint8_t PTYPE:3; /*!< bit: 3.. 5 Pipe Type */ 872 uint8_t :2; /*!< bit: 6.. 7 Reserved */ 873 } bit; /*!< Structure used for bit access */ 874 uint8_t reg; /*!< Type used for register access */ 875 } USB_HOST_PCFG_Type; 876 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 877 878 #define USB_HOST_PCFG_OFFSET 0x100 /**< \brief (USB_HOST_PCFG offset) HOST_PIPE End Point Configuration */ 879 #define USB_HOST_PCFG_RESETVALUE _U_(0x00) /**< \brief (USB_HOST_PCFG reset_value) HOST_PIPE End Point Configuration */ 880 881 #define USB_HOST_PCFG_PTOKEN_Pos 0 /**< \brief (USB_HOST_PCFG) Pipe Token */ 882 #define USB_HOST_PCFG_PTOKEN_Msk (_U_(0x3) << USB_HOST_PCFG_PTOKEN_Pos) 883 #define USB_HOST_PCFG_PTOKEN(value) (USB_HOST_PCFG_PTOKEN_Msk & ((value) << USB_HOST_PCFG_PTOKEN_Pos)) 884 #define USB_HOST_PCFG_BK_Pos 2 /**< \brief (USB_HOST_PCFG) Pipe Bank */ 885 #define USB_HOST_PCFG_BK (_U_(0x1) << USB_HOST_PCFG_BK_Pos) 886 #define USB_HOST_PCFG_PTYPE_Pos 3 /**< \brief (USB_HOST_PCFG) Pipe Type */ 887 #define USB_HOST_PCFG_PTYPE_Msk (_U_(0x7) << USB_HOST_PCFG_PTYPE_Pos) 888 #define USB_HOST_PCFG_PTYPE(value) (USB_HOST_PCFG_PTYPE_Msk & ((value) << USB_HOST_PCFG_PTYPE_Pos)) 889 #define USB_HOST_PCFG_MASK _U_(0x3F) /**< \brief (USB_HOST_PCFG) MASK Register */ 890 891 /* -------- USB_HOST_BINTERVAL : (USB Offset: 0x103) (R/W 8) HOST HOST_PIPE Bus Access Period of Pipe -------- */ 892 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 893 typedef union { 894 struct { 895 uint8_t BITINTERVAL:8; /*!< bit: 0.. 7 Bit Interval */ 896 } bit; /*!< Structure used for bit access */ 897 uint8_t reg; /*!< Type used for register access */ 898 } USB_HOST_BINTERVAL_Type; 899 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 900 901 #define USB_HOST_BINTERVAL_OFFSET 0x103 /**< \brief (USB_HOST_BINTERVAL offset) HOST_PIPE Bus Access Period of Pipe */ 902 #define USB_HOST_BINTERVAL_RESETVALUE _U_(0x00) /**< \brief (USB_HOST_BINTERVAL reset_value) HOST_PIPE Bus Access Period of Pipe */ 903 904 #define USB_HOST_BINTERVAL_BITINTERVAL_Pos 0 /**< \brief (USB_HOST_BINTERVAL) Bit Interval */ 905 #define USB_HOST_BINTERVAL_BITINTERVAL_Msk (_U_(0xFF) << USB_HOST_BINTERVAL_BITINTERVAL_Pos) 906 #define USB_HOST_BINTERVAL_BITINTERVAL(value) (USB_HOST_BINTERVAL_BITINTERVAL_Msk & ((value) << USB_HOST_BINTERVAL_BITINTERVAL_Pos)) 907 #define USB_HOST_BINTERVAL_MASK _U_(0xFF) /**< \brief (USB_HOST_BINTERVAL) MASK Register */ 908 909 /* -------- USB_DEVICE_EPSTATUSCLR : (USB Offset: 0x104) ( /W 8) DEVICE DEVICE_ENDPOINT End Point Pipe Status Clear -------- */ 910 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 911 typedef union { 912 struct { 913 uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle OUT Clear */ 914 uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle IN Clear */ 915 uint8_t CURBK:1; /*!< bit: 2 Curren Bank Clear */ 916 uint8_t :1; /*!< bit: 3 Reserved */ 917 uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request Clear */ 918 uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request Clear */ 919 uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Clear */ 920 uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Clear */ 921 } bit; /*!< Structure used for bit access */ 922 struct { 923 uint8_t :4; /*!< bit: 0.. 3 Reserved */ 924 uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request Clear */ 925 uint8_t :2; /*!< bit: 6.. 7 Reserved */ 926 } vec; /*!< Structure used for vec access */ 927 uint8_t reg; /*!< Type used for register access */ 928 } USB_DEVICE_EPSTATUSCLR_Type; 929 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 930 931 #define USB_DEVICE_EPSTATUSCLR_OFFSET 0x104 /**< \brief (USB_DEVICE_EPSTATUSCLR offset) DEVICE_ENDPOINT End Point Pipe Status Clear */ 932 #define USB_DEVICE_EPSTATUSCLR_RESETVALUE _U_(0x00) /**< \brief (USB_DEVICE_EPSTATUSCLR reset_value) DEVICE_ENDPOINT End Point Pipe Status Clear */ 933 934 #define USB_DEVICE_EPSTATUSCLR_DTGLOUT_Pos 0 /**< \brief (USB_DEVICE_EPSTATUSCLR) Data Toggle OUT Clear */ 935 #define USB_DEVICE_EPSTATUSCLR_DTGLOUT (_U_(0x1) << USB_DEVICE_EPSTATUSCLR_DTGLOUT_Pos) 936 #define USB_DEVICE_EPSTATUSCLR_DTGLIN_Pos 1 /**< \brief (USB_DEVICE_EPSTATUSCLR) Data Toggle IN Clear */ 937 #define USB_DEVICE_EPSTATUSCLR_DTGLIN (_U_(0x1) << USB_DEVICE_EPSTATUSCLR_DTGLIN_Pos) 938 #define USB_DEVICE_EPSTATUSCLR_CURBK_Pos 2 /**< \brief (USB_DEVICE_EPSTATUSCLR) Curren Bank Clear */ 939 #define USB_DEVICE_EPSTATUSCLR_CURBK (_U_(0x1) << USB_DEVICE_EPSTATUSCLR_CURBK_Pos) 940 #define USB_DEVICE_EPSTATUSCLR_STALLRQ0_Pos 4 /**< \brief (USB_DEVICE_EPSTATUSCLR) Stall 0 Request Clear */ 941 #define USB_DEVICE_EPSTATUSCLR_STALLRQ0 (1 << USB_DEVICE_EPSTATUSCLR_STALLRQ0_Pos) 942 #define USB_DEVICE_EPSTATUSCLR_STALLRQ1_Pos 5 /**< \brief (USB_DEVICE_EPSTATUSCLR) Stall 1 Request Clear */ 943 #define USB_DEVICE_EPSTATUSCLR_STALLRQ1 (1 << USB_DEVICE_EPSTATUSCLR_STALLRQ1_Pos) 944 #define USB_DEVICE_EPSTATUSCLR_STALLRQ_Pos 4 /**< \brief (USB_DEVICE_EPSTATUSCLR) Stall x Request Clear */ 945 #define USB_DEVICE_EPSTATUSCLR_STALLRQ_Msk (_U_(0x3) << USB_DEVICE_EPSTATUSCLR_STALLRQ_Pos) 946 #define USB_DEVICE_EPSTATUSCLR_STALLRQ(value) (USB_DEVICE_EPSTATUSCLR_STALLRQ_Msk & ((value) << USB_DEVICE_EPSTATUSCLR_STALLRQ_Pos)) 947 #define USB_DEVICE_EPSTATUSCLR_BK0RDY_Pos 6 /**< \brief (USB_DEVICE_EPSTATUSCLR) Bank 0 Ready Clear */ 948 #define USB_DEVICE_EPSTATUSCLR_BK0RDY (_U_(0x1) << USB_DEVICE_EPSTATUSCLR_BK0RDY_Pos) 949 #define USB_DEVICE_EPSTATUSCLR_BK1RDY_Pos 7 /**< \brief (USB_DEVICE_EPSTATUSCLR) Bank 1 Ready Clear */ 950 #define USB_DEVICE_EPSTATUSCLR_BK1RDY (_U_(0x1) << USB_DEVICE_EPSTATUSCLR_BK1RDY_Pos) 951 #define USB_DEVICE_EPSTATUSCLR_MASK _U_(0xF7) /**< \brief (USB_DEVICE_EPSTATUSCLR) MASK Register */ 952 953 /* -------- USB_HOST_PSTATUSCLR : (USB Offset: 0x104) ( /W 8) HOST HOST_PIPE End Point Pipe Status Clear -------- */ 954 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 955 typedef union { 956 struct { 957 uint8_t DTGL:1; /*!< bit: 0 Data Toggle clear */ 958 uint8_t :1; /*!< bit: 1 Reserved */ 959 uint8_t CURBK:1; /*!< bit: 2 Curren Bank clear */ 960 uint8_t :1; /*!< bit: 3 Reserved */ 961 uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze Clear */ 962 uint8_t :1; /*!< bit: 5 Reserved */ 963 uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Clear */ 964 uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Clear */ 965 } bit; /*!< Structure used for bit access */ 966 uint8_t reg; /*!< Type used for register access */ 967 } USB_HOST_PSTATUSCLR_Type; 968 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 969 970 #define USB_HOST_PSTATUSCLR_OFFSET 0x104 /**< \brief (USB_HOST_PSTATUSCLR offset) HOST_PIPE End Point Pipe Status Clear */ 971 #define USB_HOST_PSTATUSCLR_RESETVALUE _U_(0x00) /**< \brief (USB_HOST_PSTATUSCLR reset_value) HOST_PIPE End Point Pipe Status Clear */ 972 973 #define USB_HOST_PSTATUSCLR_DTGL_Pos 0 /**< \brief (USB_HOST_PSTATUSCLR) Data Toggle clear */ 974 #define USB_HOST_PSTATUSCLR_DTGL (_U_(0x1) << USB_HOST_PSTATUSCLR_DTGL_Pos) 975 #define USB_HOST_PSTATUSCLR_CURBK_Pos 2 /**< \brief (USB_HOST_PSTATUSCLR) Curren Bank clear */ 976 #define USB_HOST_PSTATUSCLR_CURBK (_U_(0x1) << USB_HOST_PSTATUSCLR_CURBK_Pos) 977 #define USB_HOST_PSTATUSCLR_PFREEZE_Pos 4 /**< \brief (USB_HOST_PSTATUSCLR) Pipe Freeze Clear */ 978 #define USB_HOST_PSTATUSCLR_PFREEZE (_U_(0x1) << USB_HOST_PSTATUSCLR_PFREEZE_Pos) 979 #define USB_HOST_PSTATUSCLR_BK0RDY_Pos 6 /**< \brief (USB_HOST_PSTATUSCLR) Bank 0 Ready Clear */ 980 #define USB_HOST_PSTATUSCLR_BK0RDY (_U_(0x1) << USB_HOST_PSTATUSCLR_BK0RDY_Pos) 981 #define USB_HOST_PSTATUSCLR_BK1RDY_Pos 7 /**< \brief (USB_HOST_PSTATUSCLR) Bank 1 Ready Clear */ 982 #define USB_HOST_PSTATUSCLR_BK1RDY (_U_(0x1) << USB_HOST_PSTATUSCLR_BK1RDY_Pos) 983 #define USB_HOST_PSTATUSCLR_MASK _U_(0xD5) /**< \brief (USB_HOST_PSTATUSCLR) MASK Register */ 984 985 /* -------- USB_DEVICE_EPSTATUSSET : (USB Offset: 0x105) ( /W 8) DEVICE DEVICE_ENDPOINT End Point Pipe Status Set -------- */ 986 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 987 typedef union { 988 struct { 989 uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle OUT Set */ 990 uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle IN Set */ 991 uint8_t CURBK:1; /*!< bit: 2 Current Bank Set */ 992 uint8_t :1; /*!< bit: 3 Reserved */ 993 uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request Set */ 994 uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request Set */ 995 uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Set */ 996 uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Set */ 997 } bit; /*!< Structure used for bit access */ 998 struct { 999 uint8_t :4; /*!< bit: 0.. 3 Reserved */ 1000 uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request Set */ 1001 uint8_t :2; /*!< bit: 6.. 7 Reserved */ 1002 } vec; /*!< Structure used for vec access */ 1003 uint8_t reg; /*!< Type used for register access */ 1004 } USB_DEVICE_EPSTATUSSET_Type; 1005 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1006 1007 #define USB_DEVICE_EPSTATUSSET_OFFSET 0x105 /**< \brief (USB_DEVICE_EPSTATUSSET offset) DEVICE_ENDPOINT End Point Pipe Status Set */ 1008 #define USB_DEVICE_EPSTATUSSET_RESETVALUE _U_(0x00) /**< \brief (USB_DEVICE_EPSTATUSSET reset_value) DEVICE_ENDPOINT End Point Pipe Status Set */ 1009 1010 #define USB_DEVICE_EPSTATUSSET_DTGLOUT_Pos 0 /**< \brief (USB_DEVICE_EPSTATUSSET) Data Toggle OUT Set */ 1011 #define USB_DEVICE_EPSTATUSSET_DTGLOUT (_U_(0x1) << USB_DEVICE_EPSTATUSSET_DTGLOUT_Pos) 1012 #define USB_DEVICE_EPSTATUSSET_DTGLIN_Pos 1 /**< \brief (USB_DEVICE_EPSTATUSSET) Data Toggle IN Set */ 1013 #define USB_DEVICE_EPSTATUSSET_DTGLIN (_U_(0x1) << USB_DEVICE_EPSTATUSSET_DTGLIN_Pos) 1014 #define USB_DEVICE_EPSTATUSSET_CURBK_Pos 2 /**< \brief (USB_DEVICE_EPSTATUSSET) Current Bank Set */ 1015 #define USB_DEVICE_EPSTATUSSET_CURBK (_U_(0x1) << USB_DEVICE_EPSTATUSSET_CURBK_Pos) 1016 #define USB_DEVICE_EPSTATUSSET_STALLRQ0_Pos 4 /**< \brief (USB_DEVICE_EPSTATUSSET) Stall 0 Request Set */ 1017 #define USB_DEVICE_EPSTATUSSET_STALLRQ0 (1 << USB_DEVICE_EPSTATUSSET_STALLRQ0_Pos) 1018 #define USB_DEVICE_EPSTATUSSET_STALLRQ1_Pos 5 /**< \brief (USB_DEVICE_EPSTATUSSET) Stall 1 Request Set */ 1019 #define USB_DEVICE_EPSTATUSSET_STALLRQ1 (1 << USB_DEVICE_EPSTATUSSET_STALLRQ1_Pos) 1020 #define USB_DEVICE_EPSTATUSSET_STALLRQ_Pos 4 /**< \brief (USB_DEVICE_EPSTATUSSET) Stall x Request Set */ 1021 #define USB_DEVICE_EPSTATUSSET_STALLRQ_Msk (_U_(0x3) << USB_DEVICE_EPSTATUSSET_STALLRQ_Pos) 1022 #define USB_DEVICE_EPSTATUSSET_STALLRQ(value) (USB_DEVICE_EPSTATUSSET_STALLRQ_Msk & ((value) << USB_DEVICE_EPSTATUSSET_STALLRQ_Pos)) 1023 #define USB_DEVICE_EPSTATUSSET_BK0RDY_Pos 6 /**< \brief (USB_DEVICE_EPSTATUSSET) Bank 0 Ready Set */ 1024 #define USB_DEVICE_EPSTATUSSET_BK0RDY (_U_(0x1) << USB_DEVICE_EPSTATUSSET_BK0RDY_Pos) 1025 #define USB_DEVICE_EPSTATUSSET_BK1RDY_Pos 7 /**< \brief (USB_DEVICE_EPSTATUSSET) Bank 1 Ready Set */ 1026 #define USB_DEVICE_EPSTATUSSET_BK1RDY (_U_(0x1) << USB_DEVICE_EPSTATUSSET_BK1RDY_Pos) 1027 #define USB_DEVICE_EPSTATUSSET_MASK _U_(0xF7) /**< \brief (USB_DEVICE_EPSTATUSSET) MASK Register */ 1028 1029 /* -------- USB_HOST_PSTATUSSET : (USB Offset: 0x105) ( /W 8) HOST HOST_PIPE End Point Pipe Status Set -------- */ 1030 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1031 typedef union { 1032 struct { 1033 uint8_t DTGL:1; /*!< bit: 0 Data Toggle Set */ 1034 uint8_t :1; /*!< bit: 1 Reserved */ 1035 uint8_t CURBK:1; /*!< bit: 2 Current Bank Set */ 1036 uint8_t :1; /*!< bit: 3 Reserved */ 1037 uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze Set */ 1038 uint8_t :1; /*!< bit: 5 Reserved */ 1039 uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Set */ 1040 uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Set */ 1041 } bit; /*!< Structure used for bit access */ 1042 uint8_t reg; /*!< Type used for register access */ 1043 } USB_HOST_PSTATUSSET_Type; 1044 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1045 1046 #define USB_HOST_PSTATUSSET_OFFSET 0x105 /**< \brief (USB_HOST_PSTATUSSET offset) HOST_PIPE End Point Pipe Status Set */ 1047 #define USB_HOST_PSTATUSSET_RESETVALUE _U_(0x00) /**< \brief (USB_HOST_PSTATUSSET reset_value) HOST_PIPE End Point Pipe Status Set */ 1048 1049 #define USB_HOST_PSTATUSSET_DTGL_Pos 0 /**< \brief (USB_HOST_PSTATUSSET) Data Toggle Set */ 1050 #define USB_HOST_PSTATUSSET_DTGL (_U_(0x1) << USB_HOST_PSTATUSSET_DTGL_Pos) 1051 #define USB_HOST_PSTATUSSET_CURBK_Pos 2 /**< \brief (USB_HOST_PSTATUSSET) Current Bank Set */ 1052 #define USB_HOST_PSTATUSSET_CURBK (_U_(0x1) << USB_HOST_PSTATUSSET_CURBK_Pos) 1053 #define USB_HOST_PSTATUSSET_PFREEZE_Pos 4 /**< \brief (USB_HOST_PSTATUSSET) Pipe Freeze Set */ 1054 #define USB_HOST_PSTATUSSET_PFREEZE (_U_(0x1) << USB_HOST_PSTATUSSET_PFREEZE_Pos) 1055 #define USB_HOST_PSTATUSSET_BK0RDY_Pos 6 /**< \brief (USB_HOST_PSTATUSSET) Bank 0 Ready Set */ 1056 #define USB_HOST_PSTATUSSET_BK0RDY (_U_(0x1) << USB_HOST_PSTATUSSET_BK0RDY_Pos) 1057 #define USB_HOST_PSTATUSSET_BK1RDY_Pos 7 /**< \brief (USB_HOST_PSTATUSSET) Bank 1 Ready Set */ 1058 #define USB_HOST_PSTATUSSET_BK1RDY (_U_(0x1) << USB_HOST_PSTATUSSET_BK1RDY_Pos) 1059 #define USB_HOST_PSTATUSSET_MASK _U_(0xD5) /**< \brief (USB_HOST_PSTATUSSET) MASK Register */ 1060 1061 /* -------- USB_DEVICE_EPSTATUS : (USB Offset: 0x106) (R/ 8) DEVICE DEVICE_ENDPOINT End Point Pipe Status -------- */ 1062 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1063 typedef union { 1064 struct { 1065 uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle Out */ 1066 uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle In */ 1067 uint8_t CURBK:1; /*!< bit: 2 Current Bank */ 1068 uint8_t :1; /*!< bit: 3 Reserved */ 1069 uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request */ 1070 uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request */ 1071 uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 ready */ 1072 uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 ready */ 1073 } bit; /*!< Structure used for bit access */ 1074 struct { 1075 uint8_t :4; /*!< bit: 0.. 3 Reserved */ 1076 uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request */ 1077 uint8_t :2; /*!< bit: 6.. 7 Reserved */ 1078 } vec; /*!< Structure used for vec access */ 1079 uint8_t reg; /*!< Type used for register access */ 1080 } USB_DEVICE_EPSTATUS_Type; 1081 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1082 1083 #define USB_DEVICE_EPSTATUS_OFFSET 0x106 /**< \brief (USB_DEVICE_EPSTATUS offset) DEVICE_ENDPOINT End Point Pipe Status */ 1084 #define USB_DEVICE_EPSTATUS_RESETVALUE _U_(0x00) /**< \brief (USB_DEVICE_EPSTATUS reset_value) DEVICE_ENDPOINT End Point Pipe Status */ 1085 1086 #define USB_DEVICE_EPSTATUS_DTGLOUT_Pos 0 /**< \brief (USB_DEVICE_EPSTATUS) Data Toggle Out */ 1087 #define USB_DEVICE_EPSTATUS_DTGLOUT (_U_(0x1) << USB_DEVICE_EPSTATUS_DTGLOUT_Pos) 1088 #define USB_DEVICE_EPSTATUS_DTGLIN_Pos 1 /**< \brief (USB_DEVICE_EPSTATUS) Data Toggle In */ 1089 #define USB_DEVICE_EPSTATUS_DTGLIN (_U_(0x1) << USB_DEVICE_EPSTATUS_DTGLIN_Pos) 1090 #define USB_DEVICE_EPSTATUS_CURBK_Pos 2 /**< \brief (USB_DEVICE_EPSTATUS) Current Bank */ 1091 #define USB_DEVICE_EPSTATUS_CURBK (_U_(0x1) << USB_DEVICE_EPSTATUS_CURBK_Pos) 1092 #define USB_DEVICE_EPSTATUS_STALLRQ0_Pos 4 /**< \brief (USB_DEVICE_EPSTATUS) Stall 0 Request */ 1093 #define USB_DEVICE_EPSTATUS_STALLRQ0 (1 << USB_DEVICE_EPSTATUS_STALLRQ0_Pos) 1094 #define USB_DEVICE_EPSTATUS_STALLRQ1_Pos 5 /**< \brief (USB_DEVICE_EPSTATUS) Stall 1 Request */ 1095 #define USB_DEVICE_EPSTATUS_STALLRQ1 (1 << USB_DEVICE_EPSTATUS_STALLRQ1_Pos) 1096 #define USB_DEVICE_EPSTATUS_STALLRQ_Pos 4 /**< \brief (USB_DEVICE_EPSTATUS) Stall x Request */ 1097 #define USB_DEVICE_EPSTATUS_STALLRQ_Msk (_U_(0x3) << USB_DEVICE_EPSTATUS_STALLRQ_Pos) 1098 #define USB_DEVICE_EPSTATUS_STALLRQ(value) (USB_DEVICE_EPSTATUS_STALLRQ_Msk & ((value) << USB_DEVICE_EPSTATUS_STALLRQ_Pos)) 1099 #define USB_DEVICE_EPSTATUS_BK0RDY_Pos 6 /**< \brief (USB_DEVICE_EPSTATUS) Bank 0 ready */ 1100 #define USB_DEVICE_EPSTATUS_BK0RDY (_U_(0x1) << USB_DEVICE_EPSTATUS_BK0RDY_Pos) 1101 #define USB_DEVICE_EPSTATUS_BK1RDY_Pos 7 /**< \brief (USB_DEVICE_EPSTATUS) Bank 1 ready */ 1102 #define USB_DEVICE_EPSTATUS_BK1RDY (_U_(0x1) << USB_DEVICE_EPSTATUS_BK1RDY_Pos) 1103 #define USB_DEVICE_EPSTATUS_MASK _U_(0xF7) /**< \brief (USB_DEVICE_EPSTATUS) MASK Register */ 1104 1105 /* -------- USB_HOST_PSTATUS : (USB Offset: 0x106) (R/ 8) HOST HOST_PIPE End Point Pipe Status -------- */ 1106 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1107 typedef union { 1108 struct { 1109 uint8_t DTGL:1; /*!< bit: 0 Data Toggle */ 1110 uint8_t :1; /*!< bit: 1 Reserved */ 1111 uint8_t CURBK:1; /*!< bit: 2 Current Bank */ 1112 uint8_t :1; /*!< bit: 3 Reserved */ 1113 uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze */ 1114 uint8_t :1; /*!< bit: 5 Reserved */ 1115 uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 ready */ 1116 uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 ready */ 1117 } bit; /*!< Structure used for bit access */ 1118 uint8_t reg; /*!< Type used for register access */ 1119 } USB_HOST_PSTATUS_Type; 1120 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1121 1122 #define USB_HOST_PSTATUS_OFFSET 0x106 /**< \brief (USB_HOST_PSTATUS offset) HOST_PIPE End Point Pipe Status */ 1123 #define USB_HOST_PSTATUS_RESETVALUE _U_(0x00) /**< \brief (USB_HOST_PSTATUS reset_value) HOST_PIPE End Point Pipe Status */ 1124 1125 #define USB_HOST_PSTATUS_DTGL_Pos 0 /**< \brief (USB_HOST_PSTATUS) Data Toggle */ 1126 #define USB_HOST_PSTATUS_DTGL (_U_(0x1) << USB_HOST_PSTATUS_DTGL_Pos) 1127 #define USB_HOST_PSTATUS_CURBK_Pos 2 /**< \brief (USB_HOST_PSTATUS) Current Bank */ 1128 #define USB_HOST_PSTATUS_CURBK (_U_(0x1) << USB_HOST_PSTATUS_CURBK_Pos) 1129 #define USB_HOST_PSTATUS_PFREEZE_Pos 4 /**< \brief (USB_HOST_PSTATUS) Pipe Freeze */ 1130 #define USB_HOST_PSTATUS_PFREEZE (_U_(0x1) << USB_HOST_PSTATUS_PFREEZE_Pos) 1131 #define USB_HOST_PSTATUS_BK0RDY_Pos 6 /**< \brief (USB_HOST_PSTATUS) Bank 0 ready */ 1132 #define USB_HOST_PSTATUS_BK0RDY (_U_(0x1) << USB_HOST_PSTATUS_BK0RDY_Pos) 1133 #define USB_HOST_PSTATUS_BK1RDY_Pos 7 /**< \brief (USB_HOST_PSTATUS) Bank 1 ready */ 1134 #define USB_HOST_PSTATUS_BK1RDY (_U_(0x1) << USB_HOST_PSTATUS_BK1RDY_Pos) 1135 #define USB_HOST_PSTATUS_MASK _U_(0xD5) /**< \brief (USB_HOST_PSTATUS) MASK Register */ 1136 1137 /* -------- USB_DEVICE_EPINTFLAG : (USB Offset: 0x107) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Interrupt Flag -------- */ 1138 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1139 typedef union { // __I to avoid read-modify-write on write-to-clear register 1140 struct { 1141 __I uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 */ 1142 __I uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 */ 1143 __I uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 */ 1144 __I uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 */ 1145 __I uint8_t RXSTP:1; /*!< bit: 4 Received Setup */ 1146 __I uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/out */ 1147 __I uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/out */ 1148 __I uint8_t :1; /*!< bit: 7 Reserved */ 1149 } bit; /*!< Structure used for bit access */ 1150 struct { 1151 __I uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x */ 1152 __I uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x */ 1153 __I uint8_t :1; /*!< bit: 4 Reserved */ 1154 __I uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/out */ 1155 __I uint8_t :1; /*!< bit: 7 Reserved */ 1156 } vec; /*!< Structure used for vec access */ 1157 uint8_t reg; /*!< Type used for register access */ 1158 } USB_DEVICE_EPINTFLAG_Type; 1159 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1160 1161 #define USB_DEVICE_EPINTFLAG_OFFSET 0x107 /**< \brief (USB_DEVICE_EPINTFLAG offset) DEVICE_ENDPOINT End Point Interrupt Flag */ 1162 #define USB_DEVICE_EPINTFLAG_RESETVALUE _U_(0x00) /**< \brief (USB_DEVICE_EPINTFLAG reset_value) DEVICE_ENDPOINT End Point Interrupt Flag */ 1163 1164 #define USB_DEVICE_EPINTFLAG_TRCPT0_Pos 0 /**< \brief (USB_DEVICE_EPINTFLAG) Transfer Complete 0 */ 1165 #define USB_DEVICE_EPINTFLAG_TRCPT0 (1 << USB_DEVICE_EPINTFLAG_TRCPT0_Pos) 1166 #define USB_DEVICE_EPINTFLAG_TRCPT1_Pos 1 /**< \brief (USB_DEVICE_EPINTFLAG) Transfer Complete 1 */ 1167 #define USB_DEVICE_EPINTFLAG_TRCPT1 (1 << USB_DEVICE_EPINTFLAG_TRCPT1_Pos) 1168 #define USB_DEVICE_EPINTFLAG_TRCPT_Pos 0 /**< \brief (USB_DEVICE_EPINTFLAG) Transfer Complete x */ 1169 #define USB_DEVICE_EPINTFLAG_TRCPT_Msk (_U_(0x3) << USB_DEVICE_EPINTFLAG_TRCPT_Pos) 1170 #define USB_DEVICE_EPINTFLAG_TRCPT(value) (USB_DEVICE_EPINTFLAG_TRCPT_Msk & ((value) << USB_DEVICE_EPINTFLAG_TRCPT_Pos)) 1171 #define USB_DEVICE_EPINTFLAG_TRFAIL0_Pos 2 /**< \brief (USB_DEVICE_EPINTFLAG) Error Flow 0 */ 1172 #define USB_DEVICE_EPINTFLAG_TRFAIL0 (1 << USB_DEVICE_EPINTFLAG_TRFAIL0_Pos) 1173 #define USB_DEVICE_EPINTFLAG_TRFAIL1_Pos 3 /**< \brief (USB_DEVICE_EPINTFLAG) Error Flow 1 */ 1174 #define USB_DEVICE_EPINTFLAG_TRFAIL1 (1 << USB_DEVICE_EPINTFLAG_TRFAIL1_Pos) 1175 #define USB_DEVICE_EPINTFLAG_TRFAIL_Pos 2 /**< \brief (USB_DEVICE_EPINTFLAG) Error Flow x */ 1176 #define USB_DEVICE_EPINTFLAG_TRFAIL_Msk (_U_(0x3) << USB_DEVICE_EPINTFLAG_TRFAIL_Pos) 1177 #define USB_DEVICE_EPINTFLAG_TRFAIL(value) (USB_DEVICE_EPINTFLAG_TRFAIL_Msk & ((value) << USB_DEVICE_EPINTFLAG_TRFAIL_Pos)) 1178 #define USB_DEVICE_EPINTFLAG_RXSTP_Pos 4 /**< \brief (USB_DEVICE_EPINTFLAG) Received Setup */ 1179 #define USB_DEVICE_EPINTFLAG_RXSTP (_U_(0x1) << USB_DEVICE_EPINTFLAG_RXSTP_Pos) 1180 #define USB_DEVICE_EPINTFLAG_STALL0_Pos 5 /**< \brief (USB_DEVICE_EPINTFLAG) Stall 0 In/out */ 1181 #define USB_DEVICE_EPINTFLAG_STALL0 (1 << USB_DEVICE_EPINTFLAG_STALL0_Pos) 1182 #define USB_DEVICE_EPINTFLAG_STALL1_Pos 6 /**< \brief (USB_DEVICE_EPINTFLAG) Stall 1 In/out */ 1183 #define USB_DEVICE_EPINTFLAG_STALL1 (1 << USB_DEVICE_EPINTFLAG_STALL1_Pos) 1184 #define USB_DEVICE_EPINTFLAG_STALL_Pos 5 /**< \brief (USB_DEVICE_EPINTFLAG) Stall x In/out */ 1185 #define USB_DEVICE_EPINTFLAG_STALL_Msk (_U_(0x3) << USB_DEVICE_EPINTFLAG_STALL_Pos) 1186 #define USB_DEVICE_EPINTFLAG_STALL(value) (USB_DEVICE_EPINTFLAG_STALL_Msk & ((value) << USB_DEVICE_EPINTFLAG_STALL_Pos)) 1187 #define USB_DEVICE_EPINTFLAG_MASK _U_(0x7F) /**< \brief (USB_DEVICE_EPINTFLAG) MASK Register */ 1188 1189 /* -------- USB_HOST_PINTFLAG : (USB Offset: 0x107) (R/W 8) HOST HOST_PIPE Pipe Interrupt Flag -------- */ 1190 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1191 typedef union { // __I to avoid read-modify-write on write-to-clear register 1192 struct { 1193 __I uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Flag */ 1194 __I uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Flag */ 1195 __I uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Flag */ 1196 __I uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Flag */ 1197 __I uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Flag */ 1198 __I uint8_t STALL:1; /*!< bit: 5 Stall Interrupt Flag */ 1199 __I uint8_t :2; /*!< bit: 6.. 7 Reserved */ 1200 } bit; /*!< Structure used for bit access */ 1201 struct { 1202 __I uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Flag */ 1203 __I uint8_t :6; /*!< bit: 2.. 7 Reserved */ 1204 } vec; /*!< Structure used for vec access */ 1205 uint8_t reg; /*!< Type used for register access */ 1206 } USB_HOST_PINTFLAG_Type; 1207 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1208 1209 #define USB_HOST_PINTFLAG_OFFSET 0x107 /**< \brief (USB_HOST_PINTFLAG offset) HOST_PIPE Pipe Interrupt Flag */ 1210 #define USB_HOST_PINTFLAG_RESETVALUE _U_(0x00) /**< \brief (USB_HOST_PINTFLAG reset_value) HOST_PIPE Pipe Interrupt Flag */ 1211 1212 #define USB_HOST_PINTFLAG_TRCPT0_Pos 0 /**< \brief (USB_HOST_PINTFLAG) Transfer Complete 0 Interrupt Flag */ 1213 #define USB_HOST_PINTFLAG_TRCPT0 (1 << USB_HOST_PINTFLAG_TRCPT0_Pos) 1214 #define USB_HOST_PINTFLAG_TRCPT1_Pos 1 /**< \brief (USB_HOST_PINTFLAG) Transfer Complete 1 Interrupt Flag */ 1215 #define USB_HOST_PINTFLAG_TRCPT1 (1 << USB_HOST_PINTFLAG_TRCPT1_Pos) 1216 #define USB_HOST_PINTFLAG_TRCPT_Pos 0 /**< \brief (USB_HOST_PINTFLAG) Transfer Complete x Interrupt Flag */ 1217 #define USB_HOST_PINTFLAG_TRCPT_Msk (_U_(0x3) << USB_HOST_PINTFLAG_TRCPT_Pos) 1218 #define USB_HOST_PINTFLAG_TRCPT(value) (USB_HOST_PINTFLAG_TRCPT_Msk & ((value) << USB_HOST_PINTFLAG_TRCPT_Pos)) 1219 #define USB_HOST_PINTFLAG_TRFAIL_Pos 2 /**< \brief (USB_HOST_PINTFLAG) Error Flow Interrupt Flag */ 1220 #define USB_HOST_PINTFLAG_TRFAIL (_U_(0x1) << USB_HOST_PINTFLAG_TRFAIL_Pos) 1221 #define USB_HOST_PINTFLAG_PERR_Pos 3 /**< \brief (USB_HOST_PINTFLAG) Pipe Error Interrupt Flag */ 1222 #define USB_HOST_PINTFLAG_PERR (_U_(0x1) << USB_HOST_PINTFLAG_PERR_Pos) 1223 #define USB_HOST_PINTFLAG_TXSTP_Pos 4 /**< \brief (USB_HOST_PINTFLAG) Transmit Setup Interrupt Flag */ 1224 #define USB_HOST_PINTFLAG_TXSTP (_U_(0x1) << USB_HOST_PINTFLAG_TXSTP_Pos) 1225 #define USB_HOST_PINTFLAG_STALL_Pos 5 /**< \brief (USB_HOST_PINTFLAG) Stall Interrupt Flag */ 1226 #define USB_HOST_PINTFLAG_STALL (_U_(0x1) << USB_HOST_PINTFLAG_STALL_Pos) 1227 #define USB_HOST_PINTFLAG_MASK _U_(0x3F) /**< \brief (USB_HOST_PINTFLAG) MASK Register */ 1228 1229 /* -------- USB_DEVICE_EPINTENCLR : (USB Offset: 0x108) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Interrupt Clear Flag -------- */ 1230 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1231 typedef union { 1232 struct { 1233 uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Disable */ 1234 uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Disable */ 1235 uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 Interrupt Disable */ 1236 uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 Interrupt Disable */ 1237 uint8_t RXSTP:1; /*!< bit: 4 Received Setup Interrupt Disable */ 1238 uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/Out Interrupt Disable */ 1239 uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/Out Interrupt Disable */ 1240 uint8_t :1; /*!< bit: 7 Reserved */ 1241 } bit; /*!< Structure used for bit access */ 1242 struct { 1243 uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Disable */ 1244 uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x Interrupt Disable */ 1245 uint8_t :1; /*!< bit: 4 Reserved */ 1246 uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/Out Interrupt Disable */ 1247 uint8_t :1; /*!< bit: 7 Reserved */ 1248 } vec; /*!< Structure used for vec access */ 1249 uint8_t reg; /*!< Type used for register access */ 1250 } USB_DEVICE_EPINTENCLR_Type; 1251 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1252 1253 #define USB_DEVICE_EPINTENCLR_OFFSET 0x108 /**< \brief (USB_DEVICE_EPINTENCLR offset) DEVICE_ENDPOINT End Point Interrupt Clear Flag */ 1254 #define USB_DEVICE_EPINTENCLR_RESETVALUE _U_(0x00) /**< \brief (USB_DEVICE_EPINTENCLR reset_value) DEVICE_ENDPOINT End Point Interrupt Clear Flag */ 1255 1256 #define USB_DEVICE_EPINTENCLR_TRCPT0_Pos 0 /**< \brief (USB_DEVICE_EPINTENCLR) Transfer Complete 0 Interrupt Disable */ 1257 #define USB_DEVICE_EPINTENCLR_TRCPT0 (1 << USB_DEVICE_EPINTENCLR_TRCPT0_Pos) 1258 #define USB_DEVICE_EPINTENCLR_TRCPT1_Pos 1 /**< \brief (USB_DEVICE_EPINTENCLR) Transfer Complete 1 Interrupt Disable */ 1259 #define USB_DEVICE_EPINTENCLR_TRCPT1 (1 << USB_DEVICE_EPINTENCLR_TRCPT1_Pos) 1260 #define USB_DEVICE_EPINTENCLR_TRCPT_Pos 0 /**< \brief (USB_DEVICE_EPINTENCLR) Transfer Complete x Interrupt Disable */ 1261 #define USB_DEVICE_EPINTENCLR_TRCPT_Msk (_U_(0x3) << USB_DEVICE_EPINTENCLR_TRCPT_Pos) 1262 #define USB_DEVICE_EPINTENCLR_TRCPT(value) (USB_DEVICE_EPINTENCLR_TRCPT_Msk & ((value) << USB_DEVICE_EPINTENCLR_TRCPT_Pos)) 1263 #define USB_DEVICE_EPINTENCLR_TRFAIL0_Pos 2 /**< \brief (USB_DEVICE_EPINTENCLR) Error Flow 0 Interrupt Disable */ 1264 #define USB_DEVICE_EPINTENCLR_TRFAIL0 (1 << USB_DEVICE_EPINTENCLR_TRFAIL0_Pos) 1265 #define USB_DEVICE_EPINTENCLR_TRFAIL1_Pos 3 /**< \brief (USB_DEVICE_EPINTENCLR) Error Flow 1 Interrupt Disable */ 1266 #define USB_DEVICE_EPINTENCLR_TRFAIL1 (1 << USB_DEVICE_EPINTENCLR_TRFAIL1_Pos) 1267 #define USB_DEVICE_EPINTENCLR_TRFAIL_Pos 2 /**< \brief (USB_DEVICE_EPINTENCLR) Error Flow x Interrupt Disable */ 1268 #define USB_DEVICE_EPINTENCLR_TRFAIL_Msk (_U_(0x3) << USB_DEVICE_EPINTENCLR_TRFAIL_Pos) 1269 #define USB_DEVICE_EPINTENCLR_TRFAIL(value) (USB_DEVICE_EPINTENCLR_TRFAIL_Msk & ((value) << USB_DEVICE_EPINTENCLR_TRFAIL_Pos)) 1270 #define USB_DEVICE_EPINTENCLR_RXSTP_Pos 4 /**< \brief (USB_DEVICE_EPINTENCLR) Received Setup Interrupt Disable */ 1271 #define USB_DEVICE_EPINTENCLR_RXSTP (_U_(0x1) << USB_DEVICE_EPINTENCLR_RXSTP_Pos) 1272 #define USB_DEVICE_EPINTENCLR_STALL0_Pos 5 /**< \brief (USB_DEVICE_EPINTENCLR) Stall 0 In/Out Interrupt Disable */ 1273 #define USB_DEVICE_EPINTENCLR_STALL0 (1 << USB_DEVICE_EPINTENCLR_STALL0_Pos) 1274 #define USB_DEVICE_EPINTENCLR_STALL1_Pos 6 /**< \brief (USB_DEVICE_EPINTENCLR) Stall 1 In/Out Interrupt Disable */ 1275 #define USB_DEVICE_EPINTENCLR_STALL1 (1 << USB_DEVICE_EPINTENCLR_STALL1_Pos) 1276 #define USB_DEVICE_EPINTENCLR_STALL_Pos 5 /**< \brief (USB_DEVICE_EPINTENCLR) Stall x In/Out Interrupt Disable */ 1277 #define USB_DEVICE_EPINTENCLR_STALL_Msk (_U_(0x3) << USB_DEVICE_EPINTENCLR_STALL_Pos) 1278 #define USB_DEVICE_EPINTENCLR_STALL(value) (USB_DEVICE_EPINTENCLR_STALL_Msk & ((value) << USB_DEVICE_EPINTENCLR_STALL_Pos)) 1279 #define USB_DEVICE_EPINTENCLR_MASK _U_(0x7F) /**< \brief (USB_DEVICE_EPINTENCLR) MASK Register */ 1280 1281 /* -------- USB_HOST_PINTENCLR : (USB Offset: 0x108) (R/W 8) HOST HOST_PIPE Pipe Interrupt Flag Clear -------- */ 1282 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1283 typedef union { 1284 struct { 1285 uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Disable */ 1286 uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Disable */ 1287 uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Disable */ 1288 uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Disable */ 1289 uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Disable */ 1290 uint8_t STALL:1; /*!< bit: 5 Stall Inetrrupt Disable */ 1291 uint8_t :2; /*!< bit: 6.. 7 Reserved */ 1292 } bit; /*!< Structure used for bit access */ 1293 struct { 1294 uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Disable */ 1295 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 1296 } vec; /*!< Structure used for vec access */ 1297 uint8_t reg; /*!< Type used for register access */ 1298 } USB_HOST_PINTENCLR_Type; 1299 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1300 1301 #define USB_HOST_PINTENCLR_OFFSET 0x108 /**< \brief (USB_HOST_PINTENCLR offset) HOST_PIPE Pipe Interrupt Flag Clear */ 1302 #define USB_HOST_PINTENCLR_RESETVALUE _U_(0x00) /**< \brief (USB_HOST_PINTENCLR reset_value) HOST_PIPE Pipe Interrupt Flag Clear */ 1303 1304 #define USB_HOST_PINTENCLR_TRCPT0_Pos 0 /**< \brief (USB_HOST_PINTENCLR) Transfer Complete 0 Disable */ 1305 #define USB_HOST_PINTENCLR_TRCPT0 (1 << USB_HOST_PINTENCLR_TRCPT0_Pos) 1306 #define USB_HOST_PINTENCLR_TRCPT1_Pos 1 /**< \brief (USB_HOST_PINTENCLR) Transfer Complete 1 Disable */ 1307 #define USB_HOST_PINTENCLR_TRCPT1 (1 << USB_HOST_PINTENCLR_TRCPT1_Pos) 1308 #define USB_HOST_PINTENCLR_TRCPT_Pos 0 /**< \brief (USB_HOST_PINTENCLR) Transfer Complete x Disable */ 1309 #define USB_HOST_PINTENCLR_TRCPT_Msk (_U_(0x3) << USB_HOST_PINTENCLR_TRCPT_Pos) 1310 #define USB_HOST_PINTENCLR_TRCPT(value) (USB_HOST_PINTENCLR_TRCPT_Msk & ((value) << USB_HOST_PINTENCLR_TRCPT_Pos)) 1311 #define USB_HOST_PINTENCLR_TRFAIL_Pos 2 /**< \brief (USB_HOST_PINTENCLR) Error Flow Interrupt Disable */ 1312 #define USB_HOST_PINTENCLR_TRFAIL (_U_(0x1) << USB_HOST_PINTENCLR_TRFAIL_Pos) 1313 #define USB_HOST_PINTENCLR_PERR_Pos 3 /**< \brief (USB_HOST_PINTENCLR) Pipe Error Interrupt Disable */ 1314 #define USB_HOST_PINTENCLR_PERR (_U_(0x1) << USB_HOST_PINTENCLR_PERR_Pos) 1315 #define USB_HOST_PINTENCLR_TXSTP_Pos 4 /**< \brief (USB_HOST_PINTENCLR) Transmit Setup Interrupt Disable */ 1316 #define USB_HOST_PINTENCLR_TXSTP (_U_(0x1) << USB_HOST_PINTENCLR_TXSTP_Pos) 1317 #define USB_HOST_PINTENCLR_STALL_Pos 5 /**< \brief (USB_HOST_PINTENCLR) Stall Inetrrupt Disable */ 1318 #define USB_HOST_PINTENCLR_STALL (_U_(0x1) << USB_HOST_PINTENCLR_STALL_Pos) 1319 #define USB_HOST_PINTENCLR_MASK _U_(0x3F) /**< \brief (USB_HOST_PINTENCLR) MASK Register */ 1320 1321 /* -------- USB_DEVICE_EPINTENSET : (USB Offset: 0x109) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Interrupt Set Flag -------- */ 1322 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1323 typedef union { 1324 struct { 1325 uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Enable */ 1326 uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Enable */ 1327 uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 Interrupt Enable */ 1328 uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 Interrupt Enable */ 1329 uint8_t RXSTP:1; /*!< bit: 4 Received Setup Interrupt Enable */ 1330 uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/out Interrupt enable */ 1331 uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/out Interrupt enable */ 1332 uint8_t :1; /*!< bit: 7 Reserved */ 1333 } bit; /*!< Structure used for bit access */ 1334 struct { 1335 uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Enable */ 1336 uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x Interrupt Enable */ 1337 uint8_t :1; /*!< bit: 4 Reserved */ 1338 uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/out Interrupt enable */ 1339 uint8_t :1; /*!< bit: 7 Reserved */ 1340 } vec; /*!< Structure used for vec access */ 1341 uint8_t reg; /*!< Type used for register access */ 1342 } USB_DEVICE_EPINTENSET_Type; 1343 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1344 1345 #define USB_DEVICE_EPINTENSET_OFFSET 0x109 /**< \brief (USB_DEVICE_EPINTENSET offset) DEVICE_ENDPOINT End Point Interrupt Set Flag */ 1346 #define USB_DEVICE_EPINTENSET_RESETVALUE _U_(0x00) /**< \brief (USB_DEVICE_EPINTENSET reset_value) DEVICE_ENDPOINT End Point Interrupt Set Flag */ 1347 1348 #define USB_DEVICE_EPINTENSET_TRCPT0_Pos 0 /**< \brief (USB_DEVICE_EPINTENSET) Transfer Complete 0 Interrupt Enable */ 1349 #define USB_DEVICE_EPINTENSET_TRCPT0 (1 << USB_DEVICE_EPINTENSET_TRCPT0_Pos) 1350 #define USB_DEVICE_EPINTENSET_TRCPT1_Pos 1 /**< \brief (USB_DEVICE_EPINTENSET) Transfer Complete 1 Interrupt Enable */ 1351 #define USB_DEVICE_EPINTENSET_TRCPT1 (1 << USB_DEVICE_EPINTENSET_TRCPT1_Pos) 1352 #define USB_DEVICE_EPINTENSET_TRCPT_Pos 0 /**< \brief (USB_DEVICE_EPINTENSET) Transfer Complete x Interrupt Enable */ 1353 #define USB_DEVICE_EPINTENSET_TRCPT_Msk (_U_(0x3) << USB_DEVICE_EPINTENSET_TRCPT_Pos) 1354 #define USB_DEVICE_EPINTENSET_TRCPT(value) (USB_DEVICE_EPINTENSET_TRCPT_Msk & ((value) << USB_DEVICE_EPINTENSET_TRCPT_Pos)) 1355 #define USB_DEVICE_EPINTENSET_TRFAIL0_Pos 2 /**< \brief (USB_DEVICE_EPINTENSET) Error Flow 0 Interrupt Enable */ 1356 #define USB_DEVICE_EPINTENSET_TRFAIL0 (1 << USB_DEVICE_EPINTENSET_TRFAIL0_Pos) 1357 #define USB_DEVICE_EPINTENSET_TRFAIL1_Pos 3 /**< \brief (USB_DEVICE_EPINTENSET) Error Flow 1 Interrupt Enable */ 1358 #define USB_DEVICE_EPINTENSET_TRFAIL1 (1 << USB_DEVICE_EPINTENSET_TRFAIL1_Pos) 1359 #define USB_DEVICE_EPINTENSET_TRFAIL_Pos 2 /**< \brief (USB_DEVICE_EPINTENSET) Error Flow x Interrupt Enable */ 1360 #define USB_DEVICE_EPINTENSET_TRFAIL_Msk (_U_(0x3) << USB_DEVICE_EPINTENSET_TRFAIL_Pos) 1361 #define USB_DEVICE_EPINTENSET_TRFAIL(value) (USB_DEVICE_EPINTENSET_TRFAIL_Msk & ((value) << USB_DEVICE_EPINTENSET_TRFAIL_Pos)) 1362 #define USB_DEVICE_EPINTENSET_RXSTP_Pos 4 /**< \brief (USB_DEVICE_EPINTENSET) Received Setup Interrupt Enable */ 1363 #define USB_DEVICE_EPINTENSET_RXSTP (_U_(0x1) << USB_DEVICE_EPINTENSET_RXSTP_Pos) 1364 #define USB_DEVICE_EPINTENSET_STALL0_Pos 5 /**< \brief (USB_DEVICE_EPINTENSET) Stall 0 In/out Interrupt enable */ 1365 #define USB_DEVICE_EPINTENSET_STALL0 (1 << USB_DEVICE_EPINTENSET_STALL0_Pos) 1366 #define USB_DEVICE_EPINTENSET_STALL1_Pos 6 /**< \brief (USB_DEVICE_EPINTENSET) Stall 1 In/out Interrupt enable */ 1367 #define USB_DEVICE_EPINTENSET_STALL1 (1 << USB_DEVICE_EPINTENSET_STALL1_Pos) 1368 #define USB_DEVICE_EPINTENSET_STALL_Pos 5 /**< \brief (USB_DEVICE_EPINTENSET) Stall x In/out Interrupt enable */ 1369 #define USB_DEVICE_EPINTENSET_STALL_Msk (_U_(0x3) << USB_DEVICE_EPINTENSET_STALL_Pos) 1370 #define USB_DEVICE_EPINTENSET_STALL(value) (USB_DEVICE_EPINTENSET_STALL_Msk & ((value) << USB_DEVICE_EPINTENSET_STALL_Pos)) 1371 #define USB_DEVICE_EPINTENSET_MASK _U_(0x7F) /**< \brief (USB_DEVICE_EPINTENSET) MASK Register */ 1372 1373 /* -------- USB_HOST_PINTENSET : (USB Offset: 0x109) (R/W 8) HOST HOST_PIPE Pipe Interrupt Flag Set -------- */ 1374 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1375 typedef union { 1376 struct { 1377 uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Enable */ 1378 uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Enable */ 1379 uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Enable */ 1380 uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Enable */ 1381 uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Enable */ 1382 uint8_t STALL:1; /*!< bit: 5 Stall Interrupt Enable */ 1383 uint8_t :2; /*!< bit: 6.. 7 Reserved */ 1384 } bit; /*!< Structure used for bit access */ 1385 struct { 1386 uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Enable */ 1387 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 1388 } vec; /*!< Structure used for vec access */ 1389 uint8_t reg; /*!< Type used for register access */ 1390 } USB_HOST_PINTENSET_Type; 1391 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1392 1393 #define USB_HOST_PINTENSET_OFFSET 0x109 /**< \brief (USB_HOST_PINTENSET offset) HOST_PIPE Pipe Interrupt Flag Set */ 1394 #define USB_HOST_PINTENSET_RESETVALUE _U_(0x00) /**< \brief (USB_HOST_PINTENSET reset_value) HOST_PIPE Pipe Interrupt Flag Set */ 1395 1396 #define USB_HOST_PINTENSET_TRCPT0_Pos 0 /**< \brief (USB_HOST_PINTENSET) Transfer Complete 0 Interrupt Enable */ 1397 #define USB_HOST_PINTENSET_TRCPT0 (1 << USB_HOST_PINTENSET_TRCPT0_Pos) 1398 #define USB_HOST_PINTENSET_TRCPT1_Pos 1 /**< \brief (USB_HOST_PINTENSET) Transfer Complete 1 Interrupt Enable */ 1399 #define USB_HOST_PINTENSET_TRCPT1 (1 << USB_HOST_PINTENSET_TRCPT1_Pos) 1400 #define USB_HOST_PINTENSET_TRCPT_Pos 0 /**< \brief (USB_HOST_PINTENSET) Transfer Complete x Interrupt Enable */ 1401 #define USB_HOST_PINTENSET_TRCPT_Msk (_U_(0x3) << USB_HOST_PINTENSET_TRCPT_Pos) 1402 #define USB_HOST_PINTENSET_TRCPT(value) (USB_HOST_PINTENSET_TRCPT_Msk & ((value) << USB_HOST_PINTENSET_TRCPT_Pos)) 1403 #define USB_HOST_PINTENSET_TRFAIL_Pos 2 /**< \brief (USB_HOST_PINTENSET) Error Flow Interrupt Enable */ 1404 #define USB_HOST_PINTENSET_TRFAIL (_U_(0x1) << USB_HOST_PINTENSET_TRFAIL_Pos) 1405 #define USB_HOST_PINTENSET_PERR_Pos 3 /**< \brief (USB_HOST_PINTENSET) Pipe Error Interrupt Enable */ 1406 #define USB_HOST_PINTENSET_PERR (_U_(0x1) << USB_HOST_PINTENSET_PERR_Pos) 1407 #define USB_HOST_PINTENSET_TXSTP_Pos 4 /**< \brief (USB_HOST_PINTENSET) Transmit Setup Interrupt Enable */ 1408 #define USB_HOST_PINTENSET_TXSTP (_U_(0x1) << USB_HOST_PINTENSET_TXSTP_Pos) 1409 #define USB_HOST_PINTENSET_STALL_Pos 5 /**< \brief (USB_HOST_PINTENSET) Stall Interrupt Enable */ 1410 #define USB_HOST_PINTENSET_STALL (_U_(0x1) << USB_HOST_PINTENSET_STALL_Pos) 1411 #define USB_HOST_PINTENSET_MASK _U_(0x3F) /**< \brief (USB_HOST_PINTENSET) MASK Register */ 1412 1413 /* -------- USB_DEVICE_ADDR : (USB Offset: 0x000) (R/W 32) DEVICE DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer -------- */ 1414 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1415 typedef union { 1416 struct { 1417 uint32_t ADDR:32; /*!< bit: 0..31 Adress of data buffer */ 1418 } bit; /*!< Structure used for bit access */ 1419 uint32_t reg; /*!< Type used for register access */ 1420 } USB_DEVICE_ADDR_Type; 1421 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1422 1423 #define USB_DEVICE_ADDR_OFFSET 0x000 /**< \brief (USB_DEVICE_ADDR offset) DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer */ 1424 1425 #define USB_DEVICE_ADDR_ADDR_Pos 0 /**< \brief (USB_DEVICE_ADDR) Adress of data buffer */ 1426 #define USB_DEVICE_ADDR_ADDR_Msk (_U_(0xFFFFFFFF) << USB_DEVICE_ADDR_ADDR_Pos) 1427 #define USB_DEVICE_ADDR_ADDR(value) (USB_DEVICE_ADDR_ADDR_Msk & ((value) << USB_DEVICE_ADDR_ADDR_Pos)) 1428 #define USB_DEVICE_ADDR_MASK _U_(0xFFFFFFFF) /**< \brief (USB_DEVICE_ADDR) MASK Register */ 1429 1430 /* -------- USB_HOST_ADDR : (USB Offset: 0x000) (R/W 32) HOST HOST_DESC_BANK Host Bank, Adress of Data Buffer -------- */ 1431 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1432 typedef union { 1433 struct { 1434 uint32_t ADDR:32; /*!< bit: 0..31 Adress of data buffer */ 1435 } bit; /*!< Structure used for bit access */ 1436 uint32_t reg; /*!< Type used for register access */ 1437 } USB_HOST_ADDR_Type; 1438 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1439 1440 #define USB_HOST_ADDR_OFFSET 0x000 /**< \brief (USB_HOST_ADDR offset) HOST_DESC_BANK Host Bank, Adress of Data Buffer */ 1441 1442 #define USB_HOST_ADDR_ADDR_Pos 0 /**< \brief (USB_HOST_ADDR) Adress of data buffer */ 1443 #define USB_HOST_ADDR_ADDR_Msk (_U_(0xFFFFFFFF) << USB_HOST_ADDR_ADDR_Pos) 1444 #define USB_HOST_ADDR_ADDR(value) (USB_HOST_ADDR_ADDR_Msk & ((value) << USB_HOST_ADDR_ADDR_Pos)) 1445 #define USB_HOST_ADDR_MASK _U_(0xFFFFFFFF) /**< \brief (USB_HOST_ADDR) MASK Register */ 1446 1447 /* -------- USB_DEVICE_PCKSIZE : (USB Offset: 0x004) (R/W 32) DEVICE DEVICE_DESC_BANK Endpoint Bank, Packet Size -------- */ 1448 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1449 typedef union { 1450 struct { 1451 uint32_t BYTE_COUNT:14; /*!< bit: 0..13 Byte Count */ 1452 uint32_t MULTI_PACKET_SIZE:14; /*!< bit: 14..27 Multi Packet In or Out size */ 1453 uint32_t SIZE:3; /*!< bit: 28..30 Enpoint size */ 1454 uint32_t AUTO_ZLP:1; /*!< bit: 31 Automatic Zero Length Packet */ 1455 } bit; /*!< Structure used for bit access */ 1456 uint32_t reg; /*!< Type used for register access */ 1457 } USB_DEVICE_PCKSIZE_Type; 1458 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1459 1460 #define USB_DEVICE_PCKSIZE_OFFSET 0x004 /**< \brief (USB_DEVICE_PCKSIZE offset) DEVICE_DESC_BANK Endpoint Bank, Packet Size */ 1461 1462 #define USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos 0 /**< \brief (USB_DEVICE_PCKSIZE) Byte Count */ 1463 #define USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk (_U_(0x3FFF) << USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos) 1464 #define USB_DEVICE_PCKSIZE_BYTE_COUNT(value) (USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk & ((value) << USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos)) 1465 #define USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos 14 /**< \brief (USB_DEVICE_PCKSIZE) Multi Packet In or Out size */ 1466 #define USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk (_U_(0x3FFF) << USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos) 1467 #define USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(value) (USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk & ((value) << USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos)) 1468 #define USB_DEVICE_PCKSIZE_SIZE_Pos 28 /**< \brief (USB_DEVICE_PCKSIZE) Enpoint size */ 1469 #define USB_DEVICE_PCKSIZE_SIZE_Msk (_U_(0x7) << USB_DEVICE_PCKSIZE_SIZE_Pos) 1470 #define USB_DEVICE_PCKSIZE_SIZE(value) (USB_DEVICE_PCKSIZE_SIZE_Msk & ((value) << USB_DEVICE_PCKSIZE_SIZE_Pos)) 1471 #define USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos 31 /**< \brief (USB_DEVICE_PCKSIZE) Automatic Zero Length Packet */ 1472 #define USB_DEVICE_PCKSIZE_AUTO_ZLP (_U_(0x1) << USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos) 1473 #define USB_DEVICE_PCKSIZE_MASK _U_(0xFFFFFFFF) /**< \brief (USB_DEVICE_PCKSIZE) MASK Register */ 1474 1475 /* -------- USB_HOST_PCKSIZE : (USB Offset: 0x004) (R/W 32) HOST HOST_DESC_BANK Host Bank, Packet Size -------- */ 1476 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1477 typedef union { 1478 struct { 1479 uint32_t BYTE_COUNT:14; /*!< bit: 0..13 Byte Count */ 1480 uint32_t MULTI_PACKET_SIZE:14; /*!< bit: 14..27 Multi Packet In or Out size */ 1481 uint32_t SIZE:3; /*!< bit: 28..30 Pipe size */ 1482 uint32_t AUTO_ZLP:1; /*!< bit: 31 Automatic Zero Length Packet */ 1483 } bit; /*!< Structure used for bit access */ 1484 uint32_t reg; /*!< Type used for register access */ 1485 } USB_HOST_PCKSIZE_Type; 1486 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1487 1488 #define USB_HOST_PCKSIZE_OFFSET 0x004 /**< \brief (USB_HOST_PCKSIZE offset) HOST_DESC_BANK Host Bank, Packet Size */ 1489 1490 #define USB_HOST_PCKSIZE_BYTE_COUNT_Pos 0 /**< \brief (USB_HOST_PCKSIZE) Byte Count */ 1491 #define USB_HOST_PCKSIZE_BYTE_COUNT_Msk (_U_(0x3FFF) << USB_HOST_PCKSIZE_BYTE_COUNT_Pos) 1492 #define USB_HOST_PCKSIZE_BYTE_COUNT(value) (USB_HOST_PCKSIZE_BYTE_COUNT_Msk & ((value) << USB_HOST_PCKSIZE_BYTE_COUNT_Pos)) 1493 #define USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos 14 /**< \brief (USB_HOST_PCKSIZE) Multi Packet In or Out size */ 1494 #define USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk (_U_(0x3FFF) << USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos) 1495 #define USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(value) (USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk & ((value) << USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos)) 1496 #define USB_HOST_PCKSIZE_SIZE_Pos 28 /**< \brief (USB_HOST_PCKSIZE) Pipe size */ 1497 #define USB_HOST_PCKSIZE_SIZE_Msk (_U_(0x7) << USB_HOST_PCKSIZE_SIZE_Pos) 1498 #define USB_HOST_PCKSIZE_SIZE(value) (USB_HOST_PCKSIZE_SIZE_Msk & ((value) << USB_HOST_PCKSIZE_SIZE_Pos)) 1499 #define USB_HOST_PCKSIZE_AUTO_ZLP_Pos 31 /**< \brief (USB_HOST_PCKSIZE) Automatic Zero Length Packet */ 1500 #define USB_HOST_PCKSIZE_AUTO_ZLP (_U_(0x1) << USB_HOST_PCKSIZE_AUTO_ZLP_Pos) 1501 #define USB_HOST_PCKSIZE_MASK _U_(0xFFFFFFFF) /**< \brief (USB_HOST_PCKSIZE) MASK Register */ 1502 1503 /* -------- USB_DEVICE_EXTREG : (USB Offset: 0x008) (R/W 16) DEVICE DEVICE_DESC_BANK Endpoint Bank, Extended -------- */ 1504 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1505 typedef union { 1506 struct { 1507 uint16_t SUBPID:4; /*!< bit: 0.. 3 SUBPID field send with extended token */ 1508 uint16_t VARIABLE:11; /*!< bit: 4..14 Variable field send with extended token */ 1509 uint16_t :1; /*!< bit: 15 Reserved */ 1510 } bit; /*!< Structure used for bit access */ 1511 uint16_t reg; /*!< Type used for register access */ 1512 } USB_DEVICE_EXTREG_Type; 1513 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1514 1515 #define USB_DEVICE_EXTREG_OFFSET 0x008 /**< \brief (USB_DEVICE_EXTREG offset) DEVICE_DESC_BANK Endpoint Bank, Extended */ 1516 1517 #define USB_DEVICE_EXTREG_SUBPID_Pos 0 /**< \brief (USB_DEVICE_EXTREG) SUBPID field send with extended token */ 1518 #define USB_DEVICE_EXTREG_SUBPID_Msk (_U_(0xF) << USB_DEVICE_EXTREG_SUBPID_Pos) 1519 #define USB_DEVICE_EXTREG_SUBPID(value) (USB_DEVICE_EXTREG_SUBPID_Msk & ((value) << USB_DEVICE_EXTREG_SUBPID_Pos)) 1520 #define USB_DEVICE_EXTREG_VARIABLE_Pos 4 /**< \brief (USB_DEVICE_EXTREG) Variable field send with extended token */ 1521 #define USB_DEVICE_EXTREG_VARIABLE_Msk (_U_(0x7FF) << USB_DEVICE_EXTREG_VARIABLE_Pos) 1522 #define USB_DEVICE_EXTREG_VARIABLE(value) (USB_DEVICE_EXTREG_VARIABLE_Msk & ((value) << USB_DEVICE_EXTREG_VARIABLE_Pos)) 1523 #define USB_DEVICE_EXTREG_MASK _U_(0x7FFF) /**< \brief (USB_DEVICE_EXTREG) MASK Register */ 1524 1525 /* -------- USB_HOST_EXTREG : (USB Offset: 0x008) (R/W 16) HOST HOST_DESC_BANK Host Bank, Extended -------- */ 1526 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1527 typedef union { 1528 struct { 1529 uint16_t SUBPID:4; /*!< bit: 0.. 3 SUBPID field send with extended token */ 1530 uint16_t VARIABLE:11; /*!< bit: 4..14 Variable field send with extended token */ 1531 uint16_t :1; /*!< bit: 15 Reserved */ 1532 } bit; /*!< Structure used for bit access */ 1533 uint16_t reg; /*!< Type used for register access */ 1534 } USB_HOST_EXTREG_Type; 1535 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1536 1537 #define USB_HOST_EXTREG_OFFSET 0x008 /**< \brief (USB_HOST_EXTREG offset) HOST_DESC_BANK Host Bank, Extended */ 1538 1539 #define USB_HOST_EXTREG_SUBPID_Pos 0 /**< \brief (USB_HOST_EXTREG) SUBPID field send with extended token */ 1540 #define USB_HOST_EXTREG_SUBPID_Msk (_U_(0xF) << USB_HOST_EXTREG_SUBPID_Pos) 1541 #define USB_HOST_EXTREG_SUBPID(value) (USB_HOST_EXTREG_SUBPID_Msk & ((value) << USB_HOST_EXTREG_SUBPID_Pos)) 1542 #define USB_HOST_EXTREG_VARIABLE_Pos 4 /**< \brief (USB_HOST_EXTREG) Variable field send with extended token */ 1543 #define USB_HOST_EXTREG_VARIABLE_Msk (_U_(0x7FF) << USB_HOST_EXTREG_VARIABLE_Pos) 1544 #define USB_HOST_EXTREG_VARIABLE(value) (USB_HOST_EXTREG_VARIABLE_Msk & ((value) << USB_HOST_EXTREG_VARIABLE_Pos)) 1545 #define USB_HOST_EXTREG_MASK _U_(0x7FFF) /**< \brief (USB_HOST_EXTREG) MASK Register */ 1546 1547 /* -------- USB_DEVICE_STATUS_BK : (USB Offset: 0x00A) (R/W 8) DEVICE DEVICE_DESC_BANK Enpoint Bank, Status of Bank -------- */ 1548 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1549 typedef union { 1550 struct { 1551 uint8_t CRCERR:1; /*!< bit: 0 CRC Error Status */ 1552 uint8_t ERRORFLOW:1; /*!< bit: 1 Error Flow Status */ 1553 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 1554 } bit; /*!< Structure used for bit access */ 1555 uint8_t reg; /*!< Type used for register access */ 1556 } USB_DEVICE_STATUS_BK_Type; 1557 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1558 1559 #define USB_DEVICE_STATUS_BK_OFFSET 0x00A /**< \brief (USB_DEVICE_STATUS_BK offset) DEVICE_DESC_BANK Enpoint Bank, Status of Bank */ 1560 1561 #define USB_DEVICE_STATUS_BK_CRCERR_Pos 0 /**< \brief (USB_DEVICE_STATUS_BK) CRC Error Status */ 1562 #define USB_DEVICE_STATUS_BK_CRCERR (_U_(0x1) << USB_DEVICE_STATUS_BK_CRCERR_Pos) 1563 #define USB_DEVICE_STATUS_BK_ERRORFLOW_Pos 1 /**< \brief (USB_DEVICE_STATUS_BK) Error Flow Status */ 1564 #define USB_DEVICE_STATUS_BK_ERRORFLOW (_U_(0x1) << USB_DEVICE_STATUS_BK_ERRORFLOW_Pos) 1565 #define USB_DEVICE_STATUS_BK_MASK _U_(0x03) /**< \brief (USB_DEVICE_STATUS_BK) MASK Register */ 1566 1567 /* -------- USB_HOST_STATUS_BK : (USB Offset: 0x00A) (R/W 8) HOST HOST_DESC_BANK Host Bank, Status of Bank -------- */ 1568 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1569 typedef union { 1570 struct { 1571 uint8_t CRCERR:1; /*!< bit: 0 CRC Error Status */ 1572 uint8_t ERRORFLOW:1; /*!< bit: 1 Error Flow Status */ 1573 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 1574 } bit; /*!< Structure used for bit access */ 1575 uint8_t reg; /*!< Type used for register access */ 1576 } USB_HOST_STATUS_BK_Type; 1577 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1578 1579 #define USB_HOST_STATUS_BK_OFFSET 0x00A /**< \brief (USB_HOST_STATUS_BK offset) HOST_DESC_BANK Host Bank, Status of Bank */ 1580 1581 #define USB_HOST_STATUS_BK_CRCERR_Pos 0 /**< \brief (USB_HOST_STATUS_BK) CRC Error Status */ 1582 #define USB_HOST_STATUS_BK_CRCERR (_U_(0x1) << USB_HOST_STATUS_BK_CRCERR_Pos) 1583 #define USB_HOST_STATUS_BK_ERRORFLOW_Pos 1 /**< \brief (USB_HOST_STATUS_BK) Error Flow Status */ 1584 #define USB_HOST_STATUS_BK_ERRORFLOW (_U_(0x1) << USB_HOST_STATUS_BK_ERRORFLOW_Pos) 1585 #define USB_HOST_STATUS_BK_MASK _U_(0x03) /**< \brief (USB_HOST_STATUS_BK) MASK Register */ 1586 1587 /* -------- USB_HOST_CTRL_PIPE : (USB Offset: 0x00C) (R/W 16) HOST HOST_DESC_BANK Host Bank, Host Control Pipe -------- */ 1588 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1589 typedef union { 1590 struct { 1591 uint16_t PDADDR:7; /*!< bit: 0.. 6 Pipe Device Adress */ 1592 uint16_t :1; /*!< bit: 7 Reserved */ 1593 uint16_t PEPNUM:4; /*!< bit: 8..11 Pipe Endpoint Number */ 1594 uint16_t PERMAX:4; /*!< bit: 12..15 Pipe Error Max Number */ 1595 } bit; /*!< Structure used for bit access */ 1596 uint16_t reg; /*!< Type used for register access */ 1597 } USB_HOST_CTRL_PIPE_Type; 1598 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1599 1600 #define USB_HOST_CTRL_PIPE_OFFSET 0x00C /**< \brief (USB_HOST_CTRL_PIPE offset) HOST_DESC_BANK Host Bank, Host Control Pipe */ 1601 #define USB_HOST_CTRL_PIPE_RESETVALUE _U_(0x0000) /**< \brief (USB_HOST_CTRL_PIPE reset_value) HOST_DESC_BANK Host Bank, Host Control Pipe */ 1602 1603 #define USB_HOST_CTRL_PIPE_PDADDR_Pos 0 /**< \brief (USB_HOST_CTRL_PIPE) Pipe Device Adress */ 1604 #define USB_HOST_CTRL_PIPE_PDADDR_Msk (_U_(0x7F) << USB_HOST_CTRL_PIPE_PDADDR_Pos) 1605 #define USB_HOST_CTRL_PIPE_PDADDR(value) (USB_HOST_CTRL_PIPE_PDADDR_Msk & ((value) << USB_HOST_CTRL_PIPE_PDADDR_Pos)) 1606 #define USB_HOST_CTRL_PIPE_PEPNUM_Pos 8 /**< \brief (USB_HOST_CTRL_PIPE) Pipe Endpoint Number */ 1607 #define USB_HOST_CTRL_PIPE_PEPNUM_Msk (_U_(0xF) << USB_HOST_CTRL_PIPE_PEPNUM_Pos) 1608 #define USB_HOST_CTRL_PIPE_PEPNUM(value) (USB_HOST_CTRL_PIPE_PEPNUM_Msk & ((value) << USB_HOST_CTRL_PIPE_PEPNUM_Pos)) 1609 #define USB_HOST_CTRL_PIPE_PERMAX_Pos 12 /**< \brief (USB_HOST_CTRL_PIPE) Pipe Error Max Number */ 1610 #define USB_HOST_CTRL_PIPE_PERMAX_Msk (_U_(0xF) << USB_HOST_CTRL_PIPE_PERMAX_Pos) 1611 #define USB_HOST_CTRL_PIPE_PERMAX(value) (USB_HOST_CTRL_PIPE_PERMAX_Msk & ((value) << USB_HOST_CTRL_PIPE_PERMAX_Pos)) 1612 #define USB_HOST_CTRL_PIPE_MASK _U_(0xFF7F) /**< \brief (USB_HOST_CTRL_PIPE) MASK Register */ 1613 1614 /* -------- USB_HOST_STATUS_PIPE : (USB Offset: 0x00E) (R/W 16) HOST HOST_DESC_BANK Host Bank, Host Status Pipe -------- */ 1615 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1616 typedef union { 1617 struct { 1618 uint16_t DTGLER:1; /*!< bit: 0 Data Toggle Error */ 1619 uint16_t DAPIDER:1; /*!< bit: 1 Data PID Error */ 1620 uint16_t PIDER:1; /*!< bit: 2 PID Error */ 1621 uint16_t TOUTER:1; /*!< bit: 3 Time Out Error */ 1622 uint16_t CRC16ER:1; /*!< bit: 4 CRC16 Error */ 1623 uint16_t ERCNT:3; /*!< bit: 5.. 7 Pipe Error Count */ 1624 uint16_t :8; /*!< bit: 8..15 Reserved */ 1625 } bit; /*!< Structure used for bit access */ 1626 uint16_t reg; /*!< Type used for register access */ 1627 } USB_HOST_STATUS_PIPE_Type; 1628 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1629 1630 #define USB_HOST_STATUS_PIPE_OFFSET 0x00E /**< \brief (USB_HOST_STATUS_PIPE offset) HOST_DESC_BANK Host Bank, Host Status Pipe */ 1631 1632 #define USB_HOST_STATUS_PIPE_DTGLER_Pos 0 /**< \brief (USB_HOST_STATUS_PIPE) Data Toggle Error */ 1633 #define USB_HOST_STATUS_PIPE_DTGLER (_U_(0x1) << USB_HOST_STATUS_PIPE_DTGLER_Pos) 1634 #define USB_HOST_STATUS_PIPE_DAPIDER_Pos 1 /**< \brief (USB_HOST_STATUS_PIPE) Data PID Error */ 1635 #define USB_HOST_STATUS_PIPE_DAPIDER (_U_(0x1) << USB_HOST_STATUS_PIPE_DAPIDER_Pos) 1636 #define USB_HOST_STATUS_PIPE_PIDER_Pos 2 /**< \brief (USB_HOST_STATUS_PIPE) PID Error */ 1637 #define USB_HOST_STATUS_PIPE_PIDER (_U_(0x1) << USB_HOST_STATUS_PIPE_PIDER_Pos) 1638 #define USB_HOST_STATUS_PIPE_TOUTER_Pos 3 /**< \brief (USB_HOST_STATUS_PIPE) Time Out Error */ 1639 #define USB_HOST_STATUS_PIPE_TOUTER (_U_(0x1) << USB_HOST_STATUS_PIPE_TOUTER_Pos) 1640 #define USB_HOST_STATUS_PIPE_CRC16ER_Pos 4 /**< \brief (USB_HOST_STATUS_PIPE) CRC16 Error */ 1641 #define USB_HOST_STATUS_PIPE_CRC16ER (_U_(0x1) << USB_HOST_STATUS_PIPE_CRC16ER_Pos) 1642 #define USB_HOST_STATUS_PIPE_ERCNT_Pos 5 /**< \brief (USB_HOST_STATUS_PIPE) Pipe Error Count */ 1643 #define USB_HOST_STATUS_PIPE_ERCNT_Msk (_U_(0x7) << USB_HOST_STATUS_PIPE_ERCNT_Pos) 1644 #define USB_HOST_STATUS_PIPE_ERCNT(value) (USB_HOST_STATUS_PIPE_ERCNT_Msk & ((value) << USB_HOST_STATUS_PIPE_ERCNT_Pos)) 1645 #define USB_HOST_STATUS_PIPE_MASK _U_(0x00FF) /**< \brief (USB_HOST_STATUS_PIPE) MASK Register */ 1646 1647 /** \brief UsbDeviceDescBank SRAM registers */ 1648 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1649 typedef struct { 1650 __IO USB_DEVICE_ADDR_Type ADDR; /**< \brief Offset: 0x000 (R/W 32) DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer */ 1651 __IO USB_DEVICE_PCKSIZE_Type PCKSIZE; /**< \brief Offset: 0x004 (R/W 32) DEVICE_DESC_BANK Endpoint Bank, Packet Size */ 1652 __IO USB_DEVICE_EXTREG_Type EXTREG; /**< \brief Offset: 0x008 (R/W 16) DEVICE_DESC_BANK Endpoint Bank, Extended */ 1653 __IO USB_DEVICE_STATUS_BK_Type STATUS_BK; /**< \brief Offset: 0x00A (R/W 8) DEVICE_DESC_BANK Enpoint Bank, Status of Bank */ 1654 RoReg8 Reserved1[0x5]; 1655 } UsbDeviceDescBank; 1656 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1657 1658 /** \brief UsbHostDescBank SRAM registers */ 1659 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1660 typedef struct { 1661 __IO USB_HOST_ADDR_Type ADDR; /**< \brief Offset: 0x000 (R/W 32) HOST_DESC_BANK Host Bank, Adress of Data Buffer */ 1662 __IO USB_HOST_PCKSIZE_Type PCKSIZE; /**< \brief Offset: 0x004 (R/W 32) HOST_DESC_BANK Host Bank, Packet Size */ 1663 __IO USB_HOST_EXTREG_Type EXTREG; /**< \brief Offset: 0x008 (R/W 16) HOST_DESC_BANK Host Bank, Extended */ 1664 __IO USB_HOST_STATUS_BK_Type STATUS_BK; /**< \brief Offset: 0x00A (R/W 8) HOST_DESC_BANK Host Bank, Status of Bank */ 1665 RoReg8 Reserved1[0x1]; 1666 __IO USB_HOST_CTRL_PIPE_Type CTRL_PIPE; /**< \brief Offset: 0x00C (R/W 16) HOST_DESC_BANK Host Bank, Host Control Pipe */ 1667 __IO USB_HOST_STATUS_PIPE_Type STATUS_PIPE; /**< \brief Offset: 0x00E (R/W 16) HOST_DESC_BANK Host Bank, Host Status Pipe */ 1668 } UsbHostDescBank; 1669 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1670 1671 /** \brief UsbDeviceEndpoint hardware registers */ 1672 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1673 typedef struct { 1674 __IO USB_DEVICE_EPCFG_Type EPCFG; /**< \brief Offset: 0x000 (R/W 8) DEVICE_ENDPOINT End Point Configuration */ 1675 RoReg8 Reserved1[0x3]; 1676 __O USB_DEVICE_EPSTATUSCLR_Type EPSTATUSCLR; /**< \brief Offset: 0x004 ( /W 8) DEVICE_ENDPOINT End Point Pipe Status Clear */ 1677 __O USB_DEVICE_EPSTATUSSET_Type EPSTATUSSET; /**< \brief Offset: 0x005 ( /W 8) DEVICE_ENDPOINT End Point Pipe Status Set */ 1678 __I USB_DEVICE_EPSTATUS_Type EPSTATUS; /**< \brief Offset: 0x006 (R/ 8) DEVICE_ENDPOINT End Point Pipe Status */ 1679 __IO USB_DEVICE_EPINTFLAG_Type EPINTFLAG; /**< \brief Offset: 0x007 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Flag */ 1680 __IO USB_DEVICE_EPINTENCLR_Type EPINTENCLR; /**< \brief Offset: 0x008 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Clear Flag */ 1681 __IO USB_DEVICE_EPINTENSET_Type EPINTENSET; /**< \brief Offset: 0x009 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Set Flag */ 1682 RoReg8 Reserved2[0x16]; 1683 } UsbDeviceEndpoint; 1684 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1685 1686 /** \brief UsbHostPipe hardware registers */ 1687 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1688 typedef struct { 1689 __IO USB_HOST_PCFG_Type PCFG; /**< \brief Offset: 0x000 (R/W 8) HOST_PIPE End Point Configuration */ 1690 RoReg8 Reserved1[0x2]; 1691 __IO USB_HOST_BINTERVAL_Type BINTERVAL; /**< \brief Offset: 0x003 (R/W 8) HOST_PIPE Bus Access Period of Pipe */ 1692 __O USB_HOST_PSTATUSCLR_Type PSTATUSCLR; /**< \brief Offset: 0x004 ( /W 8) HOST_PIPE End Point Pipe Status Clear */ 1693 __O USB_HOST_PSTATUSSET_Type PSTATUSSET; /**< \brief Offset: 0x005 ( /W 8) HOST_PIPE End Point Pipe Status Set */ 1694 __I USB_HOST_PSTATUS_Type PSTATUS; /**< \brief Offset: 0x006 (R/ 8) HOST_PIPE End Point Pipe Status */ 1695 __IO USB_HOST_PINTFLAG_Type PINTFLAG; /**< \brief Offset: 0x007 (R/W 8) HOST_PIPE Pipe Interrupt Flag */ 1696 __IO USB_HOST_PINTENCLR_Type PINTENCLR; /**< \brief Offset: 0x008 (R/W 8) HOST_PIPE Pipe Interrupt Flag Clear */ 1697 __IO USB_HOST_PINTENSET_Type PINTENSET; /**< \brief Offset: 0x009 (R/W 8) HOST_PIPE Pipe Interrupt Flag Set */ 1698 RoReg8 Reserved2[0x16]; 1699 } UsbHostPipe; 1700 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1701 1702 /** \brief USB_DEVICE APB hardware registers */ 1703 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1704 typedef struct { /* USB is Device */ 1705 __IO USB_CTRLA_Type CTRLA; /**< \brief Offset: 0x000 (R/W 8) Control A */ 1706 RoReg8 Reserved1[0x1]; 1707 __I USB_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x002 (R/ 8) Synchronization Busy */ 1708 __IO USB_QOSCTRL_Type QOSCTRL; /**< \brief Offset: 0x003 (R/W 8) USB Quality Of Service */ 1709 RoReg8 Reserved2[0x4]; 1710 __IO USB_DEVICE_CTRLB_Type CTRLB; /**< \brief Offset: 0x008 (R/W 16) DEVICE Control B */ 1711 __IO USB_DEVICE_DADD_Type DADD; /**< \brief Offset: 0x00A (R/W 8) DEVICE Device Address */ 1712 RoReg8 Reserved3[0x1]; 1713 __I USB_DEVICE_STATUS_Type STATUS; /**< \brief Offset: 0x00C (R/ 8) DEVICE Status */ 1714 __I USB_FSMSTATUS_Type FSMSTATUS; /**< \brief Offset: 0x00D (R/ 8) Finite State Machine Status */ 1715 RoReg8 Reserved4[0x2]; 1716 __I USB_DEVICE_FNUM_Type FNUM; /**< \brief Offset: 0x010 (R/ 16) DEVICE Device Frame Number */ 1717 RoReg8 Reserved5[0x2]; 1718 __IO USB_DEVICE_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x014 (R/W 16) DEVICE Device Interrupt Enable Clear */ 1719 RoReg8 Reserved6[0x2]; 1720 __IO USB_DEVICE_INTENSET_Type INTENSET; /**< \brief Offset: 0x018 (R/W 16) DEVICE Device Interrupt Enable Set */ 1721 RoReg8 Reserved7[0x2]; 1722 __IO USB_DEVICE_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x01C (R/W 16) DEVICE Device Interrupt Flag */ 1723 RoReg8 Reserved8[0x2]; 1724 __I USB_DEVICE_EPINTSMRY_Type EPINTSMRY; /**< \brief Offset: 0x020 (R/ 16) DEVICE End Point Interrupt Summary */ 1725 RoReg8 Reserved9[0x2]; 1726 __IO USB_DESCADD_Type DESCADD; /**< \brief Offset: 0x024 (R/W 32) Descriptor Address */ 1727 __IO USB_PADCAL_Type PADCAL; /**< \brief Offset: 0x028 (R/W 16) USB PAD Calibration */ 1728 RoReg8 Reserved10[0xD6]; 1729 UsbDeviceEndpoint DeviceEndpoint[8]; /**< \brief Offset: 0x100 UsbDeviceEndpoint groups [EPT_NUM] */ 1730 } UsbDevice; 1731 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1732 1733 /** \brief USB_HOST hardware registers */ 1734 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1735 typedef struct { /* USB is Host */ 1736 __IO USB_CTRLA_Type CTRLA; /**< \brief Offset: 0x000 (R/W 8) Control A */ 1737 RoReg8 Reserved1[0x1]; 1738 __I USB_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x002 (R/ 8) Synchronization Busy */ 1739 __IO USB_QOSCTRL_Type QOSCTRL; /**< \brief Offset: 0x003 (R/W 8) USB Quality Of Service */ 1740 RoReg8 Reserved2[0x4]; 1741 __IO USB_HOST_CTRLB_Type CTRLB; /**< \brief Offset: 0x008 (R/W 16) HOST Control B */ 1742 __IO USB_HOST_HSOFC_Type HSOFC; /**< \brief Offset: 0x00A (R/W 8) HOST Host Start Of Frame Control */ 1743 RoReg8 Reserved3[0x1]; 1744 __IO USB_HOST_STATUS_Type STATUS; /**< \brief Offset: 0x00C (R/W 8) HOST Status */ 1745 __I USB_FSMSTATUS_Type FSMSTATUS; /**< \brief Offset: 0x00D (R/ 8) Finite State Machine Status */ 1746 RoReg8 Reserved4[0x2]; 1747 __IO USB_HOST_FNUM_Type FNUM; /**< \brief Offset: 0x010 (R/W 16) HOST Host Frame Number */ 1748 __I USB_HOST_FLENHIGH_Type FLENHIGH; /**< \brief Offset: 0x012 (R/ 8) HOST Host Frame Length */ 1749 RoReg8 Reserved5[0x1]; 1750 __IO USB_HOST_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x014 (R/W 16) HOST Host Interrupt Enable Clear */ 1751 RoReg8 Reserved6[0x2]; 1752 __IO USB_HOST_INTENSET_Type INTENSET; /**< \brief Offset: 0x018 (R/W 16) HOST Host Interrupt Enable Set */ 1753 RoReg8 Reserved7[0x2]; 1754 __IO USB_HOST_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x01C (R/W 16) HOST Host Interrupt Flag */ 1755 RoReg8 Reserved8[0x2]; 1756 __I USB_HOST_PINTSMRY_Type PINTSMRY; /**< \brief Offset: 0x020 (R/ 16) HOST Pipe Interrupt Summary */ 1757 RoReg8 Reserved9[0x2]; 1758 __IO USB_DESCADD_Type DESCADD; /**< \brief Offset: 0x024 (R/W 32) Descriptor Address */ 1759 __IO USB_PADCAL_Type PADCAL; /**< \brief Offset: 0x028 (R/W 16) USB PAD Calibration */ 1760 RoReg8 Reserved10[0xD6]; 1761 UsbHostPipe HostPipe[8]; /**< \brief Offset: 0x100 UsbHostPipe groups [EPT_NUM*HOST_IMPLEMENTED] */ 1762 } UsbHost; 1763 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1764 1765 /** \brief USB_DEVICE Descriptor SRAM registers */ 1766 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1767 typedef struct { /* USB is Device */ 1768 UsbDeviceDescBank DeviceDescBank[2]; /**< \brief Offset: 0x000 UsbDeviceDescBank groups */ 1769 } UsbDeviceDescriptor; 1770 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1771 1772 /** \brief USB_HOST Descriptor SRAM registers */ 1773 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1774 typedef struct { /* USB is Host */ 1775 UsbHostDescBank HostDescBank[2]; /**< \brief Offset: 0x000 UsbHostDescBank groups [2*HOST_IMPLEMENTED] */ 1776 } UsbHostDescriptor; 1777 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1778 1779 #define SECTION_USB_DESCRIPTOR 1780 1781 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1782 typedef union { 1783 UsbDevice DEVICE; /**< \brief Offset: 0x000 USB is Device */ 1784 UsbHost HOST; /**< \brief Offset: 0x000 USB is Host */ 1785 } Usb; 1786 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1787 1788 /*@}*/ 1789 1790 #endif /* _SAMR21_USB_COMPONENT_ */ 1791
