1 /** 2 * \file 3 * 4 * \brief Peripheral I/O description for SAML21J18BU 5 * 6 * Copyright (c) 2018 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAML21J18BU_PIO_ 31 #define _SAML21J18BU_PIO_ 32 33 #define PIN_PA00 0 /**< \brief Pin Number for PA00 */ 34 #define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */ 35 #define PIN_PA01 1 /**< \brief Pin Number for PA01 */ 36 #define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */ 37 #define PIN_PA02 2 /**< \brief Pin Number for PA02 */ 38 #define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */ 39 #define PIN_PA03 3 /**< \brief Pin Number for PA03 */ 40 #define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */ 41 #define PIN_PA04 4 /**< \brief Pin Number for PA04 */ 42 #define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */ 43 #define PIN_PA05 5 /**< \brief Pin Number for PA05 */ 44 #define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */ 45 #define PIN_PA06 6 /**< \brief Pin Number for PA06 */ 46 #define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */ 47 #define PIN_PA07 7 /**< \brief Pin Number for PA07 */ 48 #define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */ 49 #define PIN_PA08 8 /**< \brief Pin Number for PA08 */ 50 #define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */ 51 #define PIN_PA09 9 /**< \brief Pin Number for PA09 */ 52 #define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */ 53 #define PIN_PA10 10 /**< \brief Pin Number for PA10 */ 54 #define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */ 55 #define PIN_PA11 11 /**< \brief Pin Number for PA11 */ 56 #define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */ 57 #define PIN_PA12 12 /**< \brief Pin Number for PA12 */ 58 #define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */ 59 #define PIN_PA13 13 /**< \brief Pin Number for PA13 */ 60 #define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */ 61 #define PIN_PA14 14 /**< \brief Pin Number for PA14 */ 62 #define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */ 63 #define PIN_PA15 15 /**< \brief Pin Number for PA15 */ 64 #define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */ 65 #define PIN_PA16 16 /**< \brief Pin Number for PA16 */ 66 #define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */ 67 #define PIN_PA17 17 /**< \brief Pin Number for PA17 */ 68 #define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */ 69 #define PIN_PA18 18 /**< \brief Pin Number for PA18 */ 70 #define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */ 71 #define PIN_PA19 19 /**< \brief Pin Number for PA19 */ 72 #define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */ 73 #define PIN_PA20 20 /**< \brief Pin Number for PA20 */ 74 #define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */ 75 #define PIN_PA21 21 /**< \brief Pin Number for PA21 */ 76 #define PORT_PA21 (_UL_(1) << 21) /**< \brief PORT Mask for PA21 */ 77 #define PIN_PA22 22 /**< \brief Pin Number for PA22 */ 78 #define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */ 79 #define PIN_PA23 23 /**< \brief Pin Number for PA23 */ 80 #define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */ 81 #define PIN_PA24 24 /**< \brief Pin Number for PA24 */ 82 #define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */ 83 #define PIN_PA25 25 /**< \brief Pin Number for PA25 */ 84 #define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */ 85 #define PIN_PA27 27 /**< \brief Pin Number for PA27 */ 86 #define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */ 87 #define PIN_PA30 30 /**< \brief Pin Number for PA30 */ 88 #define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */ 89 #define PIN_PA31 31 /**< \brief Pin Number for PA31 */ 90 #define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */ 91 #define PIN_PB00 32 /**< \brief Pin Number for PB00 */ 92 #define PORT_PB00 (_UL_(1) << 0) /**< \brief PORT Mask for PB00 */ 93 #define PIN_PB01 33 /**< \brief Pin Number for PB01 */ 94 #define PORT_PB01 (_UL_(1) << 1) /**< \brief PORT Mask for PB01 */ 95 #define PIN_PB02 34 /**< \brief Pin Number for PB02 */ 96 #define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */ 97 #define PIN_PB03 35 /**< \brief Pin Number for PB03 */ 98 #define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */ 99 #define PIN_PB04 36 /**< \brief Pin Number for PB04 */ 100 #define PORT_PB04 (_UL_(1) << 4) /**< \brief PORT Mask for PB04 */ 101 #define PIN_PB05 37 /**< \brief Pin Number for PB05 */ 102 #define PORT_PB05 (_UL_(1) << 5) /**< \brief PORT Mask for PB05 */ 103 #define PIN_PB06 38 /**< \brief Pin Number for PB06 */ 104 #define PORT_PB06 (_UL_(1) << 6) /**< \brief PORT Mask for PB06 */ 105 #define PIN_PB07 39 /**< \brief Pin Number for PB07 */ 106 #define PORT_PB07 (_UL_(1) << 7) /**< \brief PORT Mask for PB07 */ 107 #define PIN_PB08 40 /**< \brief Pin Number for PB08 */ 108 #define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */ 109 #define PIN_PB09 41 /**< \brief Pin Number for PB09 */ 110 #define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */ 111 #define PIN_PB10 42 /**< \brief Pin Number for PB10 */ 112 #define PORT_PB10 (_UL_(1) << 10) /**< \brief PORT Mask for PB10 */ 113 #define PIN_PB11 43 /**< \brief Pin Number for PB11 */ 114 #define PORT_PB11 (_UL_(1) << 11) /**< \brief PORT Mask for PB11 */ 115 #define PIN_PB12 44 /**< \brief Pin Number for PB12 */ 116 #define PORT_PB12 (_UL_(1) << 12) /**< \brief PORT Mask for PB12 */ 117 #define PIN_PB13 45 /**< \brief Pin Number for PB13 */ 118 #define PORT_PB13 (_UL_(1) << 13) /**< \brief PORT Mask for PB13 */ 119 #define PIN_PB14 46 /**< \brief Pin Number for PB14 */ 120 #define PORT_PB14 (_UL_(1) << 14) /**< \brief PORT Mask for PB14 */ 121 #define PIN_PB15 47 /**< \brief Pin Number for PB15 */ 122 #define PORT_PB15 (_UL_(1) << 15) /**< \brief PORT Mask for PB15 */ 123 #define PIN_PB16 48 /**< \brief Pin Number for PB16 */ 124 #define PORT_PB16 (_UL_(1) << 16) /**< \brief PORT Mask for PB16 */ 125 #define PIN_PB17 49 /**< \brief Pin Number for PB17 */ 126 #define PORT_PB17 (_UL_(1) << 17) /**< \brief PORT Mask for PB17 */ 127 #define PIN_PB22 54 /**< \brief Pin Number for PB22 */ 128 #define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */ 129 #define PIN_PB23 55 /**< \brief Pin Number for PB23 */ 130 #define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */ 131 #define PIN_PB30 62 /**< \brief Pin Number for PB30 */ 132 #define PORT_PB30 (_UL_(1) << 30) /**< \brief PORT Mask for PB30 */ 133 #define PIN_PB31 63 /**< \brief Pin Number for PB31 */ 134 #define PORT_PB31 (_UL_(1) << 31) /**< \brief PORT Mask for PB31 */ 135 /* ========== PORT definition for RSTC peripheral ========== */ 136 #define PIN_PA00A_RSTC_EXTWAKE0 _L_(0) /**< \brief RSTC signal: EXTWAKE0 on PA00 mux A */ 137 #define MUX_PA00A_RSTC_EXTWAKE0 _L_(0) 138 #define PINMUX_PA00A_RSTC_EXTWAKE0 ((PIN_PA00A_RSTC_EXTWAKE0 << 16) | MUX_PA00A_RSTC_EXTWAKE0) 139 #define PORT_PA00A_RSTC_EXTWAKE0 (_UL_(1) << 0) 140 #define PIN_PA01A_RSTC_EXTWAKE1 _L_(1) /**< \brief RSTC signal: EXTWAKE1 on PA01 mux A */ 141 #define MUX_PA01A_RSTC_EXTWAKE1 _L_(0) 142 #define PINMUX_PA01A_RSTC_EXTWAKE1 ((PIN_PA01A_RSTC_EXTWAKE1 << 16) | MUX_PA01A_RSTC_EXTWAKE1) 143 #define PORT_PA01A_RSTC_EXTWAKE1 (_UL_(1) << 1) 144 #define PIN_PA02A_RSTC_EXTWAKE2 _L_(2) /**< \brief RSTC signal: EXTWAKE2 on PA02 mux A */ 145 #define MUX_PA02A_RSTC_EXTWAKE2 _L_(0) 146 #define PINMUX_PA02A_RSTC_EXTWAKE2 ((PIN_PA02A_RSTC_EXTWAKE2 << 16) | MUX_PA02A_RSTC_EXTWAKE2) 147 #define PORT_PA02A_RSTC_EXTWAKE2 (_UL_(1) << 2) 148 #define PIN_PA03A_RSTC_EXTWAKE3 _L_(3) /**< \brief RSTC signal: EXTWAKE3 on PA03 mux A */ 149 #define MUX_PA03A_RSTC_EXTWAKE3 _L_(0) 150 #define PINMUX_PA03A_RSTC_EXTWAKE3 ((PIN_PA03A_RSTC_EXTWAKE3 << 16) | MUX_PA03A_RSTC_EXTWAKE3) 151 #define PORT_PA03A_RSTC_EXTWAKE3 (_UL_(1) << 3) 152 #define PIN_PA04A_RSTC_EXTWAKE4 _L_(4) /**< \brief RSTC signal: EXTWAKE4 on PA04 mux A */ 153 #define MUX_PA04A_RSTC_EXTWAKE4 _L_(0) 154 #define PINMUX_PA04A_RSTC_EXTWAKE4 ((PIN_PA04A_RSTC_EXTWAKE4 << 16) | MUX_PA04A_RSTC_EXTWAKE4) 155 #define PORT_PA04A_RSTC_EXTWAKE4 (_UL_(1) << 4) 156 #define PIN_PA05A_RSTC_EXTWAKE5 _L_(5) /**< \brief RSTC signal: EXTWAKE5 on PA05 mux A */ 157 #define MUX_PA05A_RSTC_EXTWAKE5 _L_(0) 158 #define PINMUX_PA05A_RSTC_EXTWAKE5 ((PIN_PA05A_RSTC_EXTWAKE5 << 16) | MUX_PA05A_RSTC_EXTWAKE5) 159 #define PORT_PA05A_RSTC_EXTWAKE5 (_UL_(1) << 5) 160 #define PIN_PA06A_RSTC_EXTWAKE6 _L_(6) /**< \brief RSTC signal: EXTWAKE6 on PA06 mux A */ 161 #define MUX_PA06A_RSTC_EXTWAKE6 _L_(0) 162 #define PINMUX_PA06A_RSTC_EXTWAKE6 ((PIN_PA06A_RSTC_EXTWAKE6 << 16) | MUX_PA06A_RSTC_EXTWAKE6) 163 #define PORT_PA06A_RSTC_EXTWAKE6 (_UL_(1) << 6) 164 #define PIN_PA07A_RSTC_EXTWAKE7 _L_(7) /**< \brief RSTC signal: EXTWAKE7 on PA07 mux A */ 165 #define MUX_PA07A_RSTC_EXTWAKE7 _L_(0) 166 #define PINMUX_PA07A_RSTC_EXTWAKE7 ((PIN_PA07A_RSTC_EXTWAKE7 << 16) | MUX_PA07A_RSTC_EXTWAKE7) 167 #define PORT_PA07A_RSTC_EXTWAKE7 (_UL_(1) << 7) 168 /* ========== PORT definition for SUPC peripheral ========== */ 169 #define PIN_PB01H_SUPC_OUT0 _L_(33) /**< \brief SUPC signal: OUT0 on PB01 mux H */ 170 #define MUX_PB01H_SUPC_OUT0 _L_(7) 171 #define PINMUX_PB01H_SUPC_OUT0 ((PIN_PB01H_SUPC_OUT0 << 16) | MUX_PB01H_SUPC_OUT0) 172 #define PORT_PB01H_SUPC_OUT0 (_UL_(1) << 1) 173 #define PIN_PB02H_SUPC_OUT1 _L_(34) /**< \brief SUPC signal: OUT1 on PB02 mux H */ 174 #define MUX_PB02H_SUPC_OUT1 _L_(7) 175 #define PINMUX_PB02H_SUPC_OUT1 ((PIN_PB02H_SUPC_OUT1 << 16) | MUX_PB02H_SUPC_OUT1) 176 #define PORT_PB02H_SUPC_OUT1 (_UL_(1) << 2) 177 #define PIN_PB00H_SUPC_PSOK _L_(32) /**< \brief SUPC signal: PSOK on PB00 mux H */ 178 #define MUX_PB00H_SUPC_PSOK _L_(7) 179 #define PINMUX_PB00H_SUPC_PSOK ((PIN_PB00H_SUPC_PSOK << 16) | MUX_PB00H_SUPC_PSOK) 180 #define PORT_PB00H_SUPC_PSOK (_UL_(1) << 0) 181 #define PIN_PB03H_SUPC_VBAT _L_(35) /**< \brief SUPC signal: VBAT on PB03 mux H */ 182 #define MUX_PB03H_SUPC_VBAT _L_(7) 183 #define PINMUX_PB03H_SUPC_VBAT ((PIN_PB03H_SUPC_VBAT << 16) | MUX_PB03H_SUPC_VBAT) 184 #define PORT_PB03H_SUPC_VBAT (_UL_(1) << 3) 185 /* ========== PORT definition for GCLK peripheral ========== */ 186 #define PIN_PB14H_GCLK_IO0 _L_(46) /**< \brief GCLK signal: IO0 on PB14 mux H */ 187 #define MUX_PB14H_GCLK_IO0 _L_(7) 188 #define PINMUX_PB14H_GCLK_IO0 ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0) 189 #define PORT_PB14H_GCLK_IO0 (_UL_(1) << 14) 190 #define PIN_PB22H_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux H */ 191 #define MUX_PB22H_GCLK_IO0 _L_(7) 192 #define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0) 193 #define PORT_PB22H_GCLK_IO0 (_UL_(1) << 22) 194 #define PIN_PA14H_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux H */ 195 #define MUX_PA14H_GCLK_IO0 _L_(7) 196 #define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) 197 #define PORT_PA14H_GCLK_IO0 (_UL_(1) << 14) 198 #define PIN_PA27H_GCLK_IO0 _L_(27) /**< \brief GCLK signal: IO0 on PA27 mux H */ 199 #define MUX_PA27H_GCLK_IO0 _L_(7) 200 #define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) 201 #define PORT_PA27H_GCLK_IO0 (_UL_(1) << 27) 202 #define PIN_PA30H_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux H */ 203 #define MUX_PA30H_GCLK_IO0 _L_(7) 204 #define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) 205 #define PORT_PA30H_GCLK_IO0 (_UL_(1) << 30) 206 #define PIN_PB15H_GCLK_IO1 _L_(47) /**< \brief GCLK signal: IO1 on PB15 mux H */ 207 #define MUX_PB15H_GCLK_IO1 _L_(7) 208 #define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1) 209 #define PORT_PB15H_GCLK_IO1 (_UL_(1) << 15) 210 #define PIN_PB23H_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux H */ 211 #define MUX_PB23H_GCLK_IO1 _L_(7) 212 #define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1) 213 #define PORT_PB23H_GCLK_IO1 (_UL_(1) << 23) 214 #define PIN_PA15H_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux H */ 215 #define MUX_PA15H_GCLK_IO1 _L_(7) 216 #define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) 217 #define PORT_PA15H_GCLK_IO1 (_UL_(1) << 15) 218 #define PIN_PB16H_GCLK_IO2 _L_(48) /**< \brief GCLK signal: IO2 on PB16 mux H */ 219 #define MUX_PB16H_GCLK_IO2 _L_(7) 220 #define PINMUX_PB16H_GCLK_IO2 ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2) 221 #define PORT_PB16H_GCLK_IO2 (_UL_(1) << 16) 222 #define PIN_PA16H_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux H */ 223 #define MUX_PA16H_GCLK_IO2 _L_(7) 224 #define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) 225 #define PORT_PA16H_GCLK_IO2 (_UL_(1) << 16) 226 #define PIN_PA17H_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux H */ 227 #define MUX_PA17H_GCLK_IO3 _L_(7) 228 #define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) 229 #define PORT_PA17H_GCLK_IO3 (_UL_(1) << 17) 230 #define PIN_PB17H_GCLK_IO3 _L_(49) /**< \brief GCLK signal: IO3 on PB17 mux H */ 231 #define MUX_PB17H_GCLK_IO3 _L_(7) 232 #define PINMUX_PB17H_GCLK_IO3 ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3) 233 #define PORT_PB17H_GCLK_IO3 (_UL_(1) << 17) 234 #define PIN_PA10H_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux H */ 235 #define MUX_PA10H_GCLK_IO4 _L_(7) 236 #define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) 237 #define PORT_PA10H_GCLK_IO4 (_UL_(1) << 10) 238 #define PIN_PA20H_GCLK_IO4 _L_(20) /**< \brief GCLK signal: IO4 on PA20 mux H */ 239 #define MUX_PA20H_GCLK_IO4 _L_(7) 240 #define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4) 241 #define PORT_PA20H_GCLK_IO4 (_UL_(1) << 20) 242 #define PIN_PB10H_GCLK_IO4 _L_(42) /**< \brief GCLK signal: IO4 on PB10 mux H */ 243 #define MUX_PB10H_GCLK_IO4 _L_(7) 244 #define PINMUX_PB10H_GCLK_IO4 ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4) 245 #define PORT_PB10H_GCLK_IO4 (_UL_(1) << 10) 246 #define PIN_PA11H_GCLK_IO5 _L_(11) /**< \brief GCLK signal: IO5 on PA11 mux H */ 247 #define MUX_PA11H_GCLK_IO5 _L_(7) 248 #define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) 249 #define PORT_PA11H_GCLK_IO5 (_UL_(1) << 11) 250 #define PIN_PA21H_GCLK_IO5 _L_(21) /**< \brief GCLK signal: IO5 on PA21 mux H */ 251 #define MUX_PA21H_GCLK_IO5 _L_(7) 252 #define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5) 253 #define PORT_PA21H_GCLK_IO5 (_UL_(1) << 21) 254 #define PIN_PB11H_GCLK_IO5 _L_(43) /**< \brief GCLK signal: IO5 on PB11 mux H */ 255 #define MUX_PB11H_GCLK_IO5 _L_(7) 256 #define PINMUX_PB11H_GCLK_IO5 ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5) 257 #define PORT_PB11H_GCLK_IO5 (_UL_(1) << 11) 258 #define PIN_PA22H_GCLK_IO6 _L_(22) /**< \brief GCLK signal: IO6 on PA22 mux H */ 259 #define MUX_PA22H_GCLK_IO6 _L_(7) 260 #define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6) 261 #define PORT_PA22H_GCLK_IO6 (_UL_(1) << 22) 262 #define PIN_PB12H_GCLK_IO6 _L_(44) /**< \brief GCLK signal: IO6 on PB12 mux H */ 263 #define MUX_PB12H_GCLK_IO6 _L_(7) 264 #define PINMUX_PB12H_GCLK_IO6 ((PIN_PB12H_GCLK_IO6 << 16) | MUX_PB12H_GCLK_IO6) 265 #define PORT_PB12H_GCLK_IO6 (_UL_(1) << 12) 266 #define PIN_PA23H_GCLK_IO7 _L_(23) /**< \brief GCLK signal: IO7 on PA23 mux H */ 267 #define MUX_PA23H_GCLK_IO7 _L_(7) 268 #define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7) 269 #define PORT_PA23H_GCLK_IO7 (_UL_(1) << 23) 270 #define PIN_PB13H_GCLK_IO7 _L_(45) /**< \brief GCLK signal: IO7 on PB13 mux H */ 271 #define MUX_PB13H_GCLK_IO7 _L_(7) 272 #define PINMUX_PB13H_GCLK_IO7 ((PIN_PB13H_GCLK_IO7 << 16) | MUX_PB13H_GCLK_IO7) 273 #define PORT_PB13H_GCLK_IO7 (_UL_(1) << 13) 274 /* ========== PORT definition for EIC peripheral ========== */ 275 #define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */ 276 #define MUX_PA16A_EIC_EXTINT0 _L_(0) 277 #define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) 278 #define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16) 279 #define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ 280 #define PIN_PB00A_EIC_EXTINT0 _L_(32) /**< \brief EIC signal: EXTINT0 on PB00 mux A */ 281 #define MUX_PB00A_EIC_EXTINT0 _L_(0) 282 #define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) 283 #define PORT_PB00A_EIC_EXTINT0 (_UL_(1) << 0) 284 #define PIN_PB00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB00 External Interrupt Line */ 285 #define PIN_PB16A_EIC_EXTINT0 _L_(48) /**< \brief EIC signal: EXTINT0 on PB16 mux A */ 286 #define MUX_PB16A_EIC_EXTINT0 _L_(0) 287 #define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) 288 #define PORT_PB16A_EIC_EXTINT0 (_UL_(1) << 16) 289 #define PIN_PB16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB16 External Interrupt Line */ 290 #define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */ 291 #define MUX_PA00A_EIC_EXTINT0 _L_(0) 292 #define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) 293 #define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0) 294 #define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */ 295 #define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */ 296 #define MUX_PA17A_EIC_EXTINT1 _L_(0) 297 #define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) 298 #define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17) 299 #define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ 300 #define PIN_PB01A_EIC_EXTINT1 _L_(33) /**< \brief EIC signal: EXTINT1 on PB01 mux A */ 301 #define MUX_PB01A_EIC_EXTINT1 _L_(0) 302 #define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) 303 #define PORT_PB01A_EIC_EXTINT1 (_UL_(1) << 1) 304 #define PIN_PB01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB01 External Interrupt Line */ 305 #define PIN_PB17A_EIC_EXTINT1 _L_(49) /**< \brief EIC signal: EXTINT1 on PB17 mux A */ 306 #define MUX_PB17A_EIC_EXTINT1 _L_(0) 307 #define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) 308 #define PORT_PB17A_EIC_EXTINT1 (_UL_(1) << 17) 309 #define PIN_PB17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB17 External Interrupt Line */ 310 #define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */ 311 #define MUX_PA01A_EIC_EXTINT1 _L_(0) 312 #define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) 313 #define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1) 314 #define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */ 315 #define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */ 316 #define MUX_PA02A_EIC_EXTINT2 _L_(0) 317 #define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) 318 #define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2) 319 #define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */ 320 #define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */ 321 #define MUX_PA18A_EIC_EXTINT2 _L_(0) 322 #define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) 323 #define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18) 324 #define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ 325 #define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */ 326 #define MUX_PB02A_EIC_EXTINT2 _L_(0) 327 #define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) 328 #define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2) 329 #define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */ 330 #define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */ 331 #define MUX_PA03A_EIC_EXTINT3 _L_(0) 332 #define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) 333 #define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3) 334 #define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */ 335 #define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */ 336 #define MUX_PA19A_EIC_EXTINT3 _L_(0) 337 #define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) 338 #define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19) 339 #define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ 340 #define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */ 341 #define MUX_PB03A_EIC_EXTINT3 _L_(0) 342 #define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) 343 #define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3) 344 #define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */ 345 #define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */ 346 #define MUX_PA04A_EIC_EXTINT4 _L_(0) 347 #define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) 348 #define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4) 349 #define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */ 350 #define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */ 351 #define MUX_PA20A_EIC_EXTINT4 _L_(0) 352 #define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) 353 #define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20) 354 #define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */ 355 #define PIN_PB04A_EIC_EXTINT4 _L_(36) /**< \brief EIC signal: EXTINT4 on PB04 mux A */ 356 #define MUX_PB04A_EIC_EXTINT4 _L_(0) 357 #define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) 358 #define PORT_PB04A_EIC_EXTINT4 (_UL_(1) << 4) 359 #define PIN_PB04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB04 External Interrupt Line */ 360 #define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */ 361 #define MUX_PA05A_EIC_EXTINT5 _L_(0) 362 #define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) 363 #define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5) 364 #define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */ 365 #define PIN_PA21A_EIC_EXTINT5 _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */ 366 #define MUX_PA21A_EIC_EXTINT5 _L_(0) 367 #define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) 368 #define PORT_PA21A_EIC_EXTINT5 (_UL_(1) << 21) 369 #define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */ 370 #define PIN_PB05A_EIC_EXTINT5 _L_(37) /**< \brief EIC signal: EXTINT5 on PB05 mux A */ 371 #define MUX_PB05A_EIC_EXTINT5 _L_(0) 372 #define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) 373 #define PORT_PB05A_EIC_EXTINT5 (_UL_(1) << 5) 374 #define PIN_PB05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB05 External Interrupt Line */ 375 #define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */ 376 #define MUX_PA06A_EIC_EXTINT6 _L_(0) 377 #define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) 378 #define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6) 379 #define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ 380 #define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */ 381 #define MUX_PA22A_EIC_EXTINT6 _L_(0) 382 #define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) 383 #define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22) 384 #define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */ 385 #define PIN_PB06A_EIC_EXTINT6 _L_(38) /**< \brief EIC signal: EXTINT6 on PB06 mux A */ 386 #define MUX_PB06A_EIC_EXTINT6 _L_(0) 387 #define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) 388 #define PORT_PB06A_EIC_EXTINT6 (_UL_(1) << 6) 389 #define PIN_PB06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB06 External Interrupt Line */ 390 #define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */ 391 #define MUX_PB22A_EIC_EXTINT6 _L_(0) 392 #define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) 393 #define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22) 394 #define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */ 395 #define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */ 396 #define MUX_PA07A_EIC_EXTINT7 _L_(0) 397 #define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) 398 #define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7) 399 #define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ 400 #define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */ 401 #define MUX_PA23A_EIC_EXTINT7 _L_(0) 402 #define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) 403 #define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23) 404 #define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */ 405 #define PIN_PB07A_EIC_EXTINT7 _L_(39) /**< \brief EIC signal: EXTINT7 on PB07 mux A */ 406 #define MUX_PB07A_EIC_EXTINT7 _L_(0) 407 #define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) 408 #define PORT_PB07A_EIC_EXTINT7 (_UL_(1) << 7) 409 #define PIN_PB07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB07 External Interrupt Line */ 410 #define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */ 411 #define MUX_PB23A_EIC_EXTINT7 _L_(0) 412 #define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) 413 #define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23) 414 #define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */ 415 #define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */ 416 #define MUX_PB08A_EIC_EXTINT8 _L_(0) 417 #define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) 418 #define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8) 419 #define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */ 420 #define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */ 421 #define MUX_PA09A_EIC_EXTINT9 _L_(0) 422 #define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) 423 #define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9) 424 #define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */ 425 #define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */ 426 #define MUX_PB09A_EIC_EXTINT9 _L_(0) 427 #define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) 428 #define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9) 429 #define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */ 430 #define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */ 431 #define MUX_PA10A_EIC_EXTINT10 _L_(0) 432 #define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) 433 #define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10) 434 #define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */ 435 #define PIN_PA30A_EIC_EXTINT10 _L_(30) /**< \brief EIC signal: EXTINT10 on PA30 mux A */ 436 #define MUX_PA30A_EIC_EXTINT10 _L_(0) 437 #define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) 438 #define PORT_PA30A_EIC_EXTINT10 (_UL_(1) << 30) 439 #define PIN_PA30A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */ 440 #define PIN_PB10A_EIC_EXTINT10 _L_(42) /**< \brief EIC signal: EXTINT10 on PB10 mux A */ 441 #define MUX_PB10A_EIC_EXTINT10 _L_(0) 442 #define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) 443 #define PORT_PB10A_EIC_EXTINT10 (_UL_(1) << 10) 444 #define PIN_PB10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PB10 External Interrupt Line */ 445 #define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */ 446 #define MUX_PA11A_EIC_EXTINT11 _L_(0) 447 #define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) 448 #define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11) 449 #define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */ 450 #define PIN_PA31A_EIC_EXTINT11 _L_(31) /**< \brief EIC signal: EXTINT11 on PA31 mux A */ 451 #define MUX_PA31A_EIC_EXTINT11 _L_(0) 452 #define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) 453 #define PORT_PA31A_EIC_EXTINT11 (_UL_(1) << 31) 454 #define PIN_PA31A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */ 455 #define PIN_PB11A_EIC_EXTINT11 _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */ 456 #define MUX_PB11A_EIC_EXTINT11 _L_(0) 457 #define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) 458 #define PORT_PB11A_EIC_EXTINT11 (_UL_(1) << 11) 459 #define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */ 460 #define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */ 461 #define MUX_PA12A_EIC_EXTINT12 _L_(0) 462 #define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) 463 #define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12) 464 #define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */ 465 #define PIN_PA24A_EIC_EXTINT12 _L_(24) /**< \brief EIC signal: EXTINT12 on PA24 mux A */ 466 #define MUX_PA24A_EIC_EXTINT12 _L_(0) 467 #define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) 468 #define PORT_PA24A_EIC_EXTINT12 (_UL_(1) << 24) 469 #define PIN_PA24A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */ 470 #define PIN_PB12A_EIC_EXTINT12 _L_(44) /**< \brief EIC signal: EXTINT12 on PB12 mux A */ 471 #define MUX_PB12A_EIC_EXTINT12 _L_(0) 472 #define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) 473 #define PORT_PB12A_EIC_EXTINT12 (_UL_(1) << 12) 474 #define PIN_PB12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PB12 External Interrupt Line */ 475 #define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */ 476 #define MUX_PA13A_EIC_EXTINT13 _L_(0) 477 #define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) 478 #define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13) 479 #define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */ 480 #define PIN_PA25A_EIC_EXTINT13 _L_(25) /**< \brief EIC signal: EXTINT13 on PA25 mux A */ 481 #define MUX_PA25A_EIC_EXTINT13 _L_(0) 482 #define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) 483 #define PORT_PA25A_EIC_EXTINT13 (_UL_(1) << 25) 484 #define PIN_PA25A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */ 485 #define PIN_PB13A_EIC_EXTINT13 _L_(45) /**< \brief EIC signal: EXTINT13 on PB13 mux A */ 486 #define MUX_PB13A_EIC_EXTINT13 _L_(0) 487 #define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) 488 #define PORT_PB13A_EIC_EXTINT13 (_UL_(1) << 13) 489 #define PIN_PB13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PB13 External Interrupt Line */ 490 #define PIN_PB14A_EIC_EXTINT14 _L_(46) /**< \brief EIC signal: EXTINT14 on PB14 mux A */ 491 #define MUX_PB14A_EIC_EXTINT14 _L_(0) 492 #define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) 493 #define PORT_PB14A_EIC_EXTINT14 (_UL_(1) << 14) 494 #define PIN_PB14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB14 External Interrupt Line */ 495 #define PIN_PB30A_EIC_EXTINT14 _L_(62) /**< \brief EIC signal: EXTINT14 on PB30 mux A */ 496 #define MUX_PB30A_EIC_EXTINT14 _L_(0) 497 #define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) 498 #define PORT_PB30A_EIC_EXTINT14 (_UL_(1) << 30) 499 #define PIN_PB30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB30 External Interrupt Line */ 500 #define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */ 501 #define MUX_PA14A_EIC_EXTINT14 _L_(0) 502 #define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) 503 #define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14) 504 #define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */ 505 #define PIN_PA27A_EIC_EXTINT15 _L_(27) /**< \brief EIC signal: EXTINT15 on PA27 mux A */ 506 #define MUX_PA27A_EIC_EXTINT15 _L_(0) 507 #define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) 508 #define PORT_PA27A_EIC_EXTINT15 (_UL_(1) << 27) 509 #define PIN_PA27A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */ 510 #define PIN_PB15A_EIC_EXTINT15 _L_(47) /**< \brief EIC signal: EXTINT15 on PB15 mux A */ 511 #define MUX_PB15A_EIC_EXTINT15 _L_(0) 512 #define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) 513 #define PORT_PB15A_EIC_EXTINT15 (_UL_(1) << 15) 514 #define PIN_PB15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB15 External Interrupt Line */ 515 #define PIN_PB31A_EIC_EXTINT15 _L_(63) /**< \brief EIC signal: EXTINT15 on PB31 mux A */ 516 #define MUX_PB31A_EIC_EXTINT15 _L_(0) 517 #define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) 518 #define PORT_PB31A_EIC_EXTINT15 (_UL_(1) << 31) 519 #define PIN_PB31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB31 External Interrupt Line */ 520 #define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */ 521 #define MUX_PA15A_EIC_EXTINT15 _L_(0) 522 #define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) 523 #define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15) 524 #define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */ 525 #define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */ 526 #define MUX_PA08A_EIC_NMI _L_(0) 527 #define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) 528 #define PORT_PA08A_EIC_NMI (_UL_(1) << 8) 529 /* ========== PORT definition for USB peripheral ========== */ 530 #define PIN_PA24G_USB_DM _L_(24) /**< \brief USB signal: DM on PA24 mux G */ 531 #define MUX_PA24G_USB_DM _L_(6) 532 #define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) 533 #define PORT_PA24G_USB_DM (_UL_(1) << 24) 534 #define PIN_PA25G_USB_DP _L_(25) /**< \brief USB signal: DP on PA25 mux G */ 535 #define MUX_PA25G_USB_DP _L_(6) 536 #define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) 537 #define PORT_PA25G_USB_DP (_UL_(1) << 25) 538 #define PIN_PA23G_USB_SOF_1KHZ _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ 539 #define MUX_PA23G_USB_SOF_1KHZ _L_(6) 540 #define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) 541 #define PORT_PA23G_USB_SOF_1KHZ (_UL_(1) << 23) 542 /* ========== PORT definition for SERCOM0 peripheral ========== */ 543 #define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ 544 #define MUX_PA04D_SERCOM0_PAD0 _L_(3) 545 #define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) 546 #define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4) 547 #define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ 548 #define MUX_PA08C_SERCOM0_PAD0 _L_(2) 549 #define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) 550 #define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8) 551 #define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ 552 #define MUX_PA05D_SERCOM0_PAD1 _L_(3) 553 #define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) 554 #define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5) 555 #define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ 556 #define MUX_PA09C_SERCOM0_PAD1 _L_(2) 557 #define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) 558 #define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9) 559 #define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ 560 #define MUX_PA06D_SERCOM0_PAD2 _L_(3) 561 #define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) 562 #define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6) 563 #define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ 564 #define MUX_PA10C_SERCOM0_PAD2 _L_(2) 565 #define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) 566 #define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10) 567 #define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ 568 #define MUX_PA07D_SERCOM0_PAD3 _L_(3) 569 #define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) 570 #define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7) 571 #define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ 572 #define MUX_PA11C_SERCOM0_PAD3 _L_(2) 573 #define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) 574 #define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11) 575 /* ========== PORT definition for SERCOM1 peripheral ========== */ 576 #define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ 577 #define MUX_PA16C_SERCOM1_PAD0 _L_(2) 578 #define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) 579 #define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16) 580 #define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ 581 #define MUX_PA00D_SERCOM1_PAD0 _L_(3) 582 #define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) 583 #define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0) 584 #define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ 585 #define MUX_PA17C_SERCOM1_PAD1 _L_(2) 586 #define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) 587 #define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17) 588 #define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ 589 #define MUX_PA01D_SERCOM1_PAD1 _L_(3) 590 #define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) 591 #define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1) 592 #define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ 593 #define MUX_PA30D_SERCOM1_PAD2 _L_(3) 594 #define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) 595 #define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30) 596 #define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ 597 #define MUX_PA18C_SERCOM1_PAD2 _L_(2) 598 #define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) 599 #define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18) 600 #define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ 601 #define MUX_PA31D_SERCOM1_PAD3 _L_(3) 602 #define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) 603 #define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31) 604 #define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ 605 #define MUX_PA19C_SERCOM1_PAD3 _L_(2) 606 #define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) 607 #define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19) 608 /* ========== PORT definition for SERCOM2 peripheral ========== */ 609 #define PIN_PA08D_SERCOM2_PAD0 _L_(8) /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ 610 #define MUX_PA08D_SERCOM2_PAD0 _L_(3) 611 #define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) 612 #define PORT_PA08D_SERCOM2_PAD0 (_UL_(1) << 8) 613 #define PIN_PA12C_SERCOM2_PAD0 _L_(12) /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ 614 #define MUX_PA12C_SERCOM2_PAD0 _L_(2) 615 #define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) 616 #define PORT_PA12C_SERCOM2_PAD0 (_UL_(1) << 12) 617 #define PIN_PA09D_SERCOM2_PAD1 _L_(9) /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ 618 #define MUX_PA09D_SERCOM2_PAD1 _L_(3) 619 #define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) 620 #define PORT_PA09D_SERCOM2_PAD1 (_UL_(1) << 9) 621 #define PIN_PA13C_SERCOM2_PAD1 _L_(13) /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ 622 #define MUX_PA13C_SERCOM2_PAD1 _L_(2) 623 #define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) 624 #define PORT_PA13C_SERCOM2_PAD1 (_UL_(1) << 13) 625 #define PIN_PA10D_SERCOM2_PAD2 _L_(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ 626 #define MUX_PA10D_SERCOM2_PAD2 _L_(3) 627 #define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) 628 #define PORT_PA10D_SERCOM2_PAD2 (_UL_(1) << 10) 629 #define PIN_PA14C_SERCOM2_PAD2 _L_(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ 630 #define MUX_PA14C_SERCOM2_PAD2 _L_(2) 631 #define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) 632 #define PORT_PA14C_SERCOM2_PAD2 (_UL_(1) << 14) 633 #define PIN_PA11D_SERCOM2_PAD3 _L_(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ 634 #define MUX_PA11D_SERCOM2_PAD3 _L_(3) 635 #define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) 636 #define PORT_PA11D_SERCOM2_PAD3 (_UL_(1) << 11) 637 #define PIN_PA15C_SERCOM2_PAD3 _L_(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ 638 #define MUX_PA15C_SERCOM2_PAD3 _L_(2) 639 #define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) 640 #define PORT_PA15C_SERCOM2_PAD3 (_UL_(1) << 15) 641 /* ========== PORT definition for SERCOM3 peripheral ========== */ 642 #define PIN_PA16D_SERCOM3_PAD0 _L_(16) /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ 643 #define MUX_PA16D_SERCOM3_PAD0 _L_(3) 644 #define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) 645 #define PORT_PA16D_SERCOM3_PAD0 (_UL_(1) << 16) 646 #define PIN_PA22C_SERCOM3_PAD0 _L_(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ 647 #define MUX_PA22C_SERCOM3_PAD0 _L_(2) 648 #define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) 649 #define PORT_PA22C_SERCOM3_PAD0 (_UL_(1) << 22) 650 #define PIN_PA17D_SERCOM3_PAD1 _L_(17) /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ 651 #define MUX_PA17D_SERCOM3_PAD1 _L_(3) 652 #define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) 653 #define PORT_PA17D_SERCOM3_PAD1 (_UL_(1) << 17) 654 #define PIN_PA23C_SERCOM3_PAD1 _L_(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ 655 #define MUX_PA23C_SERCOM3_PAD1 _L_(2) 656 #define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) 657 #define PORT_PA23C_SERCOM3_PAD1 (_UL_(1) << 23) 658 #define PIN_PA18D_SERCOM3_PAD2 _L_(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ 659 #define MUX_PA18D_SERCOM3_PAD2 _L_(3) 660 #define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) 661 #define PORT_PA18D_SERCOM3_PAD2 (_UL_(1) << 18) 662 #define PIN_PA20D_SERCOM3_PAD2 _L_(20) /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ 663 #define MUX_PA20D_SERCOM3_PAD2 _L_(3) 664 #define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) 665 #define PORT_PA20D_SERCOM3_PAD2 (_UL_(1) << 20) 666 #define PIN_PA24C_SERCOM3_PAD2 _L_(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ 667 #define MUX_PA24C_SERCOM3_PAD2 _L_(2) 668 #define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) 669 #define PORT_PA24C_SERCOM3_PAD2 (_UL_(1) << 24) 670 #define PIN_PA19D_SERCOM3_PAD3 _L_(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ 671 #define MUX_PA19D_SERCOM3_PAD3 _L_(3) 672 #define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) 673 #define PORT_PA19D_SERCOM3_PAD3 (_UL_(1) << 19) 674 #define PIN_PA21D_SERCOM3_PAD3 _L_(21) /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ 675 #define MUX_PA21D_SERCOM3_PAD3 _L_(3) 676 #define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) 677 #define PORT_PA21D_SERCOM3_PAD3 (_UL_(1) << 21) 678 #define PIN_PA25C_SERCOM3_PAD3 _L_(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ 679 #define MUX_PA25C_SERCOM3_PAD3 _L_(2) 680 #define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) 681 #define PORT_PA25C_SERCOM3_PAD3 (_UL_(1) << 25) 682 /* ========== PORT definition for SERCOM4 peripheral ========== */ 683 #define PIN_PA12D_SERCOM4_PAD0 _L_(12) /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */ 684 #define MUX_PA12D_SERCOM4_PAD0 _L_(3) 685 #define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0) 686 #define PORT_PA12D_SERCOM4_PAD0 (_UL_(1) << 12) 687 #define PIN_PB08D_SERCOM4_PAD0 _L_(40) /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ 688 #define MUX_PB08D_SERCOM4_PAD0 _L_(3) 689 #define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) 690 #define PORT_PB08D_SERCOM4_PAD0 (_UL_(1) << 8) 691 #define PIN_PB12C_SERCOM4_PAD0 _L_(44) /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */ 692 #define MUX_PB12C_SERCOM4_PAD0 _L_(2) 693 #define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0) 694 #define PORT_PB12C_SERCOM4_PAD0 (_UL_(1) << 12) 695 #define PIN_PA13D_SERCOM4_PAD1 _L_(13) /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */ 696 #define MUX_PA13D_SERCOM4_PAD1 _L_(3) 697 #define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1) 698 #define PORT_PA13D_SERCOM4_PAD1 (_UL_(1) << 13) 699 #define PIN_PB09D_SERCOM4_PAD1 _L_(41) /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ 700 #define MUX_PB09D_SERCOM4_PAD1 _L_(3) 701 #define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) 702 #define PORT_PB09D_SERCOM4_PAD1 (_UL_(1) << 9) 703 #define PIN_PB13C_SERCOM4_PAD1 _L_(45) /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */ 704 #define MUX_PB13C_SERCOM4_PAD1 _L_(2) 705 #define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1) 706 #define PORT_PB13C_SERCOM4_PAD1 (_UL_(1) << 13) 707 #define PIN_PA14D_SERCOM4_PAD2 _L_(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ 708 #define MUX_PA14D_SERCOM4_PAD2 _L_(3) 709 #define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) 710 #define PORT_PA14D_SERCOM4_PAD2 (_UL_(1) << 14) 711 #define PIN_PB10D_SERCOM4_PAD2 _L_(42) /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ 712 #define MUX_PB10D_SERCOM4_PAD2 _L_(3) 713 #define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) 714 #define PORT_PB10D_SERCOM4_PAD2 (_UL_(1) << 10) 715 #define PIN_PB14C_SERCOM4_PAD2 _L_(46) /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */ 716 #define MUX_PB14C_SERCOM4_PAD2 _L_(2) 717 #define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) 718 #define PORT_PB14C_SERCOM4_PAD2 (_UL_(1) << 14) 719 #define PIN_PA15D_SERCOM4_PAD3 _L_(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ 720 #define MUX_PA15D_SERCOM4_PAD3 _L_(3) 721 #define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) 722 #define PORT_PA15D_SERCOM4_PAD3 (_UL_(1) << 15) 723 #define PIN_PB11D_SERCOM4_PAD3 _L_(43) /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ 724 #define MUX_PB11D_SERCOM4_PAD3 _L_(3) 725 #define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) 726 #define PORT_PB11D_SERCOM4_PAD3 (_UL_(1) << 11) 727 #define PIN_PB15C_SERCOM4_PAD3 _L_(47) /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */ 728 #define MUX_PB15C_SERCOM4_PAD3 _L_(2) 729 #define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) 730 #define PORT_PB15C_SERCOM4_PAD3 (_UL_(1) << 15) 731 /* ========== PORT definition for TCC0 peripheral ========== */ 732 #define PIN_PA04E_TCC0_WO0 _L_(4) /**< \brief TCC0 signal: WO0 on PA04 mux E */ 733 #define MUX_PA04E_TCC0_WO0 _L_(4) 734 #define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) 735 #define PORT_PA04E_TCC0_WO0 (_UL_(1) << 4) 736 #define PIN_PA08E_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux E */ 737 #define MUX_PA08E_TCC0_WO0 _L_(4) 738 #define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) 739 #define PORT_PA08E_TCC0_WO0 (_UL_(1) << 8) 740 #define PIN_PB30E_TCC0_WO0 _L_(62) /**< \brief TCC0 signal: WO0 on PB30 mux E */ 741 #define MUX_PB30E_TCC0_WO0 _L_(4) 742 #define PINMUX_PB30E_TCC0_WO0 ((PIN_PB30E_TCC0_WO0 << 16) | MUX_PB30E_TCC0_WO0) 743 #define PORT_PB30E_TCC0_WO0 (_UL_(1) << 30) 744 #define PIN_PA05E_TCC0_WO1 _L_(5) /**< \brief TCC0 signal: WO1 on PA05 mux E */ 745 #define MUX_PA05E_TCC0_WO1 _L_(4) 746 #define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) 747 #define PORT_PA05E_TCC0_WO1 (_UL_(1) << 5) 748 #define PIN_PA09E_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux E */ 749 #define MUX_PA09E_TCC0_WO1 _L_(4) 750 #define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) 751 #define PORT_PA09E_TCC0_WO1 (_UL_(1) << 9) 752 #define PIN_PB31E_TCC0_WO1 _L_(63) /**< \brief TCC0 signal: WO1 on PB31 mux E */ 753 #define MUX_PB31E_TCC0_WO1 _L_(4) 754 #define PINMUX_PB31E_TCC0_WO1 ((PIN_PB31E_TCC0_WO1 << 16) | MUX_PB31E_TCC0_WO1) 755 #define PORT_PB31E_TCC0_WO1 (_UL_(1) << 31) 756 #define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */ 757 #define MUX_PA10F_TCC0_WO2 _L_(5) 758 #define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) 759 #define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10) 760 #define PIN_PA18F_TCC0_WO2 _L_(18) /**< \brief TCC0 signal: WO2 on PA18 mux F */ 761 #define MUX_PA18F_TCC0_WO2 _L_(5) 762 #define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) 763 #define PORT_PA18F_TCC0_WO2 (_UL_(1) << 18) 764 #define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */ 765 #define MUX_PA11F_TCC0_WO3 _L_(5) 766 #define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) 767 #define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11) 768 #define PIN_PA19F_TCC0_WO3 _L_(19) /**< \brief TCC0 signal: WO3 on PA19 mux F */ 769 #define MUX_PA19F_TCC0_WO3 _L_(5) 770 #define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) 771 #define PORT_PA19F_TCC0_WO3 (_UL_(1) << 19) 772 #define PIN_PA22F_TCC0_WO4 _L_(22) /**< \brief TCC0 signal: WO4 on PA22 mux F */ 773 #define MUX_PA22F_TCC0_WO4 _L_(5) 774 #define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) 775 #define PORT_PA22F_TCC0_WO4 (_UL_(1) << 22) 776 #define PIN_PB10F_TCC0_WO4 _L_(42) /**< \brief TCC0 signal: WO4 on PB10 mux F */ 777 #define MUX_PB10F_TCC0_WO4 _L_(5) 778 #define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) 779 #define PORT_PB10F_TCC0_WO4 (_UL_(1) << 10) 780 #define PIN_PB16F_TCC0_WO4 _L_(48) /**< \brief TCC0 signal: WO4 on PB16 mux F */ 781 #define MUX_PB16F_TCC0_WO4 _L_(5) 782 #define PINMUX_PB16F_TCC0_WO4 ((PIN_PB16F_TCC0_WO4 << 16) | MUX_PB16F_TCC0_WO4) 783 #define PORT_PB16F_TCC0_WO4 (_UL_(1) << 16) 784 #define PIN_PA14F_TCC0_WO4 _L_(14) /**< \brief TCC0 signal: WO4 on PA14 mux F */ 785 #define MUX_PA14F_TCC0_WO4 _L_(5) 786 #define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) 787 #define PORT_PA14F_TCC0_WO4 (_UL_(1) << 14) 788 #define PIN_PA15F_TCC0_WO5 _L_(15) /**< \brief TCC0 signal: WO5 on PA15 mux F */ 789 #define MUX_PA15F_TCC0_WO5 _L_(5) 790 #define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) 791 #define PORT_PA15F_TCC0_WO5 (_UL_(1) << 15) 792 #define PIN_PA23F_TCC0_WO5 _L_(23) /**< \brief TCC0 signal: WO5 on PA23 mux F */ 793 #define MUX_PA23F_TCC0_WO5 _L_(5) 794 #define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) 795 #define PORT_PA23F_TCC0_WO5 (_UL_(1) << 23) 796 #define PIN_PB11F_TCC0_WO5 _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */ 797 #define MUX_PB11F_TCC0_WO5 _L_(5) 798 #define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) 799 #define PORT_PB11F_TCC0_WO5 (_UL_(1) << 11) 800 #define PIN_PB17F_TCC0_WO5 _L_(49) /**< \brief TCC0 signal: WO5 on PB17 mux F */ 801 #define MUX_PB17F_TCC0_WO5 _L_(5) 802 #define PINMUX_PB17F_TCC0_WO5 ((PIN_PB17F_TCC0_WO5 << 16) | MUX_PB17F_TCC0_WO5) 803 #define PORT_PB17F_TCC0_WO5 (_UL_(1) << 17) 804 #define PIN_PA12F_TCC0_WO6 _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */ 805 #define MUX_PA12F_TCC0_WO6 _L_(5) 806 #define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) 807 #define PORT_PA12F_TCC0_WO6 (_UL_(1) << 12) 808 #define PIN_PA16F_TCC0_WO6 _L_(16) /**< \brief TCC0 signal: WO6 on PA16 mux F */ 809 #define MUX_PA16F_TCC0_WO6 _L_(5) 810 #define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) 811 #define PORT_PA16F_TCC0_WO6 (_UL_(1) << 16) 812 #define PIN_PA20F_TCC0_WO6 _L_(20) /**< \brief TCC0 signal: WO6 on PA20 mux F */ 813 #define MUX_PA20F_TCC0_WO6 _L_(5) 814 #define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6) 815 #define PORT_PA20F_TCC0_WO6 (_UL_(1) << 20) 816 #define PIN_PB12F_TCC0_WO6 _L_(44) /**< \brief TCC0 signal: WO6 on PB12 mux F */ 817 #define MUX_PB12F_TCC0_WO6 _L_(5) 818 #define PINMUX_PB12F_TCC0_WO6 ((PIN_PB12F_TCC0_WO6 << 16) | MUX_PB12F_TCC0_WO6) 819 #define PORT_PB12F_TCC0_WO6 (_UL_(1) << 12) 820 #define PIN_PA13F_TCC0_WO7 _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */ 821 #define MUX_PA13F_TCC0_WO7 _L_(5) 822 #define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) 823 #define PORT_PA13F_TCC0_WO7 (_UL_(1) << 13) 824 #define PIN_PA17F_TCC0_WO7 _L_(17) /**< \brief TCC0 signal: WO7 on PA17 mux F */ 825 #define MUX_PA17F_TCC0_WO7 _L_(5) 826 #define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) 827 #define PORT_PA17F_TCC0_WO7 (_UL_(1) << 17) 828 #define PIN_PA21F_TCC0_WO7 _L_(21) /**< \brief TCC0 signal: WO7 on PA21 mux F */ 829 #define MUX_PA21F_TCC0_WO7 _L_(5) 830 #define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7) 831 #define PORT_PA21F_TCC0_WO7 (_UL_(1) << 21) 832 #define PIN_PB13F_TCC0_WO7 _L_(45) /**< \brief TCC0 signal: WO7 on PB13 mux F */ 833 #define MUX_PB13F_TCC0_WO7 _L_(5) 834 #define PINMUX_PB13F_TCC0_WO7 ((PIN_PB13F_TCC0_WO7 << 16) | MUX_PB13F_TCC0_WO7) 835 #define PORT_PB13F_TCC0_WO7 (_UL_(1) << 13) 836 /* ========== PORT definition for TCC1 peripheral ========== */ 837 #define PIN_PA06E_TCC1_WO0 _L_(6) /**< \brief TCC1 signal: WO0 on PA06 mux E */ 838 #define MUX_PA06E_TCC1_WO0 _L_(4) 839 #define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) 840 #define PORT_PA06E_TCC1_WO0 (_UL_(1) << 6) 841 #define PIN_PA10E_TCC1_WO0 _L_(10) /**< \brief TCC1 signal: WO0 on PA10 mux E */ 842 #define MUX_PA10E_TCC1_WO0 _L_(4) 843 #define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) 844 #define PORT_PA10E_TCC1_WO0 (_UL_(1) << 10) 845 #define PIN_PA30E_TCC1_WO0 _L_(30) /**< \brief TCC1 signal: WO0 on PA30 mux E */ 846 #define MUX_PA30E_TCC1_WO0 _L_(4) 847 #define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) 848 #define PORT_PA30E_TCC1_WO0 (_UL_(1) << 30) 849 #define PIN_PA07E_TCC1_WO1 _L_(7) /**< \brief TCC1 signal: WO1 on PA07 mux E */ 850 #define MUX_PA07E_TCC1_WO1 _L_(4) 851 #define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) 852 #define PORT_PA07E_TCC1_WO1 (_UL_(1) << 7) 853 #define PIN_PA11E_TCC1_WO1 _L_(11) /**< \brief TCC1 signal: WO1 on PA11 mux E */ 854 #define MUX_PA11E_TCC1_WO1 _L_(4) 855 #define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) 856 #define PORT_PA11E_TCC1_WO1 (_UL_(1) << 11) 857 #define PIN_PA31E_TCC1_WO1 _L_(31) /**< \brief TCC1 signal: WO1 on PA31 mux E */ 858 #define MUX_PA31E_TCC1_WO1 _L_(4) 859 #define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) 860 #define PORT_PA31E_TCC1_WO1 (_UL_(1) << 31) 861 #define PIN_PA08F_TCC1_WO2 _L_(8) /**< \brief TCC1 signal: WO2 on PA08 mux F */ 862 #define MUX_PA08F_TCC1_WO2 _L_(5) 863 #define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2) 864 #define PORT_PA08F_TCC1_WO2 (_UL_(1) << 8) 865 #define PIN_PA24F_TCC1_WO2 _L_(24) /**< \brief TCC1 signal: WO2 on PA24 mux F */ 866 #define MUX_PA24F_TCC1_WO2 _L_(5) 867 #define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) 868 #define PORT_PA24F_TCC1_WO2 (_UL_(1) << 24) 869 #define PIN_PB30F_TCC1_WO2 _L_(62) /**< \brief TCC1 signal: WO2 on PB30 mux F */ 870 #define MUX_PB30F_TCC1_WO2 _L_(5) 871 #define PINMUX_PB30F_TCC1_WO2 ((PIN_PB30F_TCC1_WO2 << 16) | MUX_PB30F_TCC1_WO2) 872 #define PORT_PB30F_TCC1_WO2 (_UL_(1) << 30) 873 #define PIN_PA09F_TCC1_WO3 _L_(9) /**< \brief TCC1 signal: WO3 on PA09 mux F */ 874 #define MUX_PA09F_TCC1_WO3 _L_(5) 875 #define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3) 876 #define PORT_PA09F_TCC1_WO3 (_UL_(1) << 9) 877 #define PIN_PA25F_TCC1_WO3 _L_(25) /**< \brief TCC1 signal: WO3 on PA25 mux F */ 878 #define MUX_PA25F_TCC1_WO3 _L_(5) 879 #define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) 880 #define PORT_PA25F_TCC1_WO3 (_UL_(1) << 25) 881 #define PIN_PB31F_TCC1_WO3 _L_(63) /**< \brief TCC1 signal: WO3 on PB31 mux F */ 882 #define MUX_PB31F_TCC1_WO3 _L_(5) 883 #define PINMUX_PB31F_TCC1_WO3 ((PIN_PB31F_TCC1_WO3 << 16) | MUX_PB31F_TCC1_WO3) 884 #define PORT_PB31F_TCC1_WO3 (_UL_(1) << 31) 885 /* ========== PORT definition for TCC2 peripheral ========== */ 886 #define PIN_PA12E_TCC2_WO0 _L_(12) /**< \brief TCC2 signal: WO0 on PA12 mux E */ 887 #define MUX_PA12E_TCC2_WO0 _L_(4) 888 #define PINMUX_PA12E_TCC2_WO0 ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0) 889 #define PORT_PA12E_TCC2_WO0 (_UL_(1) << 12) 890 #define PIN_PA16E_TCC2_WO0 _L_(16) /**< \brief TCC2 signal: WO0 on PA16 mux E */ 891 #define MUX_PA16E_TCC2_WO0 _L_(4) 892 #define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) 893 #define PORT_PA16E_TCC2_WO0 (_UL_(1) << 16) 894 #define PIN_PA00E_TCC2_WO0 _L_(0) /**< \brief TCC2 signal: WO0 on PA00 mux E */ 895 #define MUX_PA00E_TCC2_WO0 _L_(4) 896 #define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0) 897 #define PORT_PA00E_TCC2_WO0 (_UL_(1) << 0) 898 #define PIN_PA13E_TCC2_WO1 _L_(13) /**< \brief TCC2 signal: WO1 on PA13 mux E */ 899 #define MUX_PA13E_TCC2_WO1 _L_(4) 900 #define PINMUX_PA13E_TCC2_WO1 ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1) 901 #define PORT_PA13E_TCC2_WO1 (_UL_(1) << 13) 902 #define PIN_PA17E_TCC2_WO1 _L_(17) /**< \brief TCC2 signal: WO1 on PA17 mux E */ 903 #define MUX_PA17E_TCC2_WO1 _L_(4) 904 #define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) 905 #define PORT_PA17E_TCC2_WO1 (_UL_(1) << 17) 906 #define PIN_PA01E_TCC2_WO1 _L_(1) /**< \brief TCC2 signal: WO1 on PA01 mux E */ 907 #define MUX_PA01E_TCC2_WO1 _L_(4) 908 #define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1) 909 #define PORT_PA01E_TCC2_WO1 (_UL_(1) << 1) 910 /* ========== PORT definition for TC0 peripheral ========== */ 911 #define PIN_PA22E_TC0_WO0 _L_(22) /**< \brief TC0 signal: WO0 on PA22 mux E */ 912 #define MUX_PA22E_TC0_WO0 _L_(4) 913 #define PINMUX_PA22E_TC0_WO0 ((PIN_PA22E_TC0_WO0 << 16) | MUX_PA22E_TC0_WO0) 914 #define PORT_PA22E_TC0_WO0 (_UL_(1) << 22) 915 #define PIN_PB08E_TC0_WO0 _L_(40) /**< \brief TC0 signal: WO0 on PB08 mux E */ 916 #define MUX_PB08E_TC0_WO0 _L_(4) 917 #define PINMUX_PB08E_TC0_WO0 ((PIN_PB08E_TC0_WO0 << 16) | MUX_PB08E_TC0_WO0) 918 #define PORT_PB08E_TC0_WO0 (_UL_(1) << 8) 919 #define PIN_PB12E_TC0_WO0 _L_(44) /**< \brief TC0 signal: WO0 on PB12 mux E */ 920 #define MUX_PB12E_TC0_WO0 _L_(4) 921 #define PINMUX_PB12E_TC0_WO0 ((PIN_PB12E_TC0_WO0 << 16) | MUX_PB12E_TC0_WO0) 922 #define PORT_PB12E_TC0_WO0 (_UL_(1) << 12) 923 #define PIN_PA23E_TC0_WO1 _L_(23) /**< \brief TC0 signal: WO1 on PA23 mux E */ 924 #define MUX_PA23E_TC0_WO1 _L_(4) 925 #define PINMUX_PA23E_TC0_WO1 ((PIN_PA23E_TC0_WO1 << 16) | MUX_PA23E_TC0_WO1) 926 #define PORT_PA23E_TC0_WO1 (_UL_(1) << 23) 927 #define PIN_PB09E_TC0_WO1 _L_(41) /**< \brief TC0 signal: WO1 on PB09 mux E */ 928 #define MUX_PB09E_TC0_WO1 _L_(4) 929 #define PINMUX_PB09E_TC0_WO1 ((PIN_PB09E_TC0_WO1 << 16) | MUX_PB09E_TC0_WO1) 930 #define PORT_PB09E_TC0_WO1 (_UL_(1) << 9) 931 #define PIN_PB13E_TC0_WO1 _L_(45) /**< \brief TC0 signal: WO1 on PB13 mux E */ 932 #define MUX_PB13E_TC0_WO1 _L_(4) 933 #define PINMUX_PB13E_TC0_WO1 ((PIN_PB13E_TC0_WO1 << 16) | MUX_PB13E_TC0_WO1) 934 #define PORT_PB13E_TC0_WO1 (_UL_(1) << 13) 935 /* ========== PORT definition for TC1 peripheral ========== */ 936 #define PIN_PA24E_TC1_WO0 _L_(24) /**< \brief TC1 signal: WO0 on PA24 mux E */ 937 #define MUX_PA24E_TC1_WO0 _L_(4) 938 #define PINMUX_PA24E_TC1_WO0 ((PIN_PA24E_TC1_WO0 << 16) | MUX_PA24E_TC1_WO0) 939 #define PORT_PA24E_TC1_WO0 (_UL_(1) << 24) 940 #define PIN_PB10E_TC1_WO0 _L_(42) /**< \brief TC1 signal: WO0 on PB10 mux E */ 941 #define MUX_PB10E_TC1_WO0 _L_(4) 942 #define PINMUX_PB10E_TC1_WO0 ((PIN_PB10E_TC1_WO0 << 16) | MUX_PB10E_TC1_WO0) 943 #define PORT_PB10E_TC1_WO0 (_UL_(1) << 10) 944 #define PIN_PB14E_TC1_WO0 _L_(46) /**< \brief TC1 signal: WO0 on PB14 mux E */ 945 #define MUX_PB14E_TC1_WO0 _L_(4) 946 #define PINMUX_PB14E_TC1_WO0 ((PIN_PB14E_TC1_WO0 << 16) | MUX_PB14E_TC1_WO0) 947 #define PORT_PB14E_TC1_WO0 (_UL_(1) << 14) 948 #define PIN_PA25E_TC1_WO1 _L_(25) /**< \brief TC1 signal: WO1 on PA25 mux E */ 949 #define MUX_PA25E_TC1_WO1 _L_(4) 950 #define PINMUX_PA25E_TC1_WO1 ((PIN_PA25E_TC1_WO1 << 16) | MUX_PA25E_TC1_WO1) 951 #define PORT_PA25E_TC1_WO1 (_UL_(1) << 25) 952 #define PIN_PB11E_TC1_WO1 _L_(43) /**< \brief TC1 signal: WO1 on PB11 mux E */ 953 #define MUX_PB11E_TC1_WO1 _L_(4) 954 #define PINMUX_PB11E_TC1_WO1 ((PIN_PB11E_TC1_WO1 << 16) | MUX_PB11E_TC1_WO1) 955 #define PORT_PB11E_TC1_WO1 (_UL_(1) << 11) 956 #define PIN_PB15E_TC1_WO1 _L_(47) /**< \brief TC1 signal: WO1 on PB15 mux E */ 957 #define MUX_PB15E_TC1_WO1 _L_(4) 958 #define PINMUX_PB15E_TC1_WO1 ((PIN_PB15E_TC1_WO1 << 16) | MUX_PB15E_TC1_WO1) 959 #define PORT_PB15E_TC1_WO1 (_UL_(1) << 15) 960 /* ========== PORT definition for TC2 peripheral ========== */ 961 #define PIN_PB02E_TC2_WO0 _L_(34) /**< \brief TC2 signal: WO0 on PB02 mux E */ 962 #define MUX_PB02E_TC2_WO0 _L_(4) 963 #define PINMUX_PB02E_TC2_WO0 ((PIN_PB02E_TC2_WO0 << 16) | MUX_PB02E_TC2_WO0) 964 #define PORT_PB02E_TC2_WO0 (_UL_(1) << 2) 965 #define PIN_PB16E_TC2_WO0 _L_(48) /**< \brief TC2 signal: WO0 on PB16 mux E */ 966 #define MUX_PB16E_TC2_WO0 _L_(4) 967 #define PINMUX_PB16E_TC2_WO0 ((PIN_PB16E_TC2_WO0 << 16) | MUX_PB16E_TC2_WO0) 968 #define PORT_PB16E_TC2_WO0 (_UL_(1) << 16) 969 #define PIN_PB03E_TC2_WO1 _L_(35) /**< \brief TC2 signal: WO1 on PB03 mux E */ 970 #define MUX_PB03E_TC2_WO1 _L_(4) 971 #define PINMUX_PB03E_TC2_WO1 ((PIN_PB03E_TC2_WO1 << 16) | MUX_PB03E_TC2_WO1) 972 #define PORT_PB03E_TC2_WO1 (_UL_(1) << 3) 973 #define PIN_PB17E_TC2_WO1 _L_(49) /**< \brief TC2 signal: WO1 on PB17 mux E */ 974 #define MUX_PB17E_TC2_WO1 _L_(4) 975 #define PINMUX_PB17E_TC2_WO1 ((PIN_PB17E_TC2_WO1 << 16) | MUX_PB17E_TC2_WO1) 976 #define PORT_PB17E_TC2_WO1 (_UL_(1) << 17) 977 /* ========== PORT definition for TC3 peripheral ========== */ 978 #define PIN_PA20E_TC3_WO0 _L_(20) /**< \brief TC3 signal: WO0 on PA20 mux E */ 979 #define MUX_PA20E_TC3_WO0 _L_(4) 980 #define PINMUX_PA20E_TC3_WO0 ((PIN_PA20E_TC3_WO0 << 16) | MUX_PA20E_TC3_WO0) 981 #define PORT_PA20E_TC3_WO0 (_UL_(1) << 20) 982 #define PIN_PB00E_TC3_WO0 _L_(32) /**< \brief TC3 signal: WO0 on PB00 mux E */ 983 #define MUX_PB00E_TC3_WO0 _L_(4) 984 #define PINMUX_PB00E_TC3_WO0 ((PIN_PB00E_TC3_WO0 << 16) | MUX_PB00E_TC3_WO0) 985 #define PORT_PB00E_TC3_WO0 (_UL_(1) << 0) 986 #define PIN_PB22E_TC3_WO0 _L_(54) /**< \brief TC3 signal: WO0 on PB22 mux E */ 987 #define MUX_PB22E_TC3_WO0 _L_(4) 988 #define PINMUX_PB22E_TC3_WO0 ((PIN_PB22E_TC3_WO0 << 16) | MUX_PB22E_TC3_WO0) 989 #define PORT_PB22E_TC3_WO0 (_UL_(1) << 22) 990 #define PIN_PA21E_TC3_WO1 _L_(21) /**< \brief TC3 signal: WO1 on PA21 mux E */ 991 #define MUX_PA21E_TC3_WO1 _L_(4) 992 #define PINMUX_PA21E_TC3_WO1 ((PIN_PA21E_TC3_WO1 << 16) | MUX_PA21E_TC3_WO1) 993 #define PORT_PA21E_TC3_WO1 (_UL_(1) << 21) 994 #define PIN_PB01E_TC3_WO1 _L_(33) /**< \brief TC3 signal: WO1 on PB01 mux E */ 995 #define MUX_PB01E_TC3_WO1 _L_(4) 996 #define PINMUX_PB01E_TC3_WO1 ((PIN_PB01E_TC3_WO1 << 16) | MUX_PB01E_TC3_WO1) 997 #define PORT_PB01E_TC3_WO1 (_UL_(1) << 1) 998 #define PIN_PB23E_TC3_WO1 _L_(55) /**< \brief TC3 signal: WO1 on PB23 mux E */ 999 #define MUX_PB23E_TC3_WO1 _L_(4) 1000 #define PINMUX_PB23E_TC3_WO1 ((PIN_PB23E_TC3_WO1 << 16) | MUX_PB23E_TC3_WO1) 1001 #define PORT_PB23E_TC3_WO1 (_UL_(1) << 23) 1002 /* ========== PORT definition for DAC peripheral ========== */ 1003 #define PIN_PA02B_DAC_VOUT0 _L_(2) /**< \brief DAC signal: VOUT0 on PA02 mux B */ 1004 #define MUX_PA02B_DAC_VOUT0 _L_(1) 1005 #define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0) 1006 #define PORT_PA02B_DAC_VOUT0 (_UL_(1) << 2) 1007 #define PIN_PA05B_DAC_VOUT1 _L_(5) /**< \brief DAC signal: VOUT1 on PA05 mux B */ 1008 #define MUX_PA05B_DAC_VOUT1 _L_(1) 1009 #define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) 1010 #define PORT_PA05B_DAC_VOUT1 (_UL_(1) << 5) 1011 #define PIN_PA03B_DAC_VREFP _L_(3) /**< \brief DAC signal: VREFP on PA03 mux B */ 1012 #define MUX_PA03B_DAC_VREFP _L_(1) 1013 #define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP) 1014 #define PORT_PA03B_DAC_VREFP (_UL_(1) << 3) 1015 /* ========== PORT definition for SERCOM5 peripheral ========== */ 1016 #define PIN_PA22D_SERCOM5_PAD0 _L_(22) /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */ 1017 #define MUX_PA22D_SERCOM5_PAD0 _L_(3) 1018 #define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0) 1019 #define PORT_PA22D_SERCOM5_PAD0 (_UL_(1) << 22) 1020 #define PIN_PB02D_SERCOM5_PAD0 _L_(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ 1021 #define MUX_PB02D_SERCOM5_PAD0 _L_(3) 1022 #define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) 1023 #define PORT_PB02D_SERCOM5_PAD0 (_UL_(1) << 2) 1024 #define PIN_PB30D_SERCOM5_PAD0 _L_(62) /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */ 1025 #define MUX_PB30D_SERCOM5_PAD0 _L_(3) 1026 #define PINMUX_PB30D_SERCOM5_PAD0 ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0) 1027 #define PORT_PB30D_SERCOM5_PAD0 (_UL_(1) << 30) 1028 #define PIN_PB16C_SERCOM5_PAD0 _L_(48) /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ 1029 #define MUX_PB16C_SERCOM5_PAD0 _L_(2) 1030 #define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) 1031 #define PORT_PB16C_SERCOM5_PAD0 (_UL_(1) << 16) 1032 #define PIN_PA23D_SERCOM5_PAD1 _L_(23) /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */ 1033 #define MUX_PA23D_SERCOM5_PAD1 _L_(3) 1034 #define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1) 1035 #define PORT_PA23D_SERCOM5_PAD1 (_UL_(1) << 23) 1036 #define PIN_PB03D_SERCOM5_PAD1 _L_(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ 1037 #define MUX_PB03D_SERCOM5_PAD1 _L_(3) 1038 #define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) 1039 #define PORT_PB03D_SERCOM5_PAD1 (_UL_(1) << 3) 1040 #define PIN_PB31D_SERCOM5_PAD1 _L_(63) /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */ 1041 #define MUX_PB31D_SERCOM5_PAD1 _L_(3) 1042 #define PINMUX_PB31D_SERCOM5_PAD1 ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1) 1043 #define PORT_PB31D_SERCOM5_PAD1 (_UL_(1) << 31) 1044 #define PIN_PB17C_SERCOM5_PAD1 _L_(49) /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ 1045 #define MUX_PB17C_SERCOM5_PAD1 _L_(2) 1046 #define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) 1047 #define PORT_PB17C_SERCOM5_PAD1 (_UL_(1) << 17) 1048 #define PIN_PA24D_SERCOM5_PAD2 _L_(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ 1049 #define MUX_PA24D_SERCOM5_PAD2 _L_(3) 1050 #define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) 1051 #define PORT_PA24D_SERCOM5_PAD2 (_UL_(1) << 24) 1052 #define PIN_PB00D_SERCOM5_PAD2 _L_(32) /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ 1053 #define MUX_PB00D_SERCOM5_PAD2 _L_(3) 1054 #define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) 1055 #define PORT_PB00D_SERCOM5_PAD2 (_UL_(1) << 0) 1056 #define PIN_PB22D_SERCOM5_PAD2 _L_(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ 1057 #define MUX_PB22D_SERCOM5_PAD2 _L_(3) 1058 #define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) 1059 #define PORT_PB22D_SERCOM5_PAD2 (_UL_(1) << 22) 1060 #define PIN_PA20C_SERCOM5_PAD2 _L_(20) /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ 1061 #define MUX_PA20C_SERCOM5_PAD2 _L_(2) 1062 #define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) 1063 #define PORT_PA20C_SERCOM5_PAD2 (_UL_(1) << 20) 1064 #define PIN_PA25D_SERCOM5_PAD3 _L_(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ 1065 #define MUX_PA25D_SERCOM5_PAD3 _L_(3) 1066 #define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) 1067 #define PORT_PA25D_SERCOM5_PAD3 (_UL_(1) << 25) 1068 #define PIN_PB01D_SERCOM5_PAD3 _L_(33) /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */ 1069 #define MUX_PB01D_SERCOM5_PAD3 _L_(3) 1070 #define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) 1071 #define PORT_PB01D_SERCOM5_PAD3 (_UL_(1) << 1) 1072 #define PIN_PB23D_SERCOM5_PAD3 _L_(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ 1073 #define MUX_PB23D_SERCOM5_PAD3 _L_(3) 1074 #define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) 1075 #define PORT_PB23D_SERCOM5_PAD3 (_UL_(1) << 23) 1076 #define PIN_PA21C_SERCOM5_PAD3 _L_(21) /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ 1077 #define MUX_PA21C_SERCOM5_PAD3 _L_(2) 1078 #define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) 1079 #define PORT_PA21C_SERCOM5_PAD3 (_UL_(1) << 21) 1080 /* ========== PORT definition for TC4 peripheral ========== */ 1081 #define PIN_PA18E_TC4_WO0 _L_(18) /**< \brief TC4 signal: WO0 on PA18 mux E */ 1082 #define MUX_PA18E_TC4_WO0 _L_(4) 1083 #define PINMUX_PA18E_TC4_WO0 ((PIN_PA18E_TC4_WO0 << 16) | MUX_PA18E_TC4_WO0) 1084 #define PORT_PA18E_TC4_WO0 (_UL_(1) << 18) 1085 #define PIN_PA14E_TC4_WO0 _L_(14) /**< \brief TC4 signal: WO0 on PA14 mux E */ 1086 #define MUX_PA14E_TC4_WO0 _L_(4) 1087 #define PINMUX_PA14E_TC4_WO0 ((PIN_PA14E_TC4_WO0 << 16) | MUX_PA14E_TC4_WO0) 1088 #define PORT_PA14E_TC4_WO0 (_UL_(1) << 14) 1089 #define PIN_PA19E_TC4_WO1 _L_(19) /**< \brief TC4 signal: WO1 on PA19 mux E */ 1090 #define MUX_PA19E_TC4_WO1 _L_(4) 1091 #define PINMUX_PA19E_TC4_WO1 ((PIN_PA19E_TC4_WO1 << 16) | MUX_PA19E_TC4_WO1) 1092 #define PORT_PA19E_TC4_WO1 (_UL_(1) << 19) 1093 #define PIN_PA15E_TC4_WO1 _L_(15) /**< \brief TC4 signal: WO1 on PA15 mux E */ 1094 #define MUX_PA15E_TC4_WO1 _L_(4) 1095 #define PINMUX_PA15E_TC4_WO1 ((PIN_PA15E_TC4_WO1 << 16) | MUX_PA15E_TC4_WO1) 1096 #define PORT_PA15E_TC4_WO1 (_UL_(1) << 15) 1097 /* ========== PORT definition for ADC peripheral ========== */ 1098 #define PIN_PA02B_ADC_AIN0 _L_(2) /**< \brief ADC signal: AIN0 on PA02 mux B */ 1099 #define MUX_PA02B_ADC_AIN0 _L_(1) 1100 #define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) 1101 #define PORT_PA02B_ADC_AIN0 (_UL_(1) << 2) 1102 #define PIN_PA03B_ADC_AIN1 _L_(3) /**< \brief ADC signal: AIN1 on PA03 mux B */ 1103 #define MUX_PA03B_ADC_AIN1 _L_(1) 1104 #define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) 1105 #define PORT_PA03B_ADC_AIN1 (_UL_(1) << 3) 1106 #define PIN_PB08B_ADC_AIN2 _L_(40) /**< \brief ADC signal: AIN2 on PB08 mux B */ 1107 #define MUX_PB08B_ADC_AIN2 _L_(1) 1108 #define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2) 1109 #define PORT_PB08B_ADC_AIN2 (_UL_(1) << 8) 1110 #define PIN_PB09B_ADC_AIN3 _L_(41) /**< \brief ADC signal: AIN3 on PB09 mux B */ 1111 #define MUX_PB09B_ADC_AIN3 _L_(1) 1112 #define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3) 1113 #define PORT_PB09B_ADC_AIN3 (_UL_(1) << 9) 1114 #define PIN_PA04B_ADC_AIN4 _L_(4) /**< \brief ADC signal: AIN4 on PA04 mux B */ 1115 #define MUX_PA04B_ADC_AIN4 _L_(1) 1116 #define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) 1117 #define PORT_PA04B_ADC_AIN4 (_UL_(1) << 4) 1118 #define PIN_PA05B_ADC_AIN5 _L_(5) /**< \brief ADC signal: AIN5 on PA05 mux B */ 1119 #define MUX_PA05B_ADC_AIN5 _L_(1) 1120 #define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) 1121 #define PORT_PA05B_ADC_AIN5 (_UL_(1) << 5) 1122 #define PIN_PA06B_ADC_AIN6 _L_(6) /**< \brief ADC signal: AIN6 on PA06 mux B */ 1123 #define MUX_PA06B_ADC_AIN6 _L_(1) 1124 #define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) 1125 #define PORT_PA06B_ADC_AIN6 (_UL_(1) << 6) 1126 #define PIN_PA07B_ADC_AIN7 _L_(7) /**< \brief ADC signal: AIN7 on PA07 mux B */ 1127 #define MUX_PA07B_ADC_AIN7 _L_(1) 1128 #define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) 1129 #define PORT_PA07B_ADC_AIN7 (_UL_(1) << 7) 1130 #define PIN_PB00B_ADC_AIN8 _L_(32) /**< \brief ADC signal: AIN8 on PB00 mux B */ 1131 #define MUX_PB00B_ADC_AIN8 _L_(1) 1132 #define PINMUX_PB00B_ADC_AIN8 ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8) 1133 #define PORT_PB00B_ADC_AIN8 (_UL_(1) << 0) 1134 #define PIN_PB01B_ADC_AIN9 _L_(33) /**< \brief ADC signal: AIN9 on PB01 mux B */ 1135 #define MUX_PB01B_ADC_AIN9 _L_(1) 1136 #define PINMUX_PB01B_ADC_AIN9 ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9) 1137 #define PORT_PB01B_ADC_AIN9 (_UL_(1) << 1) 1138 #define PIN_PB02B_ADC_AIN10 _L_(34) /**< \brief ADC signal: AIN10 on PB02 mux B */ 1139 #define MUX_PB02B_ADC_AIN10 _L_(1) 1140 #define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10) 1141 #define PORT_PB02B_ADC_AIN10 (_UL_(1) << 2) 1142 #define PIN_PB03B_ADC_AIN11 _L_(35) /**< \brief ADC signal: AIN11 on PB03 mux B */ 1143 #define MUX_PB03B_ADC_AIN11 _L_(1) 1144 #define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11) 1145 #define PORT_PB03B_ADC_AIN11 (_UL_(1) << 3) 1146 #define PIN_PB04B_ADC_AIN12 _L_(36) /**< \brief ADC signal: AIN12 on PB04 mux B */ 1147 #define MUX_PB04B_ADC_AIN12 _L_(1) 1148 #define PINMUX_PB04B_ADC_AIN12 ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12) 1149 #define PORT_PB04B_ADC_AIN12 (_UL_(1) << 4) 1150 #define PIN_PB05B_ADC_AIN13 _L_(37) /**< \brief ADC signal: AIN13 on PB05 mux B */ 1151 #define MUX_PB05B_ADC_AIN13 _L_(1) 1152 #define PINMUX_PB05B_ADC_AIN13 ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13) 1153 #define PORT_PB05B_ADC_AIN13 (_UL_(1) << 5) 1154 #define PIN_PB06B_ADC_AIN14 _L_(38) /**< \brief ADC signal: AIN14 on PB06 mux B */ 1155 #define MUX_PB06B_ADC_AIN14 _L_(1) 1156 #define PINMUX_PB06B_ADC_AIN14 ((PIN_PB06B_ADC_AIN14 << 16) | MUX_PB06B_ADC_AIN14) 1157 #define PORT_PB06B_ADC_AIN14 (_UL_(1) << 6) 1158 #define PIN_PB07B_ADC_AIN15 _L_(39) /**< \brief ADC signal: AIN15 on PB07 mux B */ 1159 #define MUX_PB07B_ADC_AIN15 _L_(1) 1160 #define PINMUX_PB07B_ADC_AIN15 ((PIN_PB07B_ADC_AIN15 << 16) | MUX_PB07B_ADC_AIN15) 1161 #define PORT_PB07B_ADC_AIN15 (_UL_(1) << 7) 1162 #define PIN_PA08B_ADC_AIN16 _L_(8) /**< \brief ADC signal: AIN16 on PA08 mux B */ 1163 #define MUX_PA08B_ADC_AIN16 _L_(1) 1164 #define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) 1165 #define PORT_PA08B_ADC_AIN16 (_UL_(1) << 8) 1166 #define PIN_PA09B_ADC_AIN17 _L_(9) /**< \brief ADC signal: AIN17 on PA09 mux B */ 1167 #define MUX_PA09B_ADC_AIN17 _L_(1) 1168 #define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) 1169 #define PORT_PA09B_ADC_AIN17 (_UL_(1) << 9) 1170 #define PIN_PA10B_ADC_AIN18 _L_(10) /**< \brief ADC signal: AIN18 on PA10 mux B */ 1171 #define MUX_PA10B_ADC_AIN18 _L_(1) 1172 #define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) 1173 #define PORT_PA10B_ADC_AIN18 (_UL_(1) << 10) 1174 #define PIN_PA11B_ADC_AIN19 _L_(11) /**< \brief ADC signal: AIN19 on PA11 mux B */ 1175 #define MUX_PA11B_ADC_AIN19 _L_(1) 1176 #define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) 1177 #define PORT_PA11B_ADC_AIN19 (_UL_(1) << 11) 1178 #define PIN_PA04B_ADC_VREFP _L_(4) /**< \brief ADC signal: VREFP on PA04 mux B */ 1179 #define MUX_PA04B_ADC_VREFP _L_(1) 1180 #define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP) 1181 #define PORT_PA04B_ADC_VREFP (_UL_(1) << 4) 1182 /* ========== PORT definition for AC peripheral ========== */ 1183 #define PIN_PA04B_AC_AIN0 _L_(4) /**< \brief AC signal: AIN0 on PA04 mux B */ 1184 #define MUX_PA04B_AC_AIN0 _L_(1) 1185 #define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) 1186 #define PORT_PA04B_AC_AIN0 (_UL_(1) << 4) 1187 #define PIN_PA05B_AC_AIN1 _L_(5) /**< \brief AC signal: AIN1 on PA05 mux B */ 1188 #define MUX_PA05B_AC_AIN1 _L_(1) 1189 #define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) 1190 #define PORT_PA05B_AC_AIN1 (_UL_(1) << 5) 1191 #define PIN_PA06B_AC_AIN2 _L_(6) /**< \brief AC signal: AIN2 on PA06 mux B */ 1192 #define MUX_PA06B_AC_AIN2 _L_(1) 1193 #define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) 1194 #define PORT_PA06B_AC_AIN2 (_UL_(1) << 6) 1195 #define PIN_PA07B_AC_AIN3 _L_(7) /**< \brief AC signal: AIN3 on PA07 mux B */ 1196 #define MUX_PA07B_AC_AIN3 _L_(1) 1197 #define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) 1198 #define PORT_PA07B_AC_AIN3 (_UL_(1) << 7) 1199 #define PIN_PA12H_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux H */ 1200 #define MUX_PA12H_AC_CMP0 _L_(7) 1201 #define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0) 1202 #define PORT_PA12H_AC_CMP0 (_UL_(1) << 12) 1203 #define PIN_PA18H_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux H */ 1204 #define MUX_PA18H_AC_CMP0 _L_(7) 1205 #define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) 1206 #define PORT_PA18H_AC_CMP0 (_UL_(1) << 18) 1207 #define PIN_PA13H_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux H */ 1208 #define MUX_PA13H_AC_CMP1 _L_(7) 1209 #define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1) 1210 #define PORT_PA13H_AC_CMP1 (_UL_(1) << 13) 1211 #define PIN_PA19H_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux H */ 1212 #define MUX_PA19H_AC_CMP1 _L_(7) 1213 #define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) 1214 #define PORT_PA19H_AC_CMP1 (_UL_(1) << 19) 1215 /* ========== PORT definition for OPAMP peripheral ========== */ 1216 #define PIN_PA02B_OPAMP_OANEG0 _L_(2) /**< \brief OPAMP signal: OANEG0 on PA02 mux B */ 1217 #define MUX_PA02B_OPAMP_OANEG0 _L_(1) 1218 #define PINMUX_PA02B_OPAMP_OANEG0 ((PIN_PA02B_OPAMP_OANEG0 << 16) | MUX_PA02B_OPAMP_OANEG0) 1219 #define PORT_PA02B_OPAMP_OANEG0 (_UL_(1) << 2) 1220 #define PIN_PB05B_OPAMP_OANEG1 _L_(37) /**< \brief OPAMP signal: OANEG1 on PB05 mux B */ 1221 #define MUX_PB05B_OPAMP_OANEG1 _L_(1) 1222 #define PINMUX_PB05B_OPAMP_OANEG1 ((PIN_PB05B_OPAMP_OANEG1 << 16) | MUX_PB05B_OPAMP_OANEG1) 1223 #define PORT_PB05B_OPAMP_OANEG1 (_UL_(1) << 5) 1224 #define PIN_PB06B_OPAMP_OANEG2 _L_(38) /**< \brief OPAMP signal: OANEG2 on PB06 mux B */ 1225 #define MUX_PB06B_OPAMP_OANEG2 _L_(1) 1226 #define PINMUX_PB06B_OPAMP_OANEG2 ((PIN_PB06B_OPAMP_OANEG2 << 16) | MUX_PB06B_OPAMP_OANEG2) 1227 #define PORT_PB06B_OPAMP_OANEG2 (_UL_(1) << 6) 1228 #define PIN_PA07B_OPAMP_OAOUT0 _L_(7) /**< \brief OPAMP signal: OAOUT0 on PA07 mux B */ 1229 #define MUX_PA07B_OPAMP_OAOUT0 _L_(1) 1230 #define PINMUX_PA07B_OPAMP_OAOUT0 ((PIN_PA07B_OPAMP_OAOUT0 << 16) | MUX_PA07B_OPAMP_OAOUT0) 1231 #define PORT_PA07B_OPAMP_OAOUT0 (_UL_(1) << 7) 1232 #define PIN_PB08B_OPAMP_OAOUT1 _L_(40) /**< \brief OPAMP signal: OAOUT1 on PB08 mux B */ 1233 #define MUX_PB08B_OPAMP_OAOUT1 _L_(1) 1234 #define PINMUX_PB08B_OPAMP_OAOUT1 ((PIN_PB08B_OPAMP_OAOUT1 << 16) | MUX_PB08B_OPAMP_OAOUT1) 1235 #define PORT_PB08B_OPAMP_OAOUT1 (_UL_(1) << 8) 1236 #define PIN_PA04B_OPAMP_OAOUT2 _L_(4) /**< \brief OPAMP signal: OAOUT2 on PA04 mux B */ 1237 #define MUX_PA04B_OPAMP_OAOUT2 _L_(1) 1238 #define PINMUX_PA04B_OPAMP_OAOUT2 ((PIN_PA04B_OPAMP_OAOUT2 << 16) | MUX_PA04B_OPAMP_OAOUT2) 1239 #define PORT_PA04B_OPAMP_OAOUT2 (_UL_(1) << 4) 1240 #define PIN_PA06B_OPAMP_OAPOS0 _L_(6) /**< \brief OPAMP signal: OAPOS0 on PA06 mux B */ 1241 #define MUX_PA06B_OPAMP_OAPOS0 _L_(1) 1242 #define PINMUX_PA06B_OPAMP_OAPOS0 ((PIN_PA06B_OPAMP_OAPOS0 << 16) | MUX_PA06B_OPAMP_OAPOS0) 1243 #define PORT_PA06B_OPAMP_OAPOS0 (_UL_(1) << 6) 1244 #define PIN_PB09B_OPAMP_OAPOS1 _L_(41) /**< \brief OPAMP signal: OAPOS1 on PB09 mux B */ 1245 #define MUX_PB09B_OPAMP_OAPOS1 _L_(1) 1246 #define PINMUX_PB09B_OPAMP_OAPOS1 ((PIN_PB09B_OPAMP_OAPOS1 << 16) | MUX_PB09B_OPAMP_OAPOS1) 1247 #define PORT_PB09B_OPAMP_OAPOS1 (_UL_(1) << 9) 1248 #define PIN_PA05B_OPAMP_OAPOS2 _L_(5) /**< \brief OPAMP signal: OAPOS2 on PA05 mux B */ 1249 #define MUX_PA05B_OPAMP_OAPOS2 _L_(1) 1250 #define PINMUX_PA05B_OPAMP_OAPOS2 ((PIN_PA05B_OPAMP_OAPOS2 << 16) | MUX_PA05B_OPAMP_OAPOS2) 1251 #define PORT_PA05B_OPAMP_OAPOS2 (_UL_(1) << 5) 1252 /* ========== PORT definition for CCL peripheral ========== */ 1253 #define PIN_PA04I_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux I */ 1254 #define MUX_PA04I_CCL_IN0 _L_(8) 1255 #define PINMUX_PA04I_CCL_IN0 ((PIN_PA04I_CCL_IN0 << 16) | MUX_PA04I_CCL_IN0) 1256 #define PORT_PA04I_CCL_IN0 (_UL_(1) << 4) 1257 #define PIN_PA16I_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux I */ 1258 #define MUX_PA16I_CCL_IN0 _L_(8) 1259 #define PINMUX_PA16I_CCL_IN0 ((PIN_PA16I_CCL_IN0 << 16) | MUX_PA16I_CCL_IN0) 1260 #define PORT_PA16I_CCL_IN0 (_UL_(1) << 16) 1261 #define PIN_PB22I_CCL_IN0 _L_(54) /**< \brief CCL signal: IN0 on PB22 mux I */ 1262 #define MUX_PB22I_CCL_IN0 _L_(8) 1263 #define PINMUX_PB22I_CCL_IN0 ((PIN_PB22I_CCL_IN0 << 16) | MUX_PB22I_CCL_IN0) 1264 #define PORT_PB22I_CCL_IN0 (_UL_(1) << 22) 1265 #define PIN_PA05I_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux I */ 1266 #define MUX_PA05I_CCL_IN1 _L_(8) 1267 #define PINMUX_PA05I_CCL_IN1 ((PIN_PA05I_CCL_IN1 << 16) | MUX_PA05I_CCL_IN1) 1268 #define PORT_PA05I_CCL_IN1 (_UL_(1) << 5) 1269 #define PIN_PA17I_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux I */ 1270 #define MUX_PA17I_CCL_IN1 _L_(8) 1271 #define PINMUX_PA17I_CCL_IN1 ((PIN_PA17I_CCL_IN1 << 16) | MUX_PA17I_CCL_IN1) 1272 #define PORT_PA17I_CCL_IN1 (_UL_(1) << 17) 1273 #define PIN_PB00I_CCL_IN1 _L_(32) /**< \brief CCL signal: IN1 on PB00 mux I */ 1274 #define MUX_PB00I_CCL_IN1 _L_(8) 1275 #define PINMUX_PB00I_CCL_IN1 ((PIN_PB00I_CCL_IN1 << 16) | MUX_PB00I_CCL_IN1) 1276 #define PORT_PB00I_CCL_IN1 (_UL_(1) << 0) 1277 #define PIN_PA06I_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux I */ 1278 #define MUX_PA06I_CCL_IN2 _L_(8) 1279 #define PINMUX_PA06I_CCL_IN2 ((PIN_PA06I_CCL_IN2 << 16) | MUX_PA06I_CCL_IN2) 1280 #define PORT_PA06I_CCL_IN2 (_UL_(1) << 6) 1281 #define PIN_PA18I_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux I */ 1282 #define MUX_PA18I_CCL_IN2 _L_(8) 1283 #define PINMUX_PA18I_CCL_IN2 ((PIN_PA18I_CCL_IN2 << 16) | MUX_PA18I_CCL_IN2) 1284 #define PORT_PA18I_CCL_IN2 (_UL_(1) << 18) 1285 #define PIN_PB01I_CCL_IN2 _L_(33) /**< \brief CCL signal: IN2 on PB01 mux I */ 1286 #define MUX_PB01I_CCL_IN2 _L_(8) 1287 #define PINMUX_PB01I_CCL_IN2 ((PIN_PB01I_CCL_IN2 << 16) | MUX_PB01I_CCL_IN2) 1288 #define PORT_PB01I_CCL_IN2 (_UL_(1) << 1) 1289 #define PIN_PA08I_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux I */ 1290 #define MUX_PA08I_CCL_IN3 _L_(8) 1291 #define PINMUX_PA08I_CCL_IN3 ((PIN_PA08I_CCL_IN3 << 16) | MUX_PA08I_CCL_IN3) 1292 #define PORT_PA08I_CCL_IN3 (_UL_(1) << 8) 1293 #define PIN_PA30I_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux I */ 1294 #define MUX_PA30I_CCL_IN3 _L_(8) 1295 #define PINMUX_PA30I_CCL_IN3 ((PIN_PA30I_CCL_IN3 << 16) | MUX_PA30I_CCL_IN3) 1296 #define PORT_PA30I_CCL_IN3 (_UL_(1) << 30) 1297 #define PIN_PA09I_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux I */ 1298 #define MUX_PA09I_CCL_IN4 _L_(8) 1299 #define PINMUX_PA09I_CCL_IN4 ((PIN_PA09I_CCL_IN4 << 16) | MUX_PA09I_CCL_IN4) 1300 #define PORT_PA09I_CCL_IN4 (_UL_(1) << 9) 1301 #define PIN_PA10I_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux I */ 1302 #define MUX_PA10I_CCL_IN5 _L_(8) 1303 #define PINMUX_PA10I_CCL_IN5 ((PIN_PA10I_CCL_IN5 << 16) | MUX_PA10I_CCL_IN5) 1304 #define PORT_PA10I_CCL_IN5 (_UL_(1) << 10) 1305 #define PIN_PB10I_CCL_IN5 _L_(42) /**< \brief CCL signal: IN5 on PB10 mux I */ 1306 #define MUX_PB10I_CCL_IN5 _L_(8) 1307 #define PINMUX_PB10I_CCL_IN5 ((PIN_PB10I_CCL_IN5 << 16) | MUX_PB10I_CCL_IN5) 1308 #define PORT_PB10I_CCL_IN5 (_UL_(1) << 10) 1309 #define PIN_PA22I_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux I */ 1310 #define MUX_PA22I_CCL_IN6 _L_(8) 1311 #define PINMUX_PA22I_CCL_IN6 ((PIN_PA22I_CCL_IN6 << 16) | MUX_PA22I_CCL_IN6) 1312 #define PORT_PA22I_CCL_IN6 (_UL_(1) << 22) 1313 #define PIN_PB06I_CCL_IN6 _L_(38) /**< \brief CCL signal: IN6 on PB06 mux I */ 1314 #define MUX_PB06I_CCL_IN6 _L_(8) 1315 #define PINMUX_PB06I_CCL_IN6 ((PIN_PB06I_CCL_IN6 << 16) | MUX_PB06I_CCL_IN6) 1316 #define PORT_PB06I_CCL_IN6 (_UL_(1) << 6) 1317 #define PIN_PA23I_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux I */ 1318 #define MUX_PA23I_CCL_IN7 _L_(8) 1319 #define PINMUX_PA23I_CCL_IN7 ((PIN_PA23I_CCL_IN7 << 16) | MUX_PA23I_CCL_IN7) 1320 #define PORT_PA23I_CCL_IN7 (_UL_(1) << 23) 1321 #define PIN_PB07I_CCL_IN7 _L_(39) /**< \brief CCL signal: IN7 on PB07 mux I */ 1322 #define MUX_PB07I_CCL_IN7 _L_(8) 1323 #define PINMUX_PB07I_CCL_IN7 ((PIN_PB07I_CCL_IN7 << 16) | MUX_PB07I_CCL_IN7) 1324 #define PORT_PB07I_CCL_IN7 (_UL_(1) << 7) 1325 #define PIN_PA24I_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux I */ 1326 #define MUX_PA24I_CCL_IN8 _L_(8) 1327 #define PINMUX_PA24I_CCL_IN8 ((PIN_PA24I_CCL_IN8 << 16) | MUX_PA24I_CCL_IN8) 1328 #define PORT_PA24I_CCL_IN8 (_UL_(1) << 24) 1329 #define PIN_PB08I_CCL_IN8 _L_(40) /**< \brief CCL signal: IN8 on PB08 mux I */ 1330 #define MUX_PB08I_CCL_IN8 _L_(8) 1331 #define PINMUX_PB08I_CCL_IN8 ((PIN_PB08I_CCL_IN8 << 16) | MUX_PB08I_CCL_IN8) 1332 #define PORT_PB08I_CCL_IN8 (_UL_(1) << 8) 1333 #define PIN_PB14I_CCL_IN9 _L_(46) /**< \brief CCL signal: IN9 on PB14 mux I */ 1334 #define MUX_PB14I_CCL_IN9 _L_(8) 1335 #define PINMUX_PB14I_CCL_IN9 ((PIN_PB14I_CCL_IN9 << 16) | MUX_PB14I_CCL_IN9) 1336 #define PORT_PB14I_CCL_IN9 (_UL_(1) << 14) 1337 #define PIN_PB15I_CCL_IN10 _L_(47) /**< \brief CCL signal: IN10 on PB15 mux I */ 1338 #define MUX_PB15I_CCL_IN10 _L_(8) 1339 #define PINMUX_PB15I_CCL_IN10 ((PIN_PB15I_CCL_IN10 << 16) | MUX_PB15I_CCL_IN10) 1340 #define PORT_PB15I_CCL_IN10 (_UL_(1) << 15) 1341 #define PIN_PB16I_CCL_IN11 _L_(48) /**< \brief CCL signal: IN11 on PB16 mux I */ 1342 #define MUX_PB16I_CCL_IN11 _L_(8) 1343 #define PINMUX_PB16I_CCL_IN11 ((PIN_PB16I_CCL_IN11 << 16) | MUX_PB16I_CCL_IN11) 1344 #define PORT_PB16I_CCL_IN11 (_UL_(1) << 16) 1345 #define PIN_PA07I_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux I */ 1346 #define MUX_PA07I_CCL_OUT0 _L_(8) 1347 #define PINMUX_PA07I_CCL_OUT0 ((PIN_PA07I_CCL_OUT0 << 16) | MUX_PA07I_CCL_OUT0) 1348 #define PORT_PA07I_CCL_OUT0 (_UL_(1) << 7) 1349 #define PIN_PA19I_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux I */ 1350 #define MUX_PA19I_CCL_OUT0 _L_(8) 1351 #define PINMUX_PA19I_CCL_OUT0 ((PIN_PA19I_CCL_OUT0 << 16) | MUX_PA19I_CCL_OUT0) 1352 #define PORT_PA19I_CCL_OUT0 (_UL_(1) << 19) 1353 #define PIN_PB02I_CCL_OUT0 _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux I */ 1354 #define MUX_PB02I_CCL_OUT0 _L_(8) 1355 #define PINMUX_PB02I_CCL_OUT0 ((PIN_PB02I_CCL_OUT0 << 16) | MUX_PB02I_CCL_OUT0) 1356 #define PORT_PB02I_CCL_OUT0 (_UL_(1) << 2) 1357 #define PIN_PB23I_CCL_OUT0 _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux I */ 1358 #define MUX_PB23I_CCL_OUT0 _L_(8) 1359 #define PINMUX_PB23I_CCL_OUT0 ((PIN_PB23I_CCL_OUT0 << 16) | MUX_PB23I_CCL_OUT0) 1360 #define PORT_PB23I_CCL_OUT0 (_UL_(1) << 23) 1361 #define PIN_PA11I_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux I */ 1362 #define MUX_PA11I_CCL_OUT1 _L_(8) 1363 #define PINMUX_PA11I_CCL_OUT1 ((PIN_PA11I_CCL_OUT1 << 16) | MUX_PA11I_CCL_OUT1) 1364 #define PORT_PA11I_CCL_OUT1 (_UL_(1) << 11) 1365 #define PIN_PA31I_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux I */ 1366 #define MUX_PA31I_CCL_OUT1 _L_(8) 1367 #define PINMUX_PA31I_CCL_OUT1 ((PIN_PA31I_CCL_OUT1 << 16) | MUX_PA31I_CCL_OUT1) 1368 #define PORT_PA31I_CCL_OUT1 (_UL_(1) << 31) 1369 #define PIN_PB11I_CCL_OUT1 _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux I */ 1370 #define MUX_PB11I_CCL_OUT1 _L_(8) 1371 #define PINMUX_PB11I_CCL_OUT1 ((PIN_PB11I_CCL_OUT1 << 16) | MUX_PB11I_CCL_OUT1) 1372 #define PORT_PB11I_CCL_OUT1 (_UL_(1) << 11) 1373 #define PIN_PA25I_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux I */ 1374 #define MUX_PA25I_CCL_OUT2 _L_(8) 1375 #define PINMUX_PA25I_CCL_OUT2 ((PIN_PA25I_CCL_OUT2 << 16) | MUX_PA25I_CCL_OUT2) 1376 #define PORT_PA25I_CCL_OUT2 (_UL_(1) << 25) 1377 #define PIN_PB09I_CCL_OUT2 _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux I */ 1378 #define MUX_PB09I_CCL_OUT2 _L_(8) 1379 #define PINMUX_PB09I_CCL_OUT2 ((PIN_PB09I_CCL_OUT2 << 16) | MUX_PB09I_CCL_OUT2) 1380 #define PORT_PB09I_CCL_OUT2 (_UL_(1) << 9) 1381 #define PIN_PB17I_CCL_OUT3 _L_(49) /**< \brief CCL signal: OUT3 on PB17 mux I */ 1382 #define MUX_PB17I_CCL_OUT3 _L_(8) 1383 #define PINMUX_PB17I_CCL_OUT3 ((PIN_PB17I_CCL_OUT3 << 16) | MUX_PB17I_CCL_OUT3) 1384 #define PORT_PB17I_CCL_OUT3 (_UL_(1) << 17) 1385 1386 #endif /* _SAML21J18BU_PIO_ */ 1387
