1 /** 2 * \file 3 * 4 * \brief Instance description for PCC 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAME54_PCC_INSTANCE_ 31 #define _SAME54_PCC_INSTANCE_ 32 33 /* ========== Register definition for PCC peripheral ========== */ 34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 35 #define REG_PCC_MR (0x43002C00) /**< \brief (PCC) Mode Register */ 36 #define REG_PCC_IER (0x43002C04) /**< \brief (PCC) Interrupt Enable Register */ 37 #define REG_PCC_IDR (0x43002C08) /**< \brief (PCC) Interrupt Disable Register */ 38 #define REG_PCC_IMR (0x43002C0C) /**< \brief (PCC) Interrupt Mask Register */ 39 #define REG_PCC_ISR (0x43002C10) /**< \brief (PCC) Interrupt Status Register */ 40 #define REG_PCC_RHR (0x43002C14) /**< \brief (PCC) Reception Holding Register */ 41 #define REG_PCC_WPMR (0x43002CE0) /**< \brief (PCC) Write Protection Mode Register */ 42 #define REG_PCC_WPSR (0x43002CE4) /**< \brief (PCC) Write Protection Status Register */ 43 #else 44 #define REG_PCC_MR (*(RwReg *)0x43002C00UL) /**< \brief (PCC) Mode Register */ 45 #define REG_PCC_IER (*(WoReg *)0x43002C04UL) /**< \brief (PCC) Interrupt Enable Register */ 46 #define REG_PCC_IDR (*(WoReg *)0x43002C08UL) /**< \brief (PCC) Interrupt Disable Register */ 47 #define REG_PCC_IMR (*(RoReg *)0x43002C0CUL) /**< \brief (PCC) Interrupt Mask Register */ 48 #define REG_PCC_ISR (*(RoReg *)0x43002C10UL) /**< \brief (PCC) Interrupt Status Register */ 49 #define REG_PCC_RHR (*(RoReg *)0x43002C14UL) /**< \brief (PCC) Reception Holding Register */ 50 #define REG_PCC_WPMR (*(RwReg *)0x43002CE0UL) /**< \brief (PCC) Write Protection Mode Register */ 51 #define REG_PCC_WPSR (*(RoReg *)0x43002CE4UL) /**< \brief (PCC) Write Protection Status Register */ 52 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 53 54 /* ========== Instance parameters for PCC peripheral ========== */ 55 #define PCC_DATA_SIZE 14 56 #define PCC_DMAC_ID_RX 80 57 58 #endif /* _SAME54_PCC_INSTANCE_ */ 59
