1 /** 2 * \file 3 * 4 * \brief Header file for SAMD21G17AU 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAMD21G17AU_ 30 #define _SAMD21G17AU_ 31 32 /** 33 * \ingroup SAMD21_definitions 34 * \addtogroup SAMD21G17AU_definitions SAMD21G17AU definitions 35 * This file defines all structures and symbols for SAMD21G17AU: 36 * - registers and bitfields 37 * - peripheral base address 38 * - peripheral ID 39 * - PIO definitions 40 */ 41 /*@{*/ 42 43 #ifdef __cplusplus 44 extern "C" { 45 #endif 46 47 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 48 #include <stdint.h> 49 #ifndef __cplusplus 50 typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ 51 typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ 52 typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ 53 #else 54 typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ 55 typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ 56 typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ 57 #endif 58 typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ 59 typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ 60 typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ 61 typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ 62 typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ 63 typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ 64 #endif 65 66 #if !defined(SKIP_INTEGER_LITERALS) 67 #if defined(_U_) || defined(_L_) || defined(_UL_) 68 #error "Integer Literals macros already defined elsewhere" 69 #endif 70 71 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 72 /* Macros that deal with adding suffixes to integer literal constants for C/C++ */ 73 #define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ 74 #define _L_(x) x ## L /**< C code: Long integer literal constant value */ 75 #define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ 76 #else /* Assembler */ 77 #define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ 78 #define _L_(x) x /**< Assembler: Long integer literal constant value */ 79 #define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ 80 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 81 #endif /* SKIP_INTEGER_LITERALS */ 82 83 /* ************************************************************************** */ 84 /** CMSIS DEFINITIONS FOR SAMD21G17AU */ 85 /* ************************************************************************** */ 86 /** \defgroup SAMD21G17AU_cmsis CMSIS Definitions */ 87 /*@{*/ 88 89 /** Interrupt Number Definition */ 90 typedef enum IRQn 91 { 92 /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ 93 NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ 94 HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ 95 SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ 96 PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ 97 SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ 98 /****** SAMD21G17AU-specific Interrupt Numbers ***********************/ 99 PM_IRQn = 0, /**< 0 SAMD21G17AU Power Manager (PM) */ 100 SYSCTRL_IRQn = 1, /**< 1 SAMD21G17AU System Control (SYSCTRL) */ 101 WDT_IRQn = 2, /**< 2 SAMD21G17AU Watchdog Timer (WDT) */ 102 RTC_IRQn = 3, /**< 3 SAMD21G17AU Real-Time Counter (RTC) */ 103 EIC_IRQn = 4, /**< 4 SAMD21G17AU External Interrupt Controller (EIC) */ 104 NVMCTRL_IRQn = 5, /**< 5 SAMD21G17AU Non-Volatile Memory Controller (NVMCTRL) */ 105 DMAC_IRQn = 6, /**< 6 SAMD21G17AU Direct Memory Access Controller (DMAC) */ 106 USB_IRQn = 7, /**< 7 SAMD21G17AU Universal Serial Bus (USB) */ 107 EVSYS_IRQn = 8, /**< 8 SAMD21G17AU Event System Interface (EVSYS) */ 108 SERCOM0_IRQn = 9, /**< 9 SAMD21G17AU Serial Communication Interface 0 (SERCOM0) */ 109 SERCOM1_IRQn = 10, /**< 10 SAMD21G17AU Serial Communication Interface 1 (SERCOM1) */ 110 SERCOM2_IRQn = 11, /**< 11 SAMD21G17AU Serial Communication Interface 2 (SERCOM2) */ 111 SERCOM3_IRQn = 12, /**< 12 SAMD21G17AU Serial Communication Interface 3 (SERCOM3) */ 112 SERCOM4_IRQn = 13, /**< 13 SAMD21G17AU Serial Communication Interface 4 (SERCOM4) */ 113 SERCOM5_IRQn = 14, /**< 14 SAMD21G17AU Serial Communication Interface 5 (SERCOM5) */ 114 TCC0_IRQn = 15, /**< 15 SAMD21G17AU Timer Counter Control 0 (TCC0) */ 115 TCC1_IRQn = 16, /**< 16 SAMD21G17AU Timer Counter Control 1 (TCC1) */ 116 TCC2_IRQn = 17, /**< 17 SAMD21G17AU Timer Counter Control 2 (TCC2) */ 117 TC3_IRQn = 18, /**< 18 SAMD21G17AU Basic Timer Counter 3 (TC3) */ 118 TC4_IRQn = 19, /**< 19 SAMD21G17AU Basic Timer Counter 4 (TC4) */ 119 TC5_IRQn = 20, /**< 20 SAMD21G17AU Basic Timer Counter 5 (TC5) */ 120 TC6_IRQn = 21, /**< 21 SAMD21G17AU Basic Timer Counter 6 (TC6) */ 121 TC7_IRQn = 22, /**< 22 SAMD21G17AU Basic Timer Counter 7 (TC7) */ 122 ADC_IRQn = 23, /**< 23 SAMD21G17AU Analog Digital Converter (ADC) */ 123 AC_IRQn = 24, /**< 24 SAMD21G17AU Analog Comparators (AC) */ 124 DAC_IRQn = 25, /**< 25 SAMD21G17AU Digital Analog Converter (DAC) */ 125 PTC_IRQn = 26, /**< 26 SAMD21G17AU Peripheral Touch Controller (PTC) */ 126 I2S_IRQn = 27, /**< 27 SAMD21G17AU Inter-IC Sound Interface (I2S) */ 127 128 PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ 129 } IRQn_Type; 130 131 typedef struct _DeviceVectors 132 { 133 /* Stack pointer */ 134 void* pvStack; 135 136 /* Cortex-M handlers */ 137 void* pfnReset_Handler; 138 void* pfnNMI_Handler; 139 void* pfnHardFault_Handler; 140 void* pvReservedM12; 141 void* pvReservedM11; 142 void* pvReservedM10; 143 void* pvReservedM9; 144 void* pvReservedM8; 145 void* pvReservedM7; 146 void* pvReservedM6; 147 void* pfnSVC_Handler; 148 void* pvReservedM4; 149 void* pvReservedM3; 150 void* pfnPendSV_Handler; 151 void* pfnSysTick_Handler; 152 153 /* Peripheral handlers */ 154 void* pfnPM_Handler; /* 0 Power Manager */ 155 void* pfnSYSCTRL_Handler; /* 1 System Control */ 156 void* pfnWDT_Handler; /* 2 Watchdog Timer */ 157 void* pfnRTC_Handler; /* 3 Real-Time Counter */ 158 void* pfnEIC_Handler; /* 4 External Interrupt Controller */ 159 void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ 160 void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ 161 void* pfnUSB_Handler; /* 7 Universal Serial Bus */ 162 void* pfnEVSYS_Handler; /* 8 Event System Interface */ 163 void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ 164 void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ 165 void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ 166 void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ 167 void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ 168 void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ 169 void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ 170 void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ 171 void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ 172 void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ 173 void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ 174 void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ 175 void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ 176 void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ 177 void* pfnADC_Handler; /* 23 Analog Digital Converter */ 178 void* pfnAC_Handler; /* 24 Analog Comparators */ 179 void* pfnDAC_Handler; /* 25 Digital Analog Converter */ 180 void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ 181 void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ 182 void* pvReserved28; 183 } DeviceVectors; 184 185 /* Cortex-M0+ processor handlers */ 186 void Reset_Handler ( void ); 187 void NMI_Handler ( void ); 188 void HardFault_Handler ( void ); 189 void SVC_Handler ( void ); 190 void PendSV_Handler ( void ); 191 void SysTick_Handler ( void ); 192 193 /* Peripherals handlers */ 194 void PM_Handler ( void ); 195 void SYSCTRL_Handler ( void ); 196 void WDT_Handler ( void ); 197 void RTC_Handler ( void ); 198 void EIC_Handler ( void ); 199 void NVMCTRL_Handler ( void ); 200 void DMAC_Handler ( void ); 201 void USB_Handler ( void ); 202 void EVSYS_Handler ( void ); 203 void SERCOM0_Handler ( void ); 204 void SERCOM1_Handler ( void ); 205 void SERCOM2_Handler ( void ); 206 void SERCOM3_Handler ( void ); 207 void SERCOM4_Handler ( void ); 208 void SERCOM5_Handler ( void ); 209 void TCC0_Handler ( void ); 210 void TCC1_Handler ( void ); 211 void TCC2_Handler ( void ); 212 void TC3_Handler ( void ); 213 void TC4_Handler ( void ); 214 void TC5_Handler ( void ); 215 void TC6_Handler ( void ); 216 void TC7_Handler ( void ); 217 void ADC_Handler ( void ); 218 void AC_Handler ( void ); 219 void DAC_Handler ( void ); 220 void PTC_Handler ( void ); 221 void I2S_Handler ( void ); 222 223 /* 224 * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals 225 */ 226 227 #define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ 228 #define __MPU_PRESENT 0 /*!< MPU present or not */ 229 #define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ 230 #define __VTOR_PRESENT 1 /*!< VTOR present or not */ 231 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 232 233 /** 234 * \brief CMSIS includes 235 */ 236 237 #include <core_cm0plus.h> 238 #if !defined DONT_USE_CMSIS_INIT 239 #include "system_samd21.h" 240 #endif /* DONT_USE_CMSIS_INIT */ 241 242 /*@}*/ 243 244 /* ************************************************************************** */ 245 /** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G17AU */ 246 /* ************************************************************************** */ 247 /** \defgroup SAMD21G17AU_api Peripheral Software API */ 248 /*@{*/ 249 250 #include "component/ac.h" 251 #include "component/adc.h" 252 #include "component/dac.h" 253 #include "component/dmac.h" 254 #include "component/dsu.h" 255 #include "component/eic.h" 256 #include "component/evsys.h" 257 #include "component/gclk.h" 258 #include "component/hmatrixb.h" 259 #include "component/i2s.h" 260 #include "component/mtb.h" 261 #include "component/nvmctrl.h" 262 #include "component/pac.h" 263 #include "component/pm.h" 264 #include "component/port.h" 265 #include "component/rtc.h" 266 #include "component/sercom.h" 267 #include "component/sysctrl.h" 268 #include "component/tc.h" 269 #include "component/tcc.h" 270 #include "component/usb.h" 271 #include "component/wdt.h" 272 /*@}*/ 273 274 /* ************************************************************************** */ 275 /** REGISTERS ACCESS DEFINITIONS FOR SAMD21G17AU */ 276 /* ************************************************************************** */ 277 /** \defgroup SAMD21G17AU_reg Registers Access Definitions */ 278 /*@{*/ 279 280 #include "instance/ac.h" 281 #include "instance/adc.h" 282 #include "instance/dac.h" 283 #include "instance/dmac.h" 284 #include "instance/dsu.h" 285 #include "instance/eic.h" 286 #include "instance/evsys.h" 287 #include "instance/gclk.h" 288 #include "instance/sbmatrix.h" 289 #include "instance/i2s.h" 290 #include "instance/mtb.h" 291 #include "instance/nvmctrl.h" 292 #include "instance/pac0.h" 293 #include "instance/pac1.h" 294 #include "instance/pac2.h" 295 #include "instance/pm.h" 296 #include "instance/port.h" 297 #include "instance/rtc.h" 298 #include "instance/sercom0.h" 299 #include "instance/sercom1.h" 300 #include "instance/sercom2.h" 301 #include "instance/sercom3.h" 302 #include "instance/sercom4.h" 303 #include "instance/sercom5.h" 304 #include "instance/sysctrl.h" 305 #include "instance/tc3.h" 306 #include "instance/tc4.h" 307 #include "instance/tc5.h" 308 #include "instance/tc6.h" 309 #include "instance/tc7.h" 310 #include "instance/tcc0.h" 311 #include "instance/tcc1.h" 312 #include "instance/tcc2.h" 313 #include "instance/usb.h" 314 #include "instance/wdt.h" 315 /*@}*/ 316 317 /* ************************************************************************** */ 318 /** PERIPHERAL ID DEFINITIONS FOR SAMD21G17AU */ 319 /* ************************************************************************** */ 320 /** \defgroup SAMD21G17AU_id Peripheral Ids Definitions */ 321 /*@{*/ 322 323 // Peripheral instances on HPB0 bridge 324 #define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ 325 #define ID_PM 1 /**< \brief Power Manager (PM) */ 326 #define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ 327 #define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ 328 #define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ 329 #define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ 330 #define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ 331 332 // Peripheral instances on HPB1 bridge 333 #define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ 334 #define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ 335 #define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ 336 #define ID_PORT 35 /**< \brief Port Module (PORT) */ 337 #define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ 338 #define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ 339 #define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ 340 #define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ 341 342 // Peripheral instances on HPB2 bridge 343 #define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ 344 #define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ 345 #define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ 346 #define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ 347 #define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ 348 #define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ 349 #define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ 350 #define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ 351 #define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ 352 #define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ 353 #define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ 354 #define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ 355 #define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ 356 #define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ 357 #define ID_TC6 78 /**< \brief Basic Timer Counter 6 (TC6) */ 358 #define ID_TC7 79 /**< \brief Basic Timer Counter 7 (TC7) */ 359 #define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ 360 #define ID_AC 81 /**< \brief Analog Comparators (AC) */ 361 #define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ 362 #define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ 363 #define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ 364 365 #define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ 366 /*@}*/ 367 368 /* ************************************************************************** */ 369 /** BASE ADDRESS DEFINITIONS FOR SAMD21G17AU */ 370 /* ************************************************************************** */ 371 /** \defgroup SAMD21G17AU_base Peripheral Base Address Definitions */ 372 /*@{*/ 373 374 #if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) 375 #define AC (0x42004400) /**< \brief (AC) APB Base Address */ 376 #define ADC (0x42004000) /**< \brief (ADC) APB Base Address */ 377 #define DAC (0x42004800) /**< \brief (DAC) APB Base Address */ 378 #define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */ 379 #define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ 380 #define EIC (0x40001800) /**< \brief (EIC) APB Base Address */ 381 #define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */ 382 #define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */ 383 #define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */ 384 #define I2S (0x42005000) /**< \brief (I2S) APB Base Address */ 385 #define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ 386 #define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ 387 #define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ 388 #define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ 389 #define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ 390 #define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ 391 #define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */ 392 #define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ 393 #define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ 394 #define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */ 395 #define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */ 396 #define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */ 397 #define PM (0x40000400) /**< \brief (PM) APB Base Address */ 398 #define PORT (0x41004400) /**< \brief (PORT) APB Base Address */ 399 #define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ 400 #define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */ 401 #define RTC (0x40001400) /**< \brief (RTC) APB Base Address */ 402 #define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */ 403 #define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */ 404 #define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */ 405 #define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */ 406 #define SERCOM4 (0x42001800) /**< \brief (SERCOM4) APB Base Address */ 407 #define SERCOM5 (0x42001C00) /**< \brief (SERCOM5) APB Base Address */ 408 #define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */ 409 #define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ 410 #define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ 411 #define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */ 412 #define TC6 (0x42003800) /**< \brief (TC6) APB Base Address */ 413 #define TC7 (0x42003C00) /**< \brief (TC7) APB Base Address */ 414 #define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ 415 #define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ 416 #define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */ 417 #define USB (0x41005000) /**< \brief (USB) APB Base Address */ 418 #define WDT (0x40001000) /**< \brief (WDT) APB Base Address */ 419 #else 420 #define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ 421 #define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ 422 #define AC_INSTS { AC } /**< \brief (AC) Instances List */ 423 424 #define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ 425 #define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ 426 #define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ 427 428 #define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ 429 #define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ 430 #define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ 431 432 #define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ 433 #define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ 434 #define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ 435 436 #define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ 437 #define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ 438 #define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ 439 440 #define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ 441 #define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ 442 #define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ 443 444 #define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ 445 #define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ 446 #define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ 447 448 #define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ 449 #define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ 450 #define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ 451 452 #define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ 453 #define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ 454 #define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ 455 456 #define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ 457 #define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ 458 #define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ 459 460 #define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ 461 #define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ 462 #define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ 463 464 #define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ 465 #define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ 466 #define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ 467 #define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ 468 #define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ 469 #define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ 470 #define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ 471 #define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ 472 #define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ 473 #define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ 474 475 #define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ 476 #define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ 477 #define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ 478 #define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ 479 #define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ 480 481 #define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ 482 #define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ 483 #define PM_INSTS { PM } /**< \brief (PM) Instances List */ 484 485 #define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ 486 #define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ 487 #define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ 488 #define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ 489 #define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ 490 #define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ 491 492 #define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */ 493 #define PTC_GCLK_ID 34 494 #define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ 495 #define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ 496 497 #define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ 498 #define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ 499 #define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ 500 501 #define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ 502 #define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ 503 #define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ 504 #define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ 505 #define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ 506 #define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ 507 #define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ 508 #define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ 509 510 #define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ 511 #define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ 512 #define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ 513 514 #define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ 515 #define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ 516 #define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ 517 #define TC6 ((Tc *)0x42003800UL) /**< \brief (TC6) APB Base Address */ 518 #define TC7 ((Tc *)0x42003C00UL) /**< \brief (TC7) APB Base Address */ 519 #define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ 520 #define TC_INSTS { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ 521 522 #define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ 523 #define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ 524 #define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ 525 #define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ 526 #define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ 527 528 #define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ 529 #define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ 530 #define USB_INSTS { USB } /**< \brief (USB) Instances List */ 531 532 #define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ 533 #define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ 534 #define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ 535 536 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 537 /*@}*/ 538 539 /* ************************************************************************** */ 540 /** PORT DEFINITIONS FOR SAMD21G17AU */ 541 /* ************************************************************************** */ 542 /** \defgroup SAMD21G17AU_port PORT Definitions */ 543 /*@{*/ 544 545 #include "pio/samd21g17au.h" 546 /*@}*/ 547 548 /* ************************************************************************** */ 549 /** MEMORY MAPPING DEFINITIONS FOR SAMD21G17AU */ 550 /* ************************************************************************** */ 551 552 #define FLASH_SIZE _UL_(0x00020000) /* 128 kB */ 553 #define FLASH_PAGE_SIZE 64 554 #define FLASH_NB_OF_PAGES 2048 555 #define FLASH_USER_PAGE_SIZE 64 556 #define HMCRAMC0_SIZE _UL_(0x00004000) /* 16 kB */ 557 558 #define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ 559 #define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */ 560 #define HMCRAMC0_ADDR _UL_(0x20000000) /**< HMCRAMC0 base address */ 561 #define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ 562 #define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ 563 #define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ 564 #define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ 565 566 #define DSU_DID_RESETVALUE _UL_(0x10010310) 567 #define EIC_EXTINT_NUM 16 568 #define PORT_GROUPS 2 569 570 /* ************************************************************************** */ 571 /** ELECTRICAL DEFINITIONS FOR SAMD21G17AU */ 572 /* ************************************************************************** */ 573 574 575 #ifdef __cplusplus 576 } 577 #endif 578 579 /*@}*/ 580 581 #endif /* SAMD21G17AU_H */ 582
