1 /** 2 * \file 3 * 4 * \brief Peripheral I/O description for SAMD21E16A 5 * 6 * Copyright (c) 2017 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAMD21E16A_PIO_ 30 #define _SAMD21E16A_PIO_ 31 32 #define PIN_PA00 0 /**< \brief Pin Number for PA00 */ 33 #define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */ 34 #define PIN_PA01 1 /**< \brief Pin Number for PA01 */ 35 #define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */ 36 #define PIN_PA02 2 /**< \brief Pin Number for PA02 */ 37 #define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */ 38 #define PIN_PA03 3 /**< \brief Pin Number for PA03 */ 39 #define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */ 40 #define PIN_PA04 4 /**< \brief Pin Number for PA04 */ 41 #define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */ 42 #define PIN_PA05 5 /**< \brief Pin Number for PA05 */ 43 #define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */ 44 #define PIN_PA06 6 /**< \brief Pin Number for PA06 */ 45 #define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */ 46 #define PIN_PA07 7 /**< \brief Pin Number for PA07 */ 47 #define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */ 48 #define PIN_PA08 8 /**< \brief Pin Number for PA08 */ 49 #define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */ 50 #define PIN_PA09 9 /**< \brief Pin Number for PA09 */ 51 #define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */ 52 #define PIN_PA10 10 /**< \brief Pin Number for PA10 */ 53 #define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */ 54 #define PIN_PA11 11 /**< \brief Pin Number for PA11 */ 55 #define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */ 56 #define PIN_PA14 14 /**< \brief Pin Number for PA14 */ 57 #define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */ 58 #define PIN_PA15 15 /**< \brief Pin Number for PA15 */ 59 #define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */ 60 #define PIN_PA16 16 /**< \brief Pin Number for PA16 */ 61 #define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */ 62 #define PIN_PA17 17 /**< \brief Pin Number for PA17 */ 63 #define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */ 64 #define PIN_PA18 18 /**< \brief Pin Number for PA18 */ 65 #define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */ 66 #define PIN_PA19 19 /**< \brief Pin Number for PA19 */ 67 #define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */ 68 #define PIN_PA22 22 /**< \brief Pin Number for PA22 */ 69 #define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */ 70 #define PIN_PA23 23 /**< \brief Pin Number for PA23 */ 71 #define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */ 72 #define PIN_PA24 24 /**< \brief Pin Number for PA24 */ 73 #define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */ 74 #define PIN_PA25 25 /**< \brief Pin Number for PA25 */ 75 #define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */ 76 #define PIN_PA27 27 /**< \brief Pin Number for PA27 */ 77 #define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */ 78 #define PIN_PA28 28 /**< \brief Pin Number for PA28 */ 79 #define PORT_PA28 (_UL_(1) << 28) /**< \brief PORT Mask for PA28 */ 80 #define PIN_PA30 30 /**< \brief Pin Number for PA30 */ 81 #define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */ 82 #define PIN_PA31 31 /**< \brief Pin Number for PA31 */ 83 #define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */ 84 /* ========== PORT definition for GCLK peripheral ========== */ 85 #define PIN_PA14H_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux H */ 86 #define MUX_PA14H_GCLK_IO0 _L_(7) 87 #define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) 88 #define PORT_PA14H_GCLK_IO0 (_UL_(1) << 14) 89 #define PIN_PA27H_GCLK_IO0 _L_(27) /**< \brief GCLK signal: IO0 on PA27 mux H */ 90 #define MUX_PA27H_GCLK_IO0 _L_(7) 91 #define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) 92 #define PORT_PA27H_GCLK_IO0 (_UL_(1) << 27) 93 #define PIN_PA28H_GCLK_IO0 _L_(28) /**< \brief GCLK signal: IO0 on PA28 mux H */ 94 #define MUX_PA28H_GCLK_IO0 _L_(7) 95 #define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0) 96 #define PORT_PA28H_GCLK_IO0 (_UL_(1) << 28) 97 #define PIN_PA30H_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux H */ 98 #define MUX_PA30H_GCLK_IO0 _L_(7) 99 #define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) 100 #define PORT_PA30H_GCLK_IO0 (_UL_(1) << 30) 101 #define PIN_PA15H_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux H */ 102 #define MUX_PA15H_GCLK_IO1 _L_(7) 103 #define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) 104 #define PORT_PA15H_GCLK_IO1 (_UL_(1) << 15) 105 #define PIN_PA16H_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux H */ 106 #define MUX_PA16H_GCLK_IO2 _L_(7) 107 #define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) 108 #define PORT_PA16H_GCLK_IO2 (_UL_(1) << 16) 109 #define PIN_PA17H_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux H */ 110 #define MUX_PA17H_GCLK_IO3 _L_(7) 111 #define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) 112 #define PORT_PA17H_GCLK_IO3 (_UL_(1) << 17) 113 #define PIN_PA10H_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux H */ 114 #define MUX_PA10H_GCLK_IO4 _L_(7) 115 #define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) 116 #define PORT_PA10H_GCLK_IO4 (_UL_(1) << 10) 117 #define PIN_PA11H_GCLK_IO5 _L_(11) /**< \brief GCLK signal: IO5 on PA11 mux H */ 118 #define MUX_PA11H_GCLK_IO5 _L_(7) 119 #define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) 120 #define PORT_PA11H_GCLK_IO5 (_UL_(1) << 11) 121 #define PIN_PA22H_GCLK_IO6 _L_(22) /**< \brief GCLK signal: IO6 on PA22 mux H */ 122 #define MUX_PA22H_GCLK_IO6 _L_(7) 123 #define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6) 124 #define PORT_PA22H_GCLK_IO6 (_UL_(1) << 22) 125 #define PIN_PA23H_GCLK_IO7 _L_(23) /**< \brief GCLK signal: IO7 on PA23 mux H */ 126 #define MUX_PA23H_GCLK_IO7 _L_(7) 127 #define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7) 128 #define PORT_PA23H_GCLK_IO7 (_UL_(1) << 23) 129 /* ========== PORT definition for EIC peripheral ========== */ 130 #define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */ 131 #define MUX_PA16A_EIC_EXTINT0 _L_(0) 132 #define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) 133 #define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16) 134 #define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ 135 #define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */ 136 #define MUX_PA00A_EIC_EXTINT0 _L_(0) 137 #define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) 138 #define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0) 139 #define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */ 140 #define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */ 141 #define MUX_PA17A_EIC_EXTINT1 _L_(0) 142 #define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) 143 #define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17) 144 #define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ 145 #define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */ 146 #define MUX_PA01A_EIC_EXTINT1 _L_(0) 147 #define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) 148 #define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1) 149 #define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */ 150 #define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */ 151 #define MUX_PA18A_EIC_EXTINT2 _L_(0) 152 #define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) 153 #define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18) 154 #define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ 155 #define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */ 156 #define MUX_PA02A_EIC_EXTINT2 _L_(0) 157 #define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) 158 #define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2) 159 #define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */ 160 #define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */ 161 #define MUX_PA03A_EIC_EXTINT3 _L_(0) 162 #define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) 163 #define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3) 164 #define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */ 165 #define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */ 166 #define MUX_PA19A_EIC_EXTINT3 _L_(0) 167 #define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) 168 #define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19) 169 #define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ 170 #define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */ 171 #define MUX_PA04A_EIC_EXTINT4 _L_(0) 172 #define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) 173 #define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4) 174 #define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */ 175 #define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */ 176 #define MUX_PA05A_EIC_EXTINT5 _L_(0) 177 #define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) 178 #define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5) 179 #define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */ 180 #define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */ 181 #define MUX_PA06A_EIC_EXTINT6 _L_(0) 182 #define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) 183 #define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6) 184 #define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ 185 #define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */ 186 #define MUX_PA22A_EIC_EXTINT6 _L_(0) 187 #define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) 188 #define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22) 189 #define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */ 190 #define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */ 191 #define MUX_PA07A_EIC_EXTINT7 _L_(0) 192 #define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) 193 #define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7) 194 #define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ 195 #define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */ 196 #define MUX_PA23A_EIC_EXTINT7 _L_(0) 197 #define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) 198 #define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23) 199 #define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */ 200 #define PIN_PA28A_EIC_EXTINT8 _L_(28) /**< \brief EIC signal: EXTINT8 on PA28 mux A */ 201 #define MUX_PA28A_EIC_EXTINT8 _L_(0) 202 #define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8) 203 #define PORT_PA28A_EIC_EXTINT8 (_UL_(1) << 28) 204 #define PIN_PA28A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PA28 External Interrupt Line */ 205 #define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */ 206 #define MUX_PA09A_EIC_EXTINT9 _L_(0) 207 #define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) 208 #define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9) 209 #define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */ 210 #define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */ 211 #define MUX_PA10A_EIC_EXTINT10 _L_(0) 212 #define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) 213 #define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10) 214 #define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */ 215 #define PIN_PA30A_EIC_EXTINT10 _L_(30) /**< \brief EIC signal: EXTINT10 on PA30 mux A */ 216 #define MUX_PA30A_EIC_EXTINT10 _L_(0) 217 #define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) 218 #define PORT_PA30A_EIC_EXTINT10 (_UL_(1) << 30) 219 #define PIN_PA30A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */ 220 #define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */ 221 #define MUX_PA11A_EIC_EXTINT11 _L_(0) 222 #define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) 223 #define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11) 224 #define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */ 225 #define PIN_PA31A_EIC_EXTINT11 _L_(31) /**< \brief EIC signal: EXTINT11 on PA31 mux A */ 226 #define MUX_PA31A_EIC_EXTINT11 _L_(0) 227 #define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) 228 #define PORT_PA31A_EIC_EXTINT11 (_UL_(1) << 31) 229 #define PIN_PA31A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */ 230 #define PIN_PA24A_EIC_EXTINT12 _L_(24) /**< \brief EIC signal: EXTINT12 on PA24 mux A */ 231 #define MUX_PA24A_EIC_EXTINT12 _L_(0) 232 #define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) 233 #define PORT_PA24A_EIC_EXTINT12 (_UL_(1) << 24) 234 #define PIN_PA24A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */ 235 #define PIN_PA25A_EIC_EXTINT13 _L_(25) /**< \brief EIC signal: EXTINT13 on PA25 mux A */ 236 #define MUX_PA25A_EIC_EXTINT13 _L_(0) 237 #define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) 238 #define PORT_PA25A_EIC_EXTINT13 (_UL_(1) << 25) 239 #define PIN_PA25A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */ 240 #define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */ 241 #define MUX_PA14A_EIC_EXTINT14 _L_(0) 242 #define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) 243 #define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14) 244 #define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */ 245 #define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */ 246 #define MUX_PA15A_EIC_EXTINT15 _L_(0) 247 #define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) 248 #define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15) 249 #define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */ 250 #define PIN_PA27A_EIC_EXTINT15 _L_(27) /**< \brief EIC signal: EXTINT15 on PA27 mux A */ 251 #define MUX_PA27A_EIC_EXTINT15 _L_(0) 252 #define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) 253 #define PORT_PA27A_EIC_EXTINT15 (_UL_(1) << 27) 254 #define PIN_PA27A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */ 255 #define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */ 256 #define MUX_PA08A_EIC_NMI _L_(0) 257 #define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) 258 #define PORT_PA08A_EIC_NMI (_UL_(1) << 8) 259 /* ========== PORT definition for USB peripheral ========== */ 260 #define PIN_PA24G_USB_DM _L_(24) /**< \brief USB signal: DM on PA24 mux G */ 261 #define MUX_PA24G_USB_DM _L_(6) 262 #define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) 263 #define PORT_PA24G_USB_DM (_UL_(1) << 24) 264 #define PIN_PA25G_USB_DP _L_(25) /**< \brief USB signal: DP on PA25 mux G */ 265 #define MUX_PA25G_USB_DP _L_(6) 266 #define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) 267 #define PORT_PA25G_USB_DP (_UL_(1) << 25) 268 #define PIN_PA23G_USB_SOF_1KHZ _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ 269 #define MUX_PA23G_USB_SOF_1KHZ _L_(6) 270 #define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) 271 #define PORT_PA23G_USB_SOF_1KHZ (_UL_(1) << 23) 272 /* ========== PORT definition for SERCOM0 peripheral ========== */ 273 #define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ 274 #define MUX_PA04D_SERCOM0_PAD0 _L_(3) 275 #define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) 276 #define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4) 277 #define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ 278 #define MUX_PA08C_SERCOM0_PAD0 _L_(2) 279 #define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) 280 #define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8) 281 #define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ 282 #define MUX_PA05D_SERCOM0_PAD1 _L_(3) 283 #define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) 284 #define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5) 285 #define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ 286 #define MUX_PA09C_SERCOM0_PAD1 _L_(2) 287 #define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) 288 #define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9) 289 #define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ 290 #define MUX_PA06D_SERCOM0_PAD2 _L_(3) 291 #define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) 292 #define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6) 293 #define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ 294 #define MUX_PA10C_SERCOM0_PAD2 _L_(2) 295 #define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) 296 #define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10) 297 #define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ 298 #define MUX_PA07D_SERCOM0_PAD3 _L_(3) 299 #define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) 300 #define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7) 301 #define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ 302 #define MUX_PA11C_SERCOM0_PAD3 _L_(2) 303 #define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) 304 #define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11) 305 /* ========== PORT definition for SERCOM1 peripheral ========== */ 306 #define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ 307 #define MUX_PA16C_SERCOM1_PAD0 _L_(2) 308 #define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) 309 #define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16) 310 #define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ 311 #define MUX_PA00D_SERCOM1_PAD0 _L_(3) 312 #define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) 313 #define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0) 314 #define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ 315 #define MUX_PA17C_SERCOM1_PAD1 _L_(2) 316 #define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) 317 #define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17) 318 #define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ 319 #define MUX_PA01D_SERCOM1_PAD1 _L_(3) 320 #define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) 321 #define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1) 322 #define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ 323 #define MUX_PA30D_SERCOM1_PAD2 _L_(3) 324 #define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) 325 #define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30) 326 #define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ 327 #define MUX_PA18C_SERCOM1_PAD2 _L_(2) 328 #define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) 329 #define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18) 330 #define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ 331 #define MUX_PA31D_SERCOM1_PAD3 _L_(3) 332 #define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) 333 #define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31) 334 #define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ 335 #define MUX_PA19C_SERCOM1_PAD3 _L_(2) 336 #define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) 337 #define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19) 338 /* ========== PORT definition for SERCOM2 peripheral ========== */ 339 #define PIN_PA08D_SERCOM2_PAD0 _L_(8) /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ 340 #define MUX_PA08D_SERCOM2_PAD0 _L_(3) 341 #define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) 342 #define PORT_PA08D_SERCOM2_PAD0 (_UL_(1) << 8) 343 #define PIN_PA09D_SERCOM2_PAD1 _L_(9) /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ 344 #define MUX_PA09D_SERCOM2_PAD1 _L_(3) 345 #define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) 346 #define PORT_PA09D_SERCOM2_PAD1 (_UL_(1) << 9) 347 #define PIN_PA10D_SERCOM2_PAD2 _L_(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ 348 #define MUX_PA10D_SERCOM2_PAD2 _L_(3) 349 #define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) 350 #define PORT_PA10D_SERCOM2_PAD2 (_UL_(1) << 10) 351 #define PIN_PA14C_SERCOM2_PAD2 _L_(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ 352 #define MUX_PA14C_SERCOM2_PAD2 _L_(2) 353 #define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) 354 #define PORT_PA14C_SERCOM2_PAD2 (_UL_(1) << 14) 355 #define PIN_PA11D_SERCOM2_PAD3 _L_(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ 356 #define MUX_PA11D_SERCOM2_PAD3 _L_(3) 357 #define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) 358 #define PORT_PA11D_SERCOM2_PAD3 (_UL_(1) << 11) 359 #define PIN_PA15C_SERCOM2_PAD3 _L_(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ 360 #define MUX_PA15C_SERCOM2_PAD3 _L_(2) 361 #define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) 362 #define PORT_PA15C_SERCOM2_PAD3 (_UL_(1) << 15) 363 /* ========== PORT definition for SERCOM3 peripheral ========== */ 364 #define PIN_PA16D_SERCOM3_PAD0 _L_(16) /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ 365 #define MUX_PA16D_SERCOM3_PAD0 _L_(3) 366 #define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) 367 #define PORT_PA16D_SERCOM3_PAD0 (_UL_(1) << 16) 368 #define PIN_PA22C_SERCOM3_PAD0 _L_(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ 369 #define MUX_PA22C_SERCOM3_PAD0 _L_(2) 370 #define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) 371 #define PORT_PA22C_SERCOM3_PAD0 (_UL_(1) << 22) 372 #define PIN_PA17D_SERCOM3_PAD1 _L_(17) /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ 373 #define MUX_PA17D_SERCOM3_PAD1 _L_(3) 374 #define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) 375 #define PORT_PA17D_SERCOM3_PAD1 (_UL_(1) << 17) 376 #define PIN_PA23C_SERCOM3_PAD1 _L_(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ 377 #define MUX_PA23C_SERCOM3_PAD1 _L_(2) 378 #define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) 379 #define PORT_PA23C_SERCOM3_PAD1 (_UL_(1) << 23) 380 #define PIN_PA18D_SERCOM3_PAD2 _L_(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ 381 #define MUX_PA18D_SERCOM3_PAD2 _L_(3) 382 #define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) 383 #define PORT_PA18D_SERCOM3_PAD2 (_UL_(1) << 18) 384 #define PIN_PA24C_SERCOM3_PAD2 _L_(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ 385 #define MUX_PA24C_SERCOM3_PAD2 _L_(2) 386 #define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) 387 #define PORT_PA24C_SERCOM3_PAD2 (_UL_(1) << 24) 388 #define PIN_PA19D_SERCOM3_PAD3 _L_(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ 389 #define MUX_PA19D_SERCOM3_PAD3 _L_(3) 390 #define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) 391 #define PORT_PA19D_SERCOM3_PAD3 (_UL_(1) << 19) 392 #define PIN_PA25C_SERCOM3_PAD3 _L_(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ 393 #define MUX_PA25C_SERCOM3_PAD3 _L_(2) 394 #define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) 395 #define PORT_PA25C_SERCOM3_PAD3 (_UL_(1) << 25) 396 /* ========== PORT definition for TCC0 peripheral ========== */ 397 #define PIN_PA04E_TCC0_WO0 _L_(4) /**< \brief TCC0 signal: WO0 on PA04 mux E */ 398 #define MUX_PA04E_TCC0_WO0 _L_(4) 399 #define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) 400 #define PORT_PA04E_TCC0_WO0 (_UL_(1) << 4) 401 #define PIN_PA08E_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux E */ 402 #define MUX_PA08E_TCC0_WO0 _L_(4) 403 #define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) 404 #define PORT_PA08E_TCC0_WO0 (_UL_(1) << 8) 405 #define PIN_PA05E_TCC0_WO1 _L_(5) /**< \brief TCC0 signal: WO1 on PA05 mux E */ 406 #define MUX_PA05E_TCC0_WO1 _L_(4) 407 #define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) 408 #define PORT_PA05E_TCC0_WO1 (_UL_(1) << 5) 409 #define PIN_PA09E_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux E */ 410 #define MUX_PA09E_TCC0_WO1 _L_(4) 411 #define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) 412 #define PORT_PA09E_TCC0_WO1 (_UL_(1) << 9) 413 #define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */ 414 #define MUX_PA10F_TCC0_WO2 _L_(5) 415 #define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) 416 #define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10) 417 #define PIN_PA18F_TCC0_WO2 _L_(18) /**< \brief TCC0 signal: WO2 on PA18 mux F */ 418 #define MUX_PA18F_TCC0_WO2 _L_(5) 419 #define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) 420 #define PORT_PA18F_TCC0_WO2 (_UL_(1) << 18) 421 #define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */ 422 #define MUX_PA11F_TCC0_WO3 _L_(5) 423 #define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) 424 #define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11) 425 #define PIN_PA19F_TCC0_WO3 _L_(19) /**< \brief TCC0 signal: WO3 on PA19 mux F */ 426 #define MUX_PA19F_TCC0_WO3 _L_(5) 427 #define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) 428 #define PORT_PA19F_TCC0_WO3 (_UL_(1) << 19) 429 #define PIN_PA14F_TCC0_WO4 _L_(14) /**< \brief TCC0 signal: WO4 on PA14 mux F */ 430 #define MUX_PA14F_TCC0_WO4 _L_(5) 431 #define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) 432 #define PORT_PA14F_TCC0_WO4 (_UL_(1) << 14) 433 #define PIN_PA22F_TCC0_WO4 _L_(22) /**< \brief TCC0 signal: WO4 on PA22 mux F */ 434 #define MUX_PA22F_TCC0_WO4 _L_(5) 435 #define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) 436 #define PORT_PA22F_TCC0_WO4 (_UL_(1) << 22) 437 #define PIN_PA15F_TCC0_WO5 _L_(15) /**< \brief TCC0 signal: WO5 on PA15 mux F */ 438 #define MUX_PA15F_TCC0_WO5 _L_(5) 439 #define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) 440 #define PORT_PA15F_TCC0_WO5 (_UL_(1) << 15) 441 #define PIN_PA23F_TCC0_WO5 _L_(23) /**< \brief TCC0 signal: WO5 on PA23 mux F */ 442 #define MUX_PA23F_TCC0_WO5 _L_(5) 443 #define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) 444 #define PORT_PA23F_TCC0_WO5 (_UL_(1) << 23) 445 #define PIN_PA16F_TCC0_WO6 _L_(16) /**< \brief TCC0 signal: WO6 on PA16 mux F */ 446 #define MUX_PA16F_TCC0_WO6 _L_(5) 447 #define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) 448 #define PORT_PA16F_TCC0_WO6 (_UL_(1) << 16) 449 #define PIN_PA17F_TCC0_WO7 _L_(17) /**< \brief TCC0 signal: WO7 on PA17 mux F */ 450 #define MUX_PA17F_TCC0_WO7 _L_(5) 451 #define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) 452 #define PORT_PA17F_TCC0_WO7 (_UL_(1) << 17) 453 /* ========== PORT definition for TCC1 peripheral ========== */ 454 #define PIN_PA06E_TCC1_WO0 _L_(6) /**< \brief TCC1 signal: WO0 on PA06 mux E */ 455 #define MUX_PA06E_TCC1_WO0 _L_(4) 456 #define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) 457 #define PORT_PA06E_TCC1_WO0 (_UL_(1) << 6) 458 #define PIN_PA10E_TCC1_WO0 _L_(10) /**< \brief TCC1 signal: WO0 on PA10 mux E */ 459 #define MUX_PA10E_TCC1_WO0 _L_(4) 460 #define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) 461 #define PORT_PA10E_TCC1_WO0 (_UL_(1) << 10) 462 #define PIN_PA30E_TCC1_WO0 _L_(30) /**< \brief TCC1 signal: WO0 on PA30 mux E */ 463 #define MUX_PA30E_TCC1_WO0 _L_(4) 464 #define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) 465 #define PORT_PA30E_TCC1_WO0 (_UL_(1) << 30) 466 #define PIN_PA07E_TCC1_WO1 _L_(7) /**< \brief TCC1 signal: WO1 on PA07 mux E */ 467 #define MUX_PA07E_TCC1_WO1 _L_(4) 468 #define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) 469 #define PORT_PA07E_TCC1_WO1 (_UL_(1) << 7) 470 #define PIN_PA11E_TCC1_WO1 _L_(11) /**< \brief TCC1 signal: WO1 on PA11 mux E */ 471 #define MUX_PA11E_TCC1_WO1 _L_(4) 472 #define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) 473 #define PORT_PA11E_TCC1_WO1 (_UL_(1) << 11) 474 #define PIN_PA31E_TCC1_WO1 _L_(31) /**< \brief TCC1 signal: WO1 on PA31 mux E */ 475 #define MUX_PA31E_TCC1_WO1 _L_(4) 476 #define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) 477 #define PORT_PA31E_TCC1_WO1 (_UL_(1) << 31) 478 #define PIN_PA08F_TCC1_WO2 _L_(8) /**< \brief TCC1 signal: WO2 on PA08 mux F */ 479 #define MUX_PA08F_TCC1_WO2 _L_(5) 480 #define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2) 481 #define PORT_PA08F_TCC1_WO2 (_UL_(1) << 8) 482 #define PIN_PA24F_TCC1_WO2 _L_(24) /**< \brief TCC1 signal: WO2 on PA24 mux F */ 483 #define MUX_PA24F_TCC1_WO2 _L_(5) 484 #define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) 485 #define PORT_PA24F_TCC1_WO2 (_UL_(1) << 24) 486 #define PIN_PA09F_TCC1_WO3 _L_(9) /**< \brief TCC1 signal: WO3 on PA09 mux F */ 487 #define MUX_PA09F_TCC1_WO3 _L_(5) 488 #define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3) 489 #define PORT_PA09F_TCC1_WO3 (_UL_(1) << 9) 490 #define PIN_PA25F_TCC1_WO3 _L_(25) /**< \brief TCC1 signal: WO3 on PA25 mux F */ 491 #define MUX_PA25F_TCC1_WO3 _L_(5) 492 #define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) 493 #define PORT_PA25F_TCC1_WO3 (_UL_(1) << 25) 494 /* ========== PORT definition for TCC2 peripheral ========== */ 495 #define PIN_PA16E_TCC2_WO0 _L_(16) /**< \brief TCC2 signal: WO0 on PA16 mux E */ 496 #define MUX_PA16E_TCC2_WO0 _L_(4) 497 #define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) 498 #define PORT_PA16E_TCC2_WO0 (_UL_(1) << 16) 499 #define PIN_PA00E_TCC2_WO0 _L_(0) /**< \brief TCC2 signal: WO0 on PA00 mux E */ 500 #define MUX_PA00E_TCC2_WO0 _L_(4) 501 #define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0) 502 #define PORT_PA00E_TCC2_WO0 (_UL_(1) << 0) 503 #define PIN_PA17E_TCC2_WO1 _L_(17) /**< \brief TCC2 signal: WO1 on PA17 mux E */ 504 #define MUX_PA17E_TCC2_WO1 _L_(4) 505 #define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) 506 #define PORT_PA17E_TCC2_WO1 (_UL_(1) << 17) 507 #define PIN_PA01E_TCC2_WO1 _L_(1) /**< \brief TCC2 signal: WO1 on PA01 mux E */ 508 #define MUX_PA01E_TCC2_WO1 _L_(4) 509 #define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1) 510 #define PORT_PA01E_TCC2_WO1 (_UL_(1) << 1) 511 /* ========== PORT definition for TC3 peripheral ========== */ 512 #define PIN_PA18E_TC3_WO0 _L_(18) /**< \brief TC3 signal: WO0 on PA18 mux E */ 513 #define MUX_PA18E_TC3_WO0 _L_(4) 514 #define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) 515 #define PORT_PA18E_TC3_WO0 (_UL_(1) << 18) 516 #define PIN_PA14E_TC3_WO0 _L_(14) /**< \brief TC3 signal: WO0 on PA14 mux E */ 517 #define MUX_PA14E_TC3_WO0 _L_(4) 518 #define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) 519 #define PORT_PA14E_TC3_WO0 (_UL_(1) << 14) 520 #define PIN_PA19E_TC3_WO1 _L_(19) /**< \brief TC3 signal: WO1 on PA19 mux E */ 521 #define MUX_PA19E_TC3_WO1 _L_(4) 522 #define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) 523 #define PORT_PA19E_TC3_WO1 (_UL_(1) << 19) 524 #define PIN_PA15E_TC3_WO1 _L_(15) /**< \brief TC3 signal: WO1 on PA15 mux E */ 525 #define MUX_PA15E_TC3_WO1 _L_(4) 526 #define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) 527 #define PORT_PA15E_TC3_WO1 (_UL_(1) << 15) 528 /* ========== PORT definition for TC4 peripheral ========== */ 529 #define PIN_PA22E_TC4_WO0 _L_(22) /**< \brief TC4 signal: WO0 on PA22 mux E */ 530 #define MUX_PA22E_TC4_WO0 _L_(4) 531 #define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) 532 #define PORT_PA22E_TC4_WO0 (_UL_(1) << 22) 533 #define PIN_PA23E_TC4_WO1 _L_(23) /**< \brief TC4 signal: WO1 on PA23 mux E */ 534 #define MUX_PA23E_TC4_WO1 _L_(4) 535 #define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) 536 #define PORT_PA23E_TC4_WO1 (_UL_(1) << 23) 537 /* ========== PORT definition for TC5 peripheral ========== */ 538 #define PIN_PA24E_TC5_WO0 _L_(24) /**< \brief TC5 signal: WO0 on PA24 mux E */ 539 #define MUX_PA24E_TC5_WO0 _L_(4) 540 #define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) 541 #define PORT_PA24E_TC5_WO0 (_UL_(1) << 24) 542 #define PIN_PA25E_TC5_WO1 _L_(25) /**< \brief TC5 signal: WO1 on PA25 mux E */ 543 #define MUX_PA25E_TC5_WO1 _L_(4) 544 #define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) 545 #define PORT_PA25E_TC5_WO1 (_UL_(1) << 25) 546 /* ========== PORT definition for ADC peripheral ========== */ 547 #define PIN_PA02B_ADC_AIN0 _L_(2) /**< \brief ADC signal: AIN0 on PA02 mux B */ 548 #define MUX_PA02B_ADC_AIN0 _L_(1) 549 #define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) 550 #define PORT_PA02B_ADC_AIN0 (_UL_(1) << 2) 551 #define PIN_PA03B_ADC_AIN1 _L_(3) /**< \brief ADC signal: AIN1 on PA03 mux B */ 552 #define MUX_PA03B_ADC_AIN1 _L_(1) 553 #define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) 554 #define PORT_PA03B_ADC_AIN1 (_UL_(1) << 3) 555 #define PIN_PA04B_ADC_AIN4 _L_(4) /**< \brief ADC signal: AIN4 on PA04 mux B */ 556 #define MUX_PA04B_ADC_AIN4 _L_(1) 557 #define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) 558 #define PORT_PA04B_ADC_AIN4 (_UL_(1) << 4) 559 #define PIN_PA05B_ADC_AIN5 _L_(5) /**< \brief ADC signal: AIN5 on PA05 mux B */ 560 #define MUX_PA05B_ADC_AIN5 _L_(1) 561 #define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) 562 #define PORT_PA05B_ADC_AIN5 (_UL_(1) << 5) 563 #define PIN_PA06B_ADC_AIN6 _L_(6) /**< \brief ADC signal: AIN6 on PA06 mux B */ 564 #define MUX_PA06B_ADC_AIN6 _L_(1) 565 #define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) 566 #define PORT_PA06B_ADC_AIN6 (_UL_(1) << 6) 567 #define PIN_PA07B_ADC_AIN7 _L_(7) /**< \brief ADC signal: AIN7 on PA07 mux B */ 568 #define MUX_PA07B_ADC_AIN7 _L_(1) 569 #define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) 570 #define PORT_PA07B_ADC_AIN7 (_UL_(1) << 7) 571 #define PIN_PA08B_ADC_AIN16 _L_(8) /**< \brief ADC signal: AIN16 on PA08 mux B */ 572 #define MUX_PA08B_ADC_AIN16 _L_(1) 573 #define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) 574 #define PORT_PA08B_ADC_AIN16 (_UL_(1) << 8) 575 #define PIN_PA09B_ADC_AIN17 _L_(9) /**< \brief ADC signal: AIN17 on PA09 mux B */ 576 #define MUX_PA09B_ADC_AIN17 _L_(1) 577 #define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) 578 #define PORT_PA09B_ADC_AIN17 (_UL_(1) << 9) 579 #define PIN_PA10B_ADC_AIN18 _L_(10) /**< \brief ADC signal: AIN18 on PA10 mux B */ 580 #define MUX_PA10B_ADC_AIN18 _L_(1) 581 #define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) 582 #define PORT_PA10B_ADC_AIN18 (_UL_(1) << 10) 583 #define PIN_PA11B_ADC_AIN19 _L_(11) /**< \brief ADC signal: AIN19 on PA11 mux B */ 584 #define MUX_PA11B_ADC_AIN19 _L_(1) 585 #define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) 586 #define PORT_PA11B_ADC_AIN19 (_UL_(1) << 11) 587 #define PIN_PA04B_ADC_VREFP _L_(4) /**< \brief ADC signal: VREFP on PA04 mux B */ 588 #define MUX_PA04B_ADC_VREFP _L_(1) 589 #define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP) 590 #define PORT_PA04B_ADC_VREFP (_UL_(1) << 4) 591 /* ========== PORT definition for AC peripheral ========== */ 592 #define PIN_PA04B_AC_AIN0 _L_(4) /**< \brief AC signal: AIN0 on PA04 mux B */ 593 #define MUX_PA04B_AC_AIN0 _L_(1) 594 #define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) 595 #define PORT_PA04B_AC_AIN0 (_UL_(1) << 4) 596 #define PIN_PA05B_AC_AIN1 _L_(5) /**< \brief AC signal: AIN1 on PA05 mux B */ 597 #define MUX_PA05B_AC_AIN1 _L_(1) 598 #define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) 599 #define PORT_PA05B_AC_AIN1 (_UL_(1) << 5) 600 #define PIN_PA06B_AC_AIN2 _L_(6) /**< \brief AC signal: AIN2 on PA06 mux B */ 601 #define MUX_PA06B_AC_AIN2 _L_(1) 602 #define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) 603 #define PORT_PA06B_AC_AIN2 (_UL_(1) << 6) 604 #define PIN_PA07B_AC_AIN3 _L_(7) /**< \brief AC signal: AIN3 on PA07 mux B */ 605 #define MUX_PA07B_AC_AIN3 _L_(1) 606 #define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) 607 #define PORT_PA07B_AC_AIN3 (_UL_(1) << 7) 608 #define PIN_PA18H_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux H */ 609 #define MUX_PA18H_AC_CMP0 _L_(7) 610 #define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) 611 #define PORT_PA18H_AC_CMP0 (_UL_(1) << 18) 612 #define PIN_PA19H_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux H */ 613 #define MUX_PA19H_AC_CMP1 _L_(7) 614 #define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) 615 #define PORT_PA19H_AC_CMP1 (_UL_(1) << 19) 616 /* ========== PORT definition for DAC peripheral ========== */ 617 #define PIN_PA02B_DAC_VOUT _L_(2) /**< \brief DAC signal: VOUT on PA02 mux B */ 618 #define MUX_PA02B_DAC_VOUT _L_(1) 619 #define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT) 620 #define PORT_PA02B_DAC_VOUT (_UL_(1) << 2) 621 #define PIN_PA03B_DAC_VREFP _L_(3) /**< \brief DAC signal: VREFP on PA03 mux B */ 622 #define MUX_PA03B_DAC_VREFP _L_(1) 623 #define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP) 624 #define PORT_PA03B_DAC_VREFP (_UL_(1) << 3) 625 /* ========== PORT definition for I2S peripheral ========== */ 626 #define PIN_PA11G_I2S_FS0 _L_(11) /**< \brief I2S signal: FS0 on PA11 mux G */ 627 #define MUX_PA11G_I2S_FS0 _L_(6) 628 #define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0) 629 #define PORT_PA11G_I2S_FS0 (_UL_(1) << 11) 630 #define PIN_PA09G_I2S_MCK0 _L_(9) /**< \brief I2S signal: MCK0 on PA09 mux G */ 631 #define MUX_PA09G_I2S_MCK0 _L_(6) 632 #define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0) 633 #define PORT_PA09G_I2S_MCK0 (_UL_(1) << 9) 634 #define PIN_PA10G_I2S_SCK0 _L_(10) /**< \brief I2S signal: SCK0 on PA10 mux G */ 635 #define MUX_PA10G_I2S_SCK0 _L_(6) 636 #define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0) 637 #define PORT_PA10G_I2S_SCK0 (_UL_(1) << 10) 638 #define PIN_PA07G_I2S_SD0 _L_(7) /**< \brief I2S signal: SD0 on PA07 mux G */ 639 #define MUX_PA07G_I2S_SD0 _L_(6) 640 #define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0) 641 #define PORT_PA07G_I2S_SD0 (_UL_(1) << 7) 642 #define PIN_PA19G_I2S_SD0 _L_(19) /**< \brief I2S signal: SD0 on PA19 mux G */ 643 #define MUX_PA19G_I2S_SD0 _L_(6) 644 #define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0) 645 #define PORT_PA19G_I2S_SD0 (_UL_(1) << 19) 646 #define PIN_PA08G_I2S_SD1 _L_(8) /**< \brief I2S signal: SD1 on PA08 mux G */ 647 #define MUX_PA08G_I2S_SD1 _L_(6) 648 #define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1) 649 #define PORT_PA08G_I2S_SD1 (_UL_(1) << 8) 650 651 #endif /* _SAMD21E16A_PIO_ */ 652
