1 /** 2 * \file 3 * 4 * \brief Peripheral I/O description for SAMD20J14 5 * 6 * Copyright (c) 2017 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAMD20J14_PIO_ 31 #define _SAMD20J14_PIO_ 32 33 #define PIN_PA00 0 /**< \brief Pin Number for PA00 */ 34 #define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */ 35 #define PIN_PA01 1 /**< \brief Pin Number for PA01 */ 36 #define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */ 37 #define PIN_PA02 2 /**< \brief Pin Number for PA02 */ 38 #define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */ 39 #define PIN_PA03 3 /**< \brief Pin Number for PA03 */ 40 #define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */ 41 #define PIN_PA04 4 /**< \brief Pin Number for PA04 */ 42 #define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */ 43 #define PIN_PA05 5 /**< \brief Pin Number for PA05 */ 44 #define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */ 45 #define PIN_PA06 6 /**< \brief Pin Number for PA06 */ 46 #define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */ 47 #define PIN_PA07 7 /**< \brief Pin Number for PA07 */ 48 #define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */ 49 #define PIN_PA08 8 /**< \brief Pin Number for PA08 */ 50 #define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */ 51 #define PIN_PA09 9 /**< \brief Pin Number for PA09 */ 52 #define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */ 53 #define PIN_PA10 10 /**< \brief Pin Number for PA10 */ 54 #define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */ 55 #define PIN_PA11 11 /**< \brief Pin Number for PA11 */ 56 #define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */ 57 #define PIN_PA12 12 /**< \brief Pin Number for PA12 */ 58 #define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */ 59 #define PIN_PA13 13 /**< \brief Pin Number for PA13 */ 60 #define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */ 61 #define PIN_PA14 14 /**< \brief Pin Number for PA14 */ 62 #define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */ 63 #define PIN_PA15 15 /**< \brief Pin Number for PA15 */ 64 #define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */ 65 #define PIN_PA16 16 /**< \brief Pin Number for PA16 */ 66 #define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */ 67 #define PIN_PA17 17 /**< \brief Pin Number for PA17 */ 68 #define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */ 69 #define PIN_PA18 18 /**< \brief Pin Number for PA18 */ 70 #define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */ 71 #define PIN_PA19 19 /**< \brief Pin Number for PA19 */ 72 #define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */ 73 #define PIN_PA20 20 /**< \brief Pin Number for PA20 */ 74 #define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */ 75 #define PIN_PA21 21 /**< \brief Pin Number for PA21 */ 76 #define PORT_PA21 (_UL_(1) << 21) /**< \brief PORT Mask for PA21 */ 77 #define PIN_PA22 22 /**< \brief Pin Number for PA22 */ 78 #define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */ 79 #define PIN_PA23 23 /**< \brief Pin Number for PA23 */ 80 #define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */ 81 #define PIN_PA24 24 /**< \brief Pin Number for PA24 */ 82 #define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */ 83 #define PIN_PA25 25 /**< \brief Pin Number for PA25 */ 84 #define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */ 85 #define PIN_PA27 27 /**< \brief Pin Number for PA27 */ 86 #define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */ 87 #define PIN_PA28 28 /**< \brief Pin Number for PA28 */ 88 #define PORT_PA28 (_UL_(1) << 28) /**< \brief PORT Mask for PA28 */ 89 #define PIN_PA30 30 /**< \brief Pin Number for PA30 */ 90 #define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */ 91 #define PIN_PA31 31 /**< \brief Pin Number for PA31 */ 92 #define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */ 93 #define PIN_PB00 32 /**< \brief Pin Number for PB00 */ 94 #define PORT_PB00 (_UL_(1) << 0) /**< \brief PORT Mask for PB00 */ 95 #define PIN_PB01 33 /**< \brief Pin Number for PB01 */ 96 #define PORT_PB01 (_UL_(1) << 1) /**< \brief PORT Mask for PB01 */ 97 #define PIN_PB02 34 /**< \brief Pin Number for PB02 */ 98 #define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */ 99 #define PIN_PB03 35 /**< \brief Pin Number for PB03 */ 100 #define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */ 101 #define PIN_PB04 36 /**< \brief Pin Number for PB04 */ 102 #define PORT_PB04 (_UL_(1) << 4) /**< \brief PORT Mask for PB04 */ 103 #define PIN_PB05 37 /**< \brief Pin Number for PB05 */ 104 #define PORT_PB05 (_UL_(1) << 5) /**< \brief PORT Mask for PB05 */ 105 #define PIN_PB06 38 /**< \brief Pin Number for PB06 */ 106 #define PORT_PB06 (_UL_(1) << 6) /**< \brief PORT Mask for PB06 */ 107 #define PIN_PB07 39 /**< \brief Pin Number for PB07 */ 108 #define PORT_PB07 (_UL_(1) << 7) /**< \brief PORT Mask for PB07 */ 109 #define PIN_PB08 40 /**< \brief Pin Number for PB08 */ 110 #define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */ 111 #define PIN_PB09 41 /**< \brief Pin Number for PB09 */ 112 #define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */ 113 #define PIN_PB10 42 /**< \brief Pin Number for PB10 */ 114 #define PORT_PB10 (_UL_(1) << 10) /**< \brief PORT Mask for PB10 */ 115 #define PIN_PB11 43 /**< \brief Pin Number for PB11 */ 116 #define PORT_PB11 (_UL_(1) << 11) /**< \brief PORT Mask for PB11 */ 117 #define PIN_PB12 44 /**< \brief Pin Number for PB12 */ 118 #define PORT_PB12 (_UL_(1) << 12) /**< \brief PORT Mask for PB12 */ 119 #define PIN_PB13 45 /**< \brief Pin Number for PB13 */ 120 #define PORT_PB13 (_UL_(1) << 13) /**< \brief PORT Mask for PB13 */ 121 #define PIN_PB14 46 /**< \brief Pin Number for PB14 */ 122 #define PORT_PB14 (_UL_(1) << 14) /**< \brief PORT Mask for PB14 */ 123 #define PIN_PB15 47 /**< \brief Pin Number for PB15 */ 124 #define PORT_PB15 (_UL_(1) << 15) /**< \brief PORT Mask for PB15 */ 125 #define PIN_PB16 48 /**< \brief Pin Number for PB16 */ 126 #define PORT_PB16 (_UL_(1) << 16) /**< \brief PORT Mask for PB16 */ 127 #define PIN_PB17 49 /**< \brief Pin Number for PB17 */ 128 #define PORT_PB17 (_UL_(1) << 17) /**< \brief PORT Mask for PB17 */ 129 #define PIN_PB22 54 /**< \brief Pin Number for PB22 */ 130 #define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */ 131 #define PIN_PB23 55 /**< \brief Pin Number for PB23 */ 132 #define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */ 133 #define PIN_PB30 62 /**< \brief Pin Number for PB30 */ 134 #define PORT_PB30 (_UL_(1) << 30) /**< \brief PORT Mask for PB30 */ 135 #define PIN_PB31 63 /**< \brief Pin Number for PB31 */ 136 #define PORT_PB31 (_UL_(1) << 31) /**< \brief PORT Mask for PB31 */ 137 /* ========== PORT definition for GCLK peripheral ========== */ 138 #define PIN_PB14H_GCLK_IO0 _L_(46) /**< \brief GCLK signal: IO0 on PB14 mux H */ 139 #define MUX_PB14H_GCLK_IO0 _L_(7) 140 #define PINMUX_PB14H_GCLK_IO0 ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0) 141 #define PORT_PB14H_GCLK_IO0 (_UL_(1) << 14) 142 #define PIN_PB22H_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux H */ 143 #define MUX_PB22H_GCLK_IO0 _L_(7) 144 #define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0) 145 #define PORT_PB22H_GCLK_IO0 (_UL_(1) << 22) 146 #define PIN_PA14H_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux H */ 147 #define MUX_PA14H_GCLK_IO0 _L_(7) 148 #define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) 149 #define PORT_PA14H_GCLK_IO0 (_UL_(1) << 14) 150 #define PIN_PA27H_GCLK_IO0 _L_(27) /**< \brief GCLK signal: IO0 on PA27 mux H */ 151 #define MUX_PA27H_GCLK_IO0 _L_(7) 152 #define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) 153 #define PORT_PA27H_GCLK_IO0 (_UL_(1) << 27) 154 #define PIN_PA28H_GCLK_IO0 _L_(28) /**< \brief GCLK signal: IO0 on PA28 mux H */ 155 #define MUX_PA28H_GCLK_IO0 _L_(7) 156 #define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0) 157 #define PORT_PA28H_GCLK_IO0 (_UL_(1) << 28) 158 #define PIN_PA30H_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux H */ 159 #define MUX_PA30H_GCLK_IO0 _L_(7) 160 #define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) 161 #define PORT_PA30H_GCLK_IO0 (_UL_(1) << 30) 162 #define PIN_PB15H_GCLK_IO1 _L_(47) /**< \brief GCLK signal: IO1 on PB15 mux H */ 163 #define MUX_PB15H_GCLK_IO1 _L_(7) 164 #define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1) 165 #define PORT_PB15H_GCLK_IO1 (_UL_(1) << 15) 166 #define PIN_PB23H_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux H */ 167 #define MUX_PB23H_GCLK_IO1 _L_(7) 168 #define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1) 169 #define PORT_PB23H_GCLK_IO1 (_UL_(1) << 23) 170 #define PIN_PA15H_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux H */ 171 #define MUX_PA15H_GCLK_IO1 _L_(7) 172 #define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) 173 #define PORT_PA15H_GCLK_IO1 (_UL_(1) << 15) 174 #define PIN_PB16H_GCLK_IO2 _L_(48) /**< \brief GCLK signal: IO2 on PB16 mux H */ 175 #define MUX_PB16H_GCLK_IO2 _L_(7) 176 #define PINMUX_PB16H_GCLK_IO2 ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2) 177 #define PORT_PB16H_GCLK_IO2 (_UL_(1) << 16) 178 #define PIN_PA16H_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux H */ 179 #define MUX_PA16H_GCLK_IO2 _L_(7) 180 #define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) 181 #define PORT_PA16H_GCLK_IO2 (_UL_(1) << 16) 182 #define PIN_PA17H_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux H */ 183 #define MUX_PA17H_GCLK_IO3 _L_(7) 184 #define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) 185 #define PORT_PA17H_GCLK_IO3 (_UL_(1) << 17) 186 #define PIN_PB17H_GCLK_IO3 _L_(49) /**< \brief GCLK signal: IO3 on PB17 mux H */ 187 #define MUX_PB17H_GCLK_IO3 _L_(7) 188 #define PINMUX_PB17H_GCLK_IO3 ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3) 189 #define PORT_PB17H_GCLK_IO3 (_UL_(1) << 17) 190 #define PIN_PA10H_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux H */ 191 #define MUX_PA10H_GCLK_IO4 _L_(7) 192 #define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) 193 #define PORT_PA10H_GCLK_IO4 (_UL_(1) << 10) 194 #define PIN_PA20H_GCLK_IO4 _L_(20) /**< \brief GCLK signal: IO4 on PA20 mux H */ 195 #define MUX_PA20H_GCLK_IO4 _L_(7) 196 #define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4) 197 #define PORT_PA20H_GCLK_IO4 (_UL_(1) << 20) 198 #define PIN_PB10H_GCLK_IO4 _L_(42) /**< \brief GCLK signal: IO4 on PB10 mux H */ 199 #define MUX_PB10H_GCLK_IO4 _L_(7) 200 #define PINMUX_PB10H_GCLK_IO4 ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4) 201 #define PORT_PB10H_GCLK_IO4 (_UL_(1) << 10) 202 #define PIN_PA11H_GCLK_IO5 _L_(11) /**< \brief GCLK signal: IO5 on PA11 mux H */ 203 #define MUX_PA11H_GCLK_IO5 _L_(7) 204 #define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) 205 #define PORT_PA11H_GCLK_IO5 (_UL_(1) << 11) 206 #define PIN_PA21H_GCLK_IO5 _L_(21) /**< \brief GCLK signal: IO5 on PA21 mux H */ 207 #define MUX_PA21H_GCLK_IO5 _L_(7) 208 #define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5) 209 #define PORT_PA21H_GCLK_IO5 (_UL_(1) << 21) 210 #define PIN_PB11H_GCLK_IO5 _L_(43) /**< \brief GCLK signal: IO5 on PB11 mux H */ 211 #define MUX_PB11H_GCLK_IO5 _L_(7) 212 #define PINMUX_PB11H_GCLK_IO5 ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5) 213 #define PORT_PB11H_GCLK_IO5 (_UL_(1) << 11) 214 #define PIN_PA22H_GCLK_IO6 _L_(22) /**< \brief GCLK signal: IO6 on PA22 mux H */ 215 #define MUX_PA22H_GCLK_IO6 _L_(7) 216 #define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6) 217 #define PORT_PA22H_GCLK_IO6 (_UL_(1) << 22) 218 #define PIN_PB12H_GCLK_IO6 _L_(44) /**< \brief GCLK signal: IO6 on PB12 mux H */ 219 #define MUX_PB12H_GCLK_IO6 _L_(7) 220 #define PINMUX_PB12H_GCLK_IO6 ((PIN_PB12H_GCLK_IO6 << 16) | MUX_PB12H_GCLK_IO6) 221 #define PORT_PB12H_GCLK_IO6 (_UL_(1) << 12) 222 #define PIN_PA23H_GCLK_IO7 _L_(23) /**< \brief GCLK signal: IO7 on PA23 mux H */ 223 #define MUX_PA23H_GCLK_IO7 _L_(7) 224 #define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7) 225 #define PORT_PA23H_GCLK_IO7 (_UL_(1) << 23) 226 #define PIN_PB13H_GCLK_IO7 _L_(45) /**< \brief GCLK signal: IO7 on PB13 mux H */ 227 #define MUX_PB13H_GCLK_IO7 _L_(7) 228 #define PINMUX_PB13H_GCLK_IO7 ((PIN_PB13H_GCLK_IO7 << 16) | MUX_PB13H_GCLK_IO7) 229 #define PORT_PB13H_GCLK_IO7 (_UL_(1) << 13) 230 /* ========== PORT definition for EIC peripheral ========== */ 231 #define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */ 232 #define MUX_PA16A_EIC_EXTINT0 _L_(0) 233 #define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) 234 #define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16) 235 #define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ 236 #define PIN_PB00A_EIC_EXTINT0 _L_(32) /**< \brief EIC signal: EXTINT0 on PB00 mux A */ 237 #define MUX_PB00A_EIC_EXTINT0 _L_(0) 238 #define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) 239 #define PORT_PB00A_EIC_EXTINT0 (_UL_(1) << 0) 240 #define PIN_PB00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB00 External Interrupt Line */ 241 #define PIN_PB16A_EIC_EXTINT0 _L_(48) /**< \brief EIC signal: EXTINT0 on PB16 mux A */ 242 #define MUX_PB16A_EIC_EXTINT0 _L_(0) 243 #define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) 244 #define PORT_PB16A_EIC_EXTINT0 (_UL_(1) << 16) 245 #define PIN_PB16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB16 External Interrupt Line */ 246 #define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */ 247 #define MUX_PA00A_EIC_EXTINT0 _L_(0) 248 #define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) 249 #define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0) 250 #define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */ 251 #define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */ 252 #define MUX_PA17A_EIC_EXTINT1 _L_(0) 253 #define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) 254 #define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17) 255 #define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ 256 #define PIN_PB01A_EIC_EXTINT1 _L_(33) /**< \brief EIC signal: EXTINT1 on PB01 mux A */ 257 #define MUX_PB01A_EIC_EXTINT1 _L_(0) 258 #define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) 259 #define PORT_PB01A_EIC_EXTINT1 (_UL_(1) << 1) 260 #define PIN_PB01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB01 External Interrupt Line */ 261 #define PIN_PB17A_EIC_EXTINT1 _L_(49) /**< \brief EIC signal: EXTINT1 on PB17 mux A */ 262 #define MUX_PB17A_EIC_EXTINT1 _L_(0) 263 #define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) 264 #define PORT_PB17A_EIC_EXTINT1 (_UL_(1) << 17) 265 #define PIN_PB17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB17 External Interrupt Line */ 266 #define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */ 267 #define MUX_PA01A_EIC_EXTINT1 _L_(0) 268 #define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) 269 #define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1) 270 #define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */ 271 #define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */ 272 #define MUX_PA02A_EIC_EXTINT2 _L_(0) 273 #define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) 274 #define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2) 275 #define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */ 276 #define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */ 277 #define MUX_PA18A_EIC_EXTINT2 _L_(0) 278 #define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) 279 #define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18) 280 #define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ 281 #define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */ 282 #define MUX_PB02A_EIC_EXTINT2 _L_(0) 283 #define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) 284 #define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2) 285 #define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */ 286 #define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */ 287 #define MUX_PA03A_EIC_EXTINT3 _L_(0) 288 #define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) 289 #define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3) 290 #define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */ 291 #define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */ 292 #define MUX_PA19A_EIC_EXTINT3 _L_(0) 293 #define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) 294 #define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19) 295 #define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ 296 #define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */ 297 #define MUX_PB03A_EIC_EXTINT3 _L_(0) 298 #define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) 299 #define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3) 300 #define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */ 301 #define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */ 302 #define MUX_PA04A_EIC_EXTINT4 _L_(0) 303 #define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) 304 #define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4) 305 #define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */ 306 #define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */ 307 #define MUX_PA20A_EIC_EXTINT4 _L_(0) 308 #define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) 309 #define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20) 310 #define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */ 311 #define PIN_PB04A_EIC_EXTINT4 _L_(36) /**< \brief EIC signal: EXTINT4 on PB04 mux A */ 312 #define MUX_PB04A_EIC_EXTINT4 _L_(0) 313 #define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) 314 #define PORT_PB04A_EIC_EXTINT4 (_UL_(1) << 4) 315 #define PIN_PB04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB04 External Interrupt Line */ 316 #define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */ 317 #define MUX_PA05A_EIC_EXTINT5 _L_(0) 318 #define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) 319 #define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5) 320 #define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */ 321 #define PIN_PA21A_EIC_EXTINT5 _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */ 322 #define MUX_PA21A_EIC_EXTINT5 _L_(0) 323 #define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) 324 #define PORT_PA21A_EIC_EXTINT5 (_UL_(1) << 21) 325 #define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */ 326 #define PIN_PB05A_EIC_EXTINT5 _L_(37) /**< \brief EIC signal: EXTINT5 on PB05 mux A */ 327 #define MUX_PB05A_EIC_EXTINT5 _L_(0) 328 #define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) 329 #define PORT_PB05A_EIC_EXTINT5 (_UL_(1) << 5) 330 #define PIN_PB05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB05 External Interrupt Line */ 331 #define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */ 332 #define MUX_PA06A_EIC_EXTINT6 _L_(0) 333 #define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) 334 #define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6) 335 #define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ 336 #define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */ 337 #define MUX_PA22A_EIC_EXTINT6 _L_(0) 338 #define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) 339 #define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22) 340 #define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */ 341 #define PIN_PB06A_EIC_EXTINT6 _L_(38) /**< \brief EIC signal: EXTINT6 on PB06 mux A */ 342 #define MUX_PB06A_EIC_EXTINT6 _L_(0) 343 #define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) 344 #define PORT_PB06A_EIC_EXTINT6 (_UL_(1) << 6) 345 #define PIN_PB06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB06 External Interrupt Line */ 346 #define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */ 347 #define MUX_PB22A_EIC_EXTINT6 _L_(0) 348 #define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) 349 #define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22) 350 #define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */ 351 #define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */ 352 #define MUX_PA07A_EIC_EXTINT7 _L_(0) 353 #define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) 354 #define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7) 355 #define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ 356 #define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */ 357 #define MUX_PA23A_EIC_EXTINT7 _L_(0) 358 #define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) 359 #define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23) 360 #define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */ 361 #define PIN_PB07A_EIC_EXTINT7 _L_(39) /**< \brief EIC signal: EXTINT7 on PB07 mux A */ 362 #define MUX_PB07A_EIC_EXTINT7 _L_(0) 363 #define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) 364 #define PORT_PB07A_EIC_EXTINT7 (_UL_(1) << 7) 365 #define PIN_PB07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB07 External Interrupt Line */ 366 #define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */ 367 #define MUX_PB23A_EIC_EXTINT7 _L_(0) 368 #define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) 369 #define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23) 370 #define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */ 371 #define PIN_PA28A_EIC_EXTINT8 _L_(28) /**< \brief EIC signal: EXTINT8 on PA28 mux A */ 372 #define MUX_PA28A_EIC_EXTINT8 _L_(0) 373 #define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8) 374 #define PORT_PA28A_EIC_EXTINT8 (_UL_(1) << 28) 375 #define PIN_PA28A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PA28 External Interrupt Line */ 376 #define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */ 377 #define MUX_PB08A_EIC_EXTINT8 _L_(0) 378 #define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) 379 #define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8) 380 #define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */ 381 #define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */ 382 #define MUX_PA09A_EIC_EXTINT9 _L_(0) 383 #define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) 384 #define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9) 385 #define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */ 386 #define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */ 387 #define MUX_PB09A_EIC_EXTINT9 _L_(0) 388 #define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) 389 #define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9) 390 #define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */ 391 #define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */ 392 #define MUX_PA10A_EIC_EXTINT10 _L_(0) 393 #define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) 394 #define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10) 395 #define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */ 396 #define PIN_PA30A_EIC_EXTINT10 _L_(30) /**< \brief EIC signal: EXTINT10 on PA30 mux A */ 397 #define MUX_PA30A_EIC_EXTINT10 _L_(0) 398 #define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) 399 #define PORT_PA30A_EIC_EXTINT10 (_UL_(1) << 30) 400 #define PIN_PA30A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */ 401 #define PIN_PB10A_EIC_EXTINT10 _L_(42) /**< \brief EIC signal: EXTINT10 on PB10 mux A */ 402 #define MUX_PB10A_EIC_EXTINT10 _L_(0) 403 #define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) 404 #define PORT_PB10A_EIC_EXTINT10 (_UL_(1) << 10) 405 #define PIN_PB10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PB10 External Interrupt Line */ 406 #define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */ 407 #define MUX_PA11A_EIC_EXTINT11 _L_(0) 408 #define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) 409 #define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11) 410 #define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */ 411 #define PIN_PA31A_EIC_EXTINT11 _L_(31) /**< \brief EIC signal: EXTINT11 on PA31 mux A */ 412 #define MUX_PA31A_EIC_EXTINT11 _L_(0) 413 #define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) 414 #define PORT_PA31A_EIC_EXTINT11 (_UL_(1) << 31) 415 #define PIN_PA31A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */ 416 #define PIN_PB11A_EIC_EXTINT11 _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */ 417 #define MUX_PB11A_EIC_EXTINT11 _L_(0) 418 #define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) 419 #define PORT_PB11A_EIC_EXTINT11 (_UL_(1) << 11) 420 #define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */ 421 #define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */ 422 #define MUX_PA12A_EIC_EXTINT12 _L_(0) 423 #define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) 424 #define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12) 425 #define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */ 426 #define PIN_PA24A_EIC_EXTINT12 _L_(24) /**< \brief EIC signal: EXTINT12 on PA24 mux A */ 427 #define MUX_PA24A_EIC_EXTINT12 _L_(0) 428 #define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) 429 #define PORT_PA24A_EIC_EXTINT12 (_UL_(1) << 24) 430 #define PIN_PA24A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */ 431 #define PIN_PB12A_EIC_EXTINT12 _L_(44) /**< \brief EIC signal: EXTINT12 on PB12 mux A */ 432 #define MUX_PB12A_EIC_EXTINT12 _L_(0) 433 #define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) 434 #define PORT_PB12A_EIC_EXTINT12 (_UL_(1) << 12) 435 #define PIN_PB12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PB12 External Interrupt Line */ 436 #define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */ 437 #define MUX_PA13A_EIC_EXTINT13 _L_(0) 438 #define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) 439 #define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13) 440 #define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */ 441 #define PIN_PA25A_EIC_EXTINT13 _L_(25) /**< \brief EIC signal: EXTINT13 on PA25 mux A */ 442 #define MUX_PA25A_EIC_EXTINT13 _L_(0) 443 #define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) 444 #define PORT_PA25A_EIC_EXTINT13 (_UL_(1) << 25) 445 #define PIN_PA25A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */ 446 #define PIN_PB13A_EIC_EXTINT13 _L_(45) /**< \brief EIC signal: EXTINT13 on PB13 mux A */ 447 #define MUX_PB13A_EIC_EXTINT13 _L_(0) 448 #define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) 449 #define PORT_PB13A_EIC_EXTINT13 (_UL_(1) << 13) 450 #define PIN_PB13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PB13 External Interrupt Line */ 451 #define PIN_PB14A_EIC_EXTINT14 _L_(46) /**< \brief EIC signal: EXTINT14 on PB14 mux A */ 452 #define MUX_PB14A_EIC_EXTINT14 _L_(0) 453 #define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) 454 #define PORT_PB14A_EIC_EXTINT14 (_UL_(1) << 14) 455 #define PIN_PB14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB14 External Interrupt Line */ 456 #define PIN_PB30A_EIC_EXTINT14 _L_(62) /**< \brief EIC signal: EXTINT14 on PB30 mux A */ 457 #define MUX_PB30A_EIC_EXTINT14 _L_(0) 458 #define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) 459 #define PORT_PB30A_EIC_EXTINT14 (_UL_(1) << 30) 460 #define PIN_PB30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB30 External Interrupt Line */ 461 #define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */ 462 #define MUX_PA14A_EIC_EXTINT14 _L_(0) 463 #define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) 464 #define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14) 465 #define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */ 466 #define PIN_PA27A_EIC_EXTINT15 _L_(27) /**< \brief EIC signal: EXTINT15 on PA27 mux A */ 467 #define MUX_PA27A_EIC_EXTINT15 _L_(0) 468 #define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) 469 #define PORT_PA27A_EIC_EXTINT15 (_UL_(1) << 27) 470 #define PIN_PA27A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */ 471 #define PIN_PB15A_EIC_EXTINT15 _L_(47) /**< \brief EIC signal: EXTINT15 on PB15 mux A */ 472 #define MUX_PB15A_EIC_EXTINT15 _L_(0) 473 #define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) 474 #define PORT_PB15A_EIC_EXTINT15 (_UL_(1) << 15) 475 #define PIN_PB15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB15 External Interrupt Line */ 476 #define PIN_PB31A_EIC_EXTINT15 _L_(63) /**< \brief EIC signal: EXTINT15 on PB31 mux A */ 477 #define MUX_PB31A_EIC_EXTINT15 _L_(0) 478 #define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) 479 #define PORT_PB31A_EIC_EXTINT15 (_UL_(1) << 31) 480 #define PIN_PB31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB31 External Interrupt Line */ 481 #define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */ 482 #define MUX_PA15A_EIC_EXTINT15 _L_(0) 483 #define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) 484 #define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15) 485 #define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */ 486 #define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */ 487 #define MUX_PA08A_EIC_NMI _L_(0) 488 #define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) 489 #define PORT_PA08A_EIC_NMI (_UL_(1) << 8) 490 /* ========== PORT definition for SERCOM0 peripheral ========== */ 491 #define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ 492 #define MUX_PA04D_SERCOM0_PAD0 _L_(3) 493 #define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) 494 #define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4) 495 #define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ 496 #define MUX_PA08C_SERCOM0_PAD0 _L_(2) 497 #define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) 498 #define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8) 499 #define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ 500 #define MUX_PA05D_SERCOM0_PAD1 _L_(3) 501 #define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) 502 #define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5) 503 #define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ 504 #define MUX_PA09C_SERCOM0_PAD1 _L_(2) 505 #define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) 506 #define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9) 507 #define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ 508 #define MUX_PA06D_SERCOM0_PAD2 _L_(3) 509 #define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) 510 #define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6) 511 #define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ 512 #define MUX_PA10C_SERCOM0_PAD2 _L_(2) 513 #define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) 514 #define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10) 515 #define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ 516 #define MUX_PA07D_SERCOM0_PAD3 _L_(3) 517 #define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) 518 #define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7) 519 #define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ 520 #define MUX_PA11C_SERCOM0_PAD3 _L_(2) 521 #define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) 522 #define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11) 523 /* ========== PORT definition for SERCOM1 peripheral ========== */ 524 #define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ 525 #define MUX_PA16C_SERCOM1_PAD0 _L_(2) 526 #define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) 527 #define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16) 528 #define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ 529 #define MUX_PA00D_SERCOM1_PAD0 _L_(3) 530 #define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) 531 #define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0) 532 #define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ 533 #define MUX_PA17C_SERCOM1_PAD1 _L_(2) 534 #define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) 535 #define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17) 536 #define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ 537 #define MUX_PA01D_SERCOM1_PAD1 _L_(3) 538 #define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) 539 #define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1) 540 #define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ 541 #define MUX_PA30D_SERCOM1_PAD2 _L_(3) 542 #define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) 543 #define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30) 544 #define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ 545 #define MUX_PA18C_SERCOM1_PAD2 _L_(2) 546 #define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) 547 #define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18) 548 #define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ 549 #define MUX_PA31D_SERCOM1_PAD3 _L_(3) 550 #define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) 551 #define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31) 552 #define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ 553 #define MUX_PA19C_SERCOM1_PAD3 _L_(2) 554 #define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) 555 #define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19) 556 /* ========== PORT definition for SERCOM2 peripheral ========== */ 557 #define PIN_PA08D_SERCOM2_PAD0 _L_(8) /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ 558 #define MUX_PA08D_SERCOM2_PAD0 _L_(3) 559 #define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) 560 #define PORT_PA08D_SERCOM2_PAD0 (_UL_(1) << 8) 561 #define PIN_PA12C_SERCOM2_PAD0 _L_(12) /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ 562 #define MUX_PA12C_SERCOM2_PAD0 _L_(2) 563 #define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) 564 #define PORT_PA12C_SERCOM2_PAD0 (_UL_(1) << 12) 565 #define PIN_PA09D_SERCOM2_PAD1 _L_(9) /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ 566 #define MUX_PA09D_SERCOM2_PAD1 _L_(3) 567 #define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) 568 #define PORT_PA09D_SERCOM2_PAD1 (_UL_(1) << 9) 569 #define PIN_PA13C_SERCOM2_PAD1 _L_(13) /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ 570 #define MUX_PA13C_SERCOM2_PAD1 _L_(2) 571 #define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) 572 #define PORT_PA13C_SERCOM2_PAD1 (_UL_(1) << 13) 573 #define PIN_PA10D_SERCOM2_PAD2 _L_(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ 574 #define MUX_PA10D_SERCOM2_PAD2 _L_(3) 575 #define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) 576 #define PORT_PA10D_SERCOM2_PAD2 (_UL_(1) << 10) 577 #define PIN_PA14C_SERCOM2_PAD2 _L_(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ 578 #define MUX_PA14C_SERCOM2_PAD2 _L_(2) 579 #define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) 580 #define PORT_PA14C_SERCOM2_PAD2 (_UL_(1) << 14) 581 #define PIN_PA11D_SERCOM2_PAD3 _L_(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ 582 #define MUX_PA11D_SERCOM2_PAD3 _L_(3) 583 #define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) 584 #define PORT_PA11D_SERCOM2_PAD3 (_UL_(1) << 11) 585 #define PIN_PA15C_SERCOM2_PAD3 _L_(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ 586 #define MUX_PA15C_SERCOM2_PAD3 _L_(2) 587 #define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) 588 #define PORT_PA15C_SERCOM2_PAD3 (_UL_(1) << 15) 589 /* ========== PORT definition for SERCOM3 peripheral ========== */ 590 #define PIN_PA16D_SERCOM3_PAD0 _L_(16) /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ 591 #define MUX_PA16D_SERCOM3_PAD0 _L_(3) 592 #define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) 593 #define PORT_PA16D_SERCOM3_PAD0 (_UL_(1) << 16) 594 #define PIN_PA22C_SERCOM3_PAD0 _L_(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ 595 #define MUX_PA22C_SERCOM3_PAD0 _L_(2) 596 #define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) 597 #define PORT_PA22C_SERCOM3_PAD0 (_UL_(1) << 22) 598 #define PIN_PA17D_SERCOM3_PAD1 _L_(17) /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ 599 #define MUX_PA17D_SERCOM3_PAD1 _L_(3) 600 #define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) 601 #define PORT_PA17D_SERCOM3_PAD1 (_UL_(1) << 17) 602 #define PIN_PA23C_SERCOM3_PAD1 _L_(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ 603 #define MUX_PA23C_SERCOM3_PAD1 _L_(2) 604 #define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) 605 #define PORT_PA23C_SERCOM3_PAD1 (_UL_(1) << 23) 606 #define PIN_PA18D_SERCOM3_PAD2 _L_(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ 607 #define MUX_PA18D_SERCOM3_PAD2 _L_(3) 608 #define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) 609 #define PORT_PA18D_SERCOM3_PAD2 (_UL_(1) << 18) 610 #define PIN_PA20D_SERCOM3_PAD2 _L_(20) /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ 611 #define MUX_PA20D_SERCOM3_PAD2 _L_(3) 612 #define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) 613 #define PORT_PA20D_SERCOM3_PAD2 (_UL_(1) << 20) 614 #define PIN_PA24C_SERCOM3_PAD2 _L_(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ 615 #define MUX_PA24C_SERCOM3_PAD2 _L_(2) 616 #define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) 617 #define PORT_PA24C_SERCOM3_PAD2 (_UL_(1) << 24) 618 #define PIN_PA19D_SERCOM3_PAD3 _L_(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ 619 #define MUX_PA19D_SERCOM3_PAD3 _L_(3) 620 #define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) 621 #define PORT_PA19D_SERCOM3_PAD3 (_UL_(1) << 19) 622 #define PIN_PA21D_SERCOM3_PAD3 _L_(21) /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ 623 #define MUX_PA21D_SERCOM3_PAD3 _L_(3) 624 #define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) 625 #define PORT_PA21D_SERCOM3_PAD3 (_UL_(1) << 21) 626 #define PIN_PA25C_SERCOM3_PAD3 _L_(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ 627 #define MUX_PA25C_SERCOM3_PAD3 _L_(2) 628 #define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) 629 #define PORT_PA25C_SERCOM3_PAD3 (_UL_(1) << 25) 630 /* ========== PORT definition for SERCOM4 peripheral ========== */ 631 #define PIN_PA12D_SERCOM4_PAD0 _L_(12) /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */ 632 #define MUX_PA12D_SERCOM4_PAD0 _L_(3) 633 #define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0) 634 #define PORT_PA12D_SERCOM4_PAD0 (_UL_(1) << 12) 635 #define PIN_PB08D_SERCOM4_PAD0 _L_(40) /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ 636 #define MUX_PB08D_SERCOM4_PAD0 _L_(3) 637 #define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) 638 #define PORT_PB08D_SERCOM4_PAD0 (_UL_(1) << 8) 639 #define PIN_PB12C_SERCOM4_PAD0 _L_(44) /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */ 640 #define MUX_PB12C_SERCOM4_PAD0 _L_(2) 641 #define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0) 642 #define PORT_PB12C_SERCOM4_PAD0 (_UL_(1) << 12) 643 #define PIN_PA13D_SERCOM4_PAD1 _L_(13) /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */ 644 #define MUX_PA13D_SERCOM4_PAD1 _L_(3) 645 #define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1) 646 #define PORT_PA13D_SERCOM4_PAD1 (_UL_(1) << 13) 647 #define PIN_PB09D_SERCOM4_PAD1 _L_(41) /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ 648 #define MUX_PB09D_SERCOM4_PAD1 _L_(3) 649 #define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) 650 #define PORT_PB09D_SERCOM4_PAD1 (_UL_(1) << 9) 651 #define PIN_PB13C_SERCOM4_PAD1 _L_(45) /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */ 652 #define MUX_PB13C_SERCOM4_PAD1 _L_(2) 653 #define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1) 654 #define PORT_PB13C_SERCOM4_PAD1 (_UL_(1) << 13) 655 #define PIN_PA14D_SERCOM4_PAD2 _L_(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ 656 #define MUX_PA14D_SERCOM4_PAD2 _L_(3) 657 #define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) 658 #define PORT_PA14D_SERCOM4_PAD2 (_UL_(1) << 14) 659 #define PIN_PB10D_SERCOM4_PAD2 _L_(42) /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ 660 #define MUX_PB10D_SERCOM4_PAD2 _L_(3) 661 #define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) 662 #define PORT_PB10D_SERCOM4_PAD2 (_UL_(1) << 10) 663 #define PIN_PB14C_SERCOM4_PAD2 _L_(46) /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */ 664 #define MUX_PB14C_SERCOM4_PAD2 _L_(2) 665 #define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) 666 #define PORT_PB14C_SERCOM4_PAD2 (_UL_(1) << 14) 667 #define PIN_PA15D_SERCOM4_PAD3 _L_(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ 668 #define MUX_PA15D_SERCOM4_PAD3 _L_(3) 669 #define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) 670 #define PORT_PA15D_SERCOM4_PAD3 (_UL_(1) << 15) 671 #define PIN_PB11D_SERCOM4_PAD3 _L_(43) /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ 672 #define MUX_PB11D_SERCOM4_PAD3 _L_(3) 673 #define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) 674 #define PORT_PB11D_SERCOM4_PAD3 (_UL_(1) << 11) 675 #define PIN_PB15C_SERCOM4_PAD3 _L_(47) /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */ 676 #define MUX_PB15C_SERCOM4_PAD3 _L_(2) 677 #define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) 678 #define PORT_PB15C_SERCOM4_PAD3 (_UL_(1) << 15) 679 /* ========== PORT definition for SERCOM5 peripheral ========== */ 680 #define PIN_PA22D_SERCOM5_PAD0 _L_(22) /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */ 681 #define MUX_PA22D_SERCOM5_PAD0 _L_(3) 682 #define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0) 683 #define PORT_PA22D_SERCOM5_PAD0 (_UL_(1) << 22) 684 #define PIN_PB02D_SERCOM5_PAD0 _L_(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ 685 #define MUX_PB02D_SERCOM5_PAD0 _L_(3) 686 #define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) 687 #define PORT_PB02D_SERCOM5_PAD0 (_UL_(1) << 2) 688 #define PIN_PB30D_SERCOM5_PAD0 _L_(62) /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */ 689 #define MUX_PB30D_SERCOM5_PAD0 _L_(3) 690 #define PINMUX_PB30D_SERCOM5_PAD0 ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0) 691 #define PORT_PB30D_SERCOM5_PAD0 (_UL_(1) << 30) 692 #define PIN_PB16C_SERCOM5_PAD0 _L_(48) /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ 693 #define MUX_PB16C_SERCOM5_PAD0 _L_(2) 694 #define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) 695 #define PORT_PB16C_SERCOM5_PAD0 (_UL_(1) << 16) 696 #define PIN_PA23D_SERCOM5_PAD1 _L_(23) /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */ 697 #define MUX_PA23D_SERCOM5_PAD1 _L_(3) 698 #define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1) 699 #define PORT_PA23D_SERCOM5_PAD1 (_UL_(1) << 23) 700 #define PIN_PB03D_SERCOM5_PAD1 _L_(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ 701 #define MUX_PB03D_SERCOM5_PAD1 _L_(3) 702 #define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) 703 #define PORT_PB03D_SERCOM5_PAD1 (_UL_(1) << 3) 704 #define PIN_PB31D_SERCOM5_PAD1 _L_(63) /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */ 705 #define MUX_PB31D_SERCOM5_PAD1 _L_(3) 706 #define PINMUX_PB31D_SERCOM5_PAD1 ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1) 707 #define PORT_PB31D_SERCOM5_PAD1 (_UL_(1) << 31) 708 #define PIN_PB17C_SERCOM5_PAD1 _L_(49) /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ 709 #define MUX_PB17C_SERCOM5_PAD1 _L_(2) 710 #define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) 711 #define PORT_PB17C_SERCOM5_PAD1 (_UL_(1) << 17) 712 #define PIN_PA24D_SERCOM5_PAD2 _L_(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ 713 #define MUX_PA24D_SERCOM5_PAD2 _L_(3) 714 #define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) 715 #define PORT_PA24D_SERCOM5_PAD2 (_UL_(1) << 24) 716 #define PIN_PB00D_SERCOM5_PAD2 _L_(32) /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ 717 #define MUX_PB00D_SERCOM5_PAD2 _L_(3) 718 #define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) 719 #define PORT_PB00D_SERCOM5_PAD2 (_UL_(1) << 0) 720 #define PIN_PB22D_SERCOM5_PAD2 _L_(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ 721 #define MUX_PB22D_SERCOM5_PAD2 _L_(3) 722 #define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) 723 #define PORT_PB22D_SERCOM5_PAD2 (_UL_(1) << 22) 724 #define PIN_PA20C_SERCOM5_PAD2 _L_(20) /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ 725 #define MUX_PA20C_SERCOM5_PAD2 _L_(2) 726 #define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) 727 #define PORT_PA20C_SERCOM5_PAD2 (_UL_(1) << 20) 728 #define PIN_PA25D_SERCOM5_PAD3 _L_(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ 729 #define MUX_PA25D_SERCOM5_PAD3 _L_(3) 730 #define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) 731 #define PORT_PA25D_SERCOM5_PAD3 (_UL_(1) << 25) 732 #define PIN_PB01D_SERCOM5_PAD3 _L_(33) /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */ 733 #define MUX_PB01D_SERCOM5_PAD3 _L_(3) 734 #define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) 735 #define PORT_PB01D_SERCOM5_PAD3 (_UL_(1) << 1) 736 #define PIN_PB23D_SERCOM5_PAD3 _L_(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ 737 #define MUX_PB23D_SERCOM5_PAD3 _L_(3) 738 #define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) 739 #define PORT_PB23D_SERCOM5_PAD3 (_UL_(1) << 23) 740 #define PIN_PA21C_SERCOM5_PAD3 _L_(21) /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ 741 #define MUX_PA21C_SERCOM5_PAD3 _L_(2) 742 #define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) 743 #define PORT_PA21C_SERCOM5_PAD3 (_UL_(1) << 21) 744 /* ========== PORT definition for TC0 peripheral ========== */ 745 #define PIN_PA04F_TC0_WO0 _L_(4) /**< \brief TC0 signal: WO0 on PA04 mux F */ 746 #define MUX_PA04F_TC0_WO0 _L_(5) 747 #define PINMUX_PA04F_TC0_WO0 ((PIN_PA04F_TC0_WO0 << 16) | MUX_PA04F_TC0_WO0) 748 #define PORT_PA04F_TC0_WO0 (_UL_(1) << 4) 749 #define PIN_PB30F_TC0_WO0 _L_(62) /**< \brief TC0 signal: WO0 on PB30 mux F */ 750 #define MUX_PB30F_TC0_WO0 _L_(5) 751 #define PINMUX_PB30F_TC0_WO0 ((PIN_PB30F_TC0_WO0 << 16) | MUX_PB30F_TC0_WO0) 752 #define PORT_PB30F_TC0_WO0 (_UL_(1) << 30) 753 #define PIN_PA08E_TC0_WO0 _L_(8) /**< \brief TC0 signal: WO0 on PA08 mux E */ 754 #define MUX_PA08E_TC0_WO0 _L_(4) 755 #define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0) 756 #define PORT_PA08E_TC0_WO0 (_UL_(1) << 8) 757 #define PIN_PA05F_TC0_WO1 _L_(5) /**< \brief TC0 signal: WO1 on PA05 mux F */ 758 #define MUX_PA05F_TC0_WO1 _L_(5) 759 #define PINMUX_PA05F_TC0_WO1 ((PIN_PA05F_TC0_WO1 << 16) | MUX_PA05F_TC0_WO1) 760 #define PORT_PA05F_TC0_WO1 (_UL_(1) << 5) 761 #define PIN_PB31F_TC0_WO1 _L_(63) /**< \brief TC0 signal: WO1 on PB31 mux F */ 762 #define MUX_PB31F_TC0_WO1 _L_(5) 763 #define PINMUX_PB31F_TC0_WO1 ((PIN_PB31F_TC0_WO1 << 16) | MUX_PB31F_TC0_WO1) 764 #define PORT_PB31F_TC0_WO1 (_UL_(1) << 31) 765 #define PIN_PA09E_TC0_WO1 _L_(9) /**< \brief TC0 signal: WO1 on PA09 mux E */ 766 #define MUX_PA09E_TC0_WO1 _L_(4) 767 #define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1) 768 #define PORT_PA09E_TC0_WO1 (_UL_(1) << 9) 769 /* ========== PORT definition for TC1 peripheral ========== */ 770 #define PIN_PA06F_TC1_WO0 _L_(6) /**< \brief TC1 signal: WO0 on PA06 mux F */ 771 #define MUX_PA06F_TC1_WO0 _L_(5) 772 #define PINMUX_PA06F_TC1_WO0 ((PIN_PA06F_TC1_WO0 << 16) | MUX_PA06F_TC1_WO0) 773 #define PORT_PA06F_TC1_WO0 (_UL_(1) << 6) 774 #define PIN_PA30F_TC1_WO0 _L_(30) /**< \brief TC1 signal: WO0 on PA30 mux F */ 775 #define MUX_PA30F_TC1_WO0 _L_(5) 776 #define PINMUX_PA30F_TC1_WO0 ((PIN_PA30F_TC1_WO0 << 16) | MUX_PA30F_TC1_WO0) 777 #define PORT_PA30F_TC1_WO0 (_UL_(1) << 30) 778 #define PIN_PA10E_TC1_WO0 _L_(10) /**< \brief TC1 signal: WO0 on PA10 mux E */ 779 #define MUX_PA10E_TC1_WO0 _L_(4) 780 #define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0) 781 #define PORT_PA10E_TC1_WO0 (_UL_(1) << 10) 782 #define PIN_PA07F_TC1_WO1 _L_(7) /**< \brief TC1 signal: WO1 on PA07 mux F */ 783 #define MUX_PA07F_TC1_WO1 _L_(5) 784 #define PINMUX_PA07F_TC1_WO1 ((PIN_PA07F_TC1_WO1 << 16) | MUX_PA07F_TC1_WO1) 785 #define PORT_PA07F_TC1_WO1 (_UL_(1) << 7) 786 #define PIN_PA31F_TC1_WO1 _L_(31) /**< \brief TC1 signal: WO1 on PA31 mux F */ 787 #define MUX_PA31F_TC1_WO1 _L_(5) 788 #define PINMUX_PA31F_TC1_WO1 ((PIN_PA31F_TC1_WO1 << 16) | MUX_PA31F_TC1_WO1) 789 #define PORT_PA31F_TC1_WO1 (_UL_(1) << 31) 790 #define PIN_PA11E_TC1_WO1 _L_(11) /**< \brief TC1 signal: WO1 on PA11 mux E */ 791 #define MUX_PA11E_TC1_WO1 _L_(4) 792 #define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1) 793 #define PORT_PA11E_TC1_WO1 (_UL_(1) << 11) 794 /* ========== PORT definition for TC2 peripheral ========== */ 795 #define PIN_PA16F_TC2_WO0 _L_(16) /**< \brief TC2 signal: WO0 on PA16 mux F */ 796 #define MUX_PA16F_TC2_WO0 _L_(5) 797 #define PINMUX_PA16F_TC2_WO0 ((PIN_PA16F_TC2_WO0 << 16) | MUX_PA16F_TC2_WO0) 798 #define PORT_PA16F_TC2_WO0 (_UL_(1) << 16) 799 #define PIN_PA12E_TC2_WO0 _L_(12) /**< \brief TC2 signal: WO0 on PA12 mux E */ 800 #define MUX_PA12E_TC2_WO0 _L_(4) 801 #define PINMUX_PA12E_TC2_WO0 ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0) 802 #define PORT_PA12E_TC2_WO0 (_UL_(1) << 12) 803 #define PIN_PA00F_TC2_WO0 _L_(0) /**< \brief TC2 signal: WO0 on PA00 mux F */ 804 #define MUX_PA00F_TC2_WO0 _L_(5) 805 #define PINMUX_PA00F_TC2_WO0 ((PIN_PA00F_TC2_WO0 << 16) | MUX_PA00F_TC2_WO0) 806 #define PORT_PA00F_TC2_WO0 (_UL_(1) << 0) 807 #define PIN_PA17F_TC2_WO1 _L_(17) /**< \brief TC2 signal: WO1 on PA17 mux F */ 808 #define MUX_PA17F_TC2_WO1 _L_(5) 809 #define PINMUX_PA17F_TC2_WO1 ((PIN_PA17F_TC2_WO1 << 16) | MUX_PA17F_TC2_WO1) 810 #define PORT_PA17F_TC2_WO1 (_UL_(1) << 17) 811 #define PIN_PA13E_TC2_WO1 _L_(13) /**< \brief TC2 signal: WO1 on PA13 mux E */ 812 #define MUX_PA13E_TC2_WO1 _L_(4) 813 #define PINMUX_PA13E_TC2_WO1 ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1) 814 #define PORT_PA13E_TC2_WO1 (_UL_(1) << 13) 815 #define PIN_PA01F_TC2_WO1 _L_(1) /**< \brief TC2 signal: WO1 on PA01 mux F */ 816 #define MUX_PA01F_TC2_WO1 _L_(5) 817 #define PINMUX_PA01F_TC2_WO1 ((PIN_PA01F_TC2_WO1 << 16) | MUX_PA01F_TC2_WO1) 818 #define PORT_PA01F_TC2_WO1 (_UL_(1) << 1) 819 /* ========== PORT definition for TC3 peripheral ========== */ 820 #define PIN_PA18F_TC3_WO0 _L_(18) /**< \brief TC3 signal: WO0 on PA18 mux F */ 821 #define MUX_PA18F_TC3_WO0 _L_(5) 822 #define PINMUX_PA18F_TC3_WO0 ((PIN_PA18F_TC3_WO0 << 16) | MUX_PA18F_TC3_WO0) 823 #define PORT_PA18F_TC3_WO0 (_UL_(1) << 18) 824 #define PIN_PA14E_TC3_WO0 _L_(14) /**< \brief TC3 signal: WO0 on PA14 mux E */ 825 #define MUX_PA14E_TC3_WO0 _L_(4) 826 #define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) 827 #define PORT_PA14E_TC3_WO0 (_UL_(1) << 14) 828 #define PIN_PA19F_TC3_WO1 _L_(19) /**< \brief TC3 signal: WO1 on PA19 mux F */ 829 #define MUX_PA19F_TC3_WO1 _L_(5) 830 #define PINMUX_PA19F_TC3_WO1 ((PIN_PA19F_TC3_WO1 << 16) | MUX_PA19F_TC3_WO1) 831 #define PORT_PA19F_TC3_WO1 (_UL_(1) << 19) 832 #define PIN_PA15E_TC3_WO1 _L_(15) /**< \brief TC3 signal: WO1 on PA15 mux E */ 833 #define MUX_PA15E_TC3_WO1 _L_(4) 834 #define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) 835 #define PORT_PA15E_TC3_WO1 (_UL_(1) << 15) 836 /* ========== PORT definition for TC4 peripheral ========== */ 837 #define PIN_PA22F_TC4_WO0 _L_(22) /**< \brief TC4 signal: WO0 on PA22 mux F */ 838 #define MUX_PA22F_TC4_WO0 _L_(5) 839 #define PINMUX_PA22F_TC4_WO0 ((PIN_PA22F_TC4_WO0 << 16) | MUX_PA22F_TC4_WO0) 840 #define PORT_PA22F_TC4_WO0 (_UL_(1) << 22) 841 #define PIN_PB08F_TC4_WO0 _L_(40) /**< \brief TC4 signal: WO0 on PB08 mux F */ 842 #define MUX_PB08F_TC4_WO0 _L_(5) 843 #define PINMUX_PB08F_TC4_WO0 ((PIN_PB08F_TC4_WO0 << 16) | MUX_PB08F_TC4_WO0) 844 #define PORT_PB08F_TC4_WO0 (_UL_(1) << 8) 845 #define PIN_PB12E_TC4_WO0 _L_(44) /**< \brief TC4 signal: WO0 on PB12 mux E */ 846 #define MUX_PB12E_TC4_WO0 _L_(4) 847 #define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0) 848 #define PORT_PB12E_TC4_WO0 (_UL_(1) << 12) 849 #define PIN_PA23F_TC4_WO1 _L_(23) /**< \brief TC4 signal: WO1 on PA23 mux F */ 850 #define MUX_PA23F_TC4_WO1 _L_(5) 851 #define PINMUX_PA23F_TC4_WO1 ((PIN_PA23F_TC4_WO1 << 16) | MUX_PA23F_TC4_WO1) 852 #define PORT_PA23F_TC4_WO1 (_UL_(1) << 23) 853 #define PIN_PB09F_TC4_WO1 _L_(41) /**< \brief TC4 signal: WO1 on PB09 mux F */ 854 #define MUX_PB09F_TC4_WO1 _L_(5) 855 #define PINMUX_PB09F_TC4_WO1 ((PIN_PB09F_TC4_WO1 << 16) | MUX_PB09F_TC4_WO1) 856 #define PORT_PB09F_TC4_WO1 (_UL_(1) << 9) 857 #define PIN_PB13E_TC4_WO1 _L_(45) /**< \brief TC4 signal: WO1 on PB13 mux E */ 858 #define MUX_PB13E_TC4_WO1 _L_(4) 859 #define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1) 860 #define PORT_PB13E_TC4_WO1 (_UL_(1) << 13) 861 /* ========== PORT definition for TC5 peripheral ========== */ 862 #define PIN_PA24F_TC5_WO0 _L_(24) /**< \brief TC5 signal: WO0 on PA24 mux F */ 863 #define MUX_PA24F_TC5_WO0 _L_(5) 864 #define PINMUX_PA24F_TC5_WO0 ((PIN_PA24F_TC5_WO0 << 16) | MUX_PA24F_TC5_WO0) 865 #define PORT_PA24F_TC5_WO0 (_UL_(1) << 24) 866 #define PIN_PB10F_TC5_WO0 _L_(42) /**< \brief TC5 signal: WO0 on PB10 mux F */ 867 #define MUX_PB10F_TC5_WO0 _L_(5) 868 #define PINMUX_PB10F_TC5_WO0 ((PIN_PB10F_TC5_WO0 << 16) | MUX_PB10F_TC5_WO0) 869 #define PORT_PB10F_TC5_WO0 (_UL_(1) << 10) 870 #define PIN_PB14E_TC5_WO0 _L_(46) /**< \brief TC5 signal: WO0 on PB14 mux E */ 871 #define MUX_PB14E_TC5_WO0 _L_(4) 872 #define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0) 873 #define PORT_PB14E_TC5_WO0 (_UL_(1) << 14) 874 #define PIN_PA25F_TC5_WO1 _L_(25) /**< \brief TC5 signal: WO1 on PA25 mux F */ 875 #define MUX_PA25F_TC5_WO1 _L_(5) 876 #define PINMUX_PA25F_TC5_WO1 ((PIN_PA25F_TC5_WO1 << 16) | MUX_PA25F_TC5_WO1) 877 #define PORT_PA25F_TC5_WO1 (_UL_(1) << 25) 878 #define PIN_PB11F_TC5_WO1 _L_(43) /**< \brief TC5 signal: WO1 on PB11 mux F */ 879 #define MUX_PB11F_TC5_WO1 _L_(5) 880 #define PINMUX_PB11F_TC5_WO1 ((PIN_PB11F_TC5_WO1 << 16) | MUX_PB11F_TC5_WO1) 881 #define PORT_PB11F_TC5_WO1 (_UL_(1) << 11) 882 #define PIN_PB15E_TC5_WO1 _L_(47) /**< \brief TC5 signal: WO1 on PB15 mux E */ 883 #define MUX_PB15E_TC5_WO1 _L_(4) 884 #define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1) 885 #define PORT_PB15E_TC5_WO1 (_UL_(1) << 15) 886 /* ========== PORT definition for TC6 peripheral ========== */ 887 #define PIN_PB02F_TC6_WO0 _L_(34) /**< \brief TC6 signal: WO0 on PB02 mux F */ 888 #define MUX_PB02F_TC6_WO0 _L_(5) 889 #define PINMUX_PB02F_TC6_WO0 ((PIN_PB02F_TC6_WO0 << 16) | MUX_PB02F_TC6_WO0) 890 #define PORT_PB02F_TC6_WO0 (_UL_(1) << 2) 891 #define PIN_PB16E_TC6_WO0 _L_(48) /**< \brief TC6 signal: WO0 on PB16 mux E */ 892 #define MUX_PB16E_TC6_WO0 _L_(4) 893 #define PINMUX_PB16E_TC6_WO0 ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0) 894 #define PORT_PB16E_TC6_WO0 (_UL_(1) << 16) 895 #define PIN_PB03F_TC6_WO1 _L_(35) /**< \brief TC6 signal: WO1 on PB03 mux F */ 896 #define MUX_PB03F_TC6_WO1 _L_(5) 897 #define PINMUX_PB03F_TC6_WO1 ((PIN_PB03F_TC6_WO1 << 16) | MUX_PB03F_TC6_WO1) 898 #define PORT_PB03F_TC6_WO1 (_UL_(1) << 3) 899 #define PIN_PB17E_TC6_WO1 _L_(49) /**< \brief TC6 signal: WO1 on PB17 mux E */ 900 #define MUX_PB17E_TC6_WO1 _L_(4) 901 #define PINMUX_PB17E_TC6_WO1 ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1) 902 #define PORT_PB17E_TC6_WO1 (_UL_(1) << 17) 903 /* ========== PORT definition for TC7 peripheral ========== */ 904 #define PIN_PB00F_TC7_WO0 _L_(32) /**< \brief TC7 signal: WO0 on PB00 mux F */ 905 #define MUX_PB00F_TC7_WO0 _L_(5) 906 #define PINMUX_PB00F_TC7_WO0 ((PIN_PB00F_TC7_WO0 << 16) | MUX_PB00F_TC7_WO0) 907 #define PORT_PB00F_TC7_WO0 (_UL_(1) << 0) 908 #define PIN_PB22F_TC7_WO0 _L_(54) /**< \brief TC7 signal: WO0 on PB22 mux F */ 909 #define MUX_PB22F_TC7_WO0 _L_(5) 910 #define PINMUX_PB22F_TC7_WO0 ((PIN_PB22F_TC7_WO0 << 16) | MUX_PB22F_TC7_WO0) 911 #define PORT_PB22F_TC7_WO0 (_UL_(1) << 22) 912 #define PIN_PA20E_TC7_WO0 _L_(20) /**< \brief TC7 signal: WO0 on PA20 mux E */ 913 #define MUX_PA20E_TC7_WO0 _L_(4) 914 #define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0) 915 #define PORT_PA20E_TC7_WO0 (_UL_(1) << 20) 916 #define PIN_PB01F_TC7_WO1 _L_(33) /**< \brief TC7 signal: WO1 on PB01 mux F */ 917 #define MUX_PB01F_TC7_WO1 _L_(5) 918 #define PINMUX_PB01F_TC7_WO1 ((PIN_PB01F_TC7_WO1 << 16) | MUX_PB01F_TC7_WO1) 919 #define PORT_PB01F_TC7_WO1 (_UL_(1) << 1) 920 #define PIN_PB23F_TC7_WO1 _L_(55) /**< \brief TC7 signal: WO1 on PB23 mux F */ 921 #define MUX_PB23F_TC7_WO1 _L_(5) 922 #define PINMUX_PB23F_TC7_WO1 ((PIN_PB23F_TC7_WO1 << 16) | MUX_PB23F_TC7_WO1) 923 #define PORT_PB23F_TC7_WO1 (_UL_(1) << 23) 924 #define PIN_PA21E_TC7_WO1 _L_(21) /**< \brief TC7 signal: WO1 on PA21 mux E */ 925 #define MUX_PA21E_TC7_WO1 _L_(4) 926 #define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1) 927 #define PORT_PA21E_TC7_WO1 (_UL_(1) << 21) 928 /* ========== PORT definition for ADC peripheral ========== */ 929 #define PIN_PA02B_ADC_AIN0 _L_(2) /**< \brief ADC signal: AIN0 on PA02 mux B */ 930 #define MUX_PA02B_ADC_AIN0 _L_(1) 931 #define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) 932 #define PORT_PA02B_ADC_AIN0 (_UL_(1) << 2) 933 #define PIN_PA03B_ADC_AIN1 _L_(3) /**< \brief ADC signal: AIN1 on PA03 mux B */ 934 #define MUX_PA03B_ADC_AIN1 _L_(1) 935 #define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) 936 #define PORT_PA03B_ADC_AIN1 (_UL_(1) << 3) 937 #define PIN_PB08B_ADC_AIN2 _L_(40) /**< \brief ADC signal: AIN2 on PB08 mux B */ 938 #define MUX_PB08B_ADC_AIN2 _L_(1) 939 #define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2) 940 #define PORT_PB08B_ADC_AIN2 (_UL_(1) << 8) 941 #define PIN_PB09B_ADC_AIN3 _L_(41) /**< \brief ADC signal: AIN3 on PB09 mux B */ 942 #define MUX_PB09B_ADC_AIN3 _L_(1) 943 #define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3) 944 #define PORT_PB09B_ADC_AIN3 (_UL_(1) << 9) 945 #define PIN_PA04B_ADC_AIN4 _L_(4) /**< \brief ADC signal: AIN4 on PA04 mux B */ 946 #define MUX_PA04B_ADC_AIN4 _L_(1) 947 #define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) 948 #define PORT_PA04B_ADC_AIN4 (_UL_(1) << 4) 949 #define PIN_PA05B_ADC_AIN5 _L_(5) /**< \brief ADC signal: AIN5 on PA05 mux B */ 950 #define MUX_PA05B_ADC_AIN5 _L_(1) 951 #define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) 952 #define PORT_PA05B_ADC_AIN5 (_UL_(1) << 5) 953 #define PIN_PA06B_ADC_AIN6 _L_(6) /**< \brief ADC signal: AIN6 on PA06 mux B */ 954 #define MUX_PA06B_ADC_AIN6 _L_(1) 955 #define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) 956 #define PORT_PA06B_ADC_AIN6 (_UL_(1) << 6) 957 #define PIN_PA07B_ADC_AIN7 _L_(7) /**< \brief ADC signal: AIN7 on PA07 mux B */ 958 #define MUX_PA07B_ADC_AIN7 _L_(1) 959 #define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) 960 #define PORT_PA07B_ADC_AIN7 (_UL_(1) << 7) 961 #define PIN_PB00B_ADC_AIN8 _L_(32) /**< \brief ADC signal: AIN8 on PB00 mux B */ 962 #define MUX_PB00B_ADC_AIN8 _L_(1) 963 #define PINMUX_PB00B_ADC_AIN8 ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8) 964 #define PORT_PB00B_ADC_AIN8 (_UL_(1) << 0) 965 #define PIN_PB01B_ADC_AIN9 _L_(33) /**< \brief ADC signal: AIN9 on PB01 mux B */ 966 #define MUX_PB01B_ADC_AIN9 _L_(1) 967 #define PINMUX_PB01B_ADC_AIN9 ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9) 968 #define PORT_PB01B_ADC_AIN9 (_UL_(1) << 1) 969 #define PIN_PB02B_ADC_AIN10 _L_(34) /**< \brief ADC signal: AIN10 on PB02 mux B */ 970 #define MUX_PB02B_ADC_AIN10 _L_(1) 971 #define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10) 972 #define PORT_PB02B_ADC_AIN10 (_UL_(1) << 2) 973 #define PIN_PB03B_ADC_AIN11 _L_(35) /**< \brief ADC signal: AIN11 on PB03 mux B */ 974 #define MUX_PB03B_ADC_AIN11 _L_(1) 975 #define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11) 976 #define PORT_PB03B_ADC_AIN11 (_UL_(1) << 3) 977 #define PIN_PB04B_ADC_AIN12 _L_(36) /**< \brief ADC signal: AIN12 on PB04 mux B */ 978 #define MUX_PB04B_ADC_AIN12 _L_(1) 979 #define PINMUX_PB04B_ADC_AIN12 ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12) 980 #define PORT_PB04B_ADC_AIN12 (_UL_(1) << 4) 981 #define PIN_PB05B_ADC_AIN13 _L_(37) /**< \brief ADC signal: AIN13 on PB05 mux B */ 982 #define MUX_PB05B_ADC_AIN13 _L_(1) 983 #define PINMUX_PB05B_ADC_AIN13 ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13) 984 #define PORT_PB05B_ADC_AIN13 (_UL_(1) << 5) 985 #define PIN_PB06B_ADC_AIN14 _L_(38) /**< \brief ADC signal: AIN14 on PB06 mux B */ 986 #define MUX_PB06B_ADC_AIN14 _L_(1) 987 #define PINMUX_PB06B_ADC_AIN14 ((PIN_PB06B_ADC_AIN14 << 16) | MUX_PB06B_ADC_AIN14) 988 #define PORT_PB06B_ADC_AIN14 (_UL_(1) << 6) 989 #define PIN_PB07B_ADC_AIN15 _L_(39) /**< \brief ADC signal: AIN15 on PB07 mux B */ 990 #define MUX_PB07B_ADC_AIN15 _L_(1) 991 #define PINMUX_PB07B_ADC_AIN15 ((PIN_PB07B_ADC_AIN15 << 16) | MUX_PB07B_ADC_AIN15) 992 #define PORT_PB07B_ADC_AIN15 (_UL_(1) << 7) 993 #define PIN_PA08B_ADC_AIN16 _L_(8) /**< \brief ADC signal: AIN16 on PA08 mux B */ 994 #define MUX_PA08B_ADC_AIN16 _L_(1) 995 #define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) 996 #define PORT_PA08B_ADC_AIN16 (_UL_(1) << 8) 997 #define PIN_PA09B_ADC_AIN17 _L_(9) /**< \brief ADC signal: AIN17 on PA09 mux B */ 998 #define MUX_PA09B_ADC_AIN17 _L_(1) 999 #define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) 1000 #define PORT_PA09B_ADC_AIN17 (_UL_(1) << 9) 1001 #define PIN_PA10B_ADC_AIN18 _L_(10) /**< \brief ADC signal: AIN18 on PA10 mux B */ 1002 #define MUX_PA10B_ADC_AIN18 _L_(1) 1003 #define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) 1004 #define PORT_PA10B_ADC_AIN18 (_UL_(1) << 10) 1005 #define PIN_PA11B_ADC_AIN19 _L_(11) /**< \brief ADC signal: AIN19 on PA11 mux B */ 1006 #define MUX_PA11B_ADC_AIN19 _L_(1) 1007 #define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) 1008 #define PORT_PA11B_ADC_AIN19 (_UL_(1) << 11) 1009 #define PIN_PA04B_ADC_VREFP _L_(4) /**< \brief ADC signal: VREFP on PA04 mux B */ 1010 #define MUX_PA04B_ADC_VREFP _L_(1) 1011 #define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP) 1012 #define PORT_PA04B_ADC_VREFP (_UL_(1) << 4) 1013 /* ========== PORT definition for AC peripheral ========== */ 1014 #define PIN_PA04B_AC_AIN0 _L_(4) /**< \brief AC signal: AIN0 on PA04 mux B */ 1015 #define MUX_PA04B_AC_AIN0 _L_(1) 1016 #define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) 1017 #define PORT_PA04B_AC_AIN0 (_UL_(1) << 4) 1018 #define PIN_PA05B_AC_AIN1 _L_(5) /**< \brief AC signal: AIN1 on PA05 mux B */ 1019 #define MUX_PA05B_AC_AIN1 _L_(1) 1020 #define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) 1021 #define PORT_PA05B_AC_AIN1 (_UL_(1) << 5) 1022 #define PIN_PA06B_AC_AIN2 _L_(6) /**< \brief AC signal: AIN2 on PA06 mux B */ 1023 #define MUX_PA06B_AC_AIN2 _L_(1) 1024 #define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) 1025 #define PORT_PA06B_AC_AIN2 (_UL_(1) << 6) 1026 #define PIN_PA07B_AC_AIN3 _L_(7) /**< \brief AC signal: AIN3 on PA07 mux B */ 1027 #define MUX_PA07B_AC_AIN3 _L_(1) 1028 #define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) 1029 #define PORT_PA07B_AC_AIN3 (_UL_(1) << 7) 1030 #define PIN_PA12H_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux H */ 1031 #define MUX_PA12H_AC_CMP0 _L_(7) 1032 #define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0) 1033 #define PORT_PA12H_AC_CMP0 (_UL_(1) << 12) 1034 #define PIN_PA18H_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux H */ 1035 #define MUX_PA18H_AC_CMP0 _L_(7) 1036 #define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) 1037 #define PORT_PA18H_AC_CMP0 (_UL_(1) << 18) 1038 #define PIN_PA13H_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux H */ 1039 #define MUX_PA13H_AC_CMP1 _L_(7) 1040 #define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1) 1041 #define PORT_PA13H_AC_CMP1 (_UL_(1) << 13) 1042 #define PIN_PA19H_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux H */ 1043 #define MUX_PA19H_AC_CMP1 _L_(7) 1044 #define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) 1045 #define PORT_PA19H_AC_CMP1 (_UL_(1) << 19) 1046 /* ========== PORT definition for DAC peripheral ========== */ 1047 #define PIN_PA02B_DAC_VOUT _L_(2) /**< \brief DAC signal: VOUT on PA02 mux B */ 1048 #define MUX_PA02B_DAC_VOUT _L_(1) 1049 #define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT) 1050 #define PORT_PA02B_DAC_VOUT (_UL_(1) << 2) 1051 #define PIN_PA03B_DAC_VREFP _L_(3) /**< \brief DAC signal: VREFP on PA03 mux B */ 1052 #define MUX_PA03B_DAC_VREFP _L_(1) 1053 #define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP) 1054 #define PORT_PA03B_DAC_VREFP (_UL_(1) << 3) 1055 1056 #endif /* _SAMD20J14_PIO_ */ 1057
