1 /** 2 * \file 3 * 4 * \brief Instance description for WDT 5 * 6 * Copyright (c) 2017 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAMD20_WDT_INSTANCE_ 31 #define _SAMD20_WDT_INSTANCE_ 32 33 /* ========== Register definition for WDT peripheral ========== */ 34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 35 #define REG_WDT_CTRL (0x40001000) /**< \brief (WDT) Control */ 36 #define REG_WDT_CONFIG (0x40001001) /**< \brief (WDT) Configuration */ 37 #define REG_WDT_EWCTRL (0x40001002) /**< \brief (WDT) Early Warning Interrupt Control */ 38 #define REG_WDT_INTENCLR (0x40001004) /**< \brief (WDT) Interrupt Enable Clear */ 39 #define REG_WDT_INTENSET (0x40001005) /**< \brief (WDT) Interrupt Enable Set */ 40 #define REG_WDT_INTFLAG (0x40001006) /**< \brief (WDT) Interrupt Flag Status and Clear */ 41 #define REG_WDT_STATUS (0x40001007) /**< \brief (WDT) Status */ 42 #define REG_WDT_CLEAR (0x40001008) /**< \brief (WDT) Clear */ 43 #else 44 #define REG_WDT_CTRL (*(RwReg8 *)0x40001000UL) /**< \brief (WDT) Control */ 45 #define REG_WDT_CONFIG (*(RwReg8 *)0x40001001UL) /**< \brief (WDT) Configuration */ 46 #define REG_WDT_EWCTRL (*(RwReg8 *)0x40001002UL) /**< \brief (WDT) Early Warning Interrupt Control */ 47 #define REG_WDT_INTENCLR (*(RwReg8 *)0x40001004UL) /**< \brief (WDT) Interrupt Enable Clear */ 48 #define REG_WDT_INTENSET (*(RwReg8 *)0x40001005UL) /**< \brief (WDT) Interrupt Enable Set */ 49 #define REG_WDT_INTFLAG (*(RwReg8 *)0x40001006UL) /**< \brief (WDT) Interrupt Flag Status and Clear */ 50 #define REG_WDT_STATUS (*(RoReg8 *)0x40001007UL) /**< \brief (WDT) Status */ 51 #define REG_WDT_CLEAR (*(WoReg8 *)0x40001008UL) /**< \brief (WDT) Clear */ 52 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 53 54 /* ========== Instance parameters for WDT peripheral ========== */ 55 #define WDT_GCLK_ID 1 // Index of Generic Clock 56 57 #endif /* _SAMD20_WDT_INSTANCE_ */ 58
