1 /** 2 * \file 3 * 4 * \brief Component description for RSTC 5 * 6 * Copyright (c) 2018 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAMC21_RSTC_COMPONENT_ 31 #define _SAMC21_RSTC_COMPONENT_ 32 33 /* ========================================================================== */ 34 /** SOFTWARE API DEFINITION FOR RSTC */ 35 /* ========================================================================== */ 36 /** \addtogroup SAMC21_RSTC Reset Controller */ 37 /*@{*/ 38 39 #define RSTC_U2239 40 #define REV_RSTC 0x202 41 42 /* -------- RSTC_RCAUSE : (RSTC Offset: 0x00) (R/ 8) Reset Cause -------- */ 43 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 44 typedef union { 45 struct { 46 uint8_t POR:1; /*!< bit: 0 Power On Reset */ 47 uint8_t BODCORE:1; /*!< bit: 1 Brown Out CORE Detector Reset */ 48 uint8_t BODVDD:1; /*!< bit: 2 Brown Out VDD Detector Reset */ 49 uint8_t :1; /*!< bit: 3 Reserved */ 50 uint8_t EXT:1; /*!< bit: 4 External Reset */ 51 uint8_t WDT:1; /*!< bit: 5 Watchdog Reset */ 52 uint8_t SYST:1; /*!< bit: 6 System Reset Request */ 53 uint8_t :1; /*!< bit: 7 Reserved */ 54 } bit; /*!< Structure used for bit access */ 55 uint8_t reg; /*!< Type used for register access */ 56 } RSTC_RCAUSE_Type; 57 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 58 59 #define RSTC_RCAUSE_OFFSET 0x00 /**< \brief (RSTC_RCAUSE offset) Reset Cause */ 60 61 #define RSTC_RCAUSE_POR_Pos 0 /**< \brief (RSTC_RCAUSE) Power On Reset */ 62 #define RSTC_RCAUSE_POR (_U_(0x1) << RSTC_RCAUSE_POR_Pos) 63 #define RSTC_RCAUSE_BODCORE_Pos 1 /**< \brief (RSTC_RCAUSE) Brown Out CORE Detector Reset */ 64 #define RSTC_RCAUSE_BODCORE (_U_(0x1) << RSTC_RCAUSE_BODCORE_Pos) 65 #define RSTC_RCAUSE_BODVDD_Pos 2 /**< \brief (RSTC_RCAUSE) Brown Out VDD Detector Reset */ 66 #define RSTC_RCAUSE_BODVDD (_U_(0x1) << RSTC_RCAUSE_BODVDD_Pos) 67 #define RSTC_RCAUSE_EXT_Pos 4 /**< \brief (RSTC_RCAUSE) External Reset */ 68 #define RSTC_RCAUSE_EXT (_U_(0x1) << RSTC_RCAUSE_EXT_Pos) 69 #define RSTC_RCAUSE_WDT_Pos 5 /**< \brief (RSTC_RCAUSE) Watchdog Reset */ 70 #define RSTC_RCAUSE_WDT (_U_(0x1) << RSTC_RCAUSE_WDT_Pos) 71 #define RSTC_RCAUSE_SYST_Pos 6 /**< \brief (RSTC_RCAUSE) System Reset Request */ 72 #define RSTC_RCAUSE_SYST (_U_(0x1) << RSTC_RCAUSE_SYST_Pos) 73 #define RSTC_RCAUSE_MASK _U_(0x77) /**< \brief (RSTC_RCAUSE) MASK Register */ 74 75 /** \brief RSTC hardware registers */ 76 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 77 typedef struct { 78 __I RSTC_RCAUSE_Type RCAUSE; /**< \brief Offset: 0x00 (R/ 8) Reset Cause */ 79 } Rstc; 80 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 81 82 /*@}*/ 83 84 #endif /* _SAMC21_RSTC_COMPONENT_ */ 85
