1 /** 2 * \file 3 * 4 * \brief Header file for SAMC21J17AU 5 * 6 * Copyright (c) 2018 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAMC21J17AU_ 31 #define _SAMC21J17AU_ 32 33 /** 34 * \ingroup SAMC21_definitions 35 * \addtogroup SAMC21J17AU_definitions SAMC21J17AU definitions 36 * This file defines all structures and symbols for SAMC21J17AU: 37 * - registers and bitfields 38 * - peripheral base address 39 * - peripheral ID 40 * - PIO definitions 41 */ 42 /*@{*/ 43 44 #ifdef __cplusplus 45 extern "C" { 46 #endif 47 48 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 49 #include <stdint.h> 50 #ifndef __cplusplus 51 typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ 52 typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ 53 typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ 54 #else 55 typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ 56 typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ 57 typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ 58 #endif 59 typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ 60 typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ 61 typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ 62 typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ 63 typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ 64 typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ 65 #endif 66 67 #if !defined(SKIP_INTEGER_LITERALS) 68 #if defined(_U_) || defined(_L_) || defined(_UL_) 69 #error "Integer Literals macros already defined elsewhere" 70 #endif 71 72 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 73 /* Macros that deal with adding suffixes to integer literal constants for C/C++ */ 74 #define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ 75 #define _L_(x) x ## L /**< C code: Long integer literal constant value */ 76 #define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ 77 #else /* Assembler */ 78 #define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ 79 #define _L_(x) x /**< Assembler: Long integer literal constant value */ 80 #define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ 81 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 82 #endif /* SKIP_INTEGER_LITERALS */ 83 84 /* ************************************************************************** */ 85 /** CMSIS DEFINITIONS FOR SAMC21J17AU */ 86 /* ************************************************************************** */ 87 /** \defgroup SAMC21J17AU_cmsis CMSIS Definitions */ 88 /*@{*/ 89 90 /** Interrupt Number Definition */ 91 typedef enum IRQn 92 { 93 /****** Cortex-M0+ Processor Exceptions Numbers *******************/ 94 NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ 95 HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ 96 SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ 97 PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ 98 SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ 99 /****** SAMC21J17AU-specific Interrupt Numbers *********************/ 100 SYSTEM_IRQn = 0, /**< 0 SAMC21J17AU System Interrupts */ 101 WDT_IRQn = 1, /**< 1 SAMC21J17AU Watchdog Timer (WDT) */ 102 RTC_IRQn = 2, /**< 2 SAMC21J17AU Real-Time Counter (RTC) */ 103 EIC_IRQn = 3, /**< 3 SAMC21J17AU External Interrupt Controller (EIC) */ 104 FREQM_IRQn = 4, /**< 4 SAMC21J17AU Frequency Meter (FREQM) */ 105 TSENS_IRQn = 5, /**< 5 SAMC21J17AU Temperature Sensor (TSENS) */ 106 NVMCTRL_IRQn = 6, /**< 6 SAMC21J17AU Non-Volatile Memory Controller (NVMCTRL) */ 107 DMAC_IRQn = 7, /**< 7 SAMC21J17AU Direct Memory Access Controller (DMAC) */ 108 EVSYS_IRQn = 8, /**< 8 SAMC21J17AU Event System Interface (EVSYS) */ 109 SERCOM0_IRQn = 9, /**< 9 SAMC21J17AU Serial Communication Interface 0 (SERCOM0) */ 110 SERCOM1_IRQn = 10, /**< 10 SAMC21J17AU Serial Communication Interface 1 (SERCOM1) */ 111 SERCOM2_IRQn = 11, /**< 11 SAMC21J17AU Serial Communication Interface 2 (SERCOM2) */ 112 SERCOM3_IRQn = 12, /**< 12 SAMC21J17AU Serial Communication Interface 3 (SERCOM3) */ 113 SERCOM4_IRQn = 13, /**< 13 SAMC21J17AU Serial Communication Interface 4 (SERCOM4) */ 114 SERCOM5_IRQn = 14, /**< 14 SAMC21J17AU Serial Communication Interface 5 (SERCOM5) */ 115 CAN0_IRQn = 15, /**< 15 SAMC21J17AU Control Area Network 0 (CAN0) */ 116 CAN1_IRQn = 16, /**< 16 SAMC21J17AU Control Area Network 1 (CAN1) */ 117 TCC0_IRQn = 17, /**< 17 SAMC21J17AU Timer Counter Control 0 (TCC0) */ 118 TCC1_IRQn = 18, /**< 18 SAMC21J17AU Timer Counter Control 1 (TCC1) */ 119 TCC2_IRQn = 19, /**< 19 SAMC21J17AU Timer Counter Control 2 (TCC2) */ 120 TC0_IRQn = 20, /**< 20 SAMC21J17AU Basic Timer Counter 0 (TC0) */ 121 TC1_IRQn = 21, /**< 21 SAMC21J17AU Basic Timer Counter 1 (TC1) */ 122 TC2_IRQn = 22, /**< 22 SAMC21J17AU Basic Timer Counter 2 (TC2) */ 123 TC3_IRQn = 23, /**< 23 SAMC21J17AU Basic Timer Counter 3 (TC3) */ 124 TC4_IRQn = 24, /**< 24 SAMC21J17AU Basic Timer Counter 4 (TC4) */ 125 ADC0_IRQn = 25, /**< 25 SAMC21J17AU Analog Digital Converter 0 (ADC0) */ 126 ADC1_IRQn = 26, /**< 26 SAMC21J17AU Analog Digital Converter 1 (ADC1) */ 127 AC_IRQn = 27, /**< 27 SAMC21J17AU Analog Comparators (AC) */ 128 DAC_IRQn = 28, /**< 28 SAMC21J17AU Digital Analog Converter (DAC) */ 129 SDADC_IRQn = 29, /**< 29 SAMC21J17AU Sigma-Delta Analog Digital Converter (SDADC) */ 130 PTC_IRQn = 30, /**< 30 SAMC21J17AU Peripheral Touch Controller (PTC) */ 131 132 PERIPH_COUNT_IRQn = 31 /**< Number of peripheral IDs */ 133 } IRQn_Type; 134 135 typedef struct _DeviceVectors 136 { 137 /* Stack pointer */ 138 void* pvStack; 139 140 /* Cortex-M handlers */ 141 void* pfnReset_Handler; 142 void* pfnNonMaskableInt_Handler; 143 void* pfnHardFault_Handler; 144 void* pvReservedM12; 145 void* pvReservedM11; 146 void* pvReservedM10; 147 void* pvReservedM9; 148 void* pvReservedM8; 149 void* pvReservedM7; 150 void* pvReservedM6; 151 void* pfnSVCall_Handler; 152 void* pvReservedM4; 153 void* pvReservedM3; 154 void* pfnPendSV_Handler; 155 void* pfnSysTick_Handler; 156 157 /* Peripheral handlers */ 158 void* pfnSYSTEM_Handler; /* 0 Main Clock, 32k Oscillators Control, Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ 159 void* pfnWDT_Handler; /* 1 Watchdog Timer */ 160 void* pfnRTC_Handler; /* 2 Real-Time Counter */ 161 void* pfnEIC_Handler; /* 3 External Interrupt Controller */ 162 void* pfnFREQM_Handler; /* 4 Frequency Meter */ 163 void* pfnTSENS_Handler; /* 5 Temperature Sensor */ 164 void* pfnNVMCTRL_Handler; /* 6 Non-Volatile Memory Controller */ 165 void* pfnDMAC_Handler; /* 7 Direct Memory Access Controller */ 166 void* pfnEVSYS_Handler; /* 8 Event System Interface */ 167 void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ 168 void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ 169 void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ 170 void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ 171 void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ 172 void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ 173 void* pfnCAN0_Handler; /* 15 Control Area Network 0 */ 174 void* pfnCAN1_Handler; /* 16 Control Area Network 1 */ 175 void* pfnTCC0_Handler; /* 17 Timer Counter Control 0 */ 176 void* pfnTCC1_Handler; /* 18 Timer Counter Control 1 */ 177 void* pfnTCC2_Handler; /* 19 Timer Counter Control 2 */ 178 void* pfnTC0_Handler; /* 20 Basic Timer Counter 0 */ 179 void* pfnTC1_Handler; /* 21 Basic Timer Counter 1 */ 180 void* pfnTC2_Handler; /* 22 Basic Timer Counter 2 */ 181 void* pfnTC3_Handler; /* 23 Basic Timer Counter 3 */ 182 void* pfnTC4_Handler; /* 24 Basic Timer Counter 4 */ 183 void* pfnADC0_Handler; /* 25 Analog Digital Converter 0 */ 184 void* pfnADC1_Handler; /* 26 Analog Digital Converter 1 */ 185 void* pfnAC_Handler; /* 27 Analog Comparators */ 186 void* pfnDAC_Handler; /* 28 Digital Analog Converter */ 187 void* pfnSDADC_Handler; /* 29 Sigma-Delta Analog Digital Converter */ 188 void* pfnPTC_Handler; /* 30 Peripheral Touch Controller */ 189 } DeviceVectors; 190 191 /* Cortex-M0+ processor handlers */ 192 void Reset_Handler ( void ); 193 void NonMaskableInt_Handler ( void ); 194 void HardFault_Handler ( void ); 195 void SVCall_Handler ( void ); 196 void PendSV_Handler ( void ); 197 void SysTick_Handler ( void ); 198 199 /* Peripherals handlers */ 200 void SYSTEM_Handler ( void ); 201 void WDT_Handler ( void ); 202 void RTC_Handler ( void ); 203 void EIC_Handler ( void ); 204 void FREQM_Handler ( void ); 205 void TSENS_Handler ( void ); 206 void NVMCTRL_Handler ( void ); 207 void DMAC_Handler ( void ); 208 void EVSYS_Handler ( void ); 209 void SERCOM0_Handler ( void ); 210 void SERCOM1_Handler ( void ); 211 void SERCOM2_Handler ( void ); 212 void SERCOM3_Handler ( void ); 213 void SERCOM4_Handler ( void ); 214 void SERCOM5_Handler ( void ); 215 void CAN0_Handler ( void ); 216 void CAN1_Handler ( void ); 217 void TCC0_Handler ( void ); 218 void TCC1_Handler ( void ); 219 void TCC2_Handler ( void ); 220 void TC0_Handler ( void ); 221 void TC1_Handler ( void ); 222 void TC2_Handler ( void ); 223 void TC3_Handler ( void ); 224 void TC4_Handler ( void ); 225 void ADC0_Handler ( void ); 226 void ADC1_Handler ( void ); 227 void AC_Handler ( void ); 228 void DAC_Handler ( void ); 229 void SDADC_Handler ( void ); 230 void PTC_Handler ( void ); 231 232 /* 233 * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals 234 */ 235 236 #define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ 237 #define __MPU_PRESENT 1 /*!< MPU present or not */ 238 #define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ 239 #define __VTOR_PRESENT 1 /*!< VTOR present or not */ 240 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 241 242 /** 243 * \brief CMSIS includes 244 */ 245 246 #include <core_cm0plus.h> 247 #if !defined DONT_USE_CMSIS_INIT 248 #include "system_samc21.h" 249 #endif /* DONT_USE_CMSIS_INIT */ 250 251 /*@}*/ 252 253 /* ************************************************************************** */ 254 /** SOFTWARE PERIPHERAL API DEFINITION FOR SAMC21J17AU */ 255 /* ************************************************************************** */ 256 /** \defgroup SAMC21J17AU_api Peripheral Software API */ 257 /*@{*/ 258 259 #include "component/ac.h" 260 #include "component/adc.h" 261 #include "component/can.h" 262 #include "component/ccl.h" 263 #include "component/dac.h" 264 #include "component/divas.h" 265 #include "component/dmac.h" 266 #include "component/dsu.h" 267 #include "component/eic.h" 268 #include "component/evsys.h" 269 #include "component/freqm.h" 270 #include "component/gclk.h" 271 #include "component/hmatrixb.h" 272 #include "component/mclk.h" 273 #include "component/mtb.h" 274 #include "component/nvmctrl.h" 275 #include "component/oscctrl.h" 276 #include "component/osc32kctrl.h" 277 #include "component/pac.h" 278 #include "component/pm.h" 279 #include "component/port.h" 280 #include "component/rstc.h" 281 #include "component/rtc.h" 282 #include "component/sdadc.h" 283 #include "component/sercom.h" 284 #include "component/supc.h" 285 #include "component/tc.h" 286 #include "component/tcc.h" 287 #include "component/tsens.h" 288 #include "component/wdt.h" 289 /*@}*/ 290 291 /* ************************************************************************** */ 292 /** REGISTERS ACCESS DEFINITIONS FOR SAMC21J17AU */ 293 /* ************************************************************************** */ 294 /** \defgroup SAMC21J17AU_reg Registers Access Definitions */ 295 /*@{*/ 296 297 #include "instance/ac.h" 298 #include "instance/adc0.h" 299 #include "instance/adc1.h" 300 #include "instance/can0.h" 301 #include "instance/can1.h" 302 #include "instance/ccl.h" 303 #include "instance/dac.h" 304 #include "instance/divas.h" 305 #include "instance/dmac.h" 306 #include "instance/dsu.h" 307 #include "instance/eic.h" 308 #include "instance/evsys.h" 309 #include "instance/freqm.h" 310 #include "instance/gclk.h" 311 #include "instance/hmatrixhs.h" 312 #include "instance/mclk.h" 313 #include "instance/mtb.h" 314 #include "instance/nvmctrl.h" 315 #include "instance/oscctrl.h" 316 #include "instance/osc32kctrl.h" 317 #include "instance/pac.h" 318 #include "instance/pm.h" 319 #include "instance/port.h" 320 #include "instance/ptc.h" 321 #include "instance/rstc.h" 322 #include "instance/rtc.h" 323 #include "instance/sdadc.h" 324 #include "instance/sercom0.h" 325 #include "instance/sercom1.h" 326 #include "instance/sercom2.h" 327 #include "instance/sercom3.h" 328 #include "instance/sercom4.h" 329 #include "instance/sercom5.h" 330 #include "instance/supc.h" 331 #include "instance/tc0.h" 332 #include "instance/tc1.h" 333 #include "instance/tc2.h" 334 #include "instance/tc3.h" 335 #include "instance/tc4.h" 336 #include "instance/tcc0.h" 337 #include "instance/tcc1.h" 338 #include "instance/tcc2.h" 339 #include "instance/tsens.h" 340 #include "instance/wdt.h" 341 /*@}*/ 342 343 /* ************************************************************************** */ 344 /** PERIPHERAL ID DEFINITIONS FOR SAMC21J17AU */ 345 /* ************************************************************************** */ 346 /** \defgroup SAMC21J17AU_id Peripheral Ids Definitions */ 347 /*@{*/ 348 349 // Peripheral instances on HPB0 bridge 350 #define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ 351 #define ID_PM 1 /**< \brief Power Manager (PM) */ 352 #define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ 353 #define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ 354 #define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ 355 #define ID_OSC32KCTRL 5 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ 356 #define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ 357 #define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ 358 #define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ 359 #define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ 360 #define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ 361 #define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ 362 #define ID_TSENS 12 /**< \brief Temperature Sensor (TSENS) */ 363 364 // Peripheral instances on HPB1 bridge 365 #define ID_PORT 32 /**< \brief Port Module (PORT) */ 366 #define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ 367 #define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ 368 #define ID_DMAC 35 /**< \brief Direct Memory Access Controller (DMAC) */ 369 #define ID_MTB 36 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ 370 #define ID_HMATRIXHS 37 /**< \brief HSB Matrix (HMATRIXHS) */ 371 372 // Peripheral instances on HPB2 bridge 373 #define ID_EVSYS 64 /**< \brief Event System Interface (EVSYS) */ 374 #define ID_SERCOM0 65 /**< \brief Serial Communication Interface 0 (SERCOM0) */ 375 #define ID_SERCOM1 66 /**< \brief Serial Communication Interface 1 (SERCOM1) */ 376 #define ID_SERCOM2 67 /**< \brief Serial Communication Interface 2 (SERCOM2) */ 377 #define ID_SERCOM3 68 /**< \brief Serial Communication Interface 3 (SERCOM3) */ 378 #define ID_SERCOM4 69 /**< \brief Serial Communication Interface 4 (SERCOM4) */ 379 #define ID_SERCOM5 70 /**< \brief Serial Communication Interface 5 (SERCOM5) */ 380 #define ID_CAN0 71 /**< \brief Control Area Network 0 (CAN0) */ 381 #define ID_CAN1 72 /**< \brief Control Area Network 1 (CAN1) */ 382 #define ID_TCC0 73 /**< \brief Timer Counter Control 0 (TCC0) */ 383 #define ID_TCC1 74 /**< \brief Timer Counter Control 1 (TCC1) */ 384 #define ID_TCC2 75 /**< \brief Timer Counter Control 2 (TCC2) */ 385 #define ID_TC0 76 /**< \brief Basic Timer Counter 0 (TC0) */ 386 #define ID_TC1 77 /**< \brief Basic Timer Counter 1 (TC1) */ 387 #define ID_TC2 78 /**< \brief Basic Timer Counter 2 (TC2) */ 388 #define ID_TC3 79 /**< \brief Basic Timer Counter 3 (TC3) */ 389 #define ID_TC4 80 /**< \brief Basic Timer Counter 4 (TC4) */ 390 #define ID_ADC0 81 /**< \brief Analog Digital Converter 0 (ADC0) */ 391 #define ID_ADC1 82 /**< \brief Analog Digital Converter 1 (ADC1) */ 392 #define ID_SDADC 83 /**< \brief Sigma-Delta Analog Digital Converter (SDADC) */ 393 #define ID_AC 84 /**< \brief Analog Comparators (AC) */ 394 #define ID_DAC 85 /**< \brief Digital Analog Converter (DAC) */ 395 #define ID_PTC 86 /**< \brief Peripheral Touch Controller (PTC) */ 396 #define ID_CCL 87 /**< \brief Configurable Custom Logic (CCL) */ 397 398 // Peripheral instances on AHB (as if on bridge 3) 399 #define ID_DIVAS 96 /**< \brief Divide and Square Root Accelerator (DIVAS) */ 400 401 #define ID_PERIPH_COUNT 97 /**< \brief Max number of peripheral IDs */ 402 /*@}*/ 403 404 /* ************************************************************************** */ 405 /** BASE ADDRESS DEFINITIONS FOR SAMC21J17AU */ 406 /* ************************************************************************** */ 407 /** \defgroup SAMC21J17AU_base Peripheral Base Address Definitions */ 408 /*@{*/ 409 410 #if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) 411 #define AC (0x42005000) /**< \brief (AC) APB Base Address */ 412 #define ADC0 (0x42004400) /**< \brief (ADC0) APB Base Address */ 413 #define ADC1 (0x42004800) /**< \brief (ADC1) APB Base Address */ 414 #define CAN0 (0x42001C00) /**< \brief (CAN0) APB Base Address */ 415 #define CAN1 (0x42002000) /**< \brief (CAN1) APB Base Address */ 416 #define CCL (0x42005C00) /**< \brief (CCL) APB Base Address */ 417 #define DAC (0x42005400) /**< \brief (DAC) APB Base Address */ 418 #define DIVAS (0x48000000) /**< \brief (DIVAS) AHB Base Address */ 419 #define DIVAS_IOBUS (0x60000200) /**< \brief (DIVAS) IOBUS Base Address */ 420 #define DMAC (0x41006000) /**< \brief (DMAC) APB Base Address */ 421 #define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ 422 #define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ 423 #define EVSYS (0x42000000) /**< \brief (EVSYS) APB Base Address */ 424 #define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ 425 #define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ 426 #define HMATRIXHS (0x4100A000) /**< \brief (HMATRIXHS) APB Base Address */ 427 #define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ 428 #define MTB (0x41008000) /**< \brief (MTB) APB Base Address */ 429 #define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ 430 #define NVMCTRL_OTP5 (0x00806020) /**< \brief (NVMCTRL) OTP5 Base Address */ 431 #define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ 432 #define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ 433 #define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ 434 #define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ 435 #define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ 436 #define PM (0x40000400) /**< \brief (PM) APB Base Address */ 437 #define PORT (0x41000000) /**< \brief (PORT) APB Base Address */ 438 #define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ 439 #define PTC (0x42005800) /**< \brief (PTC) APB Base Address */ 440 #define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ 441 #define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ 442 #define SDADC (0x42004C00) /**< \brief (SDADC) APB Base Address */ 443 #define SERCOM0 (0x42000400) /**< \brief (SERCOM0) APB Base Address */ 444 #define SERCOM1 (0x42000800) /**< \brief (SERCOM1) APB Base Address */ 445 #define SERCOM2 (0x42000C00) /**< \brief (SERCOM2) APB Base Address */ 446 #define SERCOM3 (0x42001000) /**< \brief (SERCOM3) APB Base Address */ 447 #define SERCOM4 (0x42001400) /**< \brief (SERCOM4) APB Base Address */ 448 #define SERCOM5 (0x42001800) /**< \brief (SERCOM5) APB Base Address */ 449 #define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ 450 #define TC0 (0x42003000) /**< \brief (TC0) APB Base Address */ 451 #define TC1 (0x42003400) /**< \brief (TC1) APB Base Address */ 452 #define TC2 (0x42003800) /**< \brief (TC2) APB Base Address */ 453 #define TC3 (0x42003C00) /**< \brief (TC3) APB Base Address */ 454 #define TC4 (0x42004000) /**< \brief (TC4) APB Base Address */ 455 #define TCC0 (0x42002400) /**< \brief (TCC0) APB Base Address */ 456 #define TCC1 (0x42002800) /**< \brief (TCC1) APB Base Address */ 457 #define TCC2 (0x42002C00) /**< \brief (TCC2) APB Base Address */ 458 #define TSENS (0x40003000) /**< \brief (TSENS) APB Base Address */ 459 #define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ 460 #else 461 #define AC ((Ac *)0x42005000UL) /**< \brief (AC) APB Base Address */ 462 #define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ 463 #define AC_INSTS { AC } /**< \brief (AC) Instances List */ 464 465 #define ADC0 ((Adc *)0x42004400UL) /**< \brief (ADC0) APB Base Address */ 466 #define ADC1 ((Adc *)0x42004800UL) /**< \brief (ADC1) APB Base Address */ 467 #define ADC_INST_NUM 2 /**< \brief (ADC) Number of instances */ 468 #define ADC_INSTS { ADC0, ADC1 } /**< \brief (ADC) Instances List */ 469 470 #define CAN0 ((Can *)0x42001C00UL) /**< \brief (CAN0) APB Base Address */ 471 #define CAN1 ((Can *)0x42002000UL) /**< \brief (CAN1) APB Base Address */ 472 #define CAN_INST_NUM 2 /**< \brief (CAN) Number of instances */ 473 #define CAN_INSTS { CAN0, CAN1 } /**< \brief (CAN) Instances List */ 474 475 #define CCL ((Ccl *)0x42005C00UL) /**< \brief (CCL) APB Base Address */ 476 #define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ 477 #define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ 478 479 #define DAC ((Dac *)0x42005400UL) /**< \brief (DAC) APB Base Address */ 480 #define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ 481 #define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ 482 483 #define DIVAS ((Divas *)0x48000000UL) /**< \brief (DIVAS) AHB Base Address */ 484 #define DIVAS_IOBUS ((Divas *)0x60000200UL) /**< \brief (DIVAS) IOBUS Base Address */ 485 #define DIVAS_INST_NUM 1 /**< \brief (DIVAS) Number of instances */ 486 #define DIVAS_INSTS { DIVAS } /**< \brief (DIVAS) Instances List */ 487 #define DIVAS_IOBUS_INST_NUM 1 /**< \brief (DIVAS) Number of instances */ 488 #define DIVAS_IOBUS_INSTS { DIVAS_IOBUS } /**< \brief (DIVAS) Instances List */ 489 490 #define DMAC ((Dmac *)0x41006000UL) /**< \brief (DMAC) APB Base Address */ 491 #define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ 492 #define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ 493 494 #define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ 495 #define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ 496 #define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ 497 498 #define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ 499 #define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ 500 #define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ 501 502 #define EVSYS ((Evsys *)0x42000000UL) /**< \brief (EVSYS) APB Base Address */ 503 #define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ 504 #define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ 505 506 #define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ 507 #define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ 508 #define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ 509 510 #define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ 511 #define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ 512 #define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ 513 514 #define HMATRIXHS ((Hmatrixb *)0x4100A000UL) /**< \brief (HMATRIXHS) APB Base Address */ 515 #define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ 516 #define HMATRIXB_INSTS { HMATRIXHS } /**< \brief (HMATRIXB) Instances List */ 517 518 #define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ 519 #define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ 520 #define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ 521 522 #define MTB ((Mtb *)0x41008000UL) /**< \brief (MTB) APB Base Address */ 523 #define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ 524 #define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ 525 526 #define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ 527 #define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ 528 #define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ 529 #define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ 530 #define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ 531 #define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ 532 533 #define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ 534 #define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ 535 #define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ 536 537 #define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ 538 #define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ 539 #define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ 540 541 #define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ 542 #define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ 543 #define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ 544 545 #define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ 546 #define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ 547 #define PM_INSTS { PM } /**< \brief (PM) Instances List */ 548 549 #define PORT ((Port *)0x41000000UL) /**< \brief (PORT) APB Base Address */ 550 #define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ 551 #define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ 552 #define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ 553 #define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ 554 #define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ 555 556 #define PTC ((void *)0x42005800UL) /**< \brief (PTC) APB Base Address */ 557 #define PTC_GCLK_ID 37 558 #define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ 559 #define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ 560 561 #define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ 562 #define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ 563 #define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ 564 565 #define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ 566 #define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ 567 #define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ 568 569 #define SDADC ((Sdadc *)0x42004C00UL) /**< \brief (SDADC) APB Base Address */ 570 #define SDADC_INST_NUM 1 /**< \brief (SDADC) Number of instances */ 571 #define SDADC_INSTS { SDADC } /**< \brief (SDADC) Instances List */ 572 573 #define SERCOM0 ((Sercom *)0x42000400UL) /**< \brief (SERCOM0) APB Base Address */ 574 #define SERCOM1 ((Sercom *)0x42000800UL) /**< \brief (SERCOM1) APB Base Address */ 575 #define SERCOM2 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM2) APB Base Address */ 576 #define SERCOM3 ((Sercom *)0x42001000UL) /**< \brief (SERCOM3) APB Base Address */ 577 #define SERCOM4 ((Sercom *)0x42001400UL) /**< \brief (SERCOM4) APB Base Address */ 578 #define SERCOM5 ((Sercom *)0x42001800UL) /**< \brief (SERCOM5) APB Base Address */ 579 #define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ 580 #define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ 581 582 #define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ 583 #define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ 584 #define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ 585 586 #define TC0 ((Tc *)0x42003000UL) /**< \brief (TC0) APB Base Address */ 587 #define TC1 ((Tc *)0x42003400UL) /**< \brief (TC1) APB Base Address */ 588 #define TC2 ((Tc *)0x42003800UL) /**< \brief (TC2) APB Base Address */ 589 #define TC3 ((Tc *)0x42003C00UL) /**< \brief (TC3) APB Base Address */ 590 #define TC4 ((Tc *)0x42004000UL) /**< \brief (TC4) APB Base Address */ 591 #define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ 592 #define TC_INSTS { TC0, TC1, TC2, TC3, TC4 } /**< \brief (TC) Instances List */ 593 594 #define TCC0 ((Tcc *)0x42002400UL) /**< \brief (TCC0) APB Base Address */ 595 #define TCC1 ((Tcc *)0x42002800UL) /**< \brief (TCC1) APB Base Address */ 596 #define TCC2 ((Tcc *)0x42002C00UL) /**< \brief (TCC2) APB Base Address */ 597 #define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ 598 #define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ 599 600 #define TSENS ((Tsens *)0x40003000UL) /**< \brief (TSENS) APB Base Address */ 601 #define TSENS_INST_NUM 1 /**< \brief (TSENS) Number of instances */ 602 #define TSENS_INSTS { TSENS } /**< \brief (TSENS) Instances List */ 603 604 #define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ 605 #define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ 606 #define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ 607 608 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 609 /*@}*/ 610 611 /* ************************************************************************** */ 612 /** PORT DEFINITIONS FOR SAMC21J17AU */ 613 /* ************************************************************************** */ 614 /** \defgroup SAMC21J17AU_port PORT Definitions */ 615 /*@{*/ 616 617 #include "pio/samc21j17au.h" 618 /*@}*/ 619 620 /* ************************************************************************** */ 621 /** MEMORY MAPPING DEFINITIONS FOR SAMC21J17AU */ 622 /* ************************************************************************** */ 623 624 #define FLASH_SIZE _UL_(0x00020000) /* 128 kB */ 625 #define FLASH_PAGE_SIZE 64 626 #define FLASH_NB_OF_PAGES 2048 627 #define FLASH_USER_PAGE_SIZE 64 628 #define HSRAM_SIZE _UL_(0x00004000) /* 16 kB */ 629 630 #define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ 631 #define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */ 632 #define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ 633 #define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ 634 #define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ 635 #define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ 636 #define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ 637 638 #define DSU_DID_RESETVALUE _UL_(0x11010510) 639 #define AC_PAIRS 2 640 #define DMAC_CH_NUM 12 641 #define EVSYS_CHANNELS 12 642 #define NVMCTRL_RWW_EEPROM_SIZE _UL_(0x00001000) /* 4 kB */ 643 #define PORT_GROUPS 2 644 645 /* ************************************************************************** */ 646 /** ELECTRICAL DEFINITIONS FOR SAMC21J17AU */ 647 /* ************************************************************************** */ 648 649 650 #ifdef __cplusplus 651 } 652 #endif 653 654 /*@}*/ 655 656 #endif /* SAMC21J17AU_H */ 657
