1 /** 2 * \file 3 * 4 * \brief Peripheral I/O description for SAMC21J18AU 5 * 6 * Copyright (c) 2018 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAMC21J18AU_PIO_ 31 #define _SAMC21J18AU_PIO_ 32 33 #define PIN_PA00 0 /**< \brief Pin Number for PA00 */ 34 #define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */ 35 #define PIN_PA01 1 /**< \brief Pin Number for PA01 */ 36 #define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */ 37 #define PIN_PA02 2 /**< \brief Pin Number for PA02 */ 38 #define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */ 39 #define PIN_PA03 3 /**< \brief Pin Number for PA03 */ 40 #define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */ 41 #define PIN_PA04 4 /**< \brief Pin Number for PA04 */ 42 #define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */ 43 #define PIN_PA05 5 /**< \brief Pin Number for PA05 */ 44 #define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */ 45 #define PIN_PA06 6 /**< \brief Pin Number for PA06 */ 46 #define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */ 47 #define PIN_PA07 7 /**< \brief Pin Number for PA07 */ 48 #define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */ 49 #define PIN_PA08 8 /**< \brief Pin Number for PA08 */ 50 #define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */ 51 #define PIN_PA09 9 /**< \brief Pin Number for PA09 */ 52 #define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */ 53 #define PIN_PA10 10 /**< \brief Pin Number for PA10 */ 54 #define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */ 55 #define PIN_PA11 11 /**< \brief Pin Number for PA11 */ 56 #define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */ 57 #define PIN_PA12 12 /**< \brief Pin Number for PA12 */ 58 #define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */ 59 #define PIN_PA13 13 /**< \brief Pin Number for PA13 */ 60 #define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */ 61 #define PIN_PA14 14 /**< \brief Pin Number for PA14 */ 62 #define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */ 63 #define PIN_PA15 15 /**< \brief Pin Number for PA15 */ 64 #define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */ 65 #define PIN_PA16 16 /**< \brief Pin Number for PA16 */ 66 #define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */ 67 #define PIN_PA17 17 /**< \brief Pin Number for PA17 */ 68 #define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */ 69 #define PIN_PA18 18 /**< \brief Pin Number for PA18 */ 70 #define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */ 71 #define PIN_PA19 19 /**< \brief Pin Number for PA19 */ 72 #define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */ 73 #define PIN_PA20 20 /**< \brief Pin Number for PA20 */ 74 #define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */ 75 #define PIN_PA21 21 /**< \brief Pin Number for PA21 */ 76 #define PORT_PA21 (_UL_(1) << 21) /**< \brief PORT Mask for PA21 */ 77 #define PIN_PA22 22 /**< \brief Pin Number for PA22 */ 78 #define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */ 79 #define PIN_PA23 23 /**< \brief Pin Number for PA23 */ 80 #define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */ 81 #define PIN_PA24 24 /**< \brief Pin Number for PA24 */ 82 #define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */ 83 #define PIN_PA25 25 /**< \brief Pin Number for PA25 */ 84 #define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */ 85 #define PIN_PA27 27 /**< \brief Pin Number for PA27 */ 86 #define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */ 87 #define PIN_PA28 28 /**< \brief Pin Number for PA28 */ 88 #define PORT_PA28 (_UL_(1) << 28) /**< \brief PORT Mask for PA28 */ 89 #define PIN_PA30 30 /**< \brief Pin Number for PA30 */ 90 #define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */ 91 #define PIN_PA31 31 /**< \brief Pin Number for PA31 */ 92 #define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */ 93 #define PIN_PB00 32 /**< \brief Pin Number for PB00 */ 94 #define PORT_PB00 (_UL_(1) << 0) /**< \brief PORT Mask for PB00 */ 95 #define PIN_PB01 33 /**< \brief Pin Number for PB01 */ 96 #define PORT_PB01 (_UL_(1) << 1) /**< \brief PORT Mask for PB01 */ 97 #define PIN_PB02 34 /**< \brief Pin Number for PB02 */ 98 #define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */ 99 #define PIN_PB03 35 /**< \brief Pin Number for PB03 */ 100 #define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */ 101 #define PIN_PB08 40 /**< \brief Pin Number for PB08 */ 102 #define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */ 103 #define PIN_PB09 41 /**< \brief Pin Number for PB09 */ 104 #define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */ 105 #define PIN_PB10 42 /**< \brief Pin Number for PB10 */ 106 #define PORT_PB10 (_UL_(1) << 10) /**< \brief PORT Mask for PB10 */ 107 #define PIN_PB11 43 /**< \brief Pin Number for PB11 */ 108 #define PORT_PB11 (_UL_(1) << 11) /**< \brief PORT Mask for PB11 */ 109 #define PIN_PB12 44 /**< \brief Pin Number for PB12 */ 110 #define PORT_PB12 (_UL_(1) << 12) /**< \brief PORT Mask for PB12 */ 111 #define PIN_PB13 45 /**< \brief Pin Number for PB13 */ 112 #define PORT_PB13 (_UL_(1) << 13) /**< \brief PORT Mask for PB13 */ 113 #define PIN_PB14 46 /**< \brief Pin Number for PB14 */ 114 #define PORT_PB14 (_UL_(1) << 14) /**< \brief PORT Mask for PB14 */ 115 #define PIN_PB15 47 /**< \brief Pin Number for PB15 */ 116 #define PORT_PB15 (_UL_(1) << 15) /**< \brief PORT Mask for PB15 */ 117 #define PIN_PB22 54 /**< \brief Pin Number for PB22 */ 118 #define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */ 119 #define PIN_PB23 55 /**< \brief Pin Number for PB23 */ 120 #define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */ 121 /* ========== PORT definition for RSTC peripheral ========== */ 122 #define PIN_PA00A_RSTC_EXTWAKE0 _L_(0) /**< \brief RSTC signal: EXTWAKE0 on PA00 mux A */ 123 #define MUX_PA00A_RSTC_EXTWAKE0 _L_(0) 124 #define PINMUX_PA00A_RSTC_EXTWAKE0 ((PIN_PA00A_RSTC_EXTWAKE0 << 16) | MUX_PA00A_RSTC_EXTWAKE0) 125 #define PORT_PA00A_RSTC_EXTWAKE0 (_UL_(1) << 0) 126 #define PIN_PA01A_RSTC_EXTWAKE1 _L_(1) /**< \brief RSTC signal: EXTWAKE1 on PA01 mux A */ 127 #define MUX_PA01A_RSTC_EXTWAKE1 _L_(0) 128 #define PINMUX_PA01A_RSTC_EXTWAKE1 ((PIN_PA01A_RSTC_EXTWAKE1 << 16) | MUX_PA01A_RSTC_EXTWAKE1) 129 #define PORT_PA01A_RSTC_EXTWAKE1 (_UL_(1) << 1) 130 #define PIN_PA02A_RSTC_EXTWAKE2 _L_(2) /**< \brief RSTC signal: EXTWAKE2 on PA02 mux A */ 131 #define MUX_PA02A_RSTC_EXTWAKE2 _L_(0) 132 #define PINMUX_PA02A_RSTC_EXTWAKE2 ((PIN_PA02A_RSTC_EXTWAKE2 << 16) | MUX_PA02A_RSTC_EXTWAKE2) 133 #define PORT_PA02A_RSTC_EXTWAKE2 (_UL_(1) << 2) 134 #define PIN_PA03A_RSTC_EXTWAKE3 _L_(3) /**< \brief RSTC signal: EXTWAKE3 on PA03 mux A */ 135 #define MUX_PA03A_RSTC_EXTWAKE3 _L_(0) 136 #define PINMUX_PA03A_RSTC_EXTWAKE3 ((PIN_PA03A_RSTC_EXTWAKE3 << 16) | MUX_PA03A_RSTC_EXTWAKE3) 137 #define PORT_PA03A_RSTC_EXTWAKE3 (_UL_(1) << 3) 138 #define PIN_PA04A_RSTC_EXTWAKE4 _L_(4) /**< \brief RSTC signal: EXTWAKE4 on PA04 mux A */ 139 #define MUX_PA04A_RSTC_EXTWAKE4 _L_(0) 140 #define PINMUX_PA04A_RSTC_EXTWAKE4 ((PIN_PA04A_RSTC_EXTWAKE4 << 16) | MUX_PA04A_RSTC_EXTWAKE4) 141 #define PORT_PA04A_RSTC_EXTWAKE4 (_UL_(1) << 4) 142 #define PIN_PA05A_RSTC_EXTWAKE5 _L_(5) /**< \brief RSTC signal: EXTWAKE5 on PA05 mux A */ 143 #define MUX_PA05A_RSTC_EXTWAKE5 _L_(0) 144 #define PINMUX_PA05A_RSTC_EXTWAKE5 ((PIN_PA05A_RSTC_EXTWAKE5 << 16) | MUX_PA05A_RSTC_EXTWAKE5) 145 #define PORT_PA05A_RSTC_EXTWAKE5 (_UL_(1) << 5) 146 #define PIN_PA06A_RSTC_EXTWAKE6 _L_(6) /**< \brief RSTC signal: EXTWAKE6 on PA06 mux A */ 147 #define MUX_PA06A_RSTC_EXTWAKE6 _L_(0) 148 #define PINMUX_PA06A_RSTC_EXTWAKE6 ((PIN_PA06A_RSTC_EXTWAKE6 << 16) | MUX_PA06A_RSTC_EXTWAKE6) 149 #define PORT_PA06A_RSTC_EXTWAKE6 (_UL_(1) << 6) 150 #define PIN_PA07A_RSTC_EXTWAKE7 _L_(7) /**< \brief RSTC signal: EXTWAKE7 on PA07 mux A */ 151 #define MUX_PA07A_RSTC_EXTWAKE7 _L_(0) 152 #define PINMUX_PA07A_RSTC_EXTWAKE7 ((PIN_PA07A_RSTC_EXTWAKE7 << 16) | MUX_PA07A_RSTC_EXTWAKE7) 153 #define PORT_PA07A_RSTC_EXTWAKE7 (_UL_(1) << 7) 154 #define PIN_PA08A_RSTC_EXTWAKE8 _L_(8) /**< \brief RSTC signal: EXTWAKE8 on PA08 mux A */ 155 #define MUX_PA08A_RSTC_EXTWAKE8 _L_(0) 156 #define PINMUX_PA08A_RSTC_EXTWAKE8 ((PIN_PA08A_RSTC_EXTWAKE8 << 16) | MUX_PA08A_RSTC_EXTWAKE8) 157 #define PORT_PA08A_RSTC_EXTWAKE8 (_UL_(1) << 8) 158 #define PIN_PA09A_RSTC_EXTWAKE9 _L_(9) /**< \brief RSTC signal: EXTWAKE9 on PA09 mux A */ 159 #define MUX_PA09A_RSTC_EXTWAKE9 _L_(0) 160 #define PINMUX_PA09A_RSTC_EXTWAKE9 ((PIN_PA09A_RSTC_EXTWAKE9 << 16) | MUX_PA09A_RSTC_EXTWAKE9) 161 #define PORT_PA09A_RSTC_EXTWAKE9 (_UL_(1) << 9) 162 #define PIN_PA10A_RSTC_EXTWAKE10 _L_(10) /**< \brief RSTC signal: EXTWAKE10 on PA10 mux A */ 163 #define MUX_PA10A_RSTC_EXTWAKE10 _L_(0) 164 #define PINMUX_PA10A_RSTC_EXTWAKE10 ((PIN_PA10A_RSTC_EXTWAKE10 << 16) | MUX_PA10A_RSTC_EXTWAKE10) 165 #define PORT_PA10A_RSTC_EXTWAKE10 (_UL_(1) << 10) 166 #define PIN_PA11A_RSTC_EXTWAKE11 _L_(11) /**< \brief RSTC signal: EXTWAKE11 on PA11 mux A */ 167 #define MUX_PA11A_RSTC_EXTWAKE11 _L_(0) 168 #define PINMUX_PA11A_RSTC_EXTWAKE11 ((PIN_PA11A_RSTC_EXTWAKE11 << 16) | MUX_PA11A_RSTC_EXTWAKE11) 169 #define PORT_PA11A_RSTC_EXTWAKE11 (_UL_(1) << 11) 170 #define PIN_PA12A_RSTC_EXTWAKE12 _L_(12) /**< \brief RSTC signal: EXTWAKE12 on PA12 mux A */ 171 #define MUX_PA12A_RSTC_EXTWAKE12 _L_(0) 172 #define PINMUX_PA12A_RSTC_EXTWAKE12 ((PIN_PA12A_RSTC_EXTWAKE12 << 16) | MUX_PA12A_RSTC_EXTWAKE12) 173 #define PORT_PA12A_RSTC_EXTWAKE12 (_UL_(1) << 12) 174 #define PIN_PA13A_RSTC_EXTWAKE13 _L_(13) /**< \brief RSTC signal: EXTWAKE13 on PA13 mux A */ 175 #define MUX_PA13A_RSTC_EXTWAKE13 _L_(0) 176 #define PINMUX_PA13A_RSTC_EXTWAKE13 ((PIN_PA13A_RSTC_EXTWAKE13 << 16) | MUX_PA13A_RSTC_EXTWAKE13) 177 #define PORT_PA13A_RSTC_EXTWAKE13 (_UL_(1) << 13) 178 #define PIN_PA14A_RSTC_EXTWAKE14 _L_(14) /**< \brief RSTC signal: EXTWAKE14 on PA14 mux A */ 179 #define MUX_PA14A_RSTC_EXTWAKE14 _L_(0) 180 #define PINMUX_PA14A_RSTC_EXTWAKE14 ((PIN_PA14A_RSTC_EXTWAKE14 << 16) | MUX_PA14A_RSTC_EXTWAKE14) 181 #define PORT_PA14A_RSTC_EXTWAKE14 (_UL_(1) << 14) 182 #define PIN_PA15A_RSTC_EXTWAKE15 _L_(15) /**< \brief RSTC signal: EXTWAKE15 on PA15 mux A */ 183 #define MUX_PA15A_RSTC_EXTWAKE15 _L_(0) 184 #define PINMUX_PA15A_RSTC_EXTWAKE15 ((PIN_PA15A_RSTC_EXTWAKE15 << 16) | MUX_PA15A_RSTC_EXTWAKE15) 185 #define PORT_PA15A_RSTC_EXTWAKE15 (_UL_(1) << 15) 186 /* ========== PORT definition for GCLK peripheral ========== */ 187 #define PIN_PB14H_GCLK_IO0 _L_(46) /**< \brief GCLK signal: IO0 on PB14 mux H */ 188 #define MUX_PB14H_GCLK_IO0 _L_(7) 189 #define PINMUX_PB14H_GCLK_IO0 ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0) 190 #define PORT_PB14H_GCLK_IO0 (_UL_(1) << 14) 191 #define PIN_PB22H_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux H */ 192 #define MUX_PB22H_GCLK_IO0 _L_(7) 193 #define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0) 194 #define PORT_PB22H_GCLK_IO0 (_UL_(1) << 22) 195 #define PIN_PA14H_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux H */ 196 #define MUX_PA14H_GCLK_IO0 _L_(7) 197 #define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) 198 #define PORT_PA14H_GCLK_IO0 (_UL_(1) << 14) 199 #define PIN_PA27H_GCLK_IO0 _L_(27) /**< \brief GCLK signal: IO0 on PA27 mux H */ 200 #define MUX_PA27H_GCLK_IO0 _L_(7) 201 #define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) 202 #define PORT_PA27H_GCLK_IO0 (_UL_(1) << 27) 203 #define PIN_PA30H_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux H */ 204 #define MUX_PA30H_GCLK_IO0 _L_(7) 205 #define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) 206 #define PORT_PA30H_GCLK_IO0 (_UL_(1) << 30) 207 #define PIN_PA28H_GCLK_IO0 _L_(28) /**< \brief GCLK signal: IO0 on PA28 mux H */ 208 #define MUX_PA28H_GCLK_IO0 _L_(7) 209 #define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0) 210 #define PORT_PA28H_GCLK_IO0 (_UL_(1) << 28) 211 #define PIN_PB15H_GCLK_IO1 _L_(47) /**< \brief GCLK signal: IO1 on PB15 mux H */ 212 #define MUX_PB15H_GCLK_IO1 _L_(7) 213 #define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1) 214 #define PORT_PB15H_GCLK_IO1 (_UL_(1) << 15) 215 #define PIN_PB23H_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux H */ 216 #define MUX_PB23H_GCLK_IO1 _L_(7) 217 #define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1) 218 #define PORT_PB23H_GCLK_IO1 (_UL_(1) << 23) 219 #define PIN_PA15H_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux H */ 220 #define MUX_PA15H_GCLK_IO1 _L_(7) 221 #define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) 222 #define PORT_PA15H_GCLK_IO1 (_UL_(1) << 15) 223 #define PIN_PA16H_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux H */ 224 #define MUX_PA16H_GCLK_IO2 _L_(7) 225 #define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) 226 #define PORT_PA16H_GCLK_IO2 (_UL_(1) << 16) 227 #define PIN_PA17H_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux H */ 228 #define MUX_PA17H_GCLK_IO3 _L_(7) 229 #define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) 230 #define PORT_PA17H_GCLK_IO3 (_UL_(1) << 17) 231 #define PIN_PA10H_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux H */ 232 #define MUX_PA10H_GCLK_IO4 _L_(7) 233 #define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) 234 #define PORT_PA10H_GCLK_IO4 (_UL_(1) << 10) 235 #define PIN_PA20H_GCLK_IO4 _L_(20) /**< \brief GCLK signal: IO4 on PA20 mux H */ 236 #define MUX_PA20H_GCLK_IO4 _L_(7) 237 #define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4) 238 #define PORT_PA20H_GCLK_IO4 (_UL_(1) << 20) 239 #define PIN_PB10H_GCLK_IO4 _L_(42) /**< \brief GCLK signal: IO4 on PB10 mux H */ 240 #define MUX_PB10H_GCLK_IO4 _L_(7) 241 #define PINMUX_PB10H_GCLK_IO4 ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4) 242 #define PORT_PB10H_GCLK_IO4 (_UL_(1) << 10) 243 #define PIN_PA11H_GCLK_IO5 _L_(11) /**< \brief GCLK signal: IO5 on PA11 mux H */ 244 #define MUX_PA11H_GCLK_IO5 _L_(7) 245 #define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) 246 #define PORT_PA11H_GCLK_IO5 (_UL_(1) << 11) 247 #define PIN_PA21H_GCLK_IO5 _L_(21) /**< \brief GCLK signal: IO5 on PA21 mux H */ 248 #define MUX_PA21H_GCLK_IO5 _L_(7) 249 #define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5) 250 #define PORT_PA21H_GCLK_IO5 (_UL_(1) << 21) 251 #define PIN_PB11H_GCLK_IO5 _L_(43) /**< \brief GCLK signal: IO5 on PB11 mux H */ 252 #define MUX_PB11H_GCLK_IO5 _L_(7) 253 #define PINMUX_PB11H_GCLK_IO5 ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5) 254 #define PORT_PB11H_GCLK_IO5 (_UL_(1) << 11) 255 #define PIN_PA22H_GCLK_IO6 _L_(22) /**< \brief GCLK signal: IO6 on PA22 mux H */ 256 #define MUX_PA22H_GCLK_IO6 _L_(7) 257 #define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6) 258 #define PORT_PA22H_GCLK_IO6 (_UL_(1) << 22) 259 #define PIN_PB12H_GCLK_IO6 _L_(44) /**< \brief GCLK signal: IO6 on PB12 mux H */ 260 #define MUX_PB12H_GCLK_IO6 _L_(7) 261 #define PINMUX_PB12H_GCLK_IO6 ((PIN_PB12H_GCLK_IO6 << 16) | MUX_PB12H_GCLK_IO6) 262 #define PORT_PB12H_GCLK_IO6 (_UL_(1) << 12) 263 #define PIN_PA23H_GCLK_IO7 _L_(23) /**< \brief GCLK signal: IO7 on PA23 mux H */ 264 #define MUX_PA23H_GCLK_IO7 _L_(7) 265 #define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7) 266 #define PORT_PA23H_GCLK_IO7 (_UL_(1) << 23) 267 #define PIN_PB13H_GCLK_IO7 _L_(45) /**< \brief GCLK signal: IO7 on PB13 mux H */ 268 #define MUX_PB13H_GCLK_IO7 _L_(7) 269 #define PINMUX_PB13H_GCLK_IO7 ((PIN_PB13H_GCLK_IO7 << 16) | MUX_PB13H_GCLK_IO7) 270 #define PORT_PB13H_GCLK_IO7 (_UL_(1) << 13) 271 /* ========== PORT definition for EIC peripheral ========== */ 272 #define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */ 273 #define MUX_PA16A_EIC_EXTINT0 _L_(0) 274 #define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) 275 #define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16) 276 #define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ 277 #define PIN_PB00A_EIC_EXTINT0 _L_(32) /**< \brief EIC signal: EXTINT0 on PB00 mux A */ 278 #define MUX_PB00A_EIC_EXTINT0 _L_(0) 279 #define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) 280 #define PORT_PB00A_EIC_EXTINT0 (_UL_(1) << 0) 281 #define PIN_PB00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB00 External Interrupt Line */ 282 #define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */ 283 #define MUX_PA00A_EIC_EXTINT0 _L_(0) 284 #define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) 285 #define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0) 286 #define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */ 287 #define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */ 288 #define MUX_PA17A_EIC_EXTINT1 _L_(0) 289 #define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) 290 #define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17) 291 #define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ 292 #define PIN_PB01A_EIC_EXTINT1 _L_(33) /**< \brief EIC signal: EXTINT1 on PB01 mux A */ 293 #define MUX_PB01A_EIC_EXTINT1 _L_(0) 294 #define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) 295 #define PORT_PB01A_EIC_EXTINT1 (_UL_(1) << 1) 296 #define PIN_PB01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB01 External Interrupt Line */ 297 #define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */ 298 #define MUX_PA01A_EIC_EXTINT1 _L_(0) 299 #define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) 300 #define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1) 301 #define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */ 302 #define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */ 303 #define MUX_PA02A_EIC_EXTINT2 _L_(0) 304 #define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) 305 #define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2) 306 #define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */ 307 #define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */ 308 #define MUX_PA18A_EIC_EXTINT2 _L_(0) 309 #define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) 310 #define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18) 311 #define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ 312 #define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */ 313 #define MUX_PB02A_EIC_EXTINT2 _L_(0) 314 #define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) 315 #define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2) 316 #define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */ 317 #define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */ 318 #define MUX_PA03A_EIC_EXTINT3 _L_(0) 319 #define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) 320 #define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3) 321 #define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */ 322 #define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */ 323 #define MUX_PA19A_EIC_EXTINT3 _L_(0) 324 #define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) 325 #define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19) 326 #define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ 327 #define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */ 328 #define MUX_PB03A_EIC_EXTINT3 _L_(0) 329 #define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) 330 #define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3) 331 #define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */ 332 #define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */ 333 #define MUX_PA04A_EIC_EXTINT4 _L_(0) 334 #define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) 335 #define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4) 336 #define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */ 337 #define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */ 338 #define MUX_PA20A_EIC_EXTINT4 _L_(0) 339 #define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) 340 #define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20) 341 #define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */ 342 #define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */ 343 #define MUX_PA05A_EIC_EXTINT5 _L_(0) 344 #define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) 345 #define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5) 346 #define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */ 347 #define PIN_PA21A_EIC_EXTINT5 _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */ 348 #define MUX_PA21A_EIC_EXTINT5 _L_(0) 349 #define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) 350 #define PORT_PA21A_EIC_EXTINT5 (_UL_(1) << 21) 351 #define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */ 352 #define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */ 353 #define MUX_PA06A_EIC_EXTINT6 _L_(0) 354 #define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) 355 #define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6) 356 #define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ 357 #define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */ 358 #define MUX_PA22A_EIC_EXTINT6 _L_(0) 359 #define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) 360 #define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22) 361 #define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */ 362 #define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */ 363 #define MUX_PB22A_EIC_EXTINT6 _L_(0) 364 #define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) 365 #define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22) 366 #define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */ 367 #define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */ 368 #define MUX_PA07A_EIC_EXTINT7 _L_(0) 369 #define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) 370 #define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7) 371 #define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ 372 #define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */ 373 #define MUX_PA23A_EIC_EXTINT7 _L_(0) 374 #define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) 375 #define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23) 376 #define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */ 377 #define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */ 378 #define MUX_PB23A_EIC_EXTINT7 _L_(0) 379 #define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) 380 #define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23) 381 #define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */ 382 #define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */ 383 #define MUX_PB08A_EIC_EXTINT8 _L_(0) 384 #define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) 385 #define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8) 386 #define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */ 387 #define PIN_PA28A_EIC_EXTINT8 _L_(28) /**< \brief EIC signal: EXTINT8 on PA28 mux A */ 388 #define MUX_PA28A_EIC_EXTINT8 _L_(0) 389 #define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8) 390 #define PORT_PA28A_EIC_EXTINT8 (_UL_(1) << 28) 391 #define PIN_PA28A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PA28 External Interrupt Line */ 392 #define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */ 393 #define MUX_PA09A_EIC_EXTINT9 _L_(0) 394 #define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) 395 #define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9) 396 #define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */ 397 #define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */ 398 #define MUX_PB09A_EIC_EXTINT9 _L_(0) 399 #define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) 400 #define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9) 401 #define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */ 402 #define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */ 403 #define MUX_PA10A_EIC_EXTINT10 _L_(0) 404 #define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) 405 #define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10) 406 #define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */ 407 #define PIN_PA30A_EIC_EXTINT10 _L_(30) /**< \brief EIC signal: EXTINT10 on PA30 mux A */ 408 #define MUX_PA30A_EIC_EXTINT10 _L_(0) 409 #define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) 410 #define PORT_PA30A_EIC_EXTINT10 (_UL_(1) << 30) 411 #define PIN_PA30A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */ 412 #define PIN_PB10A_EIC_EXTINT10 _L_(42) /**< \brief EIC signal: EXTINT10 on PB10 mux A */ 413 #define MUX_PB10A_EIC_EXTINT10 _L_(0) 414 #define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) 415 #define PORT_PB10A_EIC_EXTINT10 (_UL_(1) << 10) 416 #define PIN_PB10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PB10 External Interrupt Line */ 417 #define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */ 418 #define MUX_PA11A_EIC_EXTINT11 _L_(0) 419 #define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) 420 #define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11) 421 #define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */ 422 #define PIN_PA31A_EIC_EXTINT11 _L_(31) /**< \brief EIC signal: EXTINT11 on PA31 mux A */ 423 #define MUX_PA31A_EIC_EXTINT11 _L_(0) 424 #define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) 425 #define PORT_PA31A_EIC_EXTINT11 (_UL_(1) << 31) 426 #define PIN_PA31A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */ 427 #define PIN_PB11A_EIC_EXTINT11 _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */ 428 #define MUX_PB11A_EIC_EXTINT11 _L_(0) 429 #define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) 430 #define PORT_PB11A_EIC_EXTINT11 (_UL_(1) << 11) 431 #define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */ 432 #define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */ 433 #define MUX_PA12A_EIC_EXTINT12 _L_(0) 434 #define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) 435 #define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12) 436 #define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */ 437 #define PIN_PA24A_EIC_EXTINT12 _L_(24) /**< \brief EIC signal: EXTINT12 on PA24 mux A */ 438 #define MUX_PA24A_EIC_EXTINT12 _L_(0) 439 #define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) 440 #define PORT_PA24A_EIC_EXTINT12 (_UL_(1) << 24) 441 #define PIN_PA24A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */ 442 #define PIN_PB12A_EIC_EXTINT12 _L_(44) /**< \brief EIC signal: EXTINT12 on PB12 mux A */ 443 #define MUX_PB12A_EIC_EXTINT12 _L_(0) 444 #define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) 445 #define PORT_PB12A_EIC_EXTINT12 (_UL_(1) << 12) 446 #define PIN_PB12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PB12 External Interrupt Line */ 447 #define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */ 448 #define MUX_PA13A_EIC_EXTINT13 _L_(0) 449 #define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) 450 #define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13) 451 #define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */ 452 #define PIN_PA25A_EIC_EXTINT13 _L_(25) /**< \brief EIC signal: EXTINT13 on PA25 mux A */ 453 #define MUX_PA25A_EIC_EXTINT13 _L_(0) 454 #define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) 455 #define PORT_PA25A_EIC_EXTINT13 (_UL_(1) << 25) 456 #define PIN_PA25A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */ 457 #define PIN_PB13A_EIC_EXTINT13 _L_(45) /**< \brief EIC signal: EXTINT13 on PB13 mux A */ 458 #define MUX_PB13A_EIC_EXTINT13 _L_(0) 459 #define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) 460 #define PORT_PB13A_EIC_EXTINT13 (_UL_(1) << 13) 461 #define PIN_PB13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PB13 External Interrupt Line */ 462 #define PIN_PB14A_EIC_EXTINT14 _L_(46) /**< \brief EIC signal: EXTINT14 on PB14 mux A */ 463 #define MUX_PB14A_EIC_EXTINT14 _L_(0) 464 #define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) 465 #define PORT_PB14A_EIC_EXTINT14 (_UL_(1) << 14) 466 #define PIN_PB14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB14 External Interrupt Line */ 467 #define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */ 468 #define MUX_PA14A_EIC_EXTINT14 _L_(0) 469 #define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) 470 #define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14) 471 #define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */ 472 #define PIN_PA27A_EIC_EXTINT15 _L_(27) /**< \brief EIC signal: EXTINT15 on PA27 mux A */ 473 #define MUX_PA27A_EIC_EXTINT15 _L_(0) 474 #define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) 475 #define PORT_PA27A_EIC_EXTINT15 (_UL_(1) << 27) 476 #define PIN_PA27A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */ 477 #define PIN_PB15A_EIC_EXTINT15 _L_(47) /**< \brief EIC signal: EXTINT15 on PB15 mux A */ 478 #define MUX_PB15A_EIC_EXTINT15 _L_(0) 479 #define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) 480 #define PORT_PB15A_EIC_EXTINT15 (_UL_(1) << 15) 481 #define PIN_PB15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB15 External Interrupt Line */ 482 #define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */ 483 #define MUX_PA15A_EIC_EXTINT15 _L_(0) 484 #define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) 485 #define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15) 486 #define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */ 487 #define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */ 488 #define MUX_PA08A_EIC_NMI _L_(0) 489 #define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) 490 #define PORT_PA08A_EIC_NMI (_UL_(1) << 8) 491 /* ========== PORT definition for SERCOM0 peripheral ========== */ 492 #define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ 493 #define MUX_PA04D_SERCOM0_PAD0 _L_(3) 494 #define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) 495 #define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4) 496 #define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ 497 #define MUX_PA08C_SERCOM0_PAD0 _L_(2) 498 #define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) 499 #define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8) 500 #define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ 501 #define MUX_PA05D_SERCOM0_PAD1 _L_(3) 502 #define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) 503 #define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5) 504 #define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ 505 #define MUX_PA09C_SERCOM0_PAD1 _L_(2) 506 #define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) 507 #define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9) 508 #define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ 509 #define MUX_PA06D_SERCOM0_PAD2 _L_(3) 510 #define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) 511 #define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6) 512 #define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ 513 #define MUX_PA10C_SERCOM0_PAD2 _L_(2) 514 #define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) 515 #define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10) 516 #define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ 517 #define MUX_PA07D_SERCOM0_PAD3 _L_(3) 518 #define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) 519 #define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7) 520 #define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ 521 #define MUX_PA11C_SERCOM0_PAD3 _L_(2) 522 #define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) 523 #define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11) 524 /* ========== PORT definition for SERCOM1 peripheral ========== */ 525 #define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ 526 #define MUX_PA16C_SERCOM1_PAD0 _L_(2) 527 #define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) 528 #define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16) 529 #define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ 530 #define MUX_PA00D_SERCOM1_PAD0 _L_(3) 531 #define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) 532 #define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0) 533 #define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ 534 #define MUX_PA17C_SERCOM1_PAD1 _L_(2) 535 #define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) 536 #define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17) 537 #define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ 538 #define MUX_PA01D_SERCOM1_PAD1 _L_(3) 539 #define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) 540 #define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1) 541 #define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ 542 #define MUX_PA30D_SERCOM1_PAD2 _L_(3) 543 #define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) 544 #define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30) 545 #define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ 546 #define MUX_PA18C_SERCOM1_PAD2 _L_(2) 547 #define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) 548 #define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18) 549 #define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ 550 #define MUX_PA31D_SERCOM1_PAD3 _L_(3) 551 #define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) 552 #define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31) 553 #define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ 554 #define MUX_PA19C_SERCOM1_PAD3 _L_(2) 555 #define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) 556 #define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19) 557 /* ========== PORT definition for SERCOM2 peripheral ========== */ 558 #define PIN_PA08D_SERCOM2_PAD0 _L_(8) /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ 559 #define MUX_PA08D_SERCOM2_PAD0 _L_(3) 560 #define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) 561 #define PORT_PA08D_SERCOM2_PAD0 (_UL_(1) << 8) 562 #define PIN_PA12C_SERCOM2_PAD0 _L_(12) /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ 563 #define MUX_PA12C_SERCOM2_PAD0 _L_(2) 564 #define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) 565 #define PORT_PA12C_SERCOM2_PAD0 (_UL_(1) << 12) 566 #define PIN_PA09D_SERCOM2_PAD1 _L_(9) /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ 567 #define MUX_PA09D_SERCOM2_PAD1 _L_(3) 568 #define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) 569 #define PORT_PA09D_SERCOM2_PAD1 (_UL_(1) << 9) 570 #define PIN_PA13C_SERCOM2_PAD1 _L_(13) /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ 571 #define MUX_PA13C_SERCOM2_PAD1 _L_(2) 572 #define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) 573 #define PORT_PA13C_SERCOM2_PAD1 (_UL_(1) << 13) 574 #define PIN_PA10D_SERCOM2_PAD2 _L_(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ 575 #define MUX_PA10D_SERCOM2_PAD2 _L_(3) 576 #define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) 577 #define PORT_PA10D_SERCOM2_PAD2 (_UL_(1) << 10) 578 #define PIN_PA14C_SERCOM2_PAD2 _L_(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ 579 #define MUX_PA14C_SERCOM2_PAD2 _L_(2) 580 #define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) 581 #define PORT_PA14C_SERCOM2_PAD2 (_UL_(1) << 14) 582 #define PIN_PA11D_SERCOM2_PAD3 _L_(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ 583 #define MUX_PA11D_SERCOM2_PAD3 _L_(3) 584 #define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) 585 #define PORT_PA11D_SERCOM2_PAD3 (_UL_(1) << 11) 586 #define PIN_PA15C_SERCOM2_PAD3 _L_(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ 587 #define MUX_PA15C_SERCOM2_PAD3 _L_(2) 588 #define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) 589 #define PORT_PA15C_SERCOM2_PAD3 (_UL_(1) << 15) 590 /* ========== PORT definition for SERCOM3 peripheral ========== */ 591 #define PIN_PA16D_SERCOM3_PAD0 _L_(16) /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ 592 #define MUX_PA16D_SERCOM3_PAD0 _L_(3) 593 #define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) 594 #define PORT_PA16D_SERCOM3_PAD0 (_UL_(1) << 16) 595 #define PIN_PA22C_SERCOM3_PAD0 _L_(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ 596 #define MUX_PA22C_SERCOM3_PAD0 _L_(2) 597 #define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) 598 #define PORT_PA22C_SERCOM3_PAD0 (_UL_(1) << 22) 599 #define PIN_PA17D_SERCOM3_PAD1 _L_(17) /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ 600 #define MUX_PA17D_SERCOM3_PAD1 _L_(3) 601 #define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) 602 #define PORT_PA17D_SERCOM3_PAD1 (_UL_(1) << 17) 603 #define PIN_PA23C_SERCOM3_PAD1 _L_(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ 604 #define MUX_PA23C_SERCOM3_PAD1 _L_(2) 605 #define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) 606 #define PORT_PA23C_SERCOM3_PAD1 (_UL_(1) << 23) 607 #define PIN_PA18D_SERCOM3_PAD2 _L_(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ 608 #define MUX_PA18D_SERCOM3_PAD2 _L_(3) 609 #define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) 610 #define PORT_PA18D_SERCOM3_PAD2 (_UL_(1) << 18) 611 #define PIN_PA20D_SERCOM3_PAD2 _L_(20) /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ 612 #define MUX_PA20D_SERCOM3_PAD2 _L_(3) 613 #define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) 614 #define PORT_PA20D_SERCOM3_PAD2 (_UL_(1) << 20) 615 #define PIN_PA24C_SERCOM3_PAD2 _L_(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ 616 #define MUX_PA24C_SERCOM3_PAD2 _L_(2) 617 #define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) 618 #define PORT_PA24C_SERCOM3_PAD2 (_UL_(1) << 24) 619 #define PIN_PA19D_SERCOM3_PAD3 _L_(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ 620 #define MUX_PA19D_SERCOM3_PAD3 _L_(3) 621 #define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) 622 #define PORT_PA19D_SERCOM3_PAD3 (_UL_(1) << 19) 623 #define PIN_PA21D_SERCOM3_PAD3 _L_(21) /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ 624 #define MUX_PA21D_SERCOM3_PAD3 _L_(3) 625 #define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) 626 #define PORT_PA21D_SERCOM3_PAD3 (_UL_(1) << 21) 627 #define PIN_PA25C_SERCOM3_PAD3 _L_(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ 628 #define MUX_PA25C_SERCOM3_PAD3 _L_(2) 629 #define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) 630 #define PORT_PA25C_SERCOM3_PAD3 (_UL_(1) << 25) 631 /* ========== PORT definition for SERCOM4 peripheral ========== */ 632 #define PIN_PA12D_SERCOM4_PAD0 _L_(12) /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */ 633 #define MUX_PA12D_SERCOM4_PAD0 _L_(3) 634 #define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0) 635 #define PORT_PA12D_SERCOM4_PAD0 (_UL_(1) << 12) 636 #define PIN_PB08D_SERCOM4_PAD0 _L_(40) /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ 637 #define MUX_PB08D_SERCOM4_PAD0 _L_(3) 638 #define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) 639 #define PORT_PB08D_SERCOM4_PAD0 (_UL_(1) << 8) 640 #define PIN_PB12C_SERCOM4_PAD0 _L_(44) /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */ 641 #define MUX_PB12C_SERCOM4_PAD0 _L_(2) 642 #define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0) 643 #define PORT_PB12C_SERCOM4_PAD0 (_UL_(1) << 12) 644 #define PIN_PA13D_SERCOM4_PAD1 _L_(13) /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */ 645 #define MUX_PA13D_SERCOM4_PAD1 _L_(3) 646 #define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1) 647 #define PORT_PA13D_SERCOM4_PAD1 (_UL_(1) << 13) 648 #define PIN_PB09D_SERCOM4_PAD1 _L_(41) /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ 649 #define MUX_PB09D_SERCOM4_PAD1 _L_(3) 650 #define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) 651 #define PORT_PB09D_SERCOM4_PAD1 (_UL_(1) << 9) 652 #define PIN_PB13C_SERCOM4_PAD1 _L_(45) /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */ 653 #define MUX_PB13C_SERCOM4_PAD1 _L_(2) 654 #define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1) 655 #define PORT_PB13C_SERCOM4_PAD1 (_UL_(1) << 13) 656 #define PIN_PA14D_SERCOM4_PAD2 _L_(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ 657 #define MUX_PA14D_SERCOM4_PAD2 _L_(3) 658 #define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) 659 #define PORT_PA14D_SERCOM4_PAD2 (_UL_(1) << 14) 660 #define PIN_PB10D_SERCOM4_PAD2 _L_(42) /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ 661 #define MUX_PB10D_SERCOM4_PAD2 _L_(3) 662 #define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) 663 #define PORT_PB10D_SERCOM4_PAD2 (_UL_(1) << 10) 664 #define PIN_PB14C_SERCOM4_PAD2 _L_(46) /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */ 665 #define MUX_PB14C_SERCOM4_PAD2 _L_(2) 666 #define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) 667 #define PORT_PB14C_SERCOM4_PAD2 (_UL_(1) << 14) 668 #define PIN_PA15D_SERCOM4_PAD3 _L_(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ 669 #define MUX_PA15D_SERCOM4_PAD3 _L_(3) 670 #define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) 671 #define PORT_PA15D_SERCOM4_PAD3 (_UL_(1) << 15) 672 #define PIN_PB11D_SERCOM4_PAD3 _L_(43) /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ 673 #define MUX_PB11D_SERCOM4_PAD3 _L_(3) 674 #define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) 675 #define PORT_PB11D_SERCOM4_PAD3 (_UL_(1) << 11) 676 #define PIN_PB15C_SERCOM4_PAD3 _L_(47) /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */ 677 #define MUX_PB15C_SERCOM4_PAD3 _L_(2) 678 #define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) 679 #define PORT_PB15C_SERCOM4_PAD3 (_UL_(1) << 15) 680 /* ========== PORT definition for SERCOM5 peripheral ========== */ 681 #define PIN_PA22D_SERCOM5_PAD0 _L_(22) /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */ 682 #define MUX_PA22D_SERCOM5_PAD0 _L_(3) 683 #define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0) 684 #define PORT_PA22D_SERCOM5_PAD0 (_UL_(1) << 22) 685 #define PIN_PB02D_SERCOM5_PAD0 _L_(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ 686 #define MUX_PB02D_SERCOM5_PAD0 _L_(3) 687 #define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) 688 #define PORT_PB02D_SERCOM5_PAD0 (_UL_(1) << 2) 689 #define PIN_PA23D_SERCOM5_PAD1 _L_(23) /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */ 690 #define MUX_PA23D_SERCOM5_PAD1 _L_(3) 691 #define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1) 692 #define PORT_PA23D_SERCOM5_PAD1 (_UL_(1) << 23) 693 #define PIN_PB03D_SERCOM5_PAD1 _L_(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ 694 #define MUX_PB03D_SERCOM5_PAD1 _L_(3) 695 #define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) 696 #define PORT_PB03D_SERCOM5_PAD1 (_UL_(1) << 3) 697 #define PIN_PA24D_SERCOM5_PAD2 _L_(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ 698 #define MUX_PA24D_SERCOM5_PAD2 _L_(3) 699 #define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) 700 #define PORT_PA24D_SERCOM5_PAD2 (_UL_(1) << 24) 701 #define PIN_PB00D_SERCOM5_PAD2 _L_(32) /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ 702 #define MUX_PB00D_SERCOM5_PAD2 _L_(3) 703 #define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) 704 #define PORT_PB00D_SERCOM5_PAD2 (_UL_(1) << 0) 705 #define PIN_PB22D_SERCOM5_PAD2 _L_(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ 706 #define MUX_PB22D_SERCOM5_PAD2 _L_(3) 707 #define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) 708 #define PORT_PB22D_SERCOM5_PAD2 (_UL_(1) << 22) 709 #define PIN_PA20C_SERCOM5_PAD2 _L_(20) /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ 710 #define MUX_PA20C_SERCOM5_PAD2 _L_(2) 711 #define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) 712 #define PORT_PA20C_SERCOM5_PAD2 (_UL_(1) << 20) 713 #define PIN_PA25D_SERCOM5_PAD3 _L_(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ 714 #define MUX_PA25D_SERCOM5_PAD3 _L_(3) 715 #define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) 716 #define PORT_PA25D_SERCOM5_PAD3 (_UL_(1) << 25) 717 #define PIN_PB01D_SERCOM5_PAD3 _L_(33) /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */ 718 #define MUX_PB01D_SERCOM5_PAD3 _L_(3) 719 #define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) 720 #define PORT_PB01D_SERCOM5_PAD3 (_UL_(1) << 1) 721 #define PIN_PB23D_SERCOM5_PAD3 _L_(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ 722 #define MUX_PB23D_SERCOM5_PAD3 _L_(3) 723 #define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) 724 #define PORT_PB23D_SERCOM5_PAD3 (_UL_(1) << 23) 725 #define PIN_PA21C_SERCOM5_PAD3 _L_(21) /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ 726 #define MUX_PA21C_SERCOM5_PAD3 _L_(2) 727 #define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) 728 #define PORT_PA21C_SERCOM5_PAD3 (_UL_(1) << 21) 729 /* ========== PORT definition for CAN0 peripheral ========== */ 730 #define PIN_PA25G_CAN0_RX _L_(25) /**< \brief CAN0 signal: RX on PA25 mux G */ 731 #define MUX_PA25G_CAN0_RX _L_(6) 732 #define PINMUX_PA25G_CAN0_RX ((PIN_PA25G_CAN0_RX << 16) | MUX_PA25G_CAN0_RX) 733 #define PORT_PA25G_CAN0_RX (_UL_(1) << 25) 734 #define PIN_PB23G_CAN0_RX _L_(55) /**< \brief CAN0 signal: RX on PB23 mux G */ 735 #define MUX_PB23G_CAN0_RX _L_(6) 736 #define PINMUX_PB23G_CAN0_RX ((PIN_PB23G_CAN0_RX << 16) | MUX_PB23G_CAN0_RX) 737 #define PORT_PB23G_CAN0_RX (_UL_(1) << 23) 738 #define PIN_PA24G_CAN0_TX _L_(24) /**< \brief CAN0 signal: TX on PA24 mux G */ 739 #define MUX_PA24G_CAN0_TX _L_(6) 740 #define PINMUX_PA24G_CAN0_TX ((PIN_PA24G_CAN0_TX << 16) | MUX_PA24G_CAN0_TX) 741 #define PORT_PA24G_CAN0_TX (_UL_(1) << 24) 742 #define PIN_PB22G_CAN0_TX _L_(54) /**< \brief CAN0 signal: TX on PB22 mux G */ 743 #define MUX_PB22G_CAN0_TX _L_(6) 744 #define PINMUX_PB22G_CAN0_TX ((PIN_PB22G_CAN0_TX << 16) | MUX_PB22G_CAN0_TX) 745 #define PORT_PB22G_CAN0_TX (_UL_(1) << 22) 746 /* ========== PORT definition for CAN1 peripheral ========== */ 747 #define PIN_PB11G_CAN1_RX _L_(43) /**< \brief CAN1 signal: RX on PB11 mux G */ 748 #define MUX_PB11G_CAN1_RX _L_(6) 749 #define PINMUX_PB11G_CAN1_RX ((PIN_PB11G_CAN1_RX << 16) | MUX_PB11G_CAN1_RX) 750 #define PORT_PB11G_CAN1_RX (_UL_(1) << 11) 751 #define PIN_PB15G_CAN1_RX _L_(47) /**< \brief CAN1 signal: RX on PB15 mux G */ 752 #define MUX_PB15G_CAN1_RX _L_(6) 753 #define PINMUX_PB15G_CAN1_RX ((PIN_PB15G_CAN1_RX << 16) | MUX_PB15G_CAN1_RX) 754 #define PORT_PB15G_CAN1_RX (_UL_(1) << 15) 755 #define PIN_PB10G_CAN1_TX _L_(42) /**< \brief CAN1 signal: TX on PB10 mux G */ 756 #define MUX_PB10G_CAN1_TX _L_(6) 757 #define PINMUX_PB10G_CAN1_TX ((PIN_PB10G_CAN1_TX << 16) | MUX_PB10G_CAN1_TX) 758 #define PORT_PB10G_CAN1_TX (_UL_(1) << 10) 759 #define PIN_PB14G_CAN1_TX _L_(46) /**< \brief CAN1 signal: TX on PB14 mux G */ 760 #define MUX_PB14G_CAN1_TX _L_(6) 761 #define PINMUX_PB14G_CAN1_TX ((PIN_PB14G_CAN1_TX << 16) | MUX_PB14G_CAN1_TX) 762 #define PORT_PB14G_CAN1_TX (_UL_(1) << 14) 763 /* ========== PORT definition for TCC0 peripheral ========== */ 764 #define PIN_PA04E_TCC0_WO0 _L_(4) /**< \brief TCC0 signal: WO0 on PA04 mux E */ 765 #define MUX_PA04E_TCC0_WO0 _L_(4) 766 #define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) 767 #define PORT_PA04E_TCC0_WO0 (_UL_(1) << 4) 768 #define PIN_PA08E_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux E */ 769 #define MUX_PA08E_TCC0_WO0 _L_(4) 770 #define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) 771 #define PORT_PA08E_TCC0_WO0 (_UL_(1) << 8) 772 #define PIN_PA05E_TCC0_WO1 _L_(5) /**< \brief TCC0 signal: WO1 on PA05 mux E */ 773 #define MUX_PA05E_TCC0_WO1 _L_(4) 774 #define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) 775 #define PORT_PA05E_TCC0_WO1 (_UL_(1) << 5) 776 #define PIN_PA09E_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux E */ 777 #define MUX_PA09E_TCC0_WO1 _L_(4) 778 #define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) 779 #define PORT_PA09E_TCC0_WO1 (_UL_(1) << 9) 780 #define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */ 781 #define MUX_PA10F_TCC0_WO2 _L_(5) 782 #define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) 783 #define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10) 784 #define PIN_PA18F_TCC0_WO2 _L_(18) /**< \brief TCC0 signal: WO2 on PA18 mux F */ 785 #define MUX_PA18F_TCC0_WO2 _L_(5) 786 #define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) 787 #define PORT_PA18F_TCC0_WO2 (_UL_(1) << 18) 788 #define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */ 789 #define MUX_PA11F_TCC0_WO3 _L_(5) 790 #define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) 791 #define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11) 792 #define PIN_PA19F_TCC0_WO3 _L_(19) /**< \brief TCC0 signal: WO3 on PA19 mux F */ 793 #define MUX_PA19F_TCC0_WO3 _L_(5) 794 #define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) 795 #define PORT_PA19F_TCC0_WO3 (_UL_(1) << 19) 796 #define PIN_PA22F_TCC0_WO4 _L_(22) /**< \brief TCC0 signal: WO4 on PA22 mux F */ 797 #define MUX_PA22F_TCC0_WO4 _L_(5) 798 #define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) 799 #define PORT_PA22F_TCC0_WO4 (_UL_(1) << 22) 800 #define PIN_PB10F_TCC0_WO4 _L_(42) /**< \brief TCC0 signal: WO4 on PB10 mux F */ 801 #define MUX_PB10F_TCC0_WO4 _L_(5) 802 #define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) 803 #define PORT_PB10F_TCC0_WO4 (_UL_(1) << 10) 804 #define PIN_PA14F_TCC0_WO4 _L_(14) /**< \brief TCC0 signal: WO4 on PA14 mux F */ 805 #define MUX_PA14F_TCC0_WO4 _L_(5) 806 #define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) 807 #define PORT_PA14F_TCC0_WO4 (_UL_(1) << 14) 808 #define PIN_PA15F_TCC0_WO5 _L_(15) /**< \brief TCC0 signal: WO5 on PA15 mux F */ 809 #define MUX_PA15F_TCC0_WO5 _L_(5) 810 #define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) 811 #define PORT_PA15F_TCC0_WO5 (_UL_(1) << 15) 812 #define PIN_PA23F_TCC0_WO5 _L_(23) /**< \brief TCC0 signal: WO5 on PA23 mux F */ 813 #define MUX_PA23F_TCC0_WO5 _L_(5) 814 #define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) 815 #define PORT_PA23F_TCC0_WO5 (_UL_(1) << 23) 816 #define PIN_PB11F_TCC0_WO5 _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */ 817 #define MUX_PB11F_TCC0_WO5 _L_(5) 818 #define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) 819 #define PORT_PB11F_TCC0_WO5 (_UL_(1) << 11) 820 #define PIN_PA12F_TCC0_WO6 _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */ 821 #define MUX_PA12F_TCC0_WO6 _L_(5) 822 #define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) 823 #define PORT_PA12F_TCC0_WO6 (_UL_(1) << 12) 824 #define PIN_PA16F_TCC0_WO6 _L_(16) /**< \brief TCC0 signal: WO6 on PA16 mux F */ 825 #define MUX_PA16F_TCC0_WO6 _L_(5) 826 #define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) 827 #define PORT_PA16F_TCC0_WO6 (_UL_(1) << 16) 828 #define PIN_PA20F_TCC0_WO6 _L_(20) /**< \brief TCC0 signal: WO6 on PA20 mux F */ 829 #define MUX_PA20F_TCC0_WO6 _L_(5) 830 #define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6) 831 #define PORT_PA20F_TCC0_WO6 (_UL_(1) << 20) 832 #define PIN_PB12F_TCC0_WO6 _L_(44) /**< \brief TCC0 signal: WO6 on PB12 mux F */ 833 #define MUX_PB12F_TCC0_WO6 _L_(5) 834 #define PINMUX_PB12F_TCC0_WO6 ((PIN_PB12F_TCC0_WO6 << 16) | MUX_PB12F_TCC0_WO6) 835 #define PORT_PB12F_TCC0_WO6 (_UL_(1) << 12) 836 #define PIN_PA13F_TCC0_WO7 _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */ 837 #define MUX_PA13F_TCC0_WO7 _L_(5) 838 #define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) 839 #define PORT_PA13F_TCC0_WO7 (_UL_(1) << 13) 840 #define PIN_PA17F_TCC0_WO7 _L_(17) /**< \brief TCC0 signal: WO7 on PA17 mux F */ 841 #define MUX_PA17F_TCC0_WO7 _L_(5) 842 #define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) 843 #define PORT_PA17F_TCC0_WO7 (_UL_(1) << 17) 844 #define PIN_PA21F_TCC0_WO7 _L_(21) /**< \brief TCC0 signal: WO7 on PA21 mux F */ 845 #define MUX_PA21F_TCC0_WO7 _L_(5) 846 #define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7) 847 #define PORT_PA21F_TCC0_WO7 (_UL_(1) << 21) 848 #define PIN_PB13F_TCC0_WO7 _L_(45) /**< \brief TCC0 signal: WO7 on PB13 mux F */ 849 #define MUX_PB13F_TCC0_WO7 _L_(5) 850 #define PINMUX_PB13F_TCC0_WO7 ((PIN_PB13F_TCC0_WO7 << 16) | MUX_PB13F_TCC0_WO7) 851 #define PORT_PB13F_TCC0_WO7 (_UL_(1) << 13) 852 /* ========== PORT definition for TCC1 peripheral ========== */ 853 #define PIN_PA06E_TCC1_WO0 _L_(6) /**< \brief TCC1 signal: WO0 on PA06 mux E */ 854 #define MUX_PA06E_TCC1_WO0 _L_(4) 855 #define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) 856 #define PORT_PA06E_TCC1_WO0 (_UL_(1) << 6) 857 #define PIN_PA10E_TCC1_WO0 _L_(10) /**< \brief TCC1 signal: WO0 on PA10 mux E */ 858 #define MUX_PA10E_TCC1_WO0 _L_(4) 859 #define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) 860 #define PORT_PA10E_TCC1_WO0 (_UL_(1) << 10) 861 #define PIN_PA30E_TCC1_WO0 _L_(30) /**< \brief TCC1 signal: WO0 on PA30 mux E */ 862 #define MUX_PA30E_TCC1_WO0 _L_(4) 863 #define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) 864 #define PORT_PA30E_TCC1_WO0 (_UL_(1) << 30) 865 #define PIN_PA07E_TCC1_WO1 _L_(7) /**< \brief TCC1 signal: WO1 on PA07 mux E */ 866 #define MUX_PA07E_TCC1_WO1 _L_(4) 867 #define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) 868 #define PORT_PA07E_TCC1_WO1 (_UL_(1) << 7) 869 #define PIN_PA11E_TCC1_WO1 _L_(11) /**< \brief TCC1 signal: WO1 on PA11 mux E */ 870 #define MUX_PA11E_TCC1_WO1 _L_(4) 871 #define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) 872 #define PORT_PA11E_TCC1_WO1 (_UL_(1) << 11) 873 #define PIN_PA31E_TCC1_WO1 _L_(31) /**< \brief TCC1 signal: WO1 on PA31 mux E */ 874 #define MUX_PA31E_TCC1_WO1 _L_(4) 875 #define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) 876 #define PORT_PA31E_TCC1_WO1 (_UL_(1) << 31) 877 #define PIN_PA08F_TCC1_WO2 _L_(8) /**< \brief TCC1 signal: WO2 on PA08 mux F */ 878 #define MUX_PA08F_TCC1_WO2 _L_(5) 879 #define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2) 880 #define PORT_PA08F_TCC1_WO2 (_UL_(1) << 8) 881 #define PIN_PA24F_TCC1_WO2 _L_(24) /**< \brief TCC1 signal: WO2 on PA24 mux F */ 882 #define MUX_PA24F_TCC1_WO2 _L_(5) 883 #define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) 884 #define PORT_PA24F_TCC1_WO2 (_UL_(1) << 24) 885 #define PIN_PA09F_TCC1_WO3 _L_(9) /**< \brief TCC1 signal: WO3 on PA09 mux F */ 886 #define MUX_PA09F_TCC1_WO3 _L_(5) 887 #define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3) 888 #define PORT_PA09F_TCC1_WO3 (_UL_(1) << 9) 889 #define PIN_PA25F_TCC1_WO3 _L_(25) /**< \brief TCC1 signal: WO3 on PA25 mux F */ 890 #define MUX_PA25F_TCC1_WO3 _L_(5) 891 #define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) 892 #define PORT_PA25F_TCC1_WO3 (_UL_(1) << 25) 893 /* ========== PORT definition for TCC2 peripheral ========== */ 894 #define PIN_PA12E_TCC2_WO0 _L_(12) /**< \brief TCC2 signal: WO0 on PA12 mux E */ 895 #define MUX_PA12E_TCC2_WO0 _L_(4) 896 #define PINMUX_PA12E_TCC2_WO0 ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0) 897 #define PORT_PA12E_TCC2_WO0 (_UL_(1) << 12) 898 #define PIN_PA16E_TCC2_WO0 _L_(16) /**< \brief TCC2 signal: WO0 on PA16 mux E */ 899 #define MUX_PA16E_TCC2_WO0 _L_(4) 900 #define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) 901 #define PORT_PA16E_TCC2_WO0 (_UL_(1) << 16) 902 #define PIN_PA00E_TCC2_WO0 _L_(0) /**< \brief TCC2 signal: WO0 on PA00 mux E */ 903 #define MUX_PA00E_TCC2_WO0 _L_(4) 904 #define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0) 905 #define PORT_PA00E_TCC2_WO0 (_UL_(1) << 0) 906 #define PIN_PA13E_TCC2_WO1 _L_(13) /**< \brief TCC2 signal: WO1 on PA13 mux E */ 907 #define MUX_PA13E_TCC2_WO1 _L_(4) 908 #define PINMUX_PA13E_TCC2_WO1 ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1) 909 #define PORT_PA13E_TCC2_WO1 (_UL_(1) << 13) 910 #define PIN_PA17E_TCC2_WO1 _L_(17) /**< \brief TCC2 signal: WO1 on PA17 mux E */ 911 #define MUX_PA17E_TCC2_WO1 _L_(4) 912 #define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) 913 #define PORT_PA17E_TCC2_WO1 (_UL_(1) << 17) 914 #define PIN_PA01E_TCC2_WO1 _L_(1) /**< \brief TCC2 signal: WO1 on PA01 mux E */ 915 #define MUX_PA01E_TCC2_WO1 _L_(4) 916 #define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1) 917 #define PORT_PA01E_TCC2_WO1 (_UL_(1) << 1) 918 /* ========== PORT definition for TC0 peripheral ========== */ 919 #define PIN_PA22E_TC0_WO0 _L_(22) /**< \brief TC0 signal: WO0 on PA22 mux E */ 920 #define MUX_PA22E_TC0_WO0 _L_(4) 921 #define PINMUX_PA22E_TC0_WO0 ((PIN_PA22E_TC0_WO0 << 16) | MUX_PA22E_TC0_WO0) 922 #define PORT_PA22E_TC0_WO0 (_UL_(1) << 22) 923 #define PIN_PB08E_TC0_WO0 _L_(40) /**< \brief TC0 signal: WO0 on PB08 mux E */ 924 #define MUX_PB08E_TC0_WO0 _L_(4) 925 #define PINMUX_PB08E_TC0_WO0 ((PIN_PB08E_TC0_WO0 << 16) | MUX_PB08E_TC0_WO0) 926 #define PORT_PB08E_TC0_WO0 (_UL_(1) << 8) 927 #define PIN_PB12E_TC0_WO0 _L_(44) /**< \brief TC0 signal: WO0 on PB12 mux E */ 928 #define MUX_PB12E_TC0_WO0 _L_(4) 929 #define PINMUX_PB12E_TC0_WO0 ((PIN_PB12E_TC0_WO0 << 16) | MUX_PB12E_TC0_WO0) 930 #define PORT_PB12E_TC0_WO0 (_UL_(1) << 12) 931 #define PIN_PA23E_TC0_WO1 _L_(23) /**< \brief TC0 signal: WO1 on PA23 mux E */ 932 #define MUX_PA23E_TC0_WO1 _L_(4) 933 #define PINMUX_PA23E_TC0_WO1 ((PIN_PA23E_TC0_WO1 << 16) | MUX_PA23E_TC0_WO1) 934 #define PORT_PA23E_TC0_WO1 (_UL_(1) << 23) 935 #define PIN_PB09E_TC0_WO1 _L_(41) /**< \brief TC0 signal: WO1 on PB09 mux E */ 936 #define MUX_PB09E_TC0_WO1 _L_(4) 937 #define PINMUX_PB09E_TC0_WO1 ((PIN_PB09E_TC0_WO1 << 16) | MUX_PB09E_TC0_WO1) 938 #define PORT_PB09E_TC0_WO1 (_UL_(1) << 9) 939 #define PIN_PB13E_TC0_WO1 _L_(45) /**< \brief TC0 signal: WO1 on PB13 mux E */ 940 #define MUX_PB13E_TC0_WO1 _L_(4) 941 #define PINMUX_PB13E_TC0_WO1 ((PIN_PB13E_TC0_WO1 << 16) | MUX_PB13E_TC0_WO1) 942 #define PORT_PB13E_TC0_WO1 (_UL_(1) << 13) 943 /* ========== PORT definition for TC1 peripheral ========== */ 944 #define PIN_PA24E_TC1_WO0 _L_(24) /**< \brief TC1 signal: WO0 on PA24 mux E */ 945 #define MUX_PA24E_TC1_WO0 _L_(4) 946 #define PINMUX_PA24E_TC1_WO0 ((PIN_PA24E_TC1_WO0 << 16) | MUX_PA24E_TC1_WO0) 947 #define PORT_PA24E_TC1_WO0 (_UL_(1) << 24) 948 #define PIN_PB10E_TC1_WO0 _L_(42) /**< \brief TC1 signal: WO0 on PB10 mux E */ 949 #define MUX_PB10E_TC1_WO0 _L_(4) 950 #define PINMUX_PB10E_TC1_WO0 ((PIN_PB10E_TC1_WO0 << 16) | MUX_PB10E_TC1_WO0) 951 #define PORT_PB10E_TC1_WO0 (_UL_(1) << 10) 952 #define PIN_PB14E_TC1_WO0 _L_(46) /**< \brief TC1 signal: WO0 on PB14 mux E */ 953 #define MUX_PB14E_TC1_WO0 _L_(4) 954 #define PINMUX_PB14E_TC1_WO0 ((PIN_PB14E_TC1_WO0 << 16) | MUX_PB14E_TC1_WO0) 955 #define PORT_PB14E_TC1_WO0 (_UL_(1) << 14) 956 #define PIN_PA25E_TC1_WO1 _L_(25) /**< \brief TC1 signal: WO1 on PA25 mux E */ 957 #define MUX_PA25E_TC1_WO1 _L_(4) 958 #define PINMUX_PA25E_TC1_WO1 ((PIN_PA25E_TC1_WO1 << 16) | MUX_PA25E_TC1_WO1) 959 #define PORT_PA25E_TC1_WO1 (_UL_(1) << 25) 960 #define PIN_PB11E_TC1_WO1 _L_(43) /**< \brief TC1 signal: WO1 on PB11 mux E */ 961 #define MUX_PB11E_TC1_WO1 _L_(4) 962 #define PINMUX_PB11E_TC1_WO1 ((PIN_PB11E_TC1_WO1 << 16) | MUX_PB11E_TC1_WO1) 963 #define PORT_PB11E_TC1_WO1 (_UL_(1) << 11) 964 #define PIN_PB15E_TC1_WO1 _L_(47) /**< \brief TC1 signal: WO1 on PB15 mux E */ 965 #define MUX_PB15E_TC1_WO1 _L_(4) 966 #define PINMUX_PB15E_TC1_WO1 ((PIN_PB15E_TC1_WO1 << 16) | MUX_PB15E_TC1_WO1) 967 #define PORT_PB15E_TC1_WO1 (_UL_(1) << 15) 968 /* ========== PORT definition for TC2 peripheral ========== */ 969 #define PIN_PB02E_TC2_WO0 _L_(34) /**< \brief TC2 signal: WO0 on PB02 mux E */ 970 #define MUX_PB02E_TC2_WO0 _L_(4) 971 #define PINMUX_PB02E_TC2_WO0 ((PIN_PB02E_TC2_WO0 << 16) | MUX_PB02E_TC2_WO0) 972 #define PORT_PB02E_TC2_WO0 (_UL_(1) << 2) 973 #define PIN_PB03E_TC2_WO1 _L_(35) /**< \brief TC2 signal: WO1 on PB03 mux E */ 974 #define MUX_PB03E_TC2_WO1 _L_(4) 975 #define PINMUX_PB03E_TC2_WO1 ((PIN_PB03E_TC2_WO1 << 16) | MUX_PB03E_TC2_WO1) 976 #define PORT_PB03E_TC2_WO1 (_UL_(1) << 3) 977 /* ========== PORT definition for TC3 peripheral ========== */ 978 #define PIN_PA20E_TC3_WO0 _L_(20) /**< \brief TC3 signal: WO0 on PA20 mux E */ 979 #define MUX_PA20E_TC3_WO0 _L_(4) 980 #define PINMUX_PA20E_TC3_WO0 ((PIN_PA20E_TC3_WO0 << 16) | MUX_PA20E_TC3_WO0) 981 #define PORT_PA20E_TC3_WO0 (_UL_(1) << 20) 982 #define PIN_PB00E_TC3_WO0 _L_(32) /**< \brief TC3 signal: WO0 on PB00 mux E */ 983 #define MUX_PB00E_TC3_WO0 _L_(4) 984 #define PINMUX_PB00E_TC3_WO0 ((PIN_PB00E_TC3_WO0 << 16) | MUX_PB00E_TC3_WO0) 985 #define PORT_PB00E_TC3_WO0 (_UL_(1) << 0) 986 #define PIN_PB22E_TC3_WO0 _L_(54) /**< \brief TC3 signal: WO0 on PB22 mux E */ 987 #define MUX_PB22E_TC3_WO0 _L_(4) 988 #define PINMUX_PB22E_TC3_WO0 ((PIN_PB22E_TC3_WO0 << 16) | MUX_PB22E_TC3_WO0) 989 #define PORT_PB22E_TC3_WO0 (_UL_(1) << 22) 990 #define PIN_PA21E_TC3_WO1 _L_(21) /**< \brief TC3 signal: WO1 on PA21 mux E */ 991 #define MUX_PA21E_TC3_WO1 _L_(4) 992 #define PINMUX_PA21E_TC3_WO1 ((PIN_PA21E_TC3_WO1 << 16) | MUX_PA21E_TC3_WO1) 993 #define PORT_PA21E_TC3_WO1 (_UL_(1) << 21) 994 #define PIN_PB01E_TC3_WO1 _L_(33) /**< \brief TC3 signal: WO1 on PB01 mux E */ 995 #define MUX_PB01E_TC3_WO1 _L_(4) 996 #define PINMUX_PB01E_TC3_WO1 ((PIN_PB01E_TC3_WO1 << 16) | MUX_PB01E_TC3_WO1) 997 #define PORT_PB01E_TC3_WO1 (_UL_(1) << 1) 998 #define PIN_PB23E_TC3_WO1 _L_(55) /**< \brief TC3 signal: WO1 on PB23 mux E */ 999 #define MUX_PB23E_TC3_WO1 _L_(4) 1000 #define PINMUX_PB23E_TC3_WO1 ((PIN_PB23E_TC3_WO1 << 16) | MUX_PB23E_TC3_WO1) 1001 #define PORT_PB23E_TC3_WO1 (_UL_(1) << 23) 1002 /* ========== PORT definition for TC4 peripheral ========== */ 1003 #define PIN_PA18E_TC4_WO0 _L_(18) /**< \brief TC4 signal: WO0 on PA18 mux E */ 1004 #define MUX_PA18E_TC4_WO0 _L_(4) 1005 #define PINMUX_PA18E_TC4_WO0 ((PIN_PA18E_TC4_WO0 << 16) | MUX_PA18E_TC4_WO0) 1006 #define PORT_PA18E_TC4_WO0 (_UL_(1) << 18) 1007 #define PIN_PA14E_TC4_WO0 _L_(14) /**< \brief TC4 signal: WO0 on PA14 mux E */ 1008 #define MUX_PA14E_TC4_WO0 _L_(4) 1009 #define PINMUX_PA14E_TC4_WO0 ((PIN_PA14E_TC4_WO0 << 16) | MUX_PA14E_TC4_WO0) 1010 #define PORT_PA14E_TC4_WO0 (_UL_(1) << 14) 1011 #define PIN_PA19E_TC4_WO1 _L_(19) /**< \brief TC4 signal: WO1 on PA19 mux E */ 1012 #define MUX_PA19E_TC4_WO1 _L_(4) 1013 #define PINMUX_PA19E_TC4_WO1 ((PIN_PA19E_TC4_WO1 << 16) | MUX_PA19E_TC4_WO1) 1014 #define PORT_PA19E_TC4_WO1 (_UL_(1) << 19) 1015 #define PIN_PA15E_TC4_WO1 _L_(15) /**< \brief TC4 signal: WO1 on PA15 mux E */ 1016 #define MUX_PA15E_TC4_WO1 _L_(4) 1017 #define PINMUX_PA15E_TC4_WO1 ((PIN_PA15E_TC4_WO1 << 16) | MUX_PA15E_TC4_WO1) 1018 #define PORT_PA15E_TC4_WO1 (_UL_(1) << 15) 1019 /* ========== PORT definition for ADC0 peripheral ========== */ 1020 #define PIN_PA02B_ADC0_AIN0 _L_(2) /**< \brief ADC0 signal: AIN0 on PA02 mux B */ 1021 #define MUX_PA02B_ADC0_AIN0 _L_(1) 1022 #define PINMUX_PA02B_ADC0_AIN0 ((PIN_PA02B_ADC0_AIN0 << 16) | MUX_PA02B_ADC0_AIN0) 1023 #define PORT_PA02B_ADC0_AIN0 (_UL_(1) << 2) 1024 #define PIN_PA03B_ADC0_AIN1 _L_(3) /**< \brief ADC0 signal: AIN1 on PA03 mux B */ 1025 #define MUX_PA03B_ADC0_AIN1 _L_(1) 1026 #define PINMUX_PA03B_ADC0_AIN1 ((PIN_PA03B_ADC0_AIN1 << 16) | MUX_PA03B_ADC0_AIN1) 1027 #define PORT_PA03B_ADC0_AIN1 (_UL_(1) << 3) 1028 #define PIN_PB08B_ADC0_AIN2 _L_(40) /**< \brief ADC0 signal: AIN2 on PB08 mux B */ 1029 #define MUX_PB08B_ADC0_AIN2 _L_(1) 1030 #define PINMUX_PB08B_ADC0_AIN2 ((PIN_PB08B_ADC0_AIN2 << 16) | MUX_PB08B_ADC0_AIN2) 1031 #define PORT_PB08B_ADC0_AIN2 (_UL_(1) << 8) 1032 #define PIN_PB09B_ADC0_AIN3 _L_(41) /**< \brief ADC0 signal: AIN3 on PB09 mux B */ 1033 #define MUX_PB09B_ADC0_AIN3 _L_(1) 1034 #define PINMUX_PB09B_ADC0_AIN3 ((PIN_PB09B_ADC0_AIN3 << 16) | MUX_PB09B_ADC0_AIN3) 1035 #define PORT_PB09B_ADC0_AIN3 (_UL_(1) << 9) 1036 #define PIN_PA04B_ADC0_AIN4 _L_(4) /**< \brief ADC0 signal: AIN4 on PA04 mux B */ 1037 #define MUX_PA04B_ADC0_AIN4 _L_(1) 1038 #define PINMUX_PA04B_ADC0_AIN4 ((PIN_PA04B_ADC0_AIN4 << 16) | MUX_PA04B_ADC0_AIN4) 1039 #define PORT_PA04B_ADC0_AIN4 (_UL_(1) << 4) 1040 #define PIN_PA05B_ADC0_AIN5 _L_(5) /**< \brief ADC0 signal: AIN5 on PA05 mux B */ 1041 #define MUX_PA05B_ADC0_AIN5 _L_(1) 1042 #define PINMUX_PA05B_ADC0_AIN5 ((PIN_PA05B_ADC0_AIN5 << 16) | MUX_PA05B_ADC0_AIN5) 1043 #define PORT_PA05B_ADC0_AIN5 (_UL_(1) << 5) 1044 #define PIN_PA06B_ADC0_AIN6 _L_(6) /**< \brief ADC0 signal: AIN6 on PA06 mux B */ 1045 #define MUX_PA06B_ADC0_AIN6 _L_(1) 1046 #define PINMUX_PA06B_ADC0_AIN6 ((PIN_PA06B_ADC0_AIN6 << 16) | MUX_PA06B_ADC0_AIN6) 1047 #define PORT_PA06B_ADC0_AIN6 (_UL_(1) << 6) 1048 #define PIN_PA07B_ADC0_AIN7 _L_(7) /**< \brief ADC0 signal: AIN7 on PA07 mux B */ 1049 #define MUX_PA07B_ADC0_AIN7 _L_(1) 1050 #define PINMUX_PA07B_ADC0_AIN7 ((PIN_PA07B_ADC0_AIN7 << 16) | MUX_PA07B_ADC0_AIN7) 1051 #define PORT_PA07B_ADC0_AIN7 (_UL_(1) << 7) 1052 #define PIN_PA08B_ADC0_AIN8 _L_(8) /**< \brief ADC0 signal: AIN8 on PA08 mux B */ 1053 #define MUX_PA08B_ADC0_AIN8 _L_(1) 1054 #define PINMUX_PA08B_ADC0_AIN8 ((PIN_PA08B_ADC0_AIN8 << 16) | MUX_PA08B_ADC0_AIN8) 1055 #define PORT_PA08B_ADC0_AIN8 (_UL_(1) << 8) 1056 #define PIN_PA09B_ADC0_AIN9 _L_(9) /**< \brief ADC0 signal: AIN9 on PA09 mux B */ 1057 #define MUX_PA09B_ADC0_AIN9 _L_(1) 1058 #define PINMUX_PA09B_ADC0_AIN9 ((PIN_PA09B_ADC0_AIN9 << 16) | MUX_PA09B_ADC0_AIN9) 1059 #define PORT_PA09B_ADC0_AIN9 (_UL_(1) << 9) 1060 #define PIN_PA10B_ADC0_AIN10 _L_(10) /**< \brief ADC0 signal: AIN10 on PA10 mux B */ 1061 #define MUX_PA10B_ADC0_AIN10 _L_(1) 1062 #define PINMUX_PA10B_ADC0_AIN10 ((PIN_PA10B_ADC0_AIN10 << 16) | MUX_PA10B_ADC0_AIN10) 1063 #define PORT_PA10B_ADC0_AIN10 (_UL_(1) << 10) 1064 #define PIN_PA11B_ADC0_AIN11 _L_(11) /**< \brief ADC0 signal: AIN11 on PA11 mux B */ 1065 #define MUX_PA11B_ADC0_AIN11 _L_(1) 1066 #define PINMUX_PA11B_ADC0_AIN11 ((PIN_PA11B_ADC0_AIN11 << 16) | MUX_PA11B_ADC0_AIN11) 1067 #define PORT_PA11B_ADC0_AIN11 (_UL_(1) << 11) 1068 #define PIN_PA03B_ADC0_VREFP _L_(3) /**< \brief ADC0 signal: VREFP on PA03 mux B */ 1069 #define MUX_PA03B_ADC0_VREFP _L_(1) 1070 #define PINMUX_PA03B_ADC0_VREFP ((PIN_PA03B_ADC0_VREFP << 16) | MUX_PA03B_ADC0_VREFP) 1071 #define PORT_PA03B_ADC0_VREFP (_UL_(1) << 3) 1072 /* ========== PORT definition for ADC1 peripheral ========== */ 1073 #define PIN_PB00B_ADC1_AIN0 _L_(32) /**< \brief ADC1 signal: AIN0 on PB00 mux B */ 1074 #define MUX_PB00B_ADC1_AIN0 _L_(1) 1075 #define PINMUX_PB00B_ADC1_AIN0 ((PIN_PB00B_ADC1_AIN0 << 16) | MUX_PB00B_ADC1_AIN0) 1076 #define PORT_PB00B_ADC1_AIN0 (_UL_(1) << 0) 1077 #define PIN_PB01B_ADC1_AIN1 _L_(33) /**< \brief ADC1 signal: AIN1 on PB01 mux B */ 1078 #define MUX_PB01B_ADC1_AIN1 _L_(1) 1079 #define PINMUX_PB01B_ADC1_AIN1 ((PIN_PB01B_ADC1_AIN1 << 16) | MUX_PB01B_ADC1_AIN1) 1080 #define PORT_PB01B_ADC1_AIN1 (_UL_(1) << 1) 1081 #define PIN_PB02B_ADC1_AIN2 _L_(34) /**< \brief ADC1 signal: AIN2 on PB02 mux B */ 1082 #define MUX_PB02B_ADC1_AIN2 _L_(1) 1083 #define PINMUX_PB02B_ADC1_AIN2 ((PIN_PB02B_ADC1_AIN2 << 16) | MUX_PB02B_ADC1_AIN2) 1084 #define PORT_PB02B_ADC1_AIN2 (_UL_(1) << 2) 1085 #define PIN_PB03B_ADC1_AIN3 _L_(35) /**< \brief ADC1 signal: AIN3 on PB03 mux B */ 1086 #define MUX_PB03B_ADC1_AIN3 _L_(1) 1087 #define PINMUX_PB03B_ADC1_AIN3 ((PIN_PB03B_ADC1_AIN3 << 16) | MUX_PB03B_ADC1_AIN3) 1088 #define PORT_PB03B_ADC1_AIN3 (_UL_(1) << 3) 1089 #define PIN_PB08B_ADC1_AIN4 _L_(40) /**< \brief ADC1 signal: AIN4 on PB08 mux B */ 1090 #define MUX_PB08B_ADC1_AIN4 _L_(1) 1091 #define PINMUX_PB08B_ADC1_AIN4 ((PIN_PB08B_ADC1_AIN4 << 16) | MUX_PB08B_ADC1_AIN4) 1092 #define PORT_PB08B_ADC1_AIN4 (_UL_(1) << 8) 1093 #define PIN_PB09B_ADC1_AIN5 _L_(41) /**< \brief ADC1 signal: AIN5 on PB09 mux B */ 1094 #define MUX_PB09B_ADC1_AIN5 _L_(1) 1095 #define PINMUX_PB09B_ADC1_AIN5 ((PIN_PB09B_ADC1_AIN5 << 16) | MUX_PB09B_ADC1_AIN5) 1096 #define PORT_PB09B_ADC1_AIN5 (_UL_(1) << 9) 1097 #define PIN_PA08B_ADC1_AIN10 _L_(8) /**< \brief ADC1 signal: AIN10 on PA08 mux B */ 1098 #define MUX_PA08B_ADC1_AIN10 _L_(1) 1099 #define PINMUX_PA08B_ADC1_AIN10 ((PIN_PA08B_ADC1_AIN10 << 16) | MUX_PA08B_ADC1_AIN10) 1100 #define PORT_PA08B_ADC1_AIN10 (_UL_(1) << 8) 1101 #define PIN_PA09B_ADC1_AIN11 _L_(9) /**< \brief ADC1 signal: AIN11 on PA09 mux B */ 1102 #define MUX_PA09B_ADC1_AIN11 _L_(1) 1103 #define PINMUX_PA09B_ADC1_AIN11 ((PIN_PA09B_ADC1_AIN11 << 16) | MUX_PA09B_ADC1_AIN11) 1104 #define PORT_PA09B_ADC1_AIN11 (_UL_(1) << 9) 1105 /* ========== PORT definition for SDADC peripheral ========== */ 1106 #define PIN_PA06B_SDADC_INN0 _L_(6) /**< \brief SDADC signal: INN0 on PA06 mux B */ 1107 #define MUX_PA06B_SDADC_INN0 _L_(1) 1108 #define PINMUX_PA06B_SDADC_INN0 ((PIN_PA06B_SDADC_INN0 << 16) | MUX_PA06B_SDADC_INN0) 1109 #define PORT_PA06B_SDADC_INN0 (_UL_(1) << 6) 1110 #define PIN_PB08B_SDADC_INN1 _L_(40) /**< \brief SDADC signal: INN1 on PB08 mux B */ 1111 #define MUX_PB08B_SDADC_INN1 _L_(1) 1112 #define PINMUX_PB08B_SDADC_INN1 ((PIN_PB08B_SDADC_INN1 << 16) | MUX_PB08B_SDADC_INN1) 1113 #define PORT_PB08B_SDADC_INN1 (_UL_(1) << 8) 1114 #define PIN_PA07B_SDADC_INP0 _L_(7) /**< \brief SDADC signal: INP0 on PA07 mux B */ 1115 #define MUX_PA07B_SDADC_INP0 _L_(1) 1116 #define PINMUX_PA07B_SDADC_INP0 ((PIN_PA07B_SDADC_INP0 << 16) | MUX_PA07B_SDADC_INP0) 1117 #define PORT_PA07B_SDADC_INP0 (_UL_(1) << 7) 1118 #define PIN_PB09B_SDADC_INP1 _L_(41) /**< \brief SDADC signal: INP1 on PB09 mux B */ 1119 #define MUX_PB09B_SDADC_INP1 _L_(1) 1120 #define PINMUX_PB09B_SDADC_INP1 ((PIN_PB09B_SDADC_INP1 << 16) | MUX_PB09B_SDADC_INP1) 1121 #define PORT_PB09B_SDADC_INP1 (_UL_(1) << 9) 1122 #define PIN_PA04B_SDADC_VREFP _L_(4) /**< \brief SDADC signal: VREFP on PA04 mux B */ 1123 #define MUX_PA04B_SDADC_VREFP _L_(1) 1124 #define PINMUX_PA04B_SDADC_VREFP ((PIN_PA04B_SDADC_VREFP << 16) | MUX_PA04B_SDADC_VREFP) 1125 #define PORT_PA04B_SDADC_VREFP (_UL_(1) << 4) 1126 /* ========== PORT definition for AC peripheral ========== */ 1127 #define PIN_PA04B_AC_AIN0 _L_(4) /**< \brief AC signal: AIN0 on PA04 mux B */ 1128 #define MUX_PA04B_AC_AIN0 _L_(1) 1129 #define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) 1130 #define PORT_PA04B_AC_AIN0 (_UL_(1) << 4) 1131 #define PIN_PA05B_AC_AIN1 _L_(5) /**< \brief AC signal: AIN1 on PA05 mux B */ 1132 #define MUX_PA05B_AC_AIN1 _L_(1) 1133 #define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) 1134 #define PORT_PA05B_AC_AIN1 (_UL_(1) << 5) 1135 #define PIN_PA06B_AC_AIN2 _L_(6) /**< \brief AC signal: AIN2 on PA06 mux B */ 1136 #define MUX_PA06B_AC_AIN2 _L_(1) 1137 #define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) 1138 #define PORT_PA06B_AC_AIN2 (_UL_(1) << 6) 1139 #define PIN_PA07B_AC_AIN3 _L_(7) /**< \brief AC signal: AIN3 on PA07 mux B */ 1140 #define MUX_PA07B_AC_AIN3 _L_(1) 1141 #define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) 1142 #define PORT_PA07B_AC_AIN3 (_UL_(1) << 7) 1143 #define PIN_PA02B_AC_AIN4 _L_(2) /**< \brief AC signal: AIN4 on PA02 mux B */ 1144 #define MUX_PA02B_AC_AIN4 _L_(1) 1145 #define PINMUX_PA02B_AC_AIN4 ((PIN_PA02B_AC_AIN4 << 16) | MUX_PA02B_AC_AIN4) 1146 #define PORT_PA02B_AC_AIN4 (_UL_(1) << 2) 1147 #define PIN_PA03B_AC_AIN5 _L_(3) /**< \brief AC signal: AIN5 on PA03 mux B */ 1148 #define MUX_PA03B_AC_AIN5 _L_(1) 1149 #define PINMUX_PA03B_AC_AIN5 ((PIN_PA03B_AC_AIN5 << 16) | MUX_PA03B_AC_AIN5) 1150 #define PORT_PA03B_AC_AIN5 (_UL_(1) << 3) 1151 #define PIN_PA12H_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux H */ 1152 #define MUX_PA12H_AC_CMP0 _L_(7) 1153 #define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0) 1154 #define PORT_PA12H_AC_CMP0 (_UL_(1) << 12) 1155 #define PIN_PA18H_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux H */ 1156 #define MUX_PA18H_AC_CMP0 _L_(7) 1157 #define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) 1158 #define PORT_PA18H_AC_CMP0 (_UL_(1) << 18) 1159 #define PIN_PA13H_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux H */ 1160 #define MUX_PA13H_AC_CMP1 _L_(7) 1161 #define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1) 1162 #define PORT_PA13H_AC_CMP1 (_UL_(1) << 13) 1163 #define PIN_PA19H_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux H */ 1164 #define MUX_PA19H_AC_CMP1 _L_(7) 1165 #define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) 1166 #define PORT_PA19H_AC_CMP1 (_UL_(1) << 19) 1167 #define PIN_PA00H_AC_CMP2 _L_(0) /**< \brief AC signal: CMP2 on PA00 mux H */ 1168 #define MUX_PA00H_AC_CMP2 _L_(7) 1169 #define PINMUX_PA00H_AC_CMP2 ((PIN_PA00H_AC_CMP2 << 16) | MUX_PA00H_AC_CMP2) 1170 #define PORT_PA00H_AC_CMP2 (_UL_(1) << 0) 1171 #define PIN_PA24H_AC_CMP2 _L_(24) /**< \brief AC signal: CMP2 on PA24 mux H */ 1172 #define MUX_PA24H_AC_CMP2 _L_(7) 1173 #define PINMUX_PA24H_AC_CMP2 ((PIN_PA24H_AC_CMP2 << 16) | MUX_PA24H_AC_CMP2) 1174 #define PORT_PA24H_AC_CMP2 (_UL_(1) << 24) 1175 #define PIN_PA01H_AC_CMP3 _L_(1) /**< \brief AC signal: CMP3 on PA01 mux H */ 1176 #define MUX_PA01H_AC_CMP3 _L_(7) 1177 #define PINMUX_PA01H_AC_CMP3 ((PIN_PA01H_AC_CMP3 << 16) | MUX_PA01H_AC_CMP3) 1178 #define PORT_PA01H_AC_CMP3 (_UL_(1) << 1) 1179 #define PIN_PA25H_AC_CMP3 _L_(25) /**< \brief AC signal: CMP3 on PA25 mux H */ 1180 #define MUX_PA25H_AC_CMP3 _L_(7) 1181 #define PINMUX_PA25H_AC_CMP3 ((PIN_PA25H_AC_CMP3 << 16) | MUX_PA25H_AC_CMP3) 1182 #define PORT_PA25H_AC_CMP3 (_UL_(1) << 25) 1183 /* ========== PORT definition for DAC peripheral ========== */ 1184 #define PIN_PA02B_DAC_VOUT _L_(2) /**< \brief DAC signal: VOUT on PA02 mux B */ 1185 #define MUX_PA02B_DAC_VOUT _L_(1) 1186 #define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT) 1187 #define PORT_PA02B_DAC_VOUT (_UL_(1) << 2) 1188 #define PIN_PA03B_DAC_VREFP _L_(3) /**< \brief DAC signal: VREFP on PA03 mux B */ 1189 #define MUX_PA03B_DAC_VREFP _L_(1) 1190 #define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP) 1191 #define PORT_PA03B_DAC_VREFP (_UL_(1) << 3) 1192 /* ========== PORT definition for CCL peripheral ========== */ 1193 #define PIN_PA04I_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux I */ 1194 #define MUX_PA04I_CCL_IN0 _L_(8) 1195 #define PINMUX_PA04I_CCL_IN0 ((PIN_PA04I_CCL_IN0 << 16) | MUX_PA04I_CCL_IN0) 1196 #define PORT_PA04I_CCL_IN0 (_UL_(1) << 4) 1197 #define PIN_PA16I_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux I */ 1198 #define MUX_PA16I_CCL_IN0 _L_(8) 1199 #define PINMUX_PA16I_CCL_IN0 ((PIN_PA16I_CCL_IN0 << 16) | MUX_PA16I_CCL_IN0) 1200 #define PORT_PA16I_CCL_IN0 (_UL_(1) << 16) 1201 #define PIN_PB22I_CCL_IN0 _L_(54) /**< \brief CCL signal: IN0 on PB22 mux I */ 1202 #define MUX_PB22I_CCL_IN0 _L_(8) 1203 #define PINMUX_PB22I_CCL_IN0 ((PIN_PB22I_CCL_IN0 << 16) | MUX_PB22I_CCL_IN0) 1204 #define PORT_PB22I_CCL_IN0 (_UL_(1) << 22) 1205 #define PIN_PA05I_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux I */ 1206 #define MUX_PA05I_CCL_IN1 _L_(8) 1207 #define PINMUX_PA05I_CCL_IN1 ((PIN_PA05I_CCL_IN1 << 16) | MUX_PA05I_CCL_IN1) 1208 #define PORT_PA05I_CCL_IN1 (_UL_(1) << 5) 1209 #define PIN_PA17I_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux I */ 1210 #define MUX_PA17I_CCL_IN1 _L_(8) 1211 #define PINMUX_PA17I_CCL_IN1 ((PIN_PA17I_CCL_IN1 << 16) | MUX_PA17I_CCL_IN1) 1212 #define PORT_PA17I_CCL_IN1 (_UL_(1) << 17) 1213 #define PIN_PB00I_CCL_IN1 _L_(32) /**< \brief CCL signal: IN1 on PB00 mux I */ 1214 #define MUX_PB00I_CCL_IN1 _L_(8) 1215 #define PINMUX_PB00I_CCL_IN1 ((PIN_PB00I_CCL_IN1 << 16) | MUX_PB00I_CCL_IN1) 1216 #define PORT_PB00I_CCL_IN1 (_UL_(1) << 0) 1217 #define PIN_PA06I_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux I */ 1218 #define MUX_PA06I_CCL_IN2 _L_(8) 1219 #define PINMUX_PA06I_CCL_IN2 ((PIN_PA06I_CCL_IN2 << 16) | MUX_PA06I_CCL_IN2) 1220 #define PORT_PA06I_CCL_IN2 (_UL_(1) << 6) 1221 #define PIN_PA18I_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux I */ 1222 #define MUX_PA18I_CCL_IN2 _L_(8) 1223 #define PINMUX_PA18I_CCL_IN2 ((PIN_PA18I_CCL_IN2 << 16) | MUX_PA18I_CCL_IN2) 1224 #define PORT_PA18I_CCL_IN2 (_UL_(1) << 18) 1225 #define PIN_PB01I_CCL_IN2 _L_(33) /**< \brief CCL signal: IN2 on PB01 mux I */ 1226 #define MUX_PB01I_CCL_IN2 _L_(8) 1227 #define PINMUX_PB01I_CCL_IN2 ((PIN_PB01I_CCL_IN2 << 16) | MUX_PB01I_CCL_IN2) 1228 #define PORT_PB01I_CCL_IN2 (_UL_(1) << 1) 1229 #define PIN_PA08I_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux I */ 1230 #define MUX_PA08I_CCL_IN3 _L_(8) 1231 #define PINMUX_PA08I_CCL_IN3 ((PIN_PA08I_CCL_IN3 << 16) | MUX_PA08I_CCL_IN3) 1232 #define PORT_PA08I_CCL_IN3 (_UL_(1) << 8) 1233 #define PIN_PA30I_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux I */ 1234 #define MUX_PA30I_CCL_IN3 _L_(8) 1235 #define PINMUX_PA30I_CCL_IN3 ((PIN_PA30I_CCL_IN3 << 16) | MUX_PA30I_CCL_IN3) 1236 #define PORT_PA30I_CCL_IN3 (_UL_(1) << 30) 1237 #define PIN_PA09I_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux I */ 1238 #define MUX_PA09I_CCL_IN4 _L_(8) 1239 #define PINMUX_PA09I_CCL_IN4 ((PIN_PA09I_CCL_IN4 << 16) | MUX_PA09I_CCL_IN4) 1240 #define PORT_PA09I_CCL_IN4 (_UL_(1) << 9) 1241 #define PIN_PA10I_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux I */ 1242 #define MUX_PA10I_CCL_IN5 _L_(8) 1243 #define PINMUX_PA10I_CCL_IN5 ((PIN_PA10I_CCL_IN5 << 16) | MUX_PA10I_CCL_IN5) 1244 #define PORT_PA10I_CCL_IN5 (_UL_(1) << 10) 1245 #define PIN_PB10I_CCL_IN5 _L_(42) /**< \brief CCL signal: IN5 on PB10 mux I */ 1246 #define MUX_PB10I_CCL_IN5 _L_(8) 1247 #define PINMUX_PB10I_CCL_IN5 ((PIN_PB10I_CCL_IN5 << 16) | MUX_PB10I_CCL_IN5) 1248 #define PORT_PB10I_CCL_IN5 (_UL_(1) << 10) 1249 #define PIN_PA22I_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux I */ 1250 #define MUX_PA22I_CCL_IN6 _L_(8) 1251 #define PINMUX_PA22I_CCL_IN6 ((PIN_PA22I_CCL_IN6 << 16) | MUX_PA22I_CCL_IN6) 1252 #define PORT_PA22I_CCL_IN6 (_UL_(1) << 22) 1253 #define PIN_PA23I_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux I */ 1254 #define MUX_PA23I_CCL_IN7 _L_(8) 1255 #define PINMUX_PA23I_CCL_IN7 ((PIN_PA23I_CCL_IN7 << 16) | MUX_PA23I_CCL_IN7) 1256 #define PORT_PA23I_CCL_IN7 (_UL_(1) << 23) 1257 #define PIN_PA24I_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux I */ 1258 #define MUX_PA24I_CCL_IN8 _L_(8) 1259 #define PINMUX_PA24I_CCL_IN8 ((PIN_PA24I_CCL_IN8 << 16) | MUX_PA24I_CCL_IN8) 1260 #define PORT_PA24I_CCL_IN8 (_UL_(1) << 24) 1261 #define PIN_PB08I_CCL_IN8 _L_(40) /**< \brief CCL signal: IN8 on PB08 mux I */ 1262 #define MUX_PB08I_CCL_IN8 _L_(8) 1263 #define PINMUX_PB08I_CCL_IN8 ((PIN_PB08I_CCL_IN8 << 16) | MUX_PB08I_CCL_IN8) 1264 #define PORT_PB08I_CCL_IN8 (_UL_(1) << 8) 1265 #define PIN_PB14I_CCL_IN9 _L_(46) /**< \brief CCL signal: IN9 on PB14 mux I */ 1266 #define MUX_PB14I_CCL_IN9 _L_(8) 1267 #define PINMUX_PB14I_CCL_IN9 ((PIN_PB14I_CCL_IN9 << 16) | MUX_PB14I_CCL_IN9) 1268 #define PORT_PB14I_CCL_IN9 (_UL_(1) << 14) 1269 #define PIN_PB15I_CCL_IN10 _L_(47) /**< \brief CCL signal: IN10 on PB15 mux I */ 1270 #define MUX_PB15I_CCL_IN10 _L_(8) 1271 #define PINMUX_PB15I_CCL_IN10 ((PIN_PB15I_CCL_IN10 << 16) | MUX_PB15I_CCL_IN10) 1272 #define PORT_PB15I_CCL_IN10 (_UL_(1) << 15) 1273 #define PIN_PA07I_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux I */ 1274 #define MUX_PA07I_CCL_OUT0 _L_(8) 1275 #define PINMUX_PA07I_CCL_OUT0 ((PIN_PA07I_CCL_OUT0 << 16) | MUX_PA07I_CCL_OUT0) 1276 #define PORT_PA07I_CCL_OUT0 (_UL_(1) << 7) 1277 #define PIN_PA19I_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux I */ 1278 #define MUX_PA19I_CCL_OUT0 _L_(8) 1279 #define PINMUX_PA19I_CCL_OUT0 ((PIN_PA19I_CCL_OUT0 << 16) | MUX_PA19I_CCL_OUT0) 1280 #define PORT_PA19I_CCL_OUT0 (_UL_(1) << 19) 1281 #define PIN_PB02I_CCL_OUT0 _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux I */ 1282 #define MUX_PB02I_CCL_OUT0 _L_(8) 1283 #define PINMUX_PB02I_CCL_OUT0 ((PIN_PB02I_CCL_OUT0 << 16) | MUX_PB02I_CCL_OUT0) 1284 #define PORT_PB02I_CCL_OUT0 (_UL_(1) << 2) 1285 #define PIN_PB23I_CCL_OUT0 _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux I */ 1286 #define MUX_PB23I_CCL_OUT0 _L_(8) 1287 #define PINMUX_PB23I_CCL_OUT0 ((PIN_PB23I_CCL_OUT0 << 16) | MUX_PB23I_CCL_OUT0) 1288 #define PORT_PB23I_CCL_OUT0 (_UL_(1) << 23) 1289 #define PIN_PA11I_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux I */ 1290 #define MUX_PA11I_CCL_OUT1 _L_(8) 1291 #define PINMUX_PA11I_CCL_OUT1 ((PIN_PA11I_CCL_OUT1 << 16) | MUX_PA11I_CCL_OUT1) 1292 #define PORT_PA11I_CCL_OUT1 (_UL_(1) << 11) 1293 #define PIN_PA31I_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux I */ 1294 #define MUX_PA31I_CCL_OUT1 _L_(8) 1295 #define PINMUX_PA31I_CCL_OUT1 ((PIN_PA31I_CCL_OUT1 << 16) | MUX_PA31I_CCL_OUT1) 1296 #define PORT_PA31I_CCL_OUT1 (_UL_(1) << 31) 1297 #define PIN_PB11I_CCL_OUT1 _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux I */ 1298 #define MUX_PB11I_CCL_OUT1 _L_(8) 1299 #define PINMUX_PB11I_CCL_OUT1 ((PIN_PB11I_CCL_OUT1 << 16) | MUX_PB11I_CCL_OUT1) 1300 #define PORT_PB11I_CCL_OUT1 (_UL_(1) << 11) 1301 #define PIN_PA25I_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux I */ 1302 #define MUX_PA25I_CCL_OUT2 _L_(8) 1303 #define PINMUX_PA25I_CCL_OUT2 ((PIN_PA25I_CCL_OUT2 << 16) | MUX_PA25I_CCL_OUT2) 1304 #define PORT_PA25I_CCL_OUT2 (_UL_(1) << 25) 1305 #define PIN_PB09I_CCL_OUT2 _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux I */ 1306 #define MUX_PB09I_CCL_OUT2 _L_(8) 1307 #define PINMUX_PB09I_CCL_OUT2 ((PIN_PB09I_CCL_OUT2 << 16) | MUX_PB09I_CCL_OUT2) 1308 #define PORT_PB09I_CCL_OUT2 (_UL_(1) << 9) 1309 1310 #endif /* _SAMC21J18AU_PIO_ */ 1311
