1 /** 2 * \file 3 * 4 * \brief Component description for HMATRIXB 5 * 6 * Copyright (c) 2018 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAMC21_HMATRIXB_COMPONENT_ 31 #define _SAMC21_HMATRIXB_COMPONENT_ 32 33 /* ========================================================================== */ 34 /** SOFTWARE API DEFINITION FOR HMATRIXB */ 35 /* ========================================================================== */ 36 /** \addtogroup SAMC21_HMATRIXB HSB Matrix */ 37 /*@{*/ 38 39 #define HMATRIXB_I7638 40 #define REV_HMATRIXB 0x213 41 42 /* -------- HMATRIXB_MCFG : (HMATRIXB Offset: 0x000) (R/W 32) Master Configuration -------- */ 43 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 44 typedef union { 45 struct { 46 uint32_t ULBT:3; /*!< bit: 0.. 2 Undefined Length Burst Type */ 47 uint32_t :29; /*!< bit: 3..31 Reserved */ 48 } bit; /*!< Structure used for bit access */ 49 uint32_t reg; /*!< Type used for register access */ 50 } HMATRIXB_MCFG_Type; 51 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 52 53 #define HMATRIXB_MCFG_OFFSET 0x000 /**< \brief (HMATRIXB_MCFG offset) Master Configuration */ 54 #define HMATRIXB_MCFG_RESETVALUE _U_(0x00000002) /**< \brief (HMATRIXB_MCFG reset_value) Master Configuration */ 55 56 #define HMATRIXB_MCFG_ULBT_Pos 0 /**< \brief (HMATRIXB_MCFG) Undefined Length Burst Type */ 57 #define HMATRIXB_MCFG_ULBT_Msk (_U_(0x7) << HMATRIXB_MCFG_ULBT_Pos) 58 #define HMATRIXB_MCFG_ULBT(value) (HMATRIXB_MCFG_ULBT_Msk & ((value) << HMATRIXB_MCFG_ULBT_Pos)) 59 #define HMATRIXB_MCFG_ULBT_INFINITE_Val _U_(0x0) /**< \brief (HMATRIXB_MCFG) Infinite Length */ 60 #define HMATRIXB_MCFG_ULBT_SINGLE_Val _U_(0x1) /**< \brief (HMATRIXB_MCFG) Single Access */ 61 #define HMATRIXB_MCFG_ULBT_FOUR_BEAT_Val _U_(0x2) /**< \brief (HMATRIXB_MCFG) Four Beat Burst */ 62 #define HMATRIXB_MCFG_ULBT_EIGHT_BEAT_Val _U_(0x3) /**< \brief (HMATRIXB_MCFG) Eight Beat Burst */ 63 #define HMATRIXB_MCFG_ULBT_SIXTEEN_BEAT_Val _U_(0x4) /**< \brief (HMATRIXB_MCFG) Sixteen Beat Burst */ 64 #define HMATRIXB_MCFG_ULBT_INFINITE (HMATRIXB_MCFG_ULBT_INFINITE_Val << HMATRIXB_MCFG_ULBT_Pos) 65 #define HMATRIXB_MCFG_ULBT_SINGLE (HMATRIXB_MCFG_ULBT_SINGLE_Val << HMATRIXB_MCFG_ULBT_Pos) 66 #define HMATRIXB_MCFG_ULBT_FOUR_BEAT (HMATRIXB_MCFG_ULBT_FOUR_BEAT_Val << HMATRIXB_MCFG_ULBT_Pos) 67 #define HMATRIXB_MCFG_ULBT_EIGHT_BEAT (HMATRIXB_MCFG_ULBT_EIGHT_BEAT_Val << HMATRIXB_MCFG_ULBT_Pos) 68 #define HMATRIXB_MCFG_ULBT_SIXTEEN_BEAT (HMATRIXB_MCFG_ULBT_SIXTEEN_BEAT_Val << HMATRIXB_MCFG_ULBT_Pos) 69 #define HMATRIXB_MCFG_MASK _U_(0x00000007) /**< \brief (HMATRIXB_MCFG) MASK Register */ 70 71 /* -------- HMATRIXB_SCFG : (HMATRIXB Offset: 0x040) (R/W 32) Slave Configuration -------- */ 72 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 73 typedef union { 74 struct { 75 uint32_t SLOT_CYCLE:8; /*!< bit: 0.. 7 Maximum Number of Allowed Cycles for a Burst */ 76 uint32_t :8; /*!< bit: 8..15 Reserved */ 77 uint32_t DEFMSTR_TYPE:2; /*!< bit: 16..17 Default Master Type */ 78 uint32_t FIXED_DEFMSTR:4; /*!< bit: 18..21 Fixed Index of Default Master */ 79 uint32_t :2; /*!< bit: 22..23 Reserved */ 80 uint32_t ARBT:1; /*!< bit: 24 Arbitration Type */ 81 uint32_t :7; /*!< bit: 25..31 Reserved */ 82 } bit; /*!< Structure used for bit access */ 83 uint32_t reg; /*!< Type used for register access */ 84 } HMATRIXB_SCFG_Type; 85 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 86 87 #define HMATRIXB_SCFG_OFFSET 0x040 /**< \brief (HMATRIXB_SCFG offset) Slave Configuration */ 88 #define HMATRIXB_SCFG_RESETVALUE _U_(0x00000010) /**< \brief (HMATRIXB_SCFG reset_value) Slave Configuration */ 89 90 #define HMATRIXB_SCFG_SLOT_CYCLE_Pos 0 /**< \brief (HMATRIXB_SCFG) Maximum Number of Allowed Cycles for a Burst */ 91 #define HMATRIXB_SCFG_SLOT_CYCLE_Msk (_U_(0xFF) << HMATRIXB_SCFG_SLOT_CYCLE_Pos) 92 #define HMATRIXB_SCFG_SLOT_CYCLE(value) (HMATRIXB_SCFG_SLOT_CYCLE_Msk & ((value) << HMATRIXB_SCFG_SLOT_CYCLE_Pos)) 93 #define HMATRIXB_SCFG_DEFMSTR_TYPE_Pos 16 /**< \brief (HMATRIXB_SCFG) Default Master Type */ 94 #define HMATRIXB_SCFG_DEFMSTR_TYPE_Msk (_U_(0x3) << HMATRIXB_SCFG_DEFMSTR_TYPE_Pos) 95 #define HMATRIXB_SCFG_DEFMSTR_TYPE(value) (HMATRIXB_SCFG_DEFMSTR_TYPE_Msk & ((value) << HMATRIXB_SCFG_DEFMSTR_TYPE_Pos)) 96 #define HMATRIXB_SCFG_DEFMSTR_TYPE_NO_DEFAULT_Val _U_(0x0) /**< \brief (HMATRIXB_SCFG) No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. */ 97 #define HMATRIXB_SCFG_DEFMSTR_TYPE_LAST_DEFAULT_Val _U_(0x1) /**< \brief (HMATRIXB_SCFG) Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. */ 98 #define HMATRIXB_SCFG_DEFMSTR_TYPE_FIXED_DEFAULT_Val _U_(0x2) /**< \brief (HMATRIXB_SCFG) Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave. */ 99 #define HMATRIXB_SCFG_DEFMSTR_TYPE_NO_DEFAULT (HMATRIXB_SCFG_DEFMSTR_TYPE_NO_DEFAULT_Val << HMATRIXB_SCFG_DEFMSTR_TYPE_Pos) 100 #define HMATRIXB_SCFG_DEFMSTR_TYPE_LAST_DEFAULT (HMATRIXB_SCFG_DEFMSTR_TYPE_LAST_DEFAULT_Val << HMATRIXB_SCFG_DEFMSTR_TYPE_Pos) 101 #define HMATRIXB_SCFG_DEFMSTR_TYPE_FIXED_DEFAULT (HMATRIXB_SCFG_DEFMSTR_TYPE_FIXED_DEFAULT_Val << HMATRIXB_SCFG_DEFMSTR_TYPE_Pos) 102 #define HMATRIXB_SCFG_FIXED_DEFMSTR_Pos 18 /**< \brief (HMATRIXB_SCFG) Fixed Index of Default Master */ 103 #define HMATRIXB_SCFG_FIXED_DEFMSTR_Msk (_U_(0xF) << HMATRIXB_SCFG_FIXED_DEFMSTR_Pos) 104 #define HMATRIXB_SCFG_FIXED_DEFMSTR(value) (HMATRIXB_SCFG_FIXED_DEFMSTR_Msk & ((value) << HMATRIXB_SCFG_FIXED_DEFMSTR_Pos)) 105 #define HMATRIXB_SCFG_ARBT_Pos 24 /**< \brief (HMATRIXB_SCFG) Arbitration Type */ 106 #define HMATRIXB_SCFG_ARBT (_U_(0x1) << HMATRIXB_SCFG_ARBT_Pos) 107 #define HMATRIXB_SCFG_ARBT_ROUND_ROBIN_Val _U_(0x0) /**< \brief (HMATRIXB_SCFG) Round-Robin Arbitration */ 108 #define HMATRIXB_SCFG_ARBT_FIXED_PRIORITY_Val _U_(0x1) /**< \brief (HMATRIXB_SCFG) Fixed Priority Arbitration */ 109 #define HMATRIXB_SCFG_ARBT_ROUND_ROBIN (HMATRIXB_SCFG_ARBT_ROUND_ROBIN_Val << HMATRIXB_SCFG_ARBT_Pos) 110 #define HMATRIXB_SCFG_ARBT_FIXED_PRIORITY (HMATRIXB_SCFG_ARBT_FIXED_PRIORITY_Val << HMATRIXB_SCFG_ARBT_Pos) 111 #define HMATRIXB_SCFG_MASK _U_(0x013F00FF) /**< \brief (HMATRIXB_SCFG) MASK Register */ 112 113 /* -------- HMATRIXB_PRAS : (HMATRIXB Offset: 0x080) (R/W 32) PRS Priority A for Slave -------- */ 114 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 115 typedef union { 116 struct { 117 uint32_t M0PR:4; /*!< bit: 0.. 3 Master 0 Priority */ 118 uint32_t M1PR:4; /*!< bit: 4.. 7 Master 1 Priority */ 119 uint32_t M2PR:4; /*!< bit: 8..11 Master 2 Priority */ 120 uint32_t M3PR:4; /*!< bit: 12..15 Master 3 Priority */ 121 uint32_t M4PR:4; /*!< bit: 16..19 Master 4 Priority */ 122 uint32_t M5PR:4; /*!< bit: 20..23 Master 5 Priority */ 123 uint32_t M6PR:4; /*!< bit: 24..27 Master 6 Priority */ 124 uint32_t M7PR:4; /*!< bit: 28..31 Master 7 Priority */ 125 } bit; /*!< Structure used for bit access */ 126 uint32_t reg; /*!< Type used for register access */ 127 } HMATRIXB_PRAS_Type; 128 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 129 130 #define HMATRIXB_PRAS_OFFSET 0x080 /**< \brief (HMATRIXB_PRAS offset) Priority A for Slave */ 131 #define HMATRIXB_PRAS_RESETVALUE _U_(0x00000000) /**< \brief (HMATRIXB_PRAS reset_value) Priority A for Slave */ 132 133 #define HMATRIXB_PRAS_M0PR_Pos 0 /**< \brief (HMATRIXB_PRAS) Master 0 Priority */ 134 #define HMATRIXB_PRAS_M0PR_Msk (_U_(0xF) << HMATRIXB_PRAS_M0PR_Pos) 135 #define HMATRIXB_PRAS_M0PR(value) (HMATRIXB_PRAS_M0PR_Msk & ((value) << HMATRIXB_PRAS_M0PR_Pos)) 136 #define HMATRIXB_PRAS_M1PR_Pos 4 /**< \brief (HMATRIXB_PRAS) Master 1 Priority */ 137 #define HMATRIXB_PRAS_M1PR_Msk (_U_(0xF) << HMATRIXB_PRAS_M1PR_Pos) 138 #define HMATRIXB_PRAS_M1PR(value) (HMATRIXB_PRAS_M1PR_Msk & ((value) << HMATRIXB_PRAS_M1PR_Pos)) 139 #define HMATRIXB_PRAS_M2PR_Pos 8 /**< \brief (HMATRIXB_PRAS) Master 2 Priority */ 140 #define HMATRIXB_PRAS_M2PR_Msk (_U_(0xF) << HMATRIXB_PRAS_M2PR_Pos) 141 #define HMATRIXB_PRAS_M2PR(value) (HMATRIXB_PRAS_M2PR_Msk & ((value) << HMATRIXB_PRAS_M2PR_Pos)) 142 #define HMATRIXB_PRAS_M3PR_Pos 12 /**< \brief (HMATRIXB_PRAS) Master 3 Priority */ 143 #define HMATRIXB_PRAS_M3PR_Msk (_U_(0xF) << HMATRIXB_PRAS_M3PR_Pos) 144 #define HMATRIXB_PRAS_M3PR(value) (HMATRIXB_PRAS_M3PR_Msk & ((value) << HMATRIXB_PRAS_M3PR_Pos)) 145 #define HMATRIXB_PRAS_M4PR_Pos 16 /**< \brief (HMATRIXB_PRAS) Master 4 Priority */ 146 #define HMATRIXB_PRAS_M4PR_Msk (_U_(0xF) << HMATRIXB_PRAS_M4PR_Pos) 147 #define HMATRIXB_PRAS_M4PR(value) (HMATRIXB_PRAS_M4PR_Msk & ((value) << HMATRIXB_PRAS_M4PR_Pos)) 148 #define HMATRIXB_PRAS_M5PR_Pos 20 /**< \brief (HMATRIXB_PRAS) Master 5 Priority */ 149 #define HMATRIXB_PRAS_M5PR_Msk (_U_(0xF) << HMATRIXB_PRAS_M5PR_Pos) 150 #define HMATRIXB_PRAS_M5PR(value) (HMATRIXB_PRAS_M5PR_Msk & ((value) << HMATRIXB_PRAS_M5PR_Pos)) 151 #define HMATRIXB_PRAS_M6PR_Pos 24 /**< \brief (HMATRIXB_PRAS) Master 6 Priority */ 152 #define HMATRIXB_PRAS_M6PR_Msk (_U_(0xF) << HMATRIXB_PRAS_M6PR_Pos) 153 #define HMATRIXB_PRAS_M6PR(value) (HMATRIXB_PRAS_M6PR_Msk & ((value) << HMATRIXB_PRAS_M6PR_Pos)) 154 #define HMATRIXB_PRAS_M7PR_Pos 28 /**< \brief (HMATRIXB_PRAS) Master 7 Priority */ 155 #define HMATRIXB_PRAS_M7PR_Msk (_U_(0xF) << HMATRIXB_PRAS_M7PR_Pos) 156 #define HMATRIXB_PRAS_M7PR(value) (HMATRIXB_PRAS_M7PR_Msk & ((value) << HMATRIXB_PRAS_M7PR_Pos)) 157 #define HMATRIXB_PRAS_MASK _U_(0xFFFFFFFF) /**< \brief (HMATRIXB_PRAS) MASK Register */ 158 159 /* -------- HMATRIXB_PRBS : (HMATRIXB Offset: 0x084) (R/W 32) PRS Priority B for Slave -------- */ 160 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 161 typedef union { 162 struct { 163 uint32_t M8PR:4; /*!< bit: 0.. 3 Master 8 Priority */ 164 uint32_t M9PR:4; /*!< bit: 4.. 7 Master 9 Priority */ 165 uint32_t M10PR:4; /*!< bit: 8..11 Master 10 Priority */ 166 uint32_t M11PR:4; /*!< bit: 12..15 Master 11 Priority */ 167 uint32_t M12PR:4; /*!< bit: 16..19 Master 12 Priority */ 168 uint32_t M13PR:4; /*!< bit: 20..23 Master 13 Priority */ 169 uint32_t M14PR:4; /*!< bit: 24..27 Master 14 Priority */ 170 uint32_t M15PR:4; /*!< bit: 28..31 Master 15 Priority */ 171 } bit; /*!< Structure used for bit access */ 172 uint32_t reg; /*!< Type used for register access */ 173 } HMATRIXB_PRBS_Type; 174 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 175 176 #define HMATRIXB_PRBS_OFFSET 0x084 /**< \brief (HMATRIXB_PRBS offset) Priority B for Slave */ 177 #define HMATRIXB_PRBS_RESETVALUE _U_(0x00000000) /**< \brief (HMATRIXB_PRBS reset_value) Priority B for Slave */ 178 179 #define HMATRIXB_PRBS_M8PR_Pos 0 /**< \brief (HMATRIXB_PRBS) Master 8 Priority */ 180 #define HMATRIXB_PRBS_M8PR_Msk (_U_(0xF) << HMATRIXB_PRBS_M8PR_Pos) 181 #define HMATRIXB_PRBS_M8PR(value) (HMATRIXB_PRBS_M8PR_Msk & ((value) << HMATRIXB_PRBS_M8PR_Pos)) 182 #define HMATRIXB_PRBS_M9PR_Pos 4 /**< \brief (HMATRIXB_PRBS) Master 9 Priority */ 183 #define HMATRIXB_PRBS_M9PR_Msk (_U_(0xF) << HMATRIXB_PRBS_M9PR_Pos) 184 #define HMATRIXB_PRBS_M9PR(value) (HMATRIXB_PRBS_M9PR_Msk & ((value) << HMATRIXB_PRBS_M9PR_Pos)) 185 #define HMATRIXB_PRBS_M10PR_Pos 8 /**< \brief (HMATRIXB_PRBS) Master 10 Priority */ 186 #define HMATRIXB_PRBS_M10PR_Msk (_U_(0xF) << HMATRIXB_PRBS_M10PR_Pos) 187 #define HMATRIXB_PRBS_M10PR(value) (HMATRIXB_PRBS_M10PR_Msk & ((value) << HMATRIXB_PRBS_M10PR_Pos)) 188 #define HMATRIXB_PRBS_M11PR_Pos 12 /**< \brief (HMATRIXB_PRBS) Master 11 Priority */ 189 #define HMATRIXB_PRBS_M11PR_Msk (_U_(0xF) << HMATRIXB_PRBS_M11PR_Pos) 190 #define HMATRIXB_PRBS_M11PR(value) (HMATRIXB_PRBS_M11PR_Msk & ((value) << HMATRIXB_PRBS_M11PR_Pos)) 191 #define HMATRIXB_PRBS_M12PR_Pos 16 /**< \brief (HMATRIXB_PRBS) Master 12 Priority */ 192 #define HMATRIXB_PRBS_M12PR_Msk (_U_(0xF) << HMATRIXB_PRBS_M12PR_Pos) 193 #define HMATRIXB_PRBS_M12PR(value) (HMATRIXB_PRBS_M12PR_Msk & ((value) << HMATRIXB_PRBS_M12PR_Pos)) 194 #define HMATRIXB_PRBS_M13PR_Pos 20 /**< \brief (HMATRIXB_PRBS) Master 13 Priority */ 195 #define HMATRIXB_PRBS_M13PR_Msk (_U_(0xF) << HMATRIXB_PRBS_M13PR_Pos) 196 #define HMATRIXB_PRBS_M13PR(value) (HMATRIXB_PRBS_M13PR_Msk & ((value) << HMATRIXB_PRBS_M13PR_Pos)) 197 #define HMATRIXB_PRBS_M14PR_Pos 24 /**< \brief (HMATRIXB_PRBS) Master 14 Priority */ 198 #define HMATRIXB_PRBS_M14PR_Msk (_U_(0xF) << HMATRIXB_PRBS_M14PR_Pos) 199 #define HMATRIXB_PRBS_M14PR(value) (HMATRIXB_PRBS_M14PR_Msk & ((value) << HMATRIXB_PRBS_M14PR_Pos)) 200 #define HMATRIXB_PRBS_M15PR_Pos 28 /**< \brief (HMATRIXB_PRBS) Master 15 Priority */ 201 #define HMATRIXB_PRBS_M15PR_Msk (_U_(0xF) << HMATRIXB_PRBS_M15PR_Pos) 202 #define HMATRIXB_PRBS_M15PR(value) (HMATRIXB_PRBS_M15PR_Msk & ((value) << HMATRIXB_PRBS_M15PR_Pos)) 203 #define HMATRIXB_PRBS_MASK _U_(0xFFFFFFFF) /**< \brief (HMATRIXB_PRBS) MASK Register */ 204 205 /* -------- HMATRIXB_MRCR : (HMATRIXB Offset: 0x100) (R/W 32) Master Remap Control -------- */ 206 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 207 typedef union { 208 struct { 209 uint32_t RCB0:1; /*!< bit: 0 Remap Command Bit for Master 0 */ 210 uint32_t RCB1:1; /*!< bit: 1 Remap Command Bit for Master 1 */ 211 uint32_t RCB2:1; /*!< bit: 2 Remap Command Bit for Master 2 */ 212 uint32_t RCB3:1; /*!< bit: 3 Remap Command Bit for Master 3 */ 213 uint32_t RCB4:1; /*!< bit: 4 Remap Command Bit for Master 4 */ 214 uint32_t RCB5:1; /*!< bit: 5 Remap Command Bit for Master 5 */ 215 uint32_t RCB6:1; /*!< bit: 6 Remap Command Bit for Master 6 */ 216 uint32_t RCB7:1; /*!< bit: 7 Remap Command Bit for Master 7 */ 217 uint32_t RCB8:1; /*!< bit: 8 Remap Command Bit for Master 8 */ 218 uint32_t RCB9:1; /*!< bit: 9 Remap Command Bit for Master 9 */ 219 uint32_t RCB10:1; /*!< bit: 10 Remap Command Bit for Master 10 */ 220 uint32_t RCB11:1; /*!< bit: 11 Remap Command Bit for Master 11 */ 221 uint32_t RCB12:1; /*!< bit: 12 Remap Command Bit for Master 12 */ 222 uint32_t RCB13:1; /*!< bit: 13 Remap Command Bit for Master 13 */ 223 uint32_t RCB14:1; /*!< bit: 14 Remap Command Bit for Master 14 */ 224 uint32_t RCB15:1; /*!< bit: 15 Remap Command Bit for Master 15 */ 225 uint32_t :16; /*!< bit: 16..31 Reserved */ 226 } bit; /*!< Structure used for bit access */ 227 uint32_t reg; /*!< Type used for register access */ 228 } HMATRIXB_MRCR_Type; 229 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 230 231 #define HMATRIXB_MRCR_OFFSET 0x100 /**< \brief (HMATRIXB_MRCR offset) Master Remap Control */ 232 #define HMATRIXB_MRCR_RESETVALUE _U_(0x00000000) /**< \brief (HMATRIXB_MRCR reset_value) Master Remap Control */ 233 234 #define HMATRIXB_MRCR_RCB0_Pos 0 /**< \brief (HMATRIXB_MRCR) Remap Command Bit for Master 0 */ 235 #define HMATRIXB_MRCR_RCB0 (_U_(0x1) << HMATRIXB_MRCR_RCB0_Pos) 236 #define HMATRIXB_MRCR_RCB0_DIS_Val _U_(0x0) /**< \brief (HMATRIXB_MRCR) Disable remapped address decoding for master */ 237 #define HMATRIXB_MRCR_RCB0_ENA_Val _U_(0x1) /**< \brief (HMATRIXB_MRCR) Enable remapped address decoding for master */ 238 #define HMATRIXB_MRCR_RCB0_DIS (HMATRIXB_MRCR_RCB0_DIS_Val << HMATRIXB_MRCR_RCB0_Pos) 239 #define HMATRIXB_MRCR_RCB0_ENA (HMATRIXB_MRCR_RCB0_ENA_Val << HMATRIXB_MRCR_RCB0_Pos) 240 #define HMATRIXB_MRCR_RCB1_Pos 1 /**< \brief (HMATRIXB_MRCR) Remap Command Bit for Master 1 */ 241 #define HMATRIXB_MRCR_RCB1 (_U_(0x1) << HMATRIXB_MRCR_RCB1_Pos) 242 #define HMATRIXB_MRCR_RCB1_DIS_Val _U_(0x0) /**< \brief (HMATRIXB_MRCR) Disable remapped address decoding for master */ 243 #define HMATRIXB_MRCR_RCB1_ENA_Val _U_(0x1) /**< \brief (HMATRIXB_MRCR) Enable remapped address decoding for master */ 244 #define HMATRIXB_MRCR_RCB1_DIS (HMATRIXB_MRCR_RCB1_DIS_Val << HMATRIXB_MRCR_RCB1_Pos) 245 #define HMATRIXB_MRCR_RCB1_ENA (HMATRIXB_MRCR_RCB1_ENA_Val << HMATRIXB_MRCR_RCB1_Pos) 246 #define HMATRIXB_MRCR_RCB2_Pos 2 /**< \brief (HMATRIXB_MRCR) Remap Command Bit for Master 2 */ 247 #define HMATRIXB_MRCR_RCB2 (_U_(0x1) << HMATRIXB_MRCR_RCB2_Pos) 248 #define HMATRIXB_MRCR_RCB2_DIS_Val _U_(0x0) /**< \brief (HMATRIXB_MRCR) Disable remapped address decoding for master */ 249 #define HMATRIXB_MRCR_RCB2_ENA_Val _U_(0x1) /**< \brief (HMATRIXB_MRCR) Enable remapped address decoding for master */ 250 #define HMATRIXB_MRCR_RCB2_DIS (HMATRIXB_MRCR_RCB2_DIS_Val << HMATRIXB_MRCR_RCB2_Pos) 251 #define HMATRIXB_MRCR_RCB2_ENA (HMATRIXB_MRCR_RCB2_ENA_Val << HMATRIXB_MRCR_RCB2_Pos) 252 #define HMATRIXB_MRCR_RCB3_Pos 3 /**< \brief (HMATRIXB_MRCR) Remap Command Bit for Master 3 */ 253 #define HMATRIXB_MRCR_RCB3 (_U_(0x1) << HMATRIXB_MRCR_RCB3_Pos) 254 #define HMATRIXB_MRCR_RCB3_DIS_Val _U_(0x0) /**< \brief (HMATRIXB_MRCR) Disable remapped address decoding for master */ 255 #define HMATRIXB_MRCR_RCB3_ENA_Val _U_(0x1) /**< \brief (HMATRIXB_MRCR) Enable remapped address decoding for master */ 256 #define HMATRIXB_MRCR_RCB3_DIS (HMATRIXB_MRCR_RCB3_DIS_Val << HMATRIXB_MRCR_RCB3_Pos) 257 #define HMATRIXB_MRCR_RCB3_ENA (HMATRIXB_MRCR_RCB3_ENA_Val << HMATRIXB_MRCR_RCB3_Pos) 258 #define HMATRIXB_MRCR_RCB4_Pos 4 /**< \brief (HMATRIXB_MRCR) Remap Command Bit for Master 4 */ 259 #define HMATRIXB_MRCR_RCB4 (_U_(0x1) << HMATRIXB_MRCR_RCB4_Pos) 260 #define HMATRIXB_MRCR_RCB4_DIS_Val _U_(0x0) /**< \brief (HMATRIXB_MRCR) Disable remapped address decoding for master */ 261 #define HMATRIXB_MRCR_RCB4_ENA_Val _U_(0x1) /**< \brief (HMATRIXB_MRCR) Enable remapped address decoding for master */ 262 #define HMATRIXB_MRCR_RCB4_DIS (HMATRIXB_MRCR_RCB4_DIS_Val << HMATRIXB_MRCR_RCB4_Pos) 263 #define HMATRIXB_MRCR_RCB4_ENA (HMATRIXB_MRCR_RCB4_ENA_Val << HMATRIXB_MRCR_RCB4_Pos) 264 #define HMATRIXB_MRCR_RCB5_Pos 5 /**< \brief (HMATRIXB_MRCR) Remap Command Bit for Master 5 */ 265 #define HMATRIXB_MRCR_RCB5 (_U_(0x1) << HMATRIXB_MRCR_RCB5_Pos) 266 #define HMATRIXB_MRCR_RCB5_DIS_Val _U_(0x0) /**< \brief (HMATRIXB_MRCR) Disable remapped address decoding for master */ 267 #define HMATRIXB_MRCR_RCB5_ENA_Val _U_(0x1) /**< \brief (HMATRIXB_MRCR) Enable remapped address decoding for master */ 268 #define HMATRIXB_MRCR_RCB5_DIS (HMATRIXB_MRCR_RCB5_DIS_Val << HMATRIXB_MRCR_RCB5_Pos) 269 #define HMATRIXB_MRCR_RCB5_ENA (HMATRIXB_MRCR_RCB5_ENA_Val << HMATRIXB_MRCR_RCB5_Pos) 270 #define HMATRIXB_MRCR_RCB6_Pos 6 /**< \brief (HMATRIXB_MRCR) Remap Command Bit for Master 6 */ 271 #define HMATRIXB_MRCR_RCB6 (_U_(0x1) << HMATRIXB_MRCR_RCB6_Pos) 272 #define HMATRIXB_MRCR_RCB6_DIS_Val _U_(0x0) /**< \brief (HMATRIXB_MRCR) Disable remapped address decoding for master */ 273 #define HMATRIXB_MRCR_RCB6_ENA_Val _U_(0x1) /**< \brief (HMATRIXB_MRCR) Enable remapped address decoding for master */ 274 #define HMATRIXB_MRCR_RCB6_DIS (HMATRIXB_MRCR_RCB6_DIS_Val << HMATRIXB_MRCR_RCB6_Pos) 275 #define HMATRIXB_MRCR_RCB6_ENA (HMATRIXB_MRCR_RCB6_ENA_Val << HMATRIXB_MRCR_RCB6_Pos) 276 #define HMATRIXB_MRCR_RCB7_Pos 7 /**< \brief (HMATRIXB_MRCR) Remap Command Bit for Master 7 */ 277 #define HMATRIXB_MRCR_RCB7 (_U_(0x1) << HMATRIXB_MRCR_RCB7_Pos) 278 #define HMATRIXB_MRCR_RCB7_DIS_Val _U_(0x0) /**< \brief (HMATRIXB_MRCR) Disable remapped address decoding for master */ 279 #define HMATRIXB_MRCR_RCB7_ENA_Val _U_(0x1) /**< \brief (HMATRIXB_MRCR) Enable remapped address decoding for master */ 280 #define HMATRIXB_MRCR_RCB7_DIS (HMATRIXB_MRCR_RCB7_DIS_Val << HMATRIXB_MRCR_RCB7_Pos) 281 #define HMATRIXB_MRCR_RCB7_ENA (HMATRIXB_MRCR_RCB7_ENA_Val << HMATRIXB_MRCR_RCB7_Pos) 282 #define HMATRIXB_MRCR_RCB8_Pos 8 /**< \brief (HMATRIXB_MRCR) Remap Command Bit for Master 8 */ 283 #define HMATRIXB_MRCR_RCB8 (_U_(0x1) << HMATRIXB_MRCR_RCB8_Pos) 284 #define HMATRIXB_MRCR_RCB8_DIS_Val _U_(0x0) /**< \brief (HMATRIXB_MRCR) Disable remapped address decoding for master */ 285 #define HMATRIXB_MRCR_RCB8_ENA_Val _U_(0x1) /**< \brief (HMATRIXB_MRCR) Enable remapped address decoding for master */ 286 #define HMATRIXB_MRCR_RCB8_DIS (HMATRIXB_MRCR_RCB8_DIS_Val << HMATRIXB_MRCR_RCB8_Pos) 287 #define HMATRIXB_MRCR_RCB8_ENA (HMATRIXB_MRCR_RCB8_ENA_Val << HMATRIXB_MRCR_RCB8_Pos) 288 #define HMATRIXB_MRCR_RCB9_Pos 9 /**< \brief (HMATRIXB_MRCR) Remap Command Bit for Master 9 */ 289 #define HMATRIXB_MRCR_RCB9 (_U_(0x1) << HMATRIXB_MRCR_RCB9_Pos) 290 #define HMATRIXB_MRCR_RCB9_DIS_Val _U_(0x0) /**< \brief (HMATRIXB_MRCR) Disable remapped address decoding for master */ 291 #define HMATRIXB_MRCR_RCB9_ENA_Val _U_(0x1) /**< \brief (HMATRIXB_MRCR) Enable remapped address decoding for master */ 292 #define HMATRIXB_MRCR_RCB9_DIS (HMATRIXB_MRCR_RCB9_DIS_Val << HMATRIXB_MRCR_RCB9_Pos) 293 #define HMATRIXB_MRCR_RCB9_ENA (HMATRIXB_MRCR_RCB9_ENA_Val << HMATRIXB_MRCR_RCB9_Pos) 294 #define HMATRIXB_MRCR_RCB10_Pos 10 /**< \brief (HMATRIXB_MRCR) Remap Command Bit for Master 10 */ 295 #define HMATRIXB_MRCR_RCB10 (_U_(0x1) << HMATRIXB_MRCR_RCB10_Pos) 296 #define HMATRIXB_MRCR_RCB10_DIS_Val _U_(0x0) /**< \brief (HMATRIXB_MRCR) Disable remapped address decoding for master */ 297 #define HMATRIXB_MRCR_RCB10_ENA_Val _U_(0x1) /**< \brief (HMATRIXB_MRCR) Enable remapped address decoding for master */ 298 #define HMATRIXB_MRCR_RCB10_DIS (HMATRIXB_MRCR_RCB10_DIS_Val << HMATRIXB_MRCR_RCB10_Pos) 299 #define HMATRIXB_MRCR_RCB10_ENA (HMATRIXB_MRCR_RCB10_ENA_Val << HMATRIXB_MRCR_RCB10_Pos) 300 #define HMATRIXB_MRCR_RCB11_Pos 11 /**< \brief (HMATRIXB_MRCR) Remap Command Bit for Master 11 */ 301 #define HMATRIXB_MRCR_RCB11 (_U_(0x1) << HMATRIXB_MRCR_RCB11_Pos) 302 #define HMATRIXB_MRCR_RCB11_DIS_Val _U_(0x0) /**< \brief (HMATRIXB_MRCR) Disable remapped address decoding for master */ 303 #define HMATRIXB_MRCR_RCB11_ENA_Val _U_(0x1) /**< \brief (HMATRIXB_MRCR) Enable remapped address decoding for master */ 304 #define HMATRIXB_MRCR_RCB11_DIS (HMATRIXB_MRCR_RCB11_DIS_Val << HMATRIXB_MRCR_RCB11_Pos) 305 #define HMATRIXB_MRCR_RCB11_ENA (HMATRIXB_MRCR_RCB11_ENA_Val << HMATRIXB_MRCR_RCB11_Pos) 306 #define HMATRIXB_MRCR_RCB12_Pos 12 /**< \brief (HMATRIXB_MRCR) Remap Command Bit for Master 12 */ 307 #define HMATRIXB_MRCR_RCB12 (_U_(0x1) << HMATRIXB_MRCR_RCB12_Pos) 308 #define HMATRIXB_MRCR_RCB12_DIS_Val _U_(0x0) /**< \brief (HMATRIXB_MRCR) Disable remapped address decoding for master */ 309 #define HMATRIXB_MRCR_RCB12_ENA_Val _U_(0x1) /**< \brief (HMATRIXB_MRCR) Enable remapped address decoding for master */ 310 #define HMATRIXB_MRCR_RCB12_DIS (HMATRIXB_MRCR_RCB12_DIS_Val << HMATRIXB_MRCR_RCB12_Pos) 311 #define HMATRIXB_MRCR_RCB12_ENA (HMATRIXB_MRCR_RCB12_ENA_Val << HMATRIXB_MRCR_RCB12_Pos) 312 #define HMATRIXB_MRCR_RCB13_Pos 13 /**< \brief (HMATRIXB_MRCR) Remap Command Bit for Master 13 */ 313 #define HMATRIXB_MRCR_RCB13 (_U_(0x1) << HMATRIXB_MRCR_RCB13_Pos) 314 #define HMATRIXB_MRCR_RCB13_DIS_Val _U_(0x0) /**< \brief (HMATRIXB_MRCR) Disable remapped address decoding for master */ 315 #define HMATRIXB_MRCR_RCB13_ENA_Val _U_(0x1) /**< \brief (HMATRIXB_MRCR) Enable remapped address decoding for master */ 316 #define HMATRIXB_MRCR_RCB13_DIS (HMATRIXB_MRCR_RCB13_DIS_Val << HMATRIXB_MRCR_RCB13_Pos) 317 #define HMATRIXB_MRCR_RCB13_ENA (HMATRIXB_MRCR_RCB13_ENA_Val << HMATRIXB_MRCR_RCB13_Pos) 318 #define HMATRIXB_MRCR_RCB14_Pos 14 /**< \brief (HMATRIXB_MRCR) Remap Command Bit for Master 14 */ 319 #define HMATRIXB_MRCR_RCB14 (_U_(0x1) << HMATRIXB_MRCR_RCB14_Pos) 320 #define HMATRIXB_MRCR_RCB14_DIS_Val _U_(0x0) /**< \brief (HMATRIXB_MRCR) Disable remapped address decoding for master */ 321 #define HMATRIXB_MRCR_RCB14_ENA_Val _U_(0x1) /**< \brief (HMATRIXB_MRCR) Enable remapped address decoding for master */ 322 #define HMATRIXB_MRCR_RCB14_DIS (HMATRIXB_MRCR_RCB14_DIS_Val << HMATRIXB_MRCR_RCB14_Pos) 323 #define HMATRIXB_MRCR_RCB14_ENA (HMATRIXB_MRCR_RCB14_ENA_Val << HMATRIXB_MRCR_RCB14_Pos) 324 #define HMATRIXB_MRCR_RCB15_Pos 15 /**< \brief (HMATRIXB_MRCR) Remap Command Bit for Master 15 */ 325 #define HMATRIXB_MRCR_RCB15 (_U_(0x1) << HMATRIXB_MRCR_RCB15_Pos) 326 #define HMATRIXB_MRCR_RCB15_DIS_Val _U_(0x0) /**< \brief (HMATRIXB_MRCR) Disable remapped address decoding for master */ 327 #define HMATRIXB_MRCR_RCB15_ENA_Val _U_(0x1) /**< \brief (HMATRIXB_MRCR) Enable remapped address decoding for master */ 328 #define HMATRIXB_MRCR_RCB15_DIS (HMATRIXB_MRCR_RCB15_DIS_Val << HMATRIXB_MRCR_RCB15_Pos) 329 #define HMATRIXB_MRCR_RCB15_ENA (HMATRIXB_MRCR_RCB15_ENA_Val << HMATRIXB_MRCR_RCB15_Pos) 330 #define HMATRIXB_MRCR_MASK _U_(0x0000FFFF) /**< \brief (HMATRIXB_MRCR) MASK Register */ 331 332 /* -------- HMATRIXB_SFR : (HMATRIXB Offset: 0x110) (R/W 32) Special Function -------- */ 333 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 334 typedef union { 335 struct { 336 uint32_t SFR:32; /*!< bit: 0..31 Special Function Register */ 337 } bit; /*!< Structure used for bit access */ 338 uint32_t reg; /*!< Type used for register access */ 339 } HMATRIXB_SFR_Type; 340 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 341 342 #define HMATRIXB_SFR_OFFSET 0x110 /**< \brief (HMATRIXB_SFR offset) Special Function */ 343 #define HMATRIXB_SFR_RESETVALUE _U_(0x00000000) /**< \brief (HMATRIXB_SFR reset_value) Special Function */ 344 345 #define HMATRIXB_SFR_SFR_Pos 0 /**< \brief (HMATRIXB_SFR) Special Function Register */ 346 #define HMATRIXB_SFR_SFR_Msk (_U_(0xFFFFFFFF) << HMATRIXB_SFR_SFR_Pos) 347 #define HMATRIXB_SFR_SFR(value) (HMATRIXB_SFR_SFR_Msk & ((value) << HMATRIXB_SFR_SFR_Pos)) 348 #define HMATRIXB_SFR_MASK _U_(0xFFFFFFFF) /**< \brief (HMATRIXB_SFR) MASK Register */ 349 350 /** \brief HmatrixbPrs hardware registers */ 351 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 352 typedef struct { 353 __IO HMATRIXB_PRAS_Type PRAS; /**< \brief Offset: 0x000 (R/W 32) Priority A for Slave */ 354 __IO HMATRIXB_PRBS_Type PRBS; /**< \brief Offset: 0x004 (R/W 32) Priority B for Slave */ 355 } HmatrixbPrs; 356 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 357 358 /** \brief HMATRIXB hardware registers */ 359 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 360 typedef struct { 361 __IO HMATRIXB_MCFG_Type MCFG[16]; /**< \brief Offset: 0x000 (R/W 32) Master Configuration */ 362 __IO HMATRIXB_SCFG_Type SCFG[16]; /**< \brief Offset: 0x040 (R/W 32) Slave Configuration */ 363 HmatrixbPrs Prs[4]; /**< \brief Offset: 0x080 HmatrixbPrs groups [CLK_AHB_ID] */ 364 RoReg8 Reserved1[0x60]; 365 __IO HMATRIXB_MRCR_Type MRCR; /**< \brief Offset: 0x100 (R/W 32) Master Remap Control */ 366 RoReg8 Reserved2[0xC]; 367 __IO HMATRIXB_SFR_Type SFR[16]; /**< \brief Offset: 0x110 (R/W 32) Special Function */ 368 } Hmatrixb; 369 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 370 371 /*@}*/ 372 373 #endif /* _SAMC21_HMATRIXB_COMPONENT_ */ 374
