1 /** 2 * \file 3 * 4 * \brief Component description for DMAC 5 * 6 * Copyright (c) 2018 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAMC20_DMAC_COMPONENT_ 31 #define _SAMC20_DMAC_COMPONENT_ 32 33 /* ========================================================================== */ 34 /** SOFTWARE API DEFINITION FOR DMAC */ 35 /* ========================================================================== */ 36 /** \addtogroup SAMC20_DMAC Direct Memory Access Controller */ 37 /*@{*/ 38 39 #define DMAC_U2223 40 #define REV_DMAC 0x230 41 42 /* -------- DMAC_CTRL : (DMAC Offset: 0x00) (R/W 16) Control -------- */ 43 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 44 typedef union { 45 struct { 46 uint16_t SWRST:1; /*!< bit: 0 Software Reset */ 47 uint16_t DMAENABLE:1; /*!< bit: 1 DMA Enable */ 48 uint16_t CRCENABLE:1; /*!< bit: 2 CRC Enable */ 49 uint16_t :5; /*!< bit: 3.. 7 Reserved */ 50 uint16_t LVLEN0:1; /*!< bit: 8 Priority Level 0 Enable */ 51 uint16_t LVLEN1:1; /*!< bit: 9 Priority Level 1 Enable */ 52 uint16_t LVLEN2:1; /*!< bit: 10 Priority Level 2 Enable */ 53 uint16_t LVLEN3:1; /*!< bit: 11 Priority Level 3 Enable */ 54 uint16_t :4; /*!< bit: 12..15 Reserved */ 55 } bit; /*!< Structure used for bit access */ 56 struct { 57 uint16_t :8; /*!< bit: 0.. 7 Reserved */ 58 uint16_t LVLEN:4; /*!< bit: 8..11 Priority Level x Enable */ 59 uint16_t :4; /*!< bit: 12..15 Reserved */ 60 } vec; /*!< Structure used for vec access */ 61 uint16_t reg; /*!< Type used for register access */ 62 } DMAC_CTRL_Type; 63 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 64 65 #define DMAC_CTRL_OFFSET 0x00 /**< \brief (DMAC_CTRL offset) Control */ 66 #define DMAC_CTRL_RESETVALUE _U_(0x0000) /**< \brief (DMAC_CTRL reset_value) Control */ 67 68 #define DMAC_CTRL_SWRST_Pos 0 /**< \brief (DMAC_CTRL) Software Reset */ 69 #define DMAC_CTRL_SWRST (_U_(0x1) << DMAC_CTRL_SWRST_Pos) 70 #define DMAC_CTRL_DMAENABLE_Pos 1 /**< \brief (DMAC_CTRL) DMA Enable */ 71 #define DMAC_CTRL_DMAENABLE (_U_(0x1) << DMAC_CTRL_DMAENABLE_Pos) 72 #define DMAC_CTRL_CRCENABLE_Pos 2 /**< \brief (DMAC_CTRL) CRC Enable */ 73 #define DMAC_CTRL_CRCENABLE (_U_(0x1) << DMAC_CTRL_CRCENABLE_Pos) 74 #define DMAC_CTRL_LVLEN0_Pos 8 /**< \brief (DMAC_CTRL) Priority Level 0 Enable */ 75 #define DMAC_CTRL_LVLEN0 (_U_(1) << DMAC_CTRL_LVLEN0_Pos) 76 #define DMAC_CTRL_LVLEN1_Pos 9 /**< \brief (DMAC_CTRL) Priority Level 1 Enable */ 77 #define DMAC_CTRL_LVLEN1 (_U_(1) << DMAC_CTRL_LVLEN1_Pos) 78 #define DMAC_CTRL_LVLEN2_Pos 10 /**< \brief (DMAC_CTRL) Priority Level 2 Enable */ 79 #define DMAC_CTRL_LVLEN2 (_U_(1) << DMAC_CTRL_LVLEN2_Pos) 80 #define DMAC_CTRL_LVLEN3_Pos 11 /**< \brief (DMAC_CTRL) Priority Level 3 Enable */ 81 #define DMAC_CTRL_LVLEN3 (_U_(1) << DMAC_CTRL_LVLEN3_Pos) 82 #define DMAC_CTRL_LVLEN_Pos 8 /**< \brief (DMAC_CTRL) Priority Level x Enable */ 83 #define DMAC_CTRL_LVLEN_Msk (_U_(0xF) << DMAC_CTRL_LVLEN_Pos) 84 #define DMAC_CTRL_LVLEN(value) (DMAC_CTRL_LVLEN_Msk & ((value) << DMAC_CTRL_LVLEN_Pos)) 85 #define DMAC_CTRL_MASK _U_(0x0F07) /**< \brief (DMAC_CTRL) MASK Register */ 86 87 /* -------- DMAC_CRCCTRL : (DMAC Offset: 0x02) (R/W 16) CRC Control -------- */ 88 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 89 typedef union { 90 struct { 91 uint16_t CRCBEATSIZE:2; /*!< bit: 0.. 1 CRC Beat Size */ 92 uint16_t CRCPOLY:2; /*!< bit: 2.. 3 CRC Polynomial Type */ 93 uint16_t :4; /*!< bit: 4.. 7 Reserved */ 94 uint16_t CRCSRC:6; /*!< bit: 8..13 CRC Input Source */ 95 uint16_t :2; /*!< bit: 14..15 Reserved */ 96 } bit; /*!< Structure used for bit access */ 97 uint16_t reg; /*!< Type used for register access */ 98 } DMAC_CRCCTRL_Type; 99 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 100 101 #define DMAC_CRCCTRL_OFFSET 0x02 /**< \brief (DMAC_CRCCTRL offset) CRC Control */ 102 #define DMAC_CRCCTRL_RESETVALUE _U_(0x0000) /**< \brief (DMAC_CRCCTRL reset_value) CRC Control */ 103 104 #define DMAC_CRCCTRL_CRCBEATSIZE_Pos 0 /**< \brief (DMAC_CRCCTRL) CRC Beat Size */ 105 #define DMAC_CRCCTRL_CRCBEATSIZE_Msk (_U_(0x3) << DMAC_CRCCTRL_CRCBEATSIZE_Pos) 106 #define DMAC_CRCCTRL_CRCBEATSIZE(value) (DMAC_CRCCTRL_CRCBEATSIZE_Msk & ((value) << DMAC_CRCCTRL_CRCBEATSIZE_Pos)) 107 #define DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val _U_(0x0) /**< \brief (DMAC_CRCCTRL) 8-bit bus transfer */ 108 #define DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val _U_(0x1) /**< \brief (DMAC_CRCCTRL) 16-bit bus transfer */ 109 #define DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val _U_(0x2) /**< \brief (DMAC_CRCCTRL) 32-bit bus transfer */ 110 #define DMAC_CRCCTRL_CRCBEATSIZE_BYTE (DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos) 111 #define DMAC_CRCCTRL_CRCBEATSIZE_HWORD (DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos) 112 #define DMAC_CRCCTRL_CRCBEATSIZE_WORD (DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos) 113 #define DMAC_CRCCTRL_CRCPOLY_Pos 2 /**< \brief (DMAC_CRCCTRL) CRC Polynomial Type */ 114 #define DMAC_CRCCTRL_CRCPOLY_Msk (_U_(0x3) << DMAC_CRCCTRL_CRCPOLY_Pos) 115 #define DMAC_CRCCTRL_CRCPOLY(value) (DMAC_CRCCTRL_CRCPOLY_Msk & ((value) << DMAC_CRCCTRL_CRCPOLY_Pos)) 116 #define DMAC_CRCCTRL_CRCPOLY_CRC16_Val _U_(0x0) /**< \brief (DMAC_CRCCTRL) CRC-16 (CRC-CCITT) */ 117 #define DMAC_CRCCTRL_CRCPOLY_CRC32_Val _U_(0x1) /**< \brief (DMAC_CRCCTRL) CRC32 (IEEE 802.3) */ 118 #define DMAC_CRCCTRL_CRCPOLY_CRC16 (DMAC_CRCCTRL_CRCPOLY_CRC16_Val << DMAC_CRCCTRL_CRCPOLY_Pos) 119 #define DMAC_CRCCTRL_CRCPOLY_CRC32 (DMAC_CRCCTRL_CRCPOLY_CRC32_Val << DMAC_CRCCTRL_CRCPOLY_Pos) 120 #define DMAC_CRCCTRL_CRCSRC_Pos 8 /**< \brief (DMAC_CRCCTRL) CRC Input Source */ 121 #define DMAC_CRCCTRL_CRCSRC_Msk (_U_(0x3F) << DMAC_CRCCTRL_CRCSRC_Pos) 122 #define DMAC_CRCCTRL_CRCSRC(value) (DMAC_CRCCTRL_CRCSRC_Msk & ((value) << DMAC_CRCCTRL_CRCSRC_Pos)) 123 #define DMAC_CRCCTRL_CRCSRC_NOACT_Val _U_(0x0) /**< \brief (DMAC_CRCCTRL) No action */ 124 #define DMAC_CRCCTRL_CRCSRC_IO_Val _U_(0x1) /**< \brief (DMAC_CRCCTRL) I/O interface */ 125 #define DMAC_CRCCTRL_CRCSRC_NOACT (DMAC_CRCCTRL_CRCSRC_NOACT_Val << DMAC_CRCCTRL_CRCSRC_Pos) 126 #define DMAC_CRCCTRL_CRCSRC_IO (DMAC_CRCCTRL_CRCSRC_IO_Val << DMAC_CRCCTRL_CRCSRC_Pos) 127 #define DMAC_CRCCTRL_MASK _U_(0x3F0F) /**< \brief (DMAC_CRCCTRL) MASK Register */ 128 129 /* -------- DMAC_CRCDATAIN : (DMAC Offset: 0x04) (R/W 32) CRC Data Input -------- */ 130 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 131 typedef union { 132 struct { 133 uint32_t CRCDATAIN:32; /*!< bit: 0..31 CRC Data Input */ 134 } bit; /*!< Structure used for bit access */ 135 uint32_t reg; /*!< Type used for register access */ 136 } DMAC_CRCDATAIN_Type; 137 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 138 139 #define DMAC_CRCDATAIN_OFFSET 0x04 /**< \brief (DMAC_CRCDATAIN offset) CRC Data Input */ 140 #define DMAC_CRCDATAIN_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_CRCDATAIN reset_value) CRC Data Input */ 141 142 #define DMAC_CRCDATAIN_CRCDATAIN_Pos 0 /**< \brief (DMAC_CRCDATAIN) CRC Data Input */ 143 #define DMAC_CRCDATAIN_CRCDATAIN_Msk (_U_(0xFFFFFFFF) << DMAC_CRCDATAIN_CRCDATAIN_Pos) 144 #define DMAC_CRCDATAIN_CRCDATAIN(value) (DMAC_CRCDATAIN_CRCDATAIN_Msk & ((value) << DMAC_CRCDATAIN_CRCDATAIN_Pos)) 145 #define DMAC_CRCDATAIN_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_CRCDATAIN) MASK Register */ 146 147 /* -------- DMAC_CRCCHKSUM : (DMAC Offset: 0x08) (R/W 32) CRC Checksum -------- */ 148 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 149 typedef union { 150 struct { 151 uint32_t CRCCHKSUM:32; /*!< bit: 0..31 CRC Checksum */ 152 } bit; /*!< Structure used for bit access */ 153 uint32_t reg; /*!< Type used for register access */ 154 } DMAC_CRCCHKSUM_Type; 155 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 156 157 #define DMAC_CRCCHKSUM_OFFSET 0x08 /**< \brief (DMAC_CRCCHKSUM offset) CRC Checksum */ 158 #define DMAC_CRCCHKSUM_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_CRCCHKSUM reset_value) CRC Checksum */ 159 160 #define DMAC_CRCCHKSUM_CRCCHKSUM_Pos 0 /**< \brief (DMAC_CRCCHKSUM) CRC Checksum */ 161 #define DMAC_CRCCHKSUM_CRCCHKSUM_Msk (_U_(0xFFFFFFFF) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos) 162 #define DMAC_CRCCHKSUM_CRCCHKSUM(value) (DMAC_CRCCHKSUM_CRCCHKSUM_Msk & ((value) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos)) 163 #define DMAC_CRCCHKSUM_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_CRCCHKSUM) MASK Register */ 164 165 /* -------- DMAC_CRCSTATUS : (DMAC Offset: 0x0C) (R/W 8) CRC Status -------- */ 166 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 167 typedef union { 168 struct { 169 uint8_t CRCBUSY:1; /*!< bit: 0 CRC Module Busy */ 170 uint8_t CRCZERO:1; /*!< bit: 1 CRC Zero */ 171 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 172 } bit; /*!< Structure used for bit access */ 173 uint8_t reg; /*!< Type used for register access */ 174 } DMAC_CRCSTATUS_Type; 175 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 176 177 #define DMAC_CRCSTATUS_OFFSET 0x0C /**< \brief (DMAC_CRCSTATUS offset) CRC Status */ 178 #define DMAC_CRCSTATUS_RESETVALUE _U_(0x00) /**< \brief (DMAC_CRCSTATUS reset_value) CRC Status */ 179 180 #define DMAC_CRCSTATUS_CRCBUSY_Pos 0 /**< \brief (DMAC_CRCSTATUS) CRC Module Busy */ 181 #define DMAC_CRCSTATUS_CRCBUSY (_U_(0x1) << DMAC_CRCSTATUS_CRCBUSY_Pos) 182 #define DMAC_CRCSTATUS_CRCZERO_Pos 1 /**< \brief (DMAC_CRCSTATUS) CRC Zero */ 183 #define DMAC_CRCSTATUS_CRCZERO (_U_(0x1) << DMAC_CRCSTATUS_CRCZERO_Pos) 184 #define DMAC_CRCSTATUS_MASK _U_(0x03) /**< \brief (DMAC_CRCSTATUS) MASK Register */ 185 186 /* -------- DMAC_DBGCTRL : (DMAC Offset: 0x0D) (R/W 8) Debug Control -------- */ 187 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 188 typedef union { 189 struct { 190 uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ 191 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 192 } bit; /*!< Structure used for bit access */ 193 uint8_t reg; /*!< Type used for register access */ 194 } DMAC_DBGCTRL_Type; 195 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 196 197 #define DMAC_DBGCTRL_OFFSET 0x0D /**< \brief (DMAC_DBGCTRL offset) Debug Control */ 198 #define DMAC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (DMAC_DBGCTRL reset_value) Debug Control */ 199 200 #define DMAC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (DMAC_DBGCTRL) Debug Run */ 201 #define DMAC_DBGCTRL_DBGRUN (_U_(0x1) << DMAC_DBGCTRL_DBGRUN_Pos) 202 #define DMAC_DBGCTRL_MASK _U_(0x01) /**< \brief (DMAC_DBGCTRL) MASK Register */ 203 204 /* -------- DMAC_SWTRIGCTRL : (DMAC Offset: 0x10) (R/W 32) Software Trigger Control -------- */ 205 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 206 typedef union { 207 struct { 208 uint32_t SWTRIG0:1; /*!< bit: 0 Channel 0 Software Trigger */ 209 uint32_t SWTRIG1:1; /*!< bit: 1 Channel 1 Software Trigger */ 210 uint32_t SWTRIG2:1; /*!< bit: 2 Channel 2 Software Trigger */ 211 uint32_t SWTRIG3:1; /*!< bit: 3 Channel 3 Software Trigger */ 212 uint32_t SWTRIG4:1; /*!< bit: 4 Channel 4 Software Trigger */ 213 uint32_t SWTRIG5:1; /*!< bit: 5 Channel 5 Software Trigger */ 214 uint32_t SWTRIG6:1; /*!< bit: 6 Channel 6 Software Trigger */ 215 uint32_t SWTRIG7:1; /*!< bit: 7 Channel 7 Software Trigger */ 216 uint32_t SWTRIG8:1; /*!< bit: 8 Channel 8 Software Trigger */ 217 uint32_t SWTRIG9:1; /*!< bit: 9 Channel 9 Software Trigger */ 218 uint32_t SWTRIG10:1; /*!< bit: 10 Channel 10 Software Trigger */ 219 uint32_t SWTRIG11:1; /*!< bit: 11 Channel 11 Software Trigger */ 220 uint32_t :20; /*!< bit: 12..31 Reserved */ 221 } bit; /*!< Structure used for bit access */ 222 struct { 223 uint32_t SWTRIG:12; /*!< bit: 0..11 Channel x Software Trigger */ 224 uint32_t :20; /*!< bit: 12..31 Reserved */ 225 } vec; /*!< Structure used for vec access */ 226 uint32_t reg; /*!< Type used for register access */ 227 } DMAC_SWTRIGCTRL_Type; 228 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 229 230 #define DMAC_SWTRIGCTRL_OFFSET 0x10 /**< \brief (DMAC_SWTRIGCTRL offset) Software Trigger Control */ 231 #define DMAC_SWTRIGCTRL_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_SWTRIGCTRL reset_value) Software Trigger Control */ 232 233 #define DMAC_SWTRIGCTRL_SWTRIG0_Pos 0 /**< \brief (DMAC_SWTRIGCTRL) Channel 0 Software Trigger */ 234 #define DMAC_SWTRIGCTRL_SWTRIG0 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG0_Pos) 235 #define DMAC_SWTRIGCTRL_SWTRIG1_Pos 1 /**< \brief (DMAC_SWTRIGCTRL) Channel 1 Software Trigger */ 236 #define DMAC_SWTRIGCTRL_SWTRIG1 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG1_Pos) 237 #define DMAC_SWTRIGCTRL_SWTRIG2_Pos 2 /**< \brief (DMAC_SWTRIGCTRL) Channel 2 Software Trigger */ 238 #define DMAC_SWTRIGCTRL_SWTRIG2 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG2_Pos) 239 #define DMAC_SWTRIGCTRL_SWTRIG3_Pos 3 /**< \brief (DMAC_SWTRIGCTRL) Channel 3 Software Trigger */ 240 #define DMAC_SWTRIGCTRL_SWTRIG3 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG3_Pos) 241 #define DMAC_SWTRIGCTRL_SWTRIG4_Pos 4 /**< \brief (DMAC_SWTRIGCTRL) Channel 4 Software Trigger */ 242 #define DMAC_SWTRIGCTRL_SWTRIG4 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG4_Pos) 243 #define DMAC_SWTRIGCTRL_SWTRIG5_Pos 5 /**< \brief (DMAC_SWTRIGCTRL) Channel 5 Software Trigger */ 244 #define DMAC_SWTRIGCTRL_SWTRIG5 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG5_Pos) 245 #define DMAC_SWTRIGCTRL_SWTRIG6_Pos 6 /**< \brief (DMAC_SWTRIGCTRL) Channel 6 Software Trigger */ 246 #define DMAC_SWTRIGCTRL_SWTRIG6 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG6_Pos) 247 #define DMAC_SWTRIGCTRL_SWTRIG7_Pos 7 /**< \brief (DMAC_SWTRIGCTRL) Channel 7 Software Trigger */ 248 #define DMAC_SWTRIGCTRL_SWTRIG7 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG7_Pos) 249 #define DMAC_SWTRIGCTRL_SWTRIG8_Pos 8 /**< \brief (DMAC_SWTRIGCTRL) Channel 8 Software Trigger */ 250 #define DMAC_SWTRIGCTRL_SWTRIG8 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG8_Pos) 251 #define DMAC_SWTRIGCTRL_SWTRIG9_Pos 9 /**< \brief (DMAC_SWTRIGCTRL) Channel 9 Software Trigger */ 252 #define DMAC_SWTRIGCTRL_SWTRIG9 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG9_Pos) 253 #define DMAC_SWTRIGCTRL_SWTRIG10_Pos 10 /**< \brief (DMAC_SWTRIGCTRL) Channel 10 Software Trigger */ 254 #define DMAC_SWTRIGCTRL_SWTRIG10 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG10_Pos) 255 #define DMAC_SWTRIGCTRL_SWTRIG11_Pos 11 /**< \brief (DMAC_SWTRIGCTRL) Channel 11 Software Trigger */ 256 #define DMAC_SWTRIGCTRL_SWTRIG11 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG11_Pos) 257 #define DMAC_SWTRIGCTRL_SWTRIG_Pos 0 /**< \brief (DMAC_SWTRIGCTRL) Channel x Software Trigger */ 258 #define DMAC_SWTRIGCTRL_SWTRIG_Msk (_U_(0xFFF) << DMAC_SWTRIGCTRL_SWTRIG_Pos) 259 #define DMAC_SWTRIGCTRL_SWTRIG(value) (DMAC_SWTRIGCTRL_SWTRIG_Msk & ((value) << DMAC_SWTRIGCTRL_SWTRIG_Pos)) 260 #define DMAC_SWTRIGCTRL_MASK _U_(0x00000FFF) /**< \brief (DMAC_SWTRIGCTRL) MASK Register */ 261 262 /* -------- DMAC_PRICTRL0 : (DMAC Offset: 0x14) (R/W 32) Priority Control 0 -------- */ 263 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 264 typedef union { 265 struct { 266 uint32_t LVLPRI0:4; /*!< bit: 0.. 3 Level 0 Channel Priority Number */ 267 uint32_t :3; /*!< bit: 4.. 6 Reserved */ 268 uint32_t RRLVLEN0:1; /*!< bit: 7 Level 0 Round-Robin Scheduling Enable */ 269 uint32_t LVLPRI1:4; /*!< bit: 8..11 Level 1 Channel Priority Number */ 270 uint32_t :3; /*!< bit: 12..14 Reserved */ 271 uint32_t RRLVLEN1:1; /*!< bit: 15 Level 1 Round-Robin Scheduling Enable */ 272 uint32_t LVLPRI2:4; /*!< bit: 16..19 Level 2 Channel Priority Number */ 273 uint32_t :3; /*!< bit: 20..22 Reserved */ 274 uint32_t RRLVLEN2:1; /*!< bit: 23 Level 2 Round-Robin Scheduling Enable */ 275 uint32_t LVLPRI3:4; /*!< bit: 24..27 Level 3 Channel Priority Number */ 276 uint32_t :3; /*!< bit: 28..30 Reserved */ 277 uint32_t RRLVLEN3:1; /*!< bit: 31 Level 3 Round-Robin Scheduling Enable */ 278 } bit; /*!< Structure used for bit access */ 279 uint32_t reg; /*!< Type used for register access */ 280 } DMAC_PRICTRL0_Type; 281 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 282 283 #define DMAC_PRICTRL0_OFFSET 0x14 /**< \brief (DMAC_PRICTRL0 offset) Priority Control 0 */ 284 #define DMAC_PRICTRL0_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_PRICTRL0 reset_value) Priority Control 0 */ 285 286 #define DMAC_PRICTRL0_LVLPRI0_Pos 0 /**< \brief (DMAC_PRICTRL0) Level 0 Channel Priority Number */ 287 #define DMAC_PRICTRL0_LVLPRI0_Msk (_U_(0xF) << DMAC_PRICTRL0_LVLPRI0_Pos) 288 #define DMAC_PRICTRL0_LVLPRI0(value) (DMAC_PRICTRL0_LVLPRI0_Msk & ((value) << DMAC_PRICTRL0_LVLPRI0_Pos)) 289 #define DMAC_PRICTRL0_RRLVLEN0_Pos 7 /**< \brief (DMAC_PRICTRL0) Level 0 Round-Robin Scheduling Enable */ 290 #define DMAC_PRICTRL0_RRLVLEN0 (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN0_Pos) 291 #define DMAC_PRICTRL0_LVLPRI1_Pos 8 /**< \brief (DMAC_PRICTRL0) Level 1 Channel Priority Number */ 292 #define DMAC_PRICTRL0_LVLPRI1_Msk (_U_(0xF) << DMAC_PRICTRL0_LVLPRI1_Pos) 293 #define DMAC_PRICTRL0_LVLPRI1(value) (DMAC_PRICTRL0_LVLPRI1_Msk & ((value) << DMAC_PRICTRL0_LVLPRI1_Pos)) 294 #define DMAC_PRICTRL0_RRLVLEN1_Pos 15 /**< \brief (DMAC_PRICTRL0) Level 1 Round-Robin Scheduling Enable */ 295 #define DMAC_PRICTRL0_RRLVLEN1 (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN1_Pos) 296 #define DMAC_PRICTRL0_LVLPRI2_Pos 16 /**< \brief (DMAC_PRICTRL0) Level 2 Channel Priority Number */ 297 #define DMAC_PRICTRL0_LVLPRI2_Msk (_U_(0xF) << DMAC_PRICTRL0_LVLPRI2_Pos) 298 #define DMAC_PRICTRL0_LVLPRI2(value) (DMAC_PRICTRL0_LVLPRI2_Msk & ((value) << DMAC_PRICTRL0_LVLPRI2_Pos)) 299 #define DMAC_PRICTRL0_RRLVLEN2_Pos 23 /**< \brief (DMAC_PRICTRL0) Level 2 Round-Robin Scheduling Enable */ 300 #define DMAC_PRICTRL0_RRLVLEN2 (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN2_Pos) 301 #define DMAC_PRICTRL0_LVLPRI3_Pos 24 /**< \brief (DMAC_PRICTRL0) Level 3 Channel Priority Number */ 302 #define DMAC_PRICTRL0_LVLPRI3_Msk (_U_(0xF) << DMAC_PRICTRL0_LVLPRI3_Pos) 303 #define DMAC_PRICTRL0_LVLPRI3(value) (DMAC_PRICTRL0_LVLPRI3_Msk & ((value) << DMAC_PRICTRL0_LVLPRI3_Pos)) 304 #define DMAC_PRICTRL0_RRLVLEN3_Pos 31 /**< \brief (DMAC_PRICTRL0) Level 3 Round-Robin Scheduling Enable */ 305 #define DMAC_PRICTRL0_RRLVLEN3 (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN3_Pos) 306 #define DMAC_PRICTRL0_MASK _U_(0x8F8F8F8F) /**< \brief (DMAC_PRICTRL0) MASK Register */ 307 308 /* -------- DMAC_INTPEND : (DMAC Offset: 0x20) (R/W 16) Interrupt Pending -------- */ 309 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 310 typedef union { 311 struct { 312 uint16_t ID:4; /*!< bit: 0.. 3 Channel ID */ 313 uint16_t :4; /*!< bit: 4.. 7 Reserved */ 314 uint16_t TERR:1; /*!< bit: 8 Transfer Error */ 315 uint16_t TCMPL:1; /*!< bit: 9 Transfer Complete */ 316 uint16_t SUSP:1; /*!< bit: 10 Channel Suspend */ 317 uint16_t :2; /*!< bit: 11..12 Reserved */ 318 uint16_t FERR:1; /*!< bit: 13 Fetch Error */ 319 uint16_t BUSY:1; /*!< bit: 14 Busy */ 320 uint16_t PEND:1; /*!< bit: 15 Pending */ 321 } bit; /*!< Structure used for bit access */ 322 uint16_t reg; /*!< Type used for register access */ 323 } DMAC_INTPEND_Type; 324 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 325 326 #define DMAC_INTPEND_OFFSET 0x20 /**< \brief (DMAC_INTPEND offset) Interrupt Pending */ 327 #define DMAC_INTPEND_RESETVALUE _U_(0x0000) /**< \brief (DMAC_INTPEND reset_value) Interrupt Pending */ 328 329 #define DMAC_INTPEND_ID_Pos 0 /**< \brief (DMAC_INTPEND) Channel ID */ 330 #define DMAC_INTPEND_ID_Msk (_U_(0xF) << DMAC_INTPEND_ID_Pos) 331 #define DMAC_INTPEND_ID(value) (DMAC_INTPEND_ID_Msk & ((value) << DMAC_INTPEND_ID_Pos)) 332 #define DMAC_INTPEND_TERR_Pos 8 /**< \brief (DMAC_INTPEND) Transfer Error */ 333 #define DMAC_INTPEND_TERR (_U_(0x1) << DMAC_INTPEND_TERR_Pos) 334 #define DMAC_INTPEND_TCMPL_Pos 9 /**< \brief (DMAC_INTPEND) Transfer Complete */ 335 #define DMAC_INTPEND_TCMPL (_U_(0x1) << DMAC_INTPEND_TCMPL_Pos) 336 #define DMAC_INTPEND_SUSP_Pos 10 /**< \brief (DMAC_INTPEND) Channel Suspend */ 337 #define DMAC_INTPEND_SUSP (_U_(0x1) << DMAC_INTPEND_SUSP_Pos) 338 #define DMAC_INTPEND_FERR_Pos 13 /**< \brief (DMAC_INTPEND) Fetch Error */ 339 #define DMAC_INTPEND_FERR (_U_(0x1) << DMAC_INTPEND_FERR_Pos) 340 #define DMAC_INTPEND_BUSY_Pos 14 /**< \brief (DMAC_INTPEND) Busy */ 341 #define DMAC_INTPEND_BUSY (_U_(0x1) << DMAC_INTPEND_BUSY_Pos) 342 #define DMAC_INTPEND_PEND_Pos 15 /**< \brief (DMAC_INTPEND) Pending */ 343 #define DMAC_INTPEND_PEND (_U_(0x1) << DMAC_INTPEND_PEND_Pos) 344 #define DMAC_INTPEND_MASK _U_(0xE70F) /**< \brief (DMAC_INTPEND) MASK Register */ 345 346 /* -------- DMAC_INTSTATUS : (DMAC Offset: 0x24) (R/ 32) Interrupt Status -------- */ 347 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 348 typedef union { 349 struct { 350 uint32_t CHINT0:1; /*!< bit: 0 Channel 0 Pending Interrupt */ 351 uint32_t CHINT1:1; /*!< bit: 1 Channel 1 Pending Interrupt */ 352 uint32_t CHINT2:1; /*!< bit: 2 Channel 2 Pending Interrupt */ 353 uint32_t CHINT3:1; /*!< bit: 3 Channel 3 Pending Interrupt */ 354 uint32_t CHINT4:1; /*!< bit: 4 Channel 4 Pending Interrupt */ 355 uint32_t CHINT5:1; /*!< bit: 5 Channel 5 Pending Interrupt */ 356 uint32_t CHINT6:1; /*!< bit: 6 Channel 6 Pending Interrupt */ 357 uint32_t CHINT7:1; /*!< bit: 7 Channel 7 Pending Interrupt */ 358 uint32_t CHINT8:1; /*!< bit: 8 Channel 8 Pending Interrupt */ 359 uint32_t CHINT9:1; /*!< bit: 9 Channel 9 Pending Interrupt */ 360 uint32_t CHINT10:1; /*!< bit: 10 Channel 10 Pending Interrupt */ 361 uint32_t CHINT11:1; /*!< bit: 11 Channel 11 Pending Interrupt */ 362 uint32_t :20; /*!< bit: 12..31 Reserved */ 363 } bit; /*!< Structure used for bit access */ 364 struct { 365 uint32_t CHINT:12; /*!< bit: 0..11 Channel x Pending Interrupt */ 366 uint32_t :20; /*!< bit: 12..31 Reserved */ 367 } vec; /*!< Structure used for vec access */ 368 uint32_t reg; /*!< Type used for register access */ 369 } DMAC_INTSTATUS_Type; 370 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 371 372 #define DMAC_INTSTATUS_OFFSET 0x24 /**< \brief (DMAC_INTSTATUS offset) Interrupt Status */ 373 #define DMAC_INTSTATUS_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_INTSTATUS reset_value) Interrupt Status */ 374 375 #define DMAC_INTSTATUS_CHINT0_Pos 0 /**< \brief (DMAC_INTSTATUS) Channel 0 Pending Interrupt */ 376 #define DMAC_INTSTATUS_CHINT0 (_U_(1) << DMAC_INTSTATUS_CHINT0_Pos) 377 #define DMAC_INTSTATUS_CHINT1_Pos 1 /**< \brief (DMAC_INTSTATUS) Channel 1 Pending Interrupt */ 378 #define DMAC_INTSTATUS_CHINT1 (_U_(1) << DMAC_INTSTATUS_CHINT1_Pos) 379 #define DMAC_INTSTATUS_CHINT2_Pos 2 /**< \brief (DMAC_INTSTATUS) Channel 2 Pending Interrupt */ 380 #define DMAC_INTSTATUS_CHINT2 (_U_(1) << DMAC_INTSTATUS_CHINT2_Pos) 381 #define DMAC_INTSTATUS_CHINT3_Pos 3 /**< \brief (DMAC_INTSTATUS) Channel 3 Pending Interrupt */ 382 #define DMAC_INTSTATUS_CHINT3 (_U_(1) << DMAC_INTSTATUS_CHINT3_Pos) 383 #define DMAC_INTSTATUS_CHINT4_Pos 4 /**< \brief (DMAC_INTSTATUS) Channel 4 Pending Interrupt */ 384 #define DMAC_INTSTATUS_CHINT4 (_U_(1) << DMAC_INTSTATUS_CHINT4_Pos) 385 #define DMAC_INTSTATUS_CHINT5_Pos 5 /**< \brief (DMAC_INTSTATUS) Channel 5 Pending Interrupt */ 386 #define DMAC_INTSTATUS_CHINT5 (_U_(1) << DMAC_INTSTATUS_CHINT5_Pos) 387 #define DMAC_INTSTATUS_CHINT6_Pos 6 /**< \brief (DMAC_INTSTATUS) Channel 6 Pending Interrupt */ 388 #define DMAC_INTSTATUS_CHINT6 (_U_(1) << DMAC_INTSTATUS_CHINT6_Pos) 389 #define DMAC_INTSTATUS_CHINT7_Pos 7 /**< \brief (DMAC_INTSTATUS) Channel 7 Pending Interrupt */ 390 #define DMAC_INTSTATUS_CHINT7 (_U_(1) << DMAC_INTSTATUS_CHINT7_Pos) 391 #define DMAC_INTSTATUS_CHINT8_Pos 8 /**< \brief (DMAC_INTSTATUS) Channel 8 Pending Interrupt */ 392 #define DMAC_INTSTATUS_CHINT8 (_U_(1) << DMAC_INTSTATUS_CHINT8_Pos) 393 #define DMAC_INTSTATUS_CHINT9_Pos 9 /**< \brief (DMAC_INTSTATUS) Channel 9 Pending Interrupt */ 394 #define DMAC_INTSTATUS_CHINT9 (_U_(1) << DMAC_INTSTATUS_CHINT9_Pos) 395 #define DMAC_INTSTATUS_CHINT10_Pos 10 /**< \brief (DMAC_INTSTATUS) Channel 10 Pending Interrupt */ 396 #define DMAC_INTSTATUS_CHINT10 (_U_(1) << DMAC_INTSTATUS_CHINT10_Pos) 397 #define DMAC_INTSTATUS_CHINT11_Pos 11 /**< \brief (DMAC_INTSTATUS) Channel 11 Pending Interrupt */ 398 #define DMAC_INTSTATUS_CHINT11 (_U_(1) << DMAC_INTSTATUS_CHINT11_Pos) 399 #define DMAC_INTSTATUS_CHINT_Pos 0 /**< \brief (DMAC_INTSTATUS) Channel x Pending Interrupt */ 400 #define DMAC_INTSTATUS_CHINT_Msk (_U_(0xFFF) << DMAC_INTSTATUS_CHINT_Pos) 401 #define DMAC_INTSTATUS_CHINT(value) (DMAC_INTSTATUS_CHINT_Msk & ((value) << DMAC_INTSTATUS_CHINT_Pos)) 402 #define DMAC_INTSTATUS_MASK _U_(0x00000FFF) /**< \brief (DMAC_INTSTATUS) MASK Register */ 403 404 /* -------- DMAC_BUSYCH : (DMAC Offset: 0x28) (R/ 32) Busy Channels -------- */ 405 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 406 typedef union { 407 struct { 408 uint32_t BUSYCH0:1; /*!< bit: 0 Busy Channel 0 */ 409 uint32_t BUSYCH1:1; /*!< bit: 1 Busy Channel 1 */ 410 uint32_t BUSYCH2:1; /*!< bit: 2 Busy Channel 2 */ 411 uint32_t BUSYCH3:1; /*!< bit: 3 Busy Channel 3 */ 412 uint32_t BUSYCH4:1; /*!< bit: 4 Busy Channel 4 */ 413 uint32_t BUSYCH5:1; /*!< bit: 5 Busy Channel 5 */ 414 uint32_t BUSYCH6:1; /*!< bit: 6 Busy Channel 6 */ 415 uint32_t BUSYCH7:1; /*!< bit: 7 Busy Channel 7 */ 416 uint32_t BUSYCH8:1; /*!< bit: 8 Busy Channel 8 */ 417 uint32_t BUSYCH9:1; /*!< bit: 9 Busy Channel 9 */ 418 uint32_t BUSYCH10:1; /*!< bit: 10 Busy Channel 10 */ 419 uint32_t BUSYCH11:1; /*!< bit: 11 Busy Channel 11 */ 420 uint32_t :20; /*!< bit: 12..31 Reserved */ 421 } bit; /*!< Structure used for bit access */ 422 struct { 423 uint32_t BUSYCH:12; /*!< bit: 0..11 Busy Channel x */ 424 uint32_t :20; /*!< bit: 12..31 Reserved */ 425 } vec; /*!< Structure used for vec access */ 426 uint32_t reg; /*!< Type used for register access */ 427 } DMAC_BUSYCH_Type; 428 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 429 430 #define DMAC_BUSYCH_OFFSET 0x28 /**< \brief (DMAC_BUSYCH offset) Busy Channels */ 431 #define DMAC_BUSYCH_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_BUSYCH reset_value) Busy Channels */ 432 433 #define DMAC_BUSYCH_BUSYCH0_Pos 0 /**< \brief (DMAC_BUSYCH) Busy Channel 0 */ 434 #define DMAC_BUSYCH_BUSYCH0 (_U_(1) << DMAC_BUSYCH_BUSYCH0_Pos) 435 #define DMAC_BUSYCH_BUSYCH1_Pos 1 /**< \brief (DMAC_BUSYCH) Busy Channel 1 */ 436 #define DMAC_BUSYCH_BUSYCH1 (_U_(1) << DMAC_BUSYCH_BUSYCH1_Pos) 437 #define DMAC_BUSYCH_BUSYCH2_Pos 2 /**< \brief (DMAC_BUSYCH) Busy Channel 2 */ 438 #define DMAC_BUSYCH_BUSYCH2 (_U_(1) << DMAC_BUSYCH_BUSYCH2_Pos) 439 #define DMAC_BUSYCH_BUSYCH3_Pos 3 /**< \brief (DMAC_BUSYCH) Busy Channel 3 */ 440 #define DMAC_BUSYCH_BUSYCH3 (_U_(1) << DMAC_BUSYCH_BUSYCH3_Pos) 441 #define DMAC_BUSYCH_BUSYCH4_Pos 4 /**< \brief (DMAC_BUSYCH) Busy Channel 4 */ 442 #define DMAC_BUSYCH_BUSYCH4 (_U_(1) << DMAC_BUSYCH_BUSYCH4_Pos) 443 #define DMAC_BUSYCH_BUSYCH5_Pos 5 /**< \brief (DMAC_BUSYCH) Busy Channel 5 */ 444 #define DMAC_BUSYCH_BUSYCH5 (_U_(1) << DMAC_BUSYCH_BUSYCH5_Pos) 445 #define DMAC_BUSYCH_BUSYCH6_Pos 6 /**< \brief (DMAC_BUSYCH) Busy Channel 6 */ 446 #define DMAC_BUSYCH_BUSYCH6 (_U_(1) << DMAC_BUSYCH_BUSYCH6_Pos) 447 #define DMAC_BUSYCH_BUSYCH7_Pos 7 /**< \brief (DMAC_BUSYCH) Busy Channel 7 */ 448 #define DMAC_BUSYCH_BUSYCH7 (_U_(1) << DMAC_BUSYCH_BUSYCH7_Pos) 449 #define DMAC_BUSYCH_BUSYCH8_Pos 8 /**< \brief (DMAC_BUSYCH) Busy Channel 8 */ 450 #define DMAC_BUSYCH_BUSYCH8 (_U_(1) << DMAC_BUSYCH_BUSYCH8_Pos) 451 #define DMAC_BUSYCH_BUSYCH9_Pos 9 /**< \brief (DMAC_BUSYCH) Busy Channel 9 */ 452 #define DMAC_BUSYCH_BUSYCH9 (_U_(1) << DMAC_BUSYCH_BUSYCH9_Pos) 453 #define DMAC_BUSYCH_BUSYCH10_Pos 10 /**< \brief (DMAC_BUSYCH) Busy Channel 10 */ 454 #define DMAC_BUSYCH_BUSYCH10 (_U_(1) << DMAC_BUSYCH_BUSYCH10_Pos) 455 #define DMAC_BUSYCH_BUSYCH11_Pos 11 /**< \brief (DMAC_BUSYCH) Busy Channel 11 */ 456 #define DMAC_BUSYCH_BUSYCH11 (_U_(1) << DMAC_BUSYCH_BUSYCH11_Pos) 457 #define DMAC_BUSYCH_BUSYCH_Pos 0 /**< \brief (DMAC_BUSYCH) Busy Channel x */ 458 #define DMAC_BUSYCH_BUSYCH_Msk (_U_(0xFFF) << DMAC_BUSYCH_BUSYCH_Pos) 459 #define DMAC_BUSYCH_BUSYCH(value) (DMAC_BUSYCH_BUSYCH_Msk & ((value) << DMAC_BUSYCH_BUSYCH_Pos)) 460 #define DMAC_BUSYCH_MASK _U_(0x00000FFF) /**< \brief (DMAC_BUSYCH) MASK Register */ 461 462 /* -------- DMAC_PENDCH : (DMAC Offset: 0x2C) (R/ 32) Pending Channels -------- */ 463 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 464 typedef union { 465 struct { 466 uint32_t PENDCH0:1; /*!< bit: 0 Pending Channel 0 */ 467 uint32_t PENDCH1:1; /*!< bit: 1 Pending Channel 1 */ 468 uint32_t PENDCH2:1; /*!< bit: 2 Pending Channel 2 */ 469 uint32_t PENDCH3:1; /*!< bit: 3 Pending Channel 3 */ 470 uint32_t PENDCH4:1; /*!< bit: 4 Pending Channel 4 */ 471 uint32_t PENDCH5:1; /*!< bit: 5 Pending Channel 5 */ 472 uint32_t PENDCH6:1; /*!< bit: 6 Pending Channel 6 */ 473 uint32_t PENDCH7:1; /*!< bit: 7 Pending Channel 7 */ 474 uint32_t PENDCH8:1; /*!< bit: 8 Pending Channel 8 */ 475 uint32_t PENDCH9:1; /*!< bit: 9 Pending Channel 9 */ 476 uint32_t PENDCH10:1; /*!< bit: 10 Pending Channel 10 */ 477 uint32_t PENDCH11:1; /*!< bit: 11 Pending Channel 11 */ 478 uint32_t :20; /*!< bit: 12..31 Reserved */ 479 } bit; /*!< Structure used for bit access */ 480 struct { 481 uint32_t PENDCH:12; /*!< bit: 0..11 Pending Channel x */ 482 uint32_t :20; /*!< bit: 12..31 Reserved */ 483 } vec; /*!< Structure used for vec access */ 484 uint32_t reg; /*!< Type used for register access */ 485 } DMAC_PENDCH_Type; 486 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 487 488 #define DMAC_PENDCH_OFFSET 0x2C /**< \brief (DMAC_PENDCH offset) Pending Channels */ 489 #define DMAC_PENDCH_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_PENDCH reset_value) Pending Channels */ 490 491 #define DMAC_PENDCH_PENDCH0_Pos 0 /**< \brief (DMAC_PENDCH) Pending Channel 0 */ 492 #define DMAC_PENDCH_PENDCH0 (_U_(1) << DMAC_PENDCH_PENDCH0_Pos) 493 #define DMAC_PENDCH_PENDCH1_Pos 1 /**< \brief (DMAC_PENDCH) Pending Channel 1 */ 494 #define DMAC_PENDCH_PENDCH1 (_U_(1) << DMAC_PENDCH_PENDCH1_Pos) 495 #define DMAC_PENDCH_PENDCH2_Pos 2 /**< \brief (DMAC_PENDCH) Pending Channel 2 */ 496 #define DMAC_PENDCH_PENDCH2 (_U_(1) << DMAC_PENDCH_PENDCH2_Pos) 497 #define DMAC_PENDCH_PENDCH3_Pos 3 /**< \brief (DMAC_PENDCH) Pending Channel 3 */ 498 #define DMAC_PENDCH_PENDCH3 (_U_(1) << DMAC_PENDCH_PENDCH3_Pos) 499 #define DMAC_PENDCH_PENDCH4_Pos 4 /**< \brief (DMAC_PENDCH) Pending Channel 4 */ 500 #define DMAC_PENDCH_PENDCH4 (_U_(1) << DMAC_PENDCH_PENDCH4_Pos) 501 #define DMAC_PENDCH_PENDCH5_Pos 5 /**< \brief (DMAC_PENDCH) Pending Channel 5 */ 502 #define DMAC_PENDCH_PENDCH5 (_U_(1) << DMAC_PENDCH_PENDCH5_Pos) 503 #define DMAC_PENDCH_PENDCH6_Pos 6 /**< \brief (DMAC_PENDCH) Pending Channel 6 */ 504 #define DMAC_PENDCH_PENDCH6 (_U_(1) << DMAC_PENDCH_PENDCH6_Pos) 505 #define DMAC_PENDCH_PENDCH7_Pos 7 /**< \brief (DMAC_PENDCH) Pending Channel 7 */ 506 #define DMAC_PENDCH_PENDCH7 (_U_(1) << DMAC_PENDCH_PENDCH7_Pos) 507 #define DMAC_PENDCH_PENDCH8_Pos 8 /**< \brief (DMAC_PENDCH) Pending Channel 8 */ 508 #define DMAC_PENDCH_PENDCH8 (_U_(1) << DMAC_PENDCH_PENDCH8_Pos) 509 #define DMAC_PENDCH_PENDCH9_Pos 9 /**< \brief (DMAC_PENDCH) Pending Channel 9 */ 510 #define DMAC_PENDCH_PENDCH9 (_U_(1) << DMAC_PENDCH_PENDCH9_Pos) 511 #define DMAC_PENDCH_PENDCH10_Pos 10 /**< \brief (DMAC_PENDCH) Pending Channel 10 */ 512 #define DMAC_PENDCH_PENDCH10 (_U_(1) << DMAC_PENDCH_PENDCH10_Pos) 513 #define DMAC_PENDCH_PENDCH11_Pos 11 /**< \brief (DMAC_PENDCH) Pending Channel 11 */ 514 #define DMAC_PENDCH_PENDCH11 (_U_(1) << DMAC_PENDCH_PENDCH11_Pos) 515 #define DMAC_PENDCH_PENDCH_Pos 0 /**< \brief (DMAC_PENDCH) Pending Channel x */ 516 #define DMAC_PENDCH_PENDCH_Msk (_U_(0xFFF) << DMAC_PENDCH_PENDCH_Pos) 517 #define DMAC_PENDCH_PENDCH(value) (DMAC_PENDCH_PENDCH_Msk & ((value) << DMAC_PENDCH_PENDCH_Pos)) 518 #define DMAC_PENDCH_MASK _U_(0x00000FFF) /**< \brief (DMAC_PENDCH) MASK Register */ 519 520 /* -------- DMAC_ACTIVE : (DMAC Offset: 0x30) (R/ 32) Active Channel and Levels -------- */ 521 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 522 typedef union { 523 struct { 524 uint32_t LVLEX0:1; /*!< bit: 0 Level 0 Channel Trigger Request Executing */ 525 uint32_t LVLEX1:1; /*!< bit: 1 Level 1 Channel Trigger Request Executing */ 526 uint32_t LVLEX2:1; /*!< bit: 2 Level 2 Channel Trigger Request Executing */ 527 uint32_t LVLEX3:1; /*!< bit: 3 Level 3 Channel Trigger Request Executing */ 528 uint32_t :4; /*!< bit: 4.. 7 Reserved */ 529 uint32_t ID:5; /*!< bit: 8..12 Active Channel ID */ 530 uint32_t :2; /*!< bit: 13..14 Reserved */ 531 uint32_t ABUSY:1; /*!< bit: 15 Active Channel Busy */ 532 uint32_t BTCNT:16; /*!< bit: 16..31 Active Channel Block Transfer Count */ 533 } bit; /*!< Structure used for bit access */ 534 struct { 535 uint32_t LVLEX:4; /*!< bit: 0.. 3 Level x Channel Trigger Request Executing */ 536 uint32_t :28; /*!< bit: 4..31 Reserved */ 537 } vec; /*!< Structure used for vec access */ 538 uint32_t reg; /*!< Type used for register access */ 539 } DMAC_ACTIVE_Type; 540 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 541 542 #define DMAC_ACTIVE_OFFSET 0x30 /**< \brief (DMAC_ACTIVE offset) Active Channel and Levels */ 543 #define DMAC_ACTIVE_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_ACTIVE reset_value) Active Channel and Levels */ 544 545 #define DMAC_ACTIVE_LVLEX0_Pos 0 /**< \brief (DMAC_ACTIVE) Level 0 Channel Trigger Request Executing */ 546 #define DMAC_ACTIVE_LVLEX0 (_U_(1) << DMAC_ACTIVE_LVLEX0_Pos) 547 #define DMAC_ACTIVE_LVLEX1_Pos 1 /**< \brief (DMAC_ACTIVE) Level 1 Channel Trigger Request Executing */ 548 #define DMAC_ACTIVE_LVLEX1 (_U_(1) << DMAC_ACTIVE_LVLEX1_Pos) 549 #define DMAC_ACTIVE_LVLEX2_Pos 2 /**< \brief (DMAC_ACTIVE) Level 2 Channel Trigger Request Executing */ 550 #define DMAC_ACTIVE_LVLEX2 (_U_(1) << DMAC_ACTIVE_LVLEX2_Pos) 551 #define DMAC_ACTIVE_LVLEX3_Pos 3 /**< \brief (DMAC_ACTIVE) Level 3 Channel Trigger Request Executing */ 552 #define DMAC_ACTIVE_LVLEX3 (_U_(1) << DMAC_ACTIVE_LVLEX3_Pos) 553 #define DMAC_ACTIVE_LVLEX_Pos 0 /**< \brief (DMAC_ACTIVE) Level x Channel Trigger Request Executing */ 554 #define DMAC_ACTIVE_LVLEX_Msk (_U_(0xF) << DMAC_ACTIVE_LVLEX_Pos) 555 #define DMAC_ACTIVE_LVLEX(value) (DMAC_ACTIVE_LVLEX_Msk & ((value) << DMAC_ACTIVE_LVLEX_Pos)) 556 #define DMAC_ACTIVE_ID_Pos 8 /**< \brief (DMAC_ACTIVE) Active Channel ID */ 557 #define DMAC_ACTIVE_ID_Msk (_U_(0x1F) << DMAC_ACTIVE_ID_Pos) 558 #define DMAC_ACTIVE_ID(value) (DMAC_ACTIVE_ID_Msk & ((value) << DMAC_ACTIVE_ID_Pos)) 559 #define DMAC_ACTIVE_ABUSY_Pos 15 /**< \brief (DMAC_ACTIVE) Active Channel Busy */ 560 #define DMAC_ACTIVE_ABUSY (_U_(0x1) << DMAC_ACTIVE_ABUSY_Pos) 561 #define DMAC_ACTIVE_BTCNT_Pos 16 /**< \brief (DMAC_ACTIVE) Active Channel Block Transfer Count */ 562 #define DMAC_ACTIVE_BTCNT_Msk (_U_(0xFFFF) << DMAC_ACTIVE_BTCNT_Pos) 563 #define DMAC_ACTIVE_BTCNT(value) (DMAC_ACTIVE_BTCNT_Msk & ((value) << DMAC_ACTIVE_BTCNT_Pos)) 564 #define DMAC_ACTIVE_MASK _U_(0xFFFF9F0F) /**< \brief (DMAC_ACTIVE) MASK Register */ 565 566 /* -------- DMAC_BASEADDR : (DMAC Offset: 0x34) (R/W 32) Descriptor Memory Section Base Address -------- */ 567 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 568 typedef union { 569 struct { 570 uint32_t BASEADDR:32; /*!< bit: 0..31 Descriptor Memory Base Address */ 571 } bit; /*!< Structure used for bit access */ 572 uint32_t reg; /*!< Type used for register access */ 573 } DMAC_BASEADDR_Type; 574 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 575 576 #define DMAC_BASEADDR_OFFSET 0x34 /**< \brief (DMAC_BASEADDR offset) Descriptor Memory Section Base Address */ 577 #define DMAC_BASEADDR_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_BASEADDR reset_value) Descriptor Memory Section Base Address */ 578 579 #define DMAC_BASEADDR_BASEADDR_Pos 0 /**< \brief (DMAC_BASEADDR) Descriptor Memory Base Address */ 580 #define DMAC_BASEADDR_BASEADDR_Msk (_U_(0xFFFFFFFF) << DMAC_BASEADDR_BASEADDR_Pos) 581 #define DMAC_BASEADDR_BASEADDR(value) (DMAC_BASEADDR_BASEADDR_Msk & ((value) << DMAC_BASEADDR_BASEADDR_Pos)) 582 #define DMAC_BASEADDR_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_BASEADDR) MASK Register */ 583 584 /* -------- DMAC_WRBADDR : (DMAC Offset: 0x38) (R/W 32) Write-Back Memory Section Base Address -------- */ 585 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 586 typedef union { 587 struct { 588 uint32_t WRBADDR:32; /*!< bit: 0..31 Write-Back Memory Base Address */ 589 } bit; /*!< Structure used for bit access */ 590 uint32_t reg; /*!< Type used for register access */ 591 } DMAC_WRBADDR_Type; 592 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 593 594 #define DMAC_WRBADDR_OFFSET 0x38 /**< \brief (DMAC_WRBADDR offset) Write-Back Memory Section Base Address */ 595 #define DMAC_WRBADDR_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_WRBADDR reset_value) Write-Back Memory Section Base Address */ 596 597 #define DMAC_WRBADDR_WRBADDR_Pos 0 /**< \brief (DMAC_WRBADDR) Write-Back Memory Base Address */ 598 #define DMAC_WRBADDR_WRBADDR_Msk (_U_(0xFFFFFFFF) << DMAC_WRBADDR_WRBADDR_Pos) 599 #define DMAC_WRBADDR_WRBADDR(value) (DMAC_WRBADDR_WRBADDR_Msk & ((value) << DMAC_WRBADDR_WRBADDR_Pos)) 600 #define DMAC_WRBADDR_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_WRBADDR) MASK Register */ 601 602 /* -------- DMAC_CHID : (DMAC Offset: 0x3F) (R/W 8) Channel ID -------- */ 603 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 604 typedef union { 605 struct { 606 uint8_t ID:4; /*!< bit: 0.. 3 Channel ID */ 607 uint8_t :4; /*!< bit: 4.. 7 Reserved */ 608 } bit; /*!< Structure used for bit access */ 609 uint8_t reg; /*!< Type used for register access */ 610 } DMAC_CHID_Type; 611 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 612 613 #define DMAC_CHID_OFFSET 0x3F /**< \brief (DMAC_CHID offset) Channel ID */ 614 #define DMAC_CHID_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHID reset_value) Channel ID */ 615 616 #define DMAC_CHID_ID_Pos 0 /**< \brief (DMAC_CHID) Channel ID */ 617 #define DMAC_CHID_ID_Msk (_U_(0xF) << DMAC_CHID_ID_Pos) 618 #define DMAC_CHID_ID(value) (DMAC_CHID_ID_Msk & ((value) << DMAC_CHID_ID_Pos)) 619 #define DMAC_CHID_MASK _U_(0x0F) /**< \brief (DMAC_CHID) MASK Register */ 620 621 /* -------- DMAC_CHCTRLA : (DMAC Offset: 0x40) (R/W 8) Channel Control A -------- */ 622 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 623 typedef union { 624 struct { 625 uint8_t SWRST:1; /*!< bit: 0 Channel Software Reset */ 626 uint8_t ENABLE:1; /*!< bit: 1 Channel Enable */ 627 uint8_t :4; /*!< bit: 2.. 5 Reserved */ 628 uint8_t RUNSTDBY:1; /*!< bit: 6 Channel run in standby */ 629 uint8_t :1; /*!< bit: 7 Reserved */ 630 } bit; /*!< Structure used for bit access */ 631 uint8_t reg; /*!< Type used for register access */ 632 } DMAC_CHCTRLA_Type; 633 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 634 635 #define DMAC_CHCTRLA_OFFSET 0x40 /**< \brief (DMAC_CHCTRLA offset) Channel Control A */ 636 #define DMAC_CHCTRLA_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHCTRLA reset_value) Channel Control A */ 637 638 #define DMAC_CHCTRLA_SWRST_Pos 0 /**< \brief (DMAC_CHCTRLA) Channel Software Reset */ 639 #define DMAC_CHCTRLA_SWRST (_U_(0x1) << DMAC_CHCTRLA_SWRST_Pos) 640 #define DMAC_CHCTRLA_ENABLE_Pos 1 /**< \brief (DMAC_CHCTRLA) Channel Enable */ 641 #define DMAC_CHCTRLA_ENABLE (_U_(0x1) << DMAC_CHCTRLA_ENABLE_Pos) 642 #define DMAC_CHCTRLA_RUNSTDBY_Pos 6 /**< \brief (DMAC_CHCTRLA) Channel run in standby */ 643 #define DMAC_CHCTRLA_RUNSTDBY (_U_(0x1) << DMAC_CHCTRLA_RUNSTDBY_Pos) 644 #define DMAC_CHCTRLA_MASK _U_(0x43) /**< \brief (DMAC_CHCTRLA) MASK Register */ 645 646 /* -------- DMAC_CHCTRLB : (DMAC Offset: 0x44) (R/W 32) Channel Control B -------- */ 647 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 648 typedef union { 649 struct { 650 uint32_t EVACT:3; /*!< bit: 0.. 2 Event Input Action */ 651 uint32_t EVIE:1; /*!< bit: 3 Channel Event Input Enable */ 652 uint32_t EVOE:1; /*!< bit: 4 Channel Event Output Enable */ 653 uint32_t LVL:2; /*!< bit: 5.. 6 Channel Arbitration Level */ 654 uint32_t :1; /*!< bit: 7 Reserved */ 655 uint32_t TRIGSRC:6; /*!< bit: 8..13 Trigger Source */ 656 uint32_t :8; /*!< bit: 14..21 Reserved */ 657 uint32_t TRIGACT:2; /*!< bit: 22..23 Trigger Action */ 658 uint32_t CMD:2; /*!< bit: 24..25 Software Command */ 659 uint32_t :6; /*!< bit: 26..31 Reserved */ 660 } bit; /*!< Structure used for bit access */ 661 uint32_t reg; /*!< Type used for register access */ 662 } DMAC_CHCTRLB_Type; 663 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 664 665 #define DMAC_CHCTRLB_OFFSET 0x44 /**< \brief (DMAC_CHCTRLB offset) Channel Control B */ 666 #define DMAC_CHCTRLB_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_CHCTRLB reset_value) Channel Control B */ 667 668 #define DMAC_CHCTRLB_EVACT_Pos 0 /**< \brief (DMAC_CHCTRLB) Event Input Action */ 669 #define DMAC_CHCTRLB_EVACT_Msk (_U_(0x7) << DMAC_CHCTRLB_EVACT_Pos) 670 #define DMAC_CHCTRLB_EVACT(value) (DMAC_CHCTRLB_EVACT_Msk & ((value) << DMAC_CHCTRLB_EVACT_Pos)) 671 #define DMAC_CHCTRLB_EVACT_NOACT_Val _U_(0x0) /**< \brief (DMAC_CHCTRLB) No action */ 672 #define DMAC_CHCTRLB_EVACT_TRIG_Val _U_(0x1) /**< \brief (DMAC_CHCTRLB) Transfer and periodic transfer trigger */ 673 #define DMAC_CHCTRLB_EVACT_CTRIG_Val _U_(0x2) /**< \brief (DMAC_CHCTRLB) Conditional transfer trigger */ 674 #define DMAC_CHCTRLB_EVACT_CBLOCK_Val _U_(0x3) /**< \brief (DMAC_CHCTRLB) Conditional block transfer */ 675 #define DMAC_CHCTRLB_EVACT_SUSPEND_Val _U_(0x4) /**< \brief (DMAC_CHCTRLB) Channel suspend operation */ 676 #define DMAC_CHCTRLB_EVACT_RESUME_Val _U_(0x5) /**< \brief (DMAC_CHCTRLB) Channel resume operation */ 677 #define DMAC_CHCTRLB_EVACT_SSKIP_Val _U_(0x6) /**< \brief (DMAC_CHCTRLB) Skip next block suspend action */ 678 #define DMAC_CHCTRLB_EVACT_NOACT (DMAC_CHCTRLB_EVACT_NOACT_Val << DMAC_CHCTRLB_EVACT_Pos) 679 #define DMAC_CHCTRLB_EVACT_TRIG (DMAC_CHCTRLB_EVACT_TRIG_Val << DMAC_CHCTRLB_EVACT_Pos) 680 #define DMAC_CHCTRLB_EVACT_CTRIG (DMAC_CHCTRLB_EVACT_CTRIG_Val << DMAC_CHCTRLB_EVACT_Pos) 681 #define DMAC_CHCTRLB_EVACT_CBLOCK (DMAC_CHCTRLB_EVACT_CBLOCK_Val << DMAC_CHCTRLB_EVACT_Pos) 682 #define DMAC_CHCTRLB_EVACT_SUSPEND (DMAC_CHCTRLB_EVACT_SUSPEND_Val << DMAC_CHCTRLB_EVACT_Pos) 683 #define DMAC_CHCTRLB_EVACT_RESUME (DMAC_CHCTRLB_EVACT_RESUME_Val << DMAC_CHCTRLB_EVACT_Pos) 684 #define DMAC_CHCTRLB_EVACT_SSKIP (DMAC_CHCTRLB_EVACT_SSKIP_Val << DMAC_CHCTRLB_EVACT_Pos) 685 #define DMAC_CHCTRLB_EVIE_Pos 3 /**< \brief (DMAC_CHCTRLB) Channel Event Input Enable */ 686 #define DMAC_CHCTRLB_EVIE (_U_(0x1) << DMAC_CHCTRLB_EVIE_Pos) 687 #define DMAC_CHCTRLB_EVOE_Pos 4 /**< \brief (DMAC_CHCTRLB) Channel Event Output Enable */ 688 #define DMAC_CHCTRLB_EVOE (_U_(0x1) << DMAC_CHCTRLB_EVOE_Pos) 689 #define DMAC_CHCTRLB_LVL_Pos 5 /**< \brief (DMAC_CHCTRLB) Channel Arbitration Level */ 690 #define DMAC_CHCTRLB_LVL_Msk (_U_(0x3) << DMAC_CHCTRLB_LVL_Pos) 691 #define DMAC_CHCTRLB_LVL(value) (DMAC_CHCTRLB_LVL_Msk & ((value) << DMAC_CHCTRLB_LVL_Pos)) 692 #define DMAC_CHCTRLB_TRIGSRC_Pos 8 /**< \brief (DMAC_CHCTRLB) Trigger Source */ 693 #define DMAC_CHCTRLB_TRIGSRC_Msk (_U_(0x3F) << DMAC_CHCTRLB_TRIGSRC_Pos) 694 #define DMAC_CHCTRLB_TRIGSRC(value) (DMAC_CHCTRLB_TRIGSRC_Msk & ((value) << DMAC_CHCTRLB_TRIGSRC_Pos)) 695 #define DMAC_CHCTRLB_TRIGSRC_DISABLE_Val _U_(0x0) /**< \brief (DMAC_CHCTRLB) Only software/event triggers */ 696 #define DMAC_CHCTRLB_TRIGSRC_DISABLE (DMAC_CHCTRLB_TRIGSRC_DISABLE_Val << DMAC_CHCTRLB_TRIGSRC_Pos) 697 #define DMAC_CHCTRLB_TRIGACT_Pos 22 /**< \brief (DMAC_CHCTRLB) Trigger Action */ 698 #define DMAC_CHCTRLB_TRIGACT_Msk (_U_(0x3) << DMAC_CHCTRLB_TRIGACT_Pos) 699 #define DMAC_CHCTRLB_TRIGACT(value) (DMAC_CHCTRLB_TRIGACT_Msk & ((value) << DMAC_CHCTRLB_TRIGACT_Pos)) 700 #define DMAC_CHCTRLB_TRIGACT_BLOCK_Val _U_(0x0) /**< \brief (DMAC_CHCTRLB) One trigger required for each block transfer */ 701 #define DMAC_CHCTRLB_TRIGACT_BEAT_Val _U_(0x2) /**< \brief (DMAC_CHCTRLB) One trigger required for each beat transfer */ 702 #define DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val _U_(0x3) /**< \brief (DMAC_CHCTRLB) One trigger required for each transaction */ 703 #define DMAC_CHCTRLB_TRIGACT_BLOCK (DMAC_CHCTRLB_TRIGACT_BLOCK_Val << DMAC_CHCTRLB_TRIGACT_Pos) 704 #define DMAC_CHCTRLB_TRIGACT_BEAT (DMAC_CHCTRLB_TRIGACT_BEAT_Val << DMAC_CHCTRLB_TRIGACT_Pos) 705 #define DMAC_CHCTRLB_TRIGACT_TRANSACTION (DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val << DMAC_CHCTRLB_TRIGACT_Pos) 706 #define DMAC_CHCTRLB_CMD_Pos 24 /**< \brief (DMAC_CHCTRLB) Software Command */ 707 #define DMAC_CHCTRLB_CMD_Msk (_U_(0x3) << DMAC_CHCTRLB_CMD_Pos) 708 #define DMAC_CHCTRLB_CMD(value) (DMAC_CHCTRLB_CMD_Msk & ((value) << DMAC_CHCTRLB_CMD_Pos)) 709 #define DMAC_CHCTRLB_CMD_NOACT_Val _U_(0x0) /**< \brief (DMAC_CHCTRLB) No action */ 710 #define DMAC_CHCTRLB_CMD_SUSPEND_Val _U_(0x1) /**< \brief (DMAC_CHCTRLB) Channel suspend operation */ 711 #define DMAC_CHCTRLB_CMD_RESUME_Val _U_(0x2) /**< \brief (DMAC_CHCTRLB) Channel resume operation */ 712 #define DMAC_CHCTRLB_CMD_NOACT (DMAC_CHCTRLB_CMD_NOACT_Val << DMAC_CHCTRLB_CMD_Pos) 713 #define DMAC_CHCTRLB_CMD_SUSPEND (DMAC_CHCTRLB_CMD_SUSPEND_Val << DMAC_CHCTRLB_CMD_Pos) 714 #define DMAC_CHCTRLB_CMD_RESUME (DMAC_CHCTRLB_CMD_RESUME_Val << DMAC_CHCTRLB_CMD_Pos) 715 #define DMAC_CHCTRLB_MASK _U_(0x03C03F7F) /**< \brief (DMAC_CHCTRLB) MASK Register */ 716 717 /* -------- DMAC_CHINTENCLR : (DMAC Offset: 0x4C) (R/W 8) Channel Interrupt Enable Clear -------- */ 718 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 719 typedef union { 720 struct { 721 uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */ 722 uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */ 723 uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */ 724 uint8_t :5; /*!< bit: 3.. 7 Reserved */ 725 } bit; /*!< Structure used for bit access */ 726 uint8_t reg; /*!< Type used for register access */ 727 } DMAC_CHINTENCLR_Type; 728 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 729 730 #define DMAC_CHINTENCLR_OFFSET 0x4C /**< \brief (DMAC_CHINTENCLR offset) Channel Interrupt Enable Clear */ 731 #define DMAC_CHINTENCLR_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHINTENCLR reset_value) Channel Interrupt Enable Clear */ 732 733 #define DMAC_CHINTENCLR_TERR_Pos 0 /**< \brief (DMAC_CHINTENCLR) Channel Transfer Error Interrupt Enable */ 734 #define DMAC_CHINTENCLR_TERR (_U_(0x1) << DMAC_CHINTENCLR_TERR_Pos) 735 #define DMAC_CHINTENCLR_TCMPL_Pos 1 /**< \brief (DMAC_CHINTENCLR) Channel Transfer Complete Interrupt Enable */ 736 #define DMAC_CHINTENCLR_TCMPL (_U_(0x1) << DMAC_CHINTENCLR_TCMPL_Pos) 737 #define DMAC_CHINTENCLR_SUSP_Pos 2 /**< \brief (DMAC_CHINTENCLR) Channel Suspend Interrupt Enable */ 738 #define DMAC_CHINTENCLR_SUSP (_U_(0x1) << DMAC_CHINTENCLR_SUSP_Pos) 739 #define DMAC_CHINTENCLR_MASK _U_(0x07) /**< \brief (DMAC_CHINTENCLR) MASK Register */ 740 741 /* -------- DMAC_CHINTENSET : (DMAC Offset: 0x4D) (R/W 8) Channel Interrupt Enable Set -------- */ 742 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 743 typedef union { 744 struct { 745 uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */ 746 uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */ 747 uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */ 748 uint8_t :5; /*!< bit: 3.. 7 Reserved */ 749 } bit; /*!< Structure used for bit access */ 750 uint8_t reg; /*!< Type used for register access */ 751 } DMAC_CHINTENSET_Type; 752 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 753 754 #define DMAC_CHINTENSET_OFFSET 0x4D /**< \brief (DMAC_CHINTENSET offset) Channel Interrupt Enable Set */ 755 #define DMAC_CHINTENSET_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHINTENSET reset_value) Channel Interrupt Enable Set */ 756 757 #define DMAC_CHINTENSET_TERR_Pos 0 /**< \brief (DMAC_CHINTENSET) Channel Transfer Error Interrupt Enable */ 758 #define DMAC_CHINTENSET_TERR (_U_(0x1) << DMAC_CHINTENSET_TERR_Pos) 759 #define DMAC_CHINTENSET_TCMPL_Pos 1 /**< \brief (DMAC_CHINTENSET) Channel Transfer Complete Interrupt Enable */ 760 #define DMAC_CHINTENSET_TCMPL (_U_(0x1) << DMAC_CHINTENSET_TCMPL_Pos) 761 #define DMAC_CHINTENSET_SUSP_Pos 2 /**< \brief (DMAC_CHINTENSET) Channel Suspend Interrupt Enable */ 762 #define DMAC_CHINTENSET_SUSP (_U_(0x1) << DMAC_CHINTENSET_SUSP_Pos) 763 #define DMAC_CHINTENSET_MASK _U_(0x07) /**< \brief (DMAC_CHINTENSET) MASK Register */ 764 765 /* -------- DMAC_CHINTFLAG : (DMAC Offset: 0x4E) (R/W 8) Channel Interrupt Flag Status and Clear -------- */ 766 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 767 typedef union { // __I to avoid read-modify-write on write-to-clear register 768 struct { 769 __I uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error */ 770 __I uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete */ 771 __I uint8_t SUSP:1; /*!< bit: 2 Channel Suspend */ 772 __I uint8_t :5; /*!< bit: 3.. 7 Reserved */ 773 } bit; /*!< Structure used for bit access */ 774 uint8_t reg; /*!< Type used for register access */ 775 } DMAC_CHINTFLAG_Type; 776 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 777 778 #define DMAC_CHINTFLAG_OFFSET 0x4E /**< \brief (DMAC_CHINTFLAG offset) Channel Interrupt Flag Status and Clear */ 779 #define DMAC_CHINTFLAG_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHINTFLAG reset_value) Channel Interrupt Flag Status and Clear */ 780 781 #define DMAC_CHINTFLAG_TERR_Pos 0 /**< \brief (DMAC_CHINTFLAG) Channel Transfer Error */ 782 #define DMAC_CHINTFLAG_TERR (_U_(0x1) << DMAC_CHINTFLAG_TERR_Pos) 783 #define DMAC_CHINTFLAG_TCMPL_Pos 1 /**< \brief (DMAC_CHINTFLAG) Channel Transfer Complete */ 784 #define DMAC_CHINTFLAG_TCMPL (_U_(0x1) << DMAC_CHINTFLAG_TCMPL_Pos) 785 #define DMAC_CHINTFLAG_SUSP_Pos 2 /**< \brief (DMAC_CHINTFLAG) Channel Suspend */ 786 #define DMAC_CHINTFLAG_SUSP (_U_(0x1) << DMAC_CHINTFLAG_SUSP_Pos) 787 #define DMAC_CHINTFLAG_MASK _U_(0x07) /**< \brief (DMAC_CHINTFLAG) MASK Register */ 788 789 /* -------- DMAC_CHSTATUS : (DMAC Offset: 0x4F) (R/ 8) Channel Status -------- */ 790 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 791 typedef union { 792 struct { 793 uint8_t PEND:1; /*!< bit: 0 Channel Pending */ 794 uint8_t BUSY:1; /*!< bit: 1 Channel Busy */ 795 uint8_t FERR:1; /*!< bit: 2 Channel Fetch Error */ 796 uint8_t :5; /*!< bit: 3.. 7 Reserved */ 797 } bit; /*!< Structure used for bit access */ 798 uint8_t reg; /*!< Type used for register access */ 799 } DMAC_CHSTATUS_Type; 800 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 801 802 #define DMAC_CHSTATUS_OFFSET 0x4F /**< \brief (DMAC_CHSTATUS offset) Channel Status */ 803 #define DMAC_CHSTATUS_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHSTATUS reset_value) Channel Status */ 804 805 #define DMAC_CHSTATUS_PEND_Pos 0 /**< \brief (DMAC_CHSTATUS) Channel Pending */ 806 #define DMAC_CHSTATUS_PEND (_U_(0x1) << DMAC_CHSTATUS_PEND_Pos) 807 #define DMAC_CHSTATUS_BUSY_Pos 1 /**< \brief (DMAC_CHSTATUS) Channel Busy */ 808 #define DMAC_CHSTATUS_BUSY (_U_(0x1) << DMAC_CHSTATUS_BUSY_Pos) 809 #define DMAC_CHSTATUS_FERR_Pos 2 /**< \brief (DMAC_CHSTATUS) Channel Fetch Error */ 810 #define DMAC_CHSTATUS_FERR (_U_(0x1) << DMAC_CHSTATUS_FERR_Pos) 811 #define DMAC_CHSTATUS_MASK _U_(0x07) /**< \brief (DMAC_CHSTATUS) MASK Register */ 812 813 /* -------- DMAC_BTCTRL : (DMAC Offset: 0x00) (R/W 16) Block Transfer Control -------- */ 814 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 815 typedef union { 816 struct { 817 uint16_t VALID:1; /*!< bit: 0 Descriptor Valid */ 818 uint16_t EVOSEL:2; /*!< bit: 1.. 2 Event Output Selection */ 819 uint16_t BLOCKACT:2; /*!< bit: 3.. 4 Block Action */ 820 uint16_t :3; /*!< bit: 5.. 7 Reserved */ 821 uint16_t BEATSIZE:2; /*!< bit: 8.. 9 Beat Size */ 822 uint16_t SRCINC:1; /*!< bit: 10 Source Address Increment Enable */ 823 uint16_t DSTINC:1; /*!< bit: 11 Destination Address Increment Enable */ 824 uint16_t STEPSEL:1; /*!< bit: 12 Step Selection */ 825 uint16_t STEPSIZE:3; /*!< bit: 13..15 Address Increment Step Size */ 826 } bit; /*!< Structure used for bit access */ 827 uint16_t reg; /*!< Type used for register access */ 828 } DMAC_BTCTRL_Type; 829 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 830 831 #define DMAC_BTCTRL_OFFSET 0x00 /**< \brief (DMAC_BTCTRL offset) Block Transfer Control */ 832 #define DMAC_BTCTRL_RESETVALUE _U_(0x0000) /**< \brief (DMAC_BTCTRL reset_value) Block Transfer Control */ 833 834 #define DMAC_BTCTRL_VALID_Pos 0 /**< \brief (DMAC_BTCTRL) Descriptor Valid */ 835 #define DMAC_BTCTRL_VALID (_U_(0x1) << DMAC_BTCTRL_VALID_Pos) 836 #define DMAC_BTCTRL_EVOSEL_Pos 1 /**< \brief (DMAC_BTCTRL) Event Output Selection */ 837 #define DMAC_BTCTRL_EVOSEL_Msk (_U_(0x3) << DMAC_BTCTRL_EVOSEL_Pos) 838 #define DMAC_BTCTRL_EVOSEL(value) (DMAC_BTCTRL_EVOSEL_Msk & ((value) << DMAC_BTCTRL_EVOSEL_Pos)) 839 #define DMAC_BTCTRL_EVOSEL_DISABLE_Val _U_(0x0) /**< \brief (DMAC_BTCTRL) Event generation disabled */ 840 #define DMAC_BTCTRL_EVOSEL_BLOCK_Val _U_(0x1) /**< \brief (DMAC_BTCTRL) Event strobe when block transfer complete */ 841 #define DMAC_BTCTRL_EVOSEL_BEAT_Val _U_(0x3) /**< \brief (DMAC_BTCTRL) Event strobe when beat transfer complete */ 842 #define DMAC_BTCTRL_EVOSEL_DISABLE (DMAC_BTCTRL_EVOSEL_DISABLE_Val << DMAC_BTCTRL_EVOSEL_Pos) 843 #define DMAC_BTCTRL_EVOSEL_BLOCK (DMAC_BTCTRL_EVOSEL_BLOCK_Val << DMAC_BTCTRL_EVOSEL_Pos) 844 #define DMAC_BTCTRL_EVOSEL_BEAT (DMAC_BTCTRL_EVOSEL_BEAT_Val << DMAC_BTCTRL_EVOSEL_Pos) 845 #define DMAC_BTCTRL_BLOCKACT_Pos 3 /**< \brief (DMAC_BTCTRL) Block Action */ 846 #define DMAC_BTCTRL_BLOCKACT_Msk (_U_(0x3) << DMAC_BTCTRL_BLOCKACT_Pos) 847 #define DMAC_BTCTRL_BLOCKACT(value) (DMAC_BTCTRL_BLOCKACT_Msk & ((value) << DMAC_BTCTRL_BLOCKACT_Pos)) 848 #define DMAC_BTCTRL_BLOCKACT_NOACT_Val _U_(0x0) /**< \brief (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction */ 849 #define DMAC_BTCTRL_BLOCKACT_INT_Val _U_(0x1) /**< \brief (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction and block interrupt */ 850 #define DMAC_BTCTRL_BLOCKACT_SUSPEND_Val _U_(0x2) /**< \brief (DMAC_BTCTRL) Channel suspend operation is completed */ 851 #define DMAC_BTCTRL_BLOCKACT_BOTH_Val _U_(0x3) /**< \brief (DMAC_BTCTRL) Both channel suspend operation and block interrupt */ 852 #define DMAC_BTCTRL_BLOCKACT_NOACT (DMAC_BTCTRL_BLOCKACT_NOACT_Val << DMAC_BTCTRL_BLOCKACT_Pos) 853 #define DMAC_BTCTRL_BLOCKACT_INT (DMAC_BTCTRL_BLOCKACT_INT_Val << DMAC_BTCTRL_BLOCKACT_Pos) 854 #define DMAC_BTCTRL_BLOCKACT_SUSPEND (DMAC_BTCTRL_BLOCKACT_SUSPEND_Val << DMAC_BTCTRL_BLOCKACT_Pos) 855 #define DMAC_BTCTRL_BLOCKACT_BOTH (DMAC_BTCTRL_BLOCKACT_BOTH_Val << DMAC_BTCTRL_BLOCKACT_Pos) 856 #define DMAC_BTCTRL_BEATSIZE_Pos 8 /**< \brief (DMAC_BTCTRL) Beat Size */ 857 #define DMAC_BTCTRL_BEATSIZE_Msk (_U_(0x3) << DMAC_BTCTRL_BEATSIZE_Pos) 858 #define DMAC_BTCTRL_BEATSIZE(value) (DMAC_BTCTRL_BEATSIZE_Msk & ((value) << DMAC_BTCTRL_BEATSIZE_Pos)) 859 #define DMAC_BTCTRL_BEATSIZE_BYTE_Val _U_(0x0) /**< \brief (DMAC_BTCTRL) 8-bit bus transfer */ 860 #define DMAC_BTCTRL_BEATSIZE_HWORD_Val _U_(0x1) /**< \brief (DMAC_BTCTRL) 16-bit bus transfer */ 861 #define DMAC_BTCTRL_BEATSIZE_WORD_Val _U_(0x2) /**< \brief (DMAC_BTCTRL) 32-bit bus transfer */ 862 #define DMAC_BTCTRL_BEATSIZE_BYTE (DMAC_BTCTRL_BEATSIZE_BYTE_Val << DMAC_BTCTRL_BEATSIZE_Pos) 863 #define DMAC_BTCTRL_BEATSIZE_HWORD (DMAC_BTCTRL_BEATSIZE_HWORD_Val << DMAC_BTCTRL_BEATSIZE_Pos) 864 #define DMAC_BTCTRL_BEATSIZE_WORD (DMAC_BTCTRL_BEATSIZE_WORD_Val << DMAC_BTCTRL_BEATSIZE_Pos) 865 #define DMAC_BTCTRL_SRCINC_Pos 10 /**< \brief (DMAC_BTCTRL) Source Address Increment Enable */ 866 #define DMAC_BTCTRL_SRCINC (_U_(0x1) << DMAC_BTCTRL_SRCINC_Pos) 867 #define DMAC_BTCTRL_DSTINC_Pos 11 /**< \brief (DMAC_BTCTRL) Destination Address Increment Enable */ 868 #define DMAC_BTCTRL_DSTINC (_U_(0x1) << DMAC_BTCTRL_DSTINC_Pos) 869 #define DMAC_BTCTRL_STEPSEL_Pos 12 /**< \brief (DMAC_BTCTRL) Step Selection */ 870 #define DMAC_BTCTRL_STEPSEL (_U_(0x1) << DMAC_BTCTRL_STEPSEL_Pos) 871 #define DMAC_BTCTRL_STEPSEL_DST_Val _U_(0x0) /**< \brief (DMAC_BTCTRL) Step size settings apply to the destination address */ 872 #define DMAC_BTCTRL_STEPSEL_SRC_Val _U_(0x1) /**< \brief (DMAC_BTCTRL) Step size settings apply to the source address */ 873 #define DMAC_BTCTRL_STEPSEL_DST (DMAC_BTCTRL_STEPSEL_DST_Val << DMAC_BTCTRL_STEPSEL_Pos) 874 #define DMAC_BTCTRL_STEPSEL_SRC (DMAC_BTCTRL_STEPSEL_SRC_Val << DMAC_BTCTRL_STEPSEL_Pos) 875 #define DMAC_BTCTRL_STEPSIZE_Pos 13 /**< \brief (DMAC_BTCTRL) Address Increment Step Size */ 876 #define DMAC_BTCTRL_STEPSIZE_Msk (_U_(0x7) << DMAC_BTCTRL_STEPSIZE_Pos) 877 #define DMAC_BTCTRL_STEPSIZE(value) (DMAC_BTCTRL_STEPSIZE_Msk & ((value) << DMAC_BTCTRL_STEPSIZE_Pos)) 878 #define DMAC_BTCTRL_STEPSIZE_X1_Val _U_(0x0) /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (BEATSIZE+1) * 1 */ 879 #define DMAC_BTCTRL_STEPSIZE_X2_Val _U_(0x1) /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (BEATSIZE+1) * 2 */ 880 #define DMAC_BTCTRL_STEPSIZE_X4_Val _U_(0x2) /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (BEATSIZE+1) * 4 */ 881 #define DMAC_BTCTRL_STEPSIZE_X8_Val _U_(0x3) /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (BEATSIZE+1) * 8 */ 882 #define DMAC_BTCTRL_STEPSIZE_X16_Val _U_(0x4) /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (BEATSIZE+1) * 16 */ 883 #define DMAC_BTCTRL_STEPSIZE_X32_Val _U_(0x5) /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (BEATSIZE+1) * 32 */ 884 #define DMAC_BTCTRL_STEPSIZE_X64_Val _U_(0x6) /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (BEATSIZE+1) * 64 */ 885 #define DMAC_BTCTRL_STEPSIZE_X128_Val _U_(0x7) /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (BEATSIZE+1) * 128 */ 886 #define DMAC_BTCTRL_STEPSIZE_X1 (DMAC_BTCTRL_STEPSIZE_X1_Val << DMAC_BTCTRL_STEPSIZE_Pos) 887 #define DMAC_BTCTRL_STEPSIZE_X2 (DMAC_BTCTRL_STEPSIZE_X2_Val << DMAC_BTCTRL_STEPSIZE_Pos) 888 #define DMAC_BTCTRL_STEPSIZE_X4 (DMAC_BTCTRL_STEPSIZE_X4_Val << DMAC_BTCTRL_STEPSIZE_Pos) 889 #define DMAC_BTCTRL_STEPSIZE_X8 (DMAC_BTCTRL_STEPSIZE_X8_Val << DMAC_BTCTRL_STEPSIZE_Pos) 890 #define DMAC_BTCTRL_STEPSIZE_X16 (DMAC_BTCTRL_STEPSIZE_X16_Val << DMAC_BTCTRL_STEPSIZE_Pos) 891 #define DMAC_BTCTRL_STEPSIZE_X32 (DMAC_BTCTRL_STEPSIZE_X32_Val << DMAC_BTCTRL_STEPSIZE_Pos) 892 #define DMAC_BTCTRL_STEPSIZE_X64 (DMAC_BTCTRL_STEPSIZE_X64_Val << DMAC_BTCTRL_STEPSIZE_Pos) 893 #define DMAC_BTCTRL_STEPSIZE_X128 (DMAC_BTCTRL_STEPSIZE_X128_Val << DMAC_BTCTRL_STEPSIZE_Pos) 894 #define DMAC_BTCTRL_MASK _U_(0xFF1F) /**< \brief (DMAC_BTCTRL) MASK Register */ 895 896 /* -------- DMAC_BTCNT : (DMAC Offset: 0x02) (R/W 16) Block Transfer Count -------- */ 897 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 898 typedef union { 899 struct { 900 uint16_t BTCNT:16; /*!< bit: 0..15 Block Transfer Count */ 901 } bit; /*!< Structure used for bit access */ 902 uint16_t reg; /*!< Type used for register access */ 903 } DMAC_BTCNT_Type; 904 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 905 906 #define DMAC_BTCNT_OFFSET 0x02 /**< \brief (DMAC_BTCNT offset) Block Transfer Count */ 907 908 #define DMAC_BTCNT_BTCNT_Pos 0 /**< \brief (DMAC_BTCNT) Block Transfer Count */ 909 #define DMAC_BTCNT_BTCNT_Msk (_U_(0xFFFF) << DMAC_BTCNT_BTCNT_Pos) 910 #define DMAC_BTCNT_BTCNT(value) (DMAC_BTCNT_BTCNT_Msk & ((value) << DMAC_BTCNT_BTCNT_Pos)) 911 #define DMAC_BTCNT_MASK _U_(0xFFFF) /**< \brief (DMAC_BTCNT) MASK Register */ 912 913 /* -------- DMAC_SRCADDR : (DMAC Offset: 0x04) (R/W 32) Block Transfer Source Address -------- */ 914 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 915 typedef union { 916 struct { 917 uint32_t SRCADDR:32; /*!< bit: 0..31 Transfer Source Address */ 918 } bit; /*!< Structure used for bit access */ 919 uint32_t reg; /*!< Type used for register access */ 920 } DMAC_SRCADDR_Type; 921 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 922 923 #define DMAC_SRCADDR_OFFSET 0x04 /**< \brief (DMAC_SRCADDR offset) Block Transfer Source Address */ 924 925 #define DMAC_SRCADDR_SRCADDR_Pos 0 /**< \brief (DMAC_SRCADDR) Transfer Source Address */ 926 #define DMAC_SRCADDR_SRCADDR_Msk (_U_(0xFFFFFFFF) << DMAC_SRCADDR_SRCADDR_Pos) 927 #define DMAC_SRCADDR_SRCADDR(value) (DMAC_SRCADDR_SRCADDR_Msk & ((value) << DMAC_SRCADDR_SRCADDR_Pos)) 928 #define DMAC_SRCADDR_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_SRCADDR) MASK Register */ 929 930 /* -------- DMAC_DSTADDR : (DMAC Offset: 0x08) (R/W 32) Block Transfer Destination Address -------- */ 931 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 932 typedef union { 933 struct { 934 uint32_t DSTADDR:32; /*!< bit: 0..31 Transfer Destination Address */ 935 } bit; /*!< Structure used for bit access */ 936 uint32_t reg; /*!< Type used for register access */ 937 } DMAC_DSTADDR_Type; 938 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 939 940 #define DMAC_DSTADDR_OFFSET 0x08 /**< \brief (DMAC_DSTADDR offset) Block Transfer Destination Address */ 941 942 #define DMAC_DSTADDR_DSTADDR_Pos 0 /**< \brief (DMAC_DSTADDR) Transfer Destination Address */ 943 #define DMAC_DSTADDR_DSTADDR_Msk (_U_(0xFFFFFFFF) << DMAC_DSTADDR_DSTADDR_Pos) 944 #define DMAC_DSTADDR_DSTADDR(value) (DMAC_DSTADDR_DSTADDR_Msk & ((value) << DMAC_DSTADDR_DSTADDR_Pos)) 945 #define DMAC_DSTADDR_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_DSTADDR) MASK Register */ 946 947 /* -------- DMAC_DESCADDR : (DMAC Offset: 0x0C) (R/W 32) Next Descriptor Address -------- */ 948 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 949 typedef union { 950 struct { 951 uint32_t DESCADDR:32; /*!< bit: 0..31 Next Descriptor Address */ 952 } bit; /*!< Structure used for bit access */ 953 uint32_t reg; /*!< Type used for register access */ 954 } DMAC_DESCADDR_Type; 955 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 956 957 #define DMAC_DESCADDR_OFFSET 0x0C /**< \brief (DMAC_DESCADDR offset) Next Descriptor Address */ 958 959 #define DMAC_DESCADDR_DESCADDR_Pos 0 /**< \brief (DMAC_DESCADDR) Next Descriptor Address */ 960 #define DMAC_DESCADDR_DESCADDR_Msk (_U_(0xFFFFFFFF) << DMAC_DESCADDR_DESCADDR_Pos) 961 #define DMAC_DESCADDR_DESCADDR(value) (DMAC_DESCADDR_DESCADDR_Msk & ((value) << DMAC_DESCADDR_DESCADDR_Pos)) 962 #define DMAC_DESCADDR_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_DESCADDR) MASK Register */ 963 964 /** \brief DMAC APB hardware registers */ 965 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 966 typedef struct { 967 __IO DMAC_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) Control */ 968 __IO DMAC_CRCCTRL_Type CRCCTRL; /**< \brief Offset: 0x02 (R/W 16) CRC Control */ 969 __IO DMAC_CRCDATAIN_Type CRCDATAIN; /**< \brief Offset: 0x04 (R/W 32) CRC Data Input */ 970 __IO DMAC_CRCCHKSUM_Type CRCCHKSUM; /**< \brief Offset: 0x08 (R/W 32) CRC Checksum */ 971 __IO DMAC_CRCSTATUS_Type CRCSTATUS; /**< \brief Offset: 0x0C (R/W 8) CRC Status */ 972 __IO DMAC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0D (R/W 8) Debug Control */ 973 RoReg8 Reserved1[0x2]; 974 __IO DMAC_SWTRIGCTRL_Type SWTRIGCTRL; /**< \brief Offset: 0x10 (R/W 32) Software Trigger Control */ 975 __IO DMAC_PRICTRL0_Type PRICTRL0; /**< \brief Offset: 0x14 (R/W 32) Priority Control 0 */ 976 RoReg8 Reserved2[0x8]; 977 __IO DMAC_INTPEND_Type INTPEND; /**< \brief Offset: 0x20 (R/W 16) Interrupt Pending */ 978 RoReg8 Reserved3[0x2]; 979 __I DMAC_INTSTATUS_Type INTSTATUS; /**< \brief Offset: 0x24 (R/ 32) Interrupt Status */ 980 __I DMAC_BUSYCH_Type BUSYCH; /**< \brief Offset: 0x28 (R/ 32) Busy Channels */ 981 __I DMAC_PENDCH_Type PENDCH; /**< \brief Offset: 0x2C (R/ 32) Pending Channels */ 982 __I DMAC_ACTIVE_Type ACTIVE; /**< \brief Offset: 0x30 (R/ 32) Active Channel and Levels */ 983 __IO DMAC_BASEADDR_Type BASEADDR; /**< \brief Offset: 0x34 (R/W 32) Descriptor Memory Section Base Address */ 984 __IO DMAC_WRBADDR_Type WRBADDR; /**< \brief Offset: 0x38 (R/W 32) Write-Back Memory Section Base Address */ 985 RoReg8 Reserved4[0x3]; 986 __IO DMAC_CHID_Type CHID; /**< \brief Offset: 0x3F (R/W 8) Channel ID */ 987 __IO DMAC_CHCTRLA_Type CHCTRLA; /**< \brief Offset: 0x40 (R/W 8) Channel Control A */ 988 RoReg8 Reserved5[0x3]; 989 __IO DMAC_CHCTRLB_Type CHCTRLB; /**< \brief Offset: 0x44 (R/W 32) Channel Control B */ 990 RoReg8 Reserved6[0x4]; 991 __IO DMAC_CHINTENCLR_Type CHINTENCLR; /**< \brief Offset: 0x4C (R/W 8) Channel Interrupt Enable Clear */ 992 __IO DMAC_CHINTENSET_Type CHINTENSET; /**< \brief Offset: 0x4D (R/W 8) Channel Interrupt Enable Set */ 993 __IO DMAC_CHINTFLAG_Type CHINTFLAG; /**< \brief Offset: 0x4E (R/W 8) Channel Interrupt Flag Status and Clear */ 994 __I DMAC_CHSTATUS_Type CHSTATUS; /**< \brief Offset: 0x4F (R/ 8) Channel Status */ 995 } Dmac; 996 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 997 998 /** \brief DMAC Descriptor SRAM registers */ 999 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1000 typedef struct { 1001 __IO DMAC_BTCTRL_Type BTCTRL; /**< \brief Offset: 0x00 (R/W 16) Block Transfer Control */ 1002 __IO DMAC_BTCNT_Type BTCNT; /**< \brief Offset: 0x02 (R/W 16) Block Transfer Count */ 1003 __IO DMAC_SRCADDR_Type SRCADDR; /**< \brief Offset: 0x04 (R/W 32) Block Transfer Source Address */ 1004 __IO DMAC_DSTADDR_Type DSTADDR; /**< \brief Offset: 0x08 (R/W 32) Block Transfer Destination Address */ 1005 __IO DMAC_DESCADDR_Type DESCADDR; /**< \brief Offset: 0x0C (R/W 32) Next Descriptor Address */ 1006 } DmacDescriptor 1007 #ifdef __GNUC__ 1008 __attribute__ ((aligned (8))) 1009 #endif 1010 ; 1011 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1012 1013 #define SECTION_DMAC_DESCRIPTOR 1014 1015 /*@}*/ 1016 1017 #endif /* _SAMC20_DMAC_COMPONENT_ */ 1018
