1 /** 2 * \file 3 * 4 * \brief Header file for SAMC20J18A 5 * 6 * Copyright (c) 2018 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAMC20J18A_ 31 #define _SAMC20J18A_ 32 33 /** 34 * \ingroup SAMC20_definitions 35 * \addtogroup SAMC20J18A_definitions SAMC20J18A definitions 36 * This file defines all structures and symbols for SAMC20J18A: 37 * - registers and bitfields 38 * - peripheral base address 39 * - peripheral ID 40 * - PIO definitions 41 */ 42 /*@{*/ 43 44 #ifdef __cplusplus 45 extern "C" { 46 #endif 47 48 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 49 #include <stdint.h> 50 #ifndef __cplusplus 51 typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ 52 typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ 53 typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ 54 #else 55 typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ 56 typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ 57 typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ 58 #endif 59 typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ 60 typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ 61 typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ 62 typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ 63 typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ 64 typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ 65 #endif 66 67 #if !defined(SKIP_INTEGER_LITERALS) 68 #if defined(_U_) || defined(_L_) || defined(_UL_) 69 #error "Integer Literals macros already defined elsewhere" 70 #endif 71 72 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 73 /* Macros that deal with adding suffixes to integer literal constants for C/C++ */ 74 #define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ 75 #define _L_(x) x ## L /**< C code: Long integer literal constant value */ 76 #define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ 77 #else /* Assembler */ 78 #define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ 79 #define _L_(x) x /**< Assembler: Long integer literal constant value */ 80 #define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ 81 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 82 #endif /* SKIP_INTEGER_LITERALS */ 83 84 /* ************************************************************************** */ 85 /** CMSIS DEFINITIONS FOR SAMC20J18A */ 86 /* ************************************************************************** */ 87 /** \defgroup SAMC20J18A_cmsis CMSIS Definitions */ 88 /*@{*/ 89 90 /** Interrupt Number Definition */ 91 typedef enum IRQn 92 { 93 /****** Cortex-M0+ Processor Exceptions Numbers *******************/ 94 NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ 95 HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ 96 SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ 97 PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ 98 SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ 99 /****** SAMC20J18A-specific Interrupt Numbers *********************/ 100 SYSTEM_IRQn = 0, /**< 0 SAMC20J18A System Interrupts */ 101 WDT_IRQn = 1, /**< 1 SAMC20J18A Watchdog Timer (WDT) */ 102 RTC_IRQn = 2, /**< 2 SAMC20J18A Real-Time Counter (RTC) */ 103 EIC_IRQn = 3, /**< 3 SAMC20J18A External Interrupt Controller (EIC) */ 104 FREQM_IRQn = 4, /**< 4 SAMC20J18A Frequency Meter (FREQM) */ 105 NVMCTRL_IRQn = 6, /**< 6 SAMC20J18A Non-Volatile Memory Controller (NVMCTRL) */ 106 DMAC_IRQn = 7, /**< 7 SAMC20J18A Direct Memory Access Controller (DMAC) */ 107 EVSYS_IRQn = 8, /**< 8 SAMC20J18A Event System Interface (EVSYS) */ 108 SERCOM0_IRQn = 9, /**< 9 SAMC20J18A Serial Communication Interface 0 (SERCOM0) */ 109 SERCOM1_IRQn = 10, /**< 10 SAMC20J18A Serial Communication Interface 1 (SERCOM1) */ 110 SERCOM2_IRQn = 11, /**< 11 SAMC20J18A Serial Communication Interface 2 (SERCOM2) */ 111 SERCOM3_IRQn = 12, /**< 12 SAMC20J18A Serial Communication Interface 3 (SERCOM3) */ 112 TCC0_IRQn = 17, /**< 17 SAMC20J18A Timer Counter Control 0 (TCC0) */ 113 TCC1_IRQn = 18, /**< 18 SAMC20J18A Timer Counter Control 1 (TCC1) */ 114 TCC2_IRQn = 19, /**< 19 SAMC20J18A Timer Counter Control 2 (TCC2) */ 115 TC0_IRQn = 20, /**< 20 SAMC20J18A Basic Timer Counter 0 (TC0) */ 116 TC1_IRQn = 21, /**< 21 SAMC20J18A Basic Timer Counter 1 (TC1) */ 117 TC2_IRQn = 22, /**< 22 SAMC20J18A Basic Timer Counter 2 (TC2) */ 118 TC3_IRQn = 23, /**< 23 SAMC20J18A Basic Timer Counter 3 (TC3) */ 119 TC4_IRQn = 24, /**< 24 SAMC20J18A Basic Timer Counter 4 (TC4) */ 120 ADC0_IRQn = 25, /**< 25 SAMC20J18A Analog Digital Converter 0 (ADC0) */ 121 AC_IRQn = 27, /**< 27 SAMC20J18A Analog Comparators (AC) */ 122 PTC_IRQn = 30, /**< 30 SAMC20J18A Peripheral Touch Controller (PTC) */ 123 124 PERIPH_COUNT_IRQn = 31 /**< Number of peripheral IDs */ 125 } IRQn_Type; 126 127 typedef struct _DeviceVectors 128 { 129 /* Stack pointer */ 130 void* pvStack; 131 132 /* Cortex-M handlers */ 133 void* pfnReset_Handler; 134 void* pfnNonMaskableInt_Handler; 135 void* pfnHardFault_Handler; 136 void* pvReservedM12; 137 void* pvReservedM11; 138 void* pvReservedM10; 139 void* pvReservedM9; 140 void* pvReservedM8; 141 void* pvReservedM7; 142 void* pvReservedM6; 143 void* pfnSVCall_Handler; 144 void* pvReservedM4; 145 void* pvReservedM3; 146 void* pfnPendSV_Handler; 147 void* pfnSysTick_Handler; 148 149 /* Peripheral handlers */ 150 void* pfnSYSTEM_Handler; /* 0 Main Clock, 32k Oscillators Control, Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ 151 void* pfnWDT_Handler; /* 1 Watchdog Timer */ 152 void* pfnRTC_Handler; /* 2 Real-Time Counter */ 153 void* pfnEIC_Handler; /* 3 External Interrupt Controller */ 154 void* pfnFREQM_Handler; /* 4 Frequency Meter */ 155 void* pvReserved5; 156 void* pfnNVMCTRL_Handler; /* 6 Non-Volatile Memory Controller */ 157 void* pfnDMAC_Handler; /* 7 Direct Memory Access Controller */ 158 void* pfnEVSYS_Handler; /* 8 Event System Interface */ 159 void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ 160 void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ 161 void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ 162 void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ 163 void* pvReserved13; 164 void* pvReserved14; 165 void* pvReserved15; 166 void* pvReserved16; 167 void* pfnTCC0_Handler; /* 17 Timer Counter Control 0 */ 168 void* pfnTCC1_Handler; /* 18 Timer Counter Control 1 */ 169 void* pfnTCC2_Handler; /* 19 Timer Counter Control 2 */ 170 void* pfnTC0_Handler; /* 20 Basic Timer Counter 0 */ 171 void* pfnTC1_Handler; /* 21 Basic Timer Counter 1 */ 172 void* pfnTC2_Handler; /* 22 Basic Timer Counter 2 */ 173 void* pfnTC3_Handler; /* 23 Basic Timer Counter 3 */ 174 void* pfnTC4_Handler; /* 24 Basic Timer Counter 4 */ 175 void* pfnADC0_Handler; /* 25 Analog Digital Converter 0 */ 176 void* pvReserved26; 177 void* pfnAC_Handler; /* 27 Analog Comparators */ 178 void* pvReserved28; 179 void* pvReserved29; 180 void* pfnPTC_Handler; /* 30 Peripheral Touch Controller */ 181 } DeviceVectors; 182 183 /* Cortex-M0+ processor handlers */ 184 void Reset_Handler ( void ); 185 void NonMaskableInt_Handler ( void ); 186 void HardFault_Handler ( void ); 187 void SVCall_Handler ( void ); 188 void PendSV_Handler ( void ); 189 void SysTick_Handler ( void ); 190 191 /* Peripherals handlers */ 192 void SYSTEM_Handler ( void ); 193 void WDT_Handler ( void ); 194 void RTC_Handler ( void ); 195 void EIC_Handler ( void ); 196 void FREQM_Handler ( void ); 197 void NVMCTRL_Handler ( void ); 198 void DMAC_Handler ( void ); 199 void EVSYS_Handler ( void ); 200 void SERCOM0_Handler ( void ); 201 void SERCOM1_Handler ( void ); 202 void SERCOM2_Handler ( void ); 203 void SERCOM3_Handler ( void ); 204 void TCC0_Handler ( void ); 205 void TCC1_Handler ( void ); 206 void TCC2_Handler ( void ); 207 void TC0_Handler ( void ); 208 void TC1_Handler ( void ); 209 void TC2_Handler ( void ); 210 void TC3_Handler ( void ); 211 void TC4_Handler ( void ); 212 void ADC0_Handler ( void ); 213 void AC_Handler ( void ); 214 void PTC_Handler ( void ); 215 216 /* 217 * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals 218 */ 219 220 #define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ 221 #define __MPU_PRESENT 1 /*!< MPU present or not */ 222 #define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ 223 #define __VTOR_PRESENT 1 /*!< VTOR present or not */ 224 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 225 226 /** 227 * \brief CMSIS includes 228 */ 229 230 #include <core_cm0plus.h> 231 #if !defined DONT_USE_CMSIS_INIT 232 #include "system_samc20.h" 233 #endif /* DONT_USE_CMSIS_INIT */ 234 235 /*@}*/ 236 237 /* ************************************************************************** */ 238 /** SOFTWARE PERIPHERAL API DEFINITION FOR SAMC20J18A */ 239 /* ************************************************************************** */ 240 /** \defgroup SAMC20J18A_api Peripheral Software API */ 241 /*@{*/ 242 243 #include "component/ac.h" 244 #include "component/adc.h" 245 #include "component/ccl.h" 246 #include "component/divas.h" 247 #include "component/dmac.h" 248 #include "component/dsu.h" 249 #include "component/eic.h" 250 #include "component/evsys.h" 251 #include "component/freqm.h" 252 #include "component/gclk.h" 253 #include "component/hmatrixb.h" 254 #include "component/mclk.h" 255 #include "component/mtb.h" 256 #include "component/nvmctrl.h" 257 #include "component/oscctrl.h" 258 #include "component/osc32kctrl.h" 259 #include "component/pac.h" 260 #include "component/pm.h" 261 #include "component/port.h" 262 #include "component/rstc.h" 263 #include "component/rtc.h" 264 #include "component/sercom.h" 265 #include "component/supc.h" 266 #include "component/tc.h" 267 #include "component/tcc.h" 268 #include "component/wdt.h" 269 /*@}*/ 270 271 /* ************************************************************************** */ 272 /** REGISTERS ACCESS DEFINITIONS FOR SAMC20J18A */ 273 /* ************************************************************************** */ 274 /** \defgroup SAMC20J18A_reg Registers Access Definitions */ 275 /*@{*/ 276 277 #include "instance/ac.h" 278 #include "instance/adc0.h" 279 #include "instance/ccl.h" 280 #include "instance/divas.h" 281 #include "instance/dmac.h" 282 #include "instance/dsu.h" 283 #include "instance/eic.h" 284 #include "instance/evsys.h" 285 #include "instance/freqm.h" 286 #include "instance/gclk.h" 287 #include "instance/hmatrixhs.h" 288 #include "instance/mclk.h" 289 #include "instance/mtb.h" 290 #include "instance/nvmctrl.h" 291 #include "instance/oscctrl.h" 292 #include "instance/osc32kctrl.h" 293 #include "instance/pac.h" 294 #include "instance/pm.h" 295 #include "instance/port.h" 296 #include "instance/ptc.h" 297 #include "instance/rstc.h" 298 #include "instance/rtc.h" 299 #include "instance/sercom0.h" 300 #include "instance/sercom1.h" 301 #include "instance/sercom2.h" 302 #include "instance/sercom3.h" 303 #include "instance/supc.h" 304 #include "instance/tc0.h" 305 #include "instance/tc1.h" 306 #include "instance/tc2.h" 307 #include "instance/tc3.h" 308 #include "instance/tc4.h" 309 #include "instance/tcc0.h" 310 #include "instance/tcc1.h" 311 #include "instance/tcc2.h" 312 #include "instance/wdt.h" 313 /*@}*/ 314 315 /* ************************************************************************** */ 316 /** PERIPHERAL ID DEFINITIONS FOR SAMC20J18A */ 317 /* ************************************************************************** */ 318 /** \defgroup SAMC20J18A_id Peripheral Ids Definitions */ 319 /*@{*/ 320 321 // Peripheral instances on HPB0 bridge 322 #define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ 323 #define ID_PM 1 /**< \brief Power Manager (PM) */ 324 #define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ 325 #define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ 326 #define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ 327 #define ID_OSC32KCTRL 5 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ 328 #define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ 329 #define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ 330 #define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ 331 #define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ 332 #define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ 333 #define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ 334 335 // Peripheral instances on HPB1 bridge 336 #define ID_PORT 32 /**< \brief Port Module (PORT) */ 337 #define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ 338 #define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ 339 #define ID_DMAC 35 /**< \brief Direct Memory Access Controller (DMAC) */ 340 #define ID_MTB 36 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ 341 #define ID_HMATRIXHS 37 /**< \brief HSB Matrix (HMATRIXHS) */ 342 343 // Peripheral instances on HPB2 bridge 344 #define ID_EVSYS 64 /**< \brief Event System Interface (EVSYS) */ 345 #define ID_SERCOM0 65 /**< \brief Serial Communication Interface 0 (SERCOM0) */ 346 #define ID_SERCOM1 66 /**< \brief Serial Communication Interface 1 (SERCOM1) */ 347 #define ID_SERCOM2 67 /**< \brief Serial Communication Interface 2 (SERCOM2) */ 348 #define ID_SERCOM3 68 /**< \brief Serial Communication Interface 3 (SERCOM3) */ 349 #define ID_TCC0 73 /**< \brief Timer Counter Control 0 (TCC0) */ 350 #define ID_TCC1 74 /**< \brief Timer Counter Control 1 (TCC1) */ 351 #define ID_TCC2 75 /**< \brief Timer Counter Control 2 (TCC2) */ 352 #define ID_TC0 76 /**< \brief Basic Timer Counter 0 (TC0) */ 353 #define ID_TC1 77 /**< \brief Basic Timer Counter 1 (TC1) */ 354 #define ID_TC2 78 /**< \brief Basic Timer Counter 2 (TC2) */ 355 #define ID_TC3 79 /**< \brief Basic Timer Counter 3 (TC3) */ 356 #define ID_TC4 80 /**< \brief Basic Timer Counter 4 (TC4) */ 357 #define ID_ADC0 81 /**< \brief Analog Digital Converter (ADC0) */ 358 #define ID_AC 84 /**< \brief Analog Comparators (AC) */ 359 #define ID_PTC 86 /**< \brief Peripheral Touch Controller (PTC) */ 360 #define ID_CCL 87 /**< \brief Configurable Custom Logic (CCL) */ 361 362 // Peripheral instances on AHB (as if on bridge 3) 363 #define ID_DIVAS 96 /**< \brief Divide and Square Root Accelerator (DIVAS) */ 364 365 #define ID_PERIPH_COUNT 97 /**< \brief Max number of peripheral IDs */ 366 /*@}*/ 367 368 /* ************************************************************************** */ 369 /** BASE ADDRESS DEFINITIONS FOR SAMC20J18A */ 370 /* ************************************************************************** */ 371 /** \defgroup SAMC20J18A_base Peripheral Base Address Definitions */ 372 /*@{*/ 373 374 #if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) 375 #define AC (0x42005000) /**< \brief (AC) APB Base Address */ 376 #define ADC0 (0x42004400) /**< \brief (ADC0) APB Base Address */ 377 #define CCL (0x42005C00) /**< \brief (CCL) APB Base Address */ 378 #define DIVAS (0x48000000) /**< \brief (DIVAS) AHB Base Address */ 379 #define DIVAS_IOBUS (0x60000200) /**< \brief (DIVAS) IOBUS Base Address */ 380 #define DMAC (0x41006000) /**< \brief (DMAC) APB Base Address */ 381 #define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ 382 #define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ 383 #define EVSYS (0x42000000) /**< \brief (EVSYS) APB Base Address */ 384 #define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ 385 #define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ 386 #define HMATRIXHS (0x4100A000) /**< \brief (HMATRIXHS) APB Base Address */ 387 #define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ 388 #define MTB (0x41008000) /**< \brief (MTB) APB Base Address */ 389 #define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ 390 #define NVMCTRL_OTP5 (0x00806020) /**< \brief (NVMCTRL) OTP5 Base Address */ 391 #define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ 392 #define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ 393 #define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ 394 #define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ 395 #define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ 396 #define PM (0x40000400) /**< \brief (PM) APB Base Address */ 397 #define PORT (0x41000000) /**< \brief (PORT) APB Base Address */ 398 #define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ 399 #define PTC (0x42005800) /**< \brief (PTC) APB Base Address */ 400 #define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ 401 #define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ 402 #define SERCOM0 (0x42000400) /**< \brief (SERCOM0) APB Base Address */ 403 #define SERCOM1 (0x42000800) /**< \brief (SERCOM1) APB Base Address */ 404 #define SERCOM2 (0x42000C00) /**< \brief (SERCOM2) APB Base Address */ 405 #define SERCOM3 (0x42001000) /**< \brief (SERCOM3) APB Base Address */ 406 #define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ 407 #define TC0 (0x42003000) /**< \brief (TC0) APB Base Address */ 408 #define TC1 (0x42003400) /**< \brief (TC1) APB Base Address */ 409 #define TC2 (0x42003800) /**< \brief (TC2) APB Base Address */ 410 #define TC3 (0x42003C00) /**< \brief (TC3) APB Base Address */ 411 #define TC4 (0x42004000) /**< \brief (TC4) APB Base Address */ 412 #define TCC0 (0x42002400) /**< \brief (TCC0) APB Base Address */ 413 #define TCC1 (0x42002800) /**< \brief (TCC1) APB Base Address */ 414 #define TCC2 (0x42002C00) /**< \brief (TCC2) APB Base Address */ 415 #define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ 416 #else 417 #define AC ((Ac *)0x42005000UL) /**< \brief (AC) APB Base Address */ 418 #define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ 419 #define AC_INSTS { AC } /**< \brief (AC) Instances List */ 420 421 #define ADC0 ((Adc *)0x42004400UL) /**< \brief (ADC0) APB Base Address */ 422 #define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ 423 #define ADC_INSTS { ADC0 } /**< \brief (ADC) Instances List */ 424 425 #define CCL ((Ccl *)0x42005C00UL) /**< \brief (CCL) APB Base Address */ 426 #define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ 427 #define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ 428 429 #define DIVAS ((Divas *)0x48000000UL) /**< \brief (DIVAS) AHB Base Address */ 430 #define DIVAS_IOBUS ((Divas *)0x60000200UL) /**< \brief (DIVAS) IOBUS Base Address */ 431 #define DIVAS_INST_NUM 1 /**< \brief (DIVAS) Number of instances */ 432 #define DIVAS_INSTS { DIVAS } /**< \brief (DIVAS) Instances List */ 433 #define DIVAS_IOBUS_INST_NUM 1 /**< \brief (DIVAS) Number of instances */ 434 #define DIVAS_IOBUS_INSTS { DIVAS_IOBUS } /**< \brief (DIVAS) Instances List */ 435 436 #define DMAC ((Dmac *)0x41006000UL) /**< \brief (DMAC) APB Base Address */ 437 #define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ 438 #define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ 439 440 #define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ 441 #define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ 442 #define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ 443 444 #define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ 445 #define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ 446 #define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ 447 448 #define EVSYS ((Evsys *)0x42000000UL) /**< \brief (EVSYS) APB Base Address */ 449 #define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ 450 #define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ 451 452 #define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ 453 #define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ 454 #define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ 455 456 #define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ 457 #define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ 458 #define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ 459 460 #define HMATRIXHS ((Hmatrixb *)0x4100A000UL) /**< \brief (HMATRIXHS) APB Base Address */ 461 #define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ 462 #define HMATRIXB_INSTS { HMATRIXHS } /**< \brief (HMATRIXB) Instances List */ 463 464 #define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ 465 #define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ 466 #define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ 467 468 #define MTB ((Mtb *)0x41008000UL) /**< \brief (MTB) APB Base Address */ 469 #define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ 470 #define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ 471 472 #define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ 473 #define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ 474 #define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ 475 #define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ 476 #define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ 477 #define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ 478 479 #define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ 480 #define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ 481 #define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ 482 483 #define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ 484 #define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ 485 #define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ 486 487 #define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ 488 #define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ 489 #define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ 490 491 #define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ 492 #define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ 493 #define PM_INSTS { PM } /**< \brief (PM) Instances List */ 494 495 #define PORT ((Port *)0x41000000UL) /**< \brief (PORT) APB Base Address */ 496 #define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ 497 #define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ 498 #define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ 499 #define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ 500 #define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ 501 502 #define PTC ((void *)0x42005800UL) /**< \brief (PTC) APB Base Address */ 503 #define PTC_GCLK_ID 37 504 #define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ 505 #define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ 506 507 #define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ 508 #define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ 509 #define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ 510 511 #define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ 512 #define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ 513 #define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ 514 515 #define SERCOM0 ((Sercom *)0x42000400UL) /**< \brief (SERCOM0) APB Base Address */ 516 #define SERCOM1 ((Sercom *)0x42000800UL) /**< \brief (SERCOM1) APB Base Address */ 517 #define SERCOM2 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM2) APB Base Address */ 518 #define SERCOM3 ((Sercom *)0x42001000UL) /**< \brief (SERCOM3) APB Base Address */ 519 #define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */ 520 #define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */ 521 522 #define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ 523 #define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ 524 #define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ 525 526 #define TC0 ((Tc *)0x42003000UL) /**< \brief (TC0) APB Base Address */ 527 #define TC1 ((Tc *)0x42003400UL) /**< \brief (TC1) APB Base Address */ 528 #define TC2 ((Tc *)0x42003800UL) /**< \brief (TC2) APB Base Address */ 529 #define TC3 ((Tc *)0x42003C00UL) /**< \brief (TC3) APB Base Address */ 530 #define TC4 ((Tc *)0x42004000UL) /**< \brief (TC4) APB Base Address */ 531 #define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ 532 #define TC_INSTS { TC0, TC1, TC2, TC3, TC4 } /**< \brief (TC) Instances List */ 533 534 #define TCC0 ((Tcc *)0x42002400UL) /**< \brief (TCC0) APB Base Address */ 535 #define TCC1 ((Tcc *)0x42002800UL) /**< \brief (TCC1) APB Base Address */ 536 #define TCC2 ((Tcc *)0x42002C00UL) /**< \brief (TCC2) APB Base Address */ 537 #define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ 538 #define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ 539 540 #define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ 541 #define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ 542 #define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ 543 544 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 545 /*@}*/ 546 547 /* ************************************************************************** */ 548 /** PORT DEFINITIONS FOR SAMC20J18A */ 549 /* ************************************************************************** */ 550 /** \defgroup SAMC20J18A_port PORT Definitions */ 551 /*@{*/ 552 553 #include "pio/samc20j18a.h" 554 /*@}*/ 555 556 /* ************************************************************************** */ 557 /** MEMORY MAPPING DEFINITIONS FOR SAMC20J18A */ 558 /* ************************************************************************** */ 559 560 #define FLASH_SIZE _UL_(0x00040000) /* 256 kB */ 561 #define FLASH_PAGE_SIZE 64 562 #define FLASH_NB_OF_PAGES 4096 563 #define FLASH_USER_PAGE_SIZE 64 564 #define HSRAM_SIZE _UL_(0x00008000) /* 32 kB */ 565 566 #define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ 567 #define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */ 568 #define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ 569 #define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ 570 #define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ 571 #define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ 572 #define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ 573 574 #define DSU_DID_RESETVALUE _UL_(0x11000500) 575 #define AC_PAIRS 1 576 #define DMAC_CH_NUM 6 577 #define EVSYS_CHANNELS 6 578 #define NVMCTRL_RWW_EEPROM_SIZE _UL_(0x00002000) /* 8 kB */ 579 #define PORT_GROUPS 2 580 581 /* ************************************************************************** */ 582 /** ELECTRICAL DEFINITIONS FOR SAMC20J18A */ 583 /* ************************************************************************** */ 584 585 586 #ifdef __cplusplus 587 } 588 #endif 589 590 /*@}*/ 591 592 #endif /* SAMC20J18A_H */ 593
