1 /** 2 * \file 3 * 4 * \brief Component description for OSCCTRL 5 * 6 * Copyright (c) 2018 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAMC20_OSCCTRL_COMPONENT_ 31 #define _SAMC20_OSCCTRL_COMPONENT_ 32 33 /* ========================================================================== */ 34 /** SOFTWARE API DEFINITION FOR OSCCTRL */ 35 /* ========================================================================== */ 36 /** \addtogroup SAMC20_OSCCTRL Oscillators Control */ 37 /*@{*/ 38 39 #define OSCCTRL_U2119 40 #define REV_OSCCTRL 0x210 41 42 /* -------- OSCCTRL_INTENCLR : (OSCCTRL Offset: 0x00) (R/W 32) Interrupt Enable Clear -------- */ 43 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 44 typedef union { 45 struct { 46 uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready Interrupt Enable */ 47 uint32_t XOSCFAIL:1; /*!< bit: 1 XOSC Clock Failure Detector Interrupt Enable */ 48 uint32_t :2; /*!< bit: 2.. 3 Reserved */ 49 uint32_t OSC48MRDY:1; /*!< bit: 4 OSC48M Ready Interrupt Enable */ 50 uint32_t :3; /*!< bit: 5.. 7 Reserved */ 51 uint32_t DPLLLCKR:1; /*!< bit: 8 DPLL Lock Rise Interrupt Enable */ 52 uint32_t DPLLLCKF:1; /*!< bit: 9 DPLL Lock Fall Interrupt Enable */ 53 uint32_t DPLLLTO:1; /*!< bit: 10 DPLL Time Out Interrupt Enable */ 54 uint32_t DPLLLDRTO:1; /*!< bit: 11 DPLL Ratio Ready Interrupt Enable */ 55 uint32_t :20; /*!< bit: 12..31 Reserved */ 56 } bit; /*!< Structure used for bit access */ 57 uint32_t reg; /*!< Type used for register access */ 58 } OSCCTRL_INTENCLR_Type; 59 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 60 61 #define OSCCTRL_INTENCLR_OFFSET 0x00 /**< \brief (OSCCTRL_INTENCLR offset) Interrupt Enable Clear */ 62 #define OSCCTRL_INTENCLR_RESETVALUE _U_(0x00000000) /**< \brief (OSCCTRL_INTENCLR reset_value) Interrupt Enable Clear */ 63 64 #define OSCCTRL_INTENCLR_XOSCRDY_Pos 0 /**< \brief (OSCCTRL_INTENCLR) XOSC Ready Interrupt Enable */ 65 #define OSCCTRL_INTENCLR_XOSCRDY (_U_(0x1) << OSCCTRL_INTENCLR_XOSCRDY_Pos) 66 #define OSCCTRL_INTENCLR_XOSCFAIL_Pos 1 /**< \brief (OSCCTRL_INTENCLR) XOSC Clock Failure Detector Interrupt Enable */ 67 #define OSCCTRL_INTENCLR_XOSCFAIL (_U_(0x1) << OSCCTRL_INTENCLR_XOSCFAIL_Pos) 68 #define OSCCTRL_INTENCLR_OSC48MRDY_Pos 4 /**< \brief (OSCCTRL_INTENCLR) OSC48M Ready Interrupt Enable */ 69 #define OSCCTRL_INTENCLR_OSC48MRDY (_U_(0x1) << OSCCTRL_INTENCLR_OSC48MRDY_Pos) 70 #define OSCCTRL_INTENCLR_DPLLLCKR_Pos 8 /**< \brief (OSCCTRL_INTENCLR) DPLL Lock Rise Interrupt Enable */ 71 #define OSCCTRL_INTENCLR_DPLLLCKR (_U_(0x1) << OSCCTRL_INTENCLR_DPLLLCKR_Pos) 72 #define OSCCTRL_INTENCLR_DPLLLCKF_Pos 9 /**< \brief (OSCCTRL_INTENCLR) DPLL Lock Fall Interrupt Enable */ 73 #define OSCCTRL_INTENCLR_DPLLLCKF (_U_(0x1) << OSCCTRL_INTENCLR_DPLLLCKF_Pos) 74 #define OSCCTRL_INTENCLR_DPLLLTO_Pos 10 /**< \brief (OSCCTRL_INTENCLR) DPLL Time Out Interrupt Enable */ 75 #define OSCCTRL_INTENCLR_DPLLLTO (_U_(0x1) << OSCCTRL_INTENCLR_DPLLLTO_Pos) 76 #define OSCCTRL_INTENCLR_DPLLLDRTO_Pos 11 /**< \brief (OSCCTRL_INTENCLR) DPLL Ratio Ready Interrupt Enable */ 77 #define OSCCTRL_INTENCLR_DPLLLDRTO (_U_(0x1) << OSCCTRL_INTENCLR_DPLLLDRTO_Pos) 78 #define OSCCTRL_INTENCLR_MASK _U_(0x00000F13) /**< \brief (OSCCTRL_INTENCLR) MASK Register */ 79 80 /* -------- OSCCTRL_INTENSET : (OSCCTRL Offset: 0x04) (R/W 32) Interrupt Enable Set -------- */ 81 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 82 typedef union { 83 struct { 84 uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready Interrupt Enable */ 85 uint32_t XOSCFAIL:1; /*!< bit: 1 XOSC Clock Failure Detector Interrupt Enable */ 86 uint32_t :2; /*!< bit: 2.. 3 Reserved */ 87 uint32_t OSC48MRDY:1; /*!< bit: 4 OSC48M Ready Interrupt Enable */ 88 uint32_t :3; /*!< bit: 5.. 7 Reserved */ 89 uint32_t DPLLLCKR:1; /*!< bit: 8 DPLL Lock Rise Interrupt Enable */ 90 uint32_t DPLLLCKF:1; /*!< bit: 9 DPLL Lock Fall Interrupt Enable */ 91 uint32_t DPLLLTO:1; /*!< bit: 10 DPLL Time Out Interrupt Enable */ 92 uint32_t DPLLLDRTO:1; /*!< bit: 11 DPLL Ratio Ready Interrupt Enable */ 93 uint32_t :20; /*!< bit: 12..31 Reserved */ 94 } bit; /*!< Structure used for bit access */ 95 uint32_t reg; /*!< Type used for register access */ 96 } OSCCTRL_INTENSET_Type; 97 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 98 99 #define OSCCTRL_INTENSET_OFFSET 0x04 /**< \brief (OSCCTRL_INTENSET offset) Interrupt Enable Set */ 100 #define OSCCTRL_INTENSET_RESETVALUE _U_(0x00000000) /**< \brief (OSCCTRL_INTENSET reset_value) Interrupt Enable Set */ 101 102 #define OSCCTRL_INTENSET_XOSCRDY_Pos 0 /**< \brief (OSCCTRL_INTENSET) XOSC Ready Interrupt Enable */ 103 #define OSCCTRL_INTENSET_XOSCRDY (_U_(0x1) << OSCCTRL_INTENSET_XOSCRDY_Pos) 104 #define OSCCTRL_INTENSET_XOSCFAIL_Pos 1 /**< \brief (OSCCTRL_INTENSET) XOSC Clock Failure Detector Interrupt Enable */ 105 #define OSCCTRL_INTENSET_XOSCFAIL (_U_(0x1) << OSCCTRL_INTENSET_XOSCFAIL_Pos) 106 #define OSCCTRL_INTENSET_OSC48MRDY_Pos 4 /**< \brief (OSCCTRL_INTENSET) OSC48M Ready Interrupt Enable */ 107 #define OSCCTRL_INTENSET_OSC48MRDY (_U_(0x1) << OSCCTRL_INTENSET_OSC48MRDY_Pos) 108 #define OSCCTRL_INTENSET_DPLLLCKR_Pos 8 /**< \brief (OSCCTRL_INTENSET) DPLL Lock Rise Interrupt Enable */ 109 #define OSCCTRL_INTENSET_DPLLLCKR (_U_(0x1) << OSCCTRL_INTENSET_DPLLLCKR_Pos) 110 #define OSCCTRL_INTENSET_DPLLLCKF_Pos 9 /**< \brief (OSCCTRL_INTENSET) DPLL Lock Fall Interrupt Enable */ 111 #define OSCCTRL_INTENSET_DPLLLCKF (_U_(0x1) << OSCCTRL_INTENSET_DPLLLCKF_Pos) 112 #define OSCCTRL_INTENSET_DPLLLTO_Pos 10 /**< \brief (OSCCTRL_INTENSET) DPLL Time Out Interrupt Enable */ 113 #define OSCCTRL_INTENSET_DPLLLTO (_U_(0x1) << OSCCTRL_INTENSET_DPLLLTO_Pos) 114 #define OSCCTRL_INTENSET_DPLLLDRTO_Pos 11 /**< \brief (OSCCTRL_INTENSET) DPLL Ratio Ready Interrupt Enable */ 115 #define OSCCTRL_INTENSET_DPLLLDRTO (_U_(0x1) << OSCCTRL_INTENSET_DPLLLDRTO_Pos) 116 #define OSCCTRL_INTENSET_MASK _U_(0x00000F13) /**< \brief (OSCCTRL_INTENSET) MASK Register */ 117 118 /* -------- OSCCTRL_INTFLAG : (OSCCTRL Offset: 0x08) (R/W 32) Interrupt Flag Status and Clear -------- */ 119 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 120 typedef union { // __I to avoid read-modify-write on write-to-clear register 121 struct { 122 __I uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready */ 123 __I uint32_t XOSCFAIL:1; /*!< bit: 1 XOSC Clock Failure Detector */ 124 __I uint32_t :2; /*!< bit: 2.. 3 Reserved */ 125 __I uint32_t OSC48MRDY:1; /*!< bit: 4 OSC48M Ready */ 126 __I uint32_t :3; /*!< bit: 5.. 7 Reserved */ 127 __I uint32_t DPLLLCKR:1; /*!< bit: 8 DPLL Lock Rise */ 128 __I uint32_t DPLLLCKF:1; /*!< bit: 9 DPLL Lock Fall */ 129 __I uint32_t DPLLLTO:1; /*!< bit: 10 DPLL Timeout */ 130 __I uint32_t DPLLLDRTO:1; /*!< bit: 11 DPLL Ratio Ready */ 131 __I uint32_t :20; /*!< bit: 12..31 Reserved */ 132 } bit; /*!< Structure used for bit access */ 133 uint32_t reg; /*!< Type used for register access */ 134 } OSCCTRL_INTFLAG_Type; 135 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 136 137 #define OSCCTRL_INTFLAG_OFFSET 0x08 /**< \brief (OSCCTRL_INTFLAG offset) Interrupt Flag Status and Clear */ 138 #define OSCCTRL_INTFLAG_RESETVALUE _U_(0x00000000) /**< \brief (OSCCTRL_INTFLAG reset_value) Interrupt Flag Status and Clear */ 139 140 #define OSCCTRL_INTFLAG_XOSCRDY_Pos 0 /**< \brief (OSCCTRL_INTFLAG) XOSC Ready */ 141 #define OSCCTRL_INTFLAG_XOSCRDY (_U_(0x1) << OSCCTRL_INTFLAG_XOSCRDY_Pos) 142 #define OSCCTRL_INTFLAG_XOSCFAIL_Pos 1 /**< \brief (OSCCTRL_INTFLAG) XOSC Clock Failure Detector */ 143 #define OSCCTRL_INTFLAG_XOSCFAIL (_U_(0x1) << OSCCTRL_INTFLAG_XOSCFAIL_Pos) 144 #define OSCCTRL_INTFLAG_OSC48MRDY_Pos 4 /**< \brief (OSCCTRL_INTFLAG) OSC48M Ready */ 145 #define OSCCTRL_INTFLAG_OSC48MRDY (_U_(0x1) << OSCCTRL_INTFLAG_OSC48MRDY_Pos) 146 #define OSCCTRL_INTFLAG_DPLLLCKR_Pos 8 /**< \brief (OSCCTRL_INTFLAG) DPLL Lock Rise */ 147 #define OSCCTRL_INTFLAG_DPLLLCKR (_U_(0x1) << OSCCTRL_INTFLAG_DPLLLCKR_Pos) 148 #define OSCCTRL_INTFLAG_DPLLLCKF_Pos 9 /**< \brief (OSCCTRL_INTFLAG) DPLL Lock Fall */ 149 #define OSCCTRL_INTFLAG_DPLLLCKF (_U_(0x1) << OSCCTRL_INTFLAG_DPLLLCKF_Pos) 150 #define OSCCTRL_INTFLAG_DPLLLTO_Pos 10 /**< \brief (OSCCTRL_INTFLAG) DPLL Timeout */ 151 #define OSCCTRL_INTFLAG_DPLLLTO (_U_(0x1) << OSCCTRL_INTFLAG_DPLLLTO_Pos) 152 #define OSCCTRL_INTFLAG_DPLLLDRTO_Pos 11 /**< \brief (OSCCTRL_INTFLAG) DPLL Ratio Ready */ 153 #define OSCCTRL_INTFLAG_DPLLLDRTO (_U_(0x1) << OSCCTRL_INTFLAG_DPLLLDRTO_Pos) 154 #define OSCCTRL_INTFLAG_MASK _U_(0x00000F13) /**< \brief (OSCCTRL_INTFLAG) MASK Register */ 155 156 /* -------- OSCCTRL_STATUS : (OSCCTRL Offset: 0x0C) (R/ 32) Power and Clocks Status -------- */ 157 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 158 typedef union { 159 struct { 160 uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready */ 161 uint32_t XOSCFAIL:1; /*!< bit: 1 XOSC Clock Failure Detector */ 162 uint32_t XOSCCKSW:1; /*!< bit: 2 XOSC Clock Switch */ 163 uint32_t :1; /*!< bit: 3 Reserved */ 164 uint32_t OSC48MRDY:1; /*!< bit: 4 OSC48M Ready */ 165 uint32_t :3; /*!< bit: 5.. 7 Reserved */ 166 uint32_t DPLLLCKR:1; /*!< bit: 8 DPLL Lock Rise */ 167 uint32_t DPLLLCKF:1; /*!< bit: 9 DPLL Lock Fall */ 168 uint32_t DPLLTO:1; /*!< bit: 10 DPLL Timeout */ 169 uint32_t DPLLLDRTO:1; /*!< bit: 11 DPLL Ratio Ready */ 170 uint32_t :20; /*!< bit: 12..31 Reserved */ 171 } bit; /*!< Structure used for bit access */ 172 uint32_t reg; /*!< Type used for register access */ 173 } OSCCTRL_STATUS_Type; 174 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 175 176 #define OSCCTRL_STATUS_OFFSET 0x0C /**< \brief (OSCCTRL_STATUS offset) Power and Clocks Status */ 177 #define OSCCTRL_STATUS_RESETVALUE _U_(0x00000000) /**< \brief (OSCCTRL_STATUS reset_value) Power and Clocks Status */ 178 179 #define OSCCTRL_STATUS_XOSCRDY_Pos 0 /**< \brief (OSCCTRL_STATUS) XOSC Ready */ 180 #define OSCCTRL_STATUS_XOSCRDY (_U_(0x1) << OSCCTRL_STATUS_XOSCRDY_Pos) 181 #define OSCCTRL_STATUS_XOSCFAIL_Pos 1 /**< \brief (OSCCTRL_STATUS) XOSC Clock Failure Detector */ 182 #define OSCCTRL_STATUS_XOSCFAIL (_U_(0x1) << OSCCTRL_STATUS_XOSCFAIL_Pos) 183 #define OSCCTRL_STATUS_XOSCCKSW_Pos 2 /**< \brief (OSCCTRL_STATUS) XOSC Clock Switch */ 184 #define OSCCTRL_STATUS_XOSCCKSW (_U_(0x1) << OSCCTRL_STATUS_XOSCCKSW_Pos) 185 #define OSCCTRL_STATUS_OSC48MRDY_Pos 4 /**< \brief (OSCCTRL_STATUS) OSC48M Ready */ 186 #define OSCCTRL_STATUS_OSC48MRDY (_U_(0x1) << OSCCTRL_STATUS_OSC48MRDY_Pos) 187 #define OSCCTRL_STATUS_DPLLLCKR_Pos 8 /**< \brief (OSCCTRL_STATUS) DPLL Lock Rise */ 188 #define OSCCTRL_STATUS_DPLLLCKR (_U_(0x1) << OSCCTRL_STATUS_DPLLLCKR_Pos) 189 #define OSCCTRL_STATUS_DPLLLCKF_Pos 9 /**< \brief (OSCCTRL_STATUS) DPLL Lock Fall */ 190 #define OSCCTRL_STATUS_DPLLLCKF (_U_(0x1) << OSCCTRL_STATUS_DPLLLCKF_Pos) 191 #define OSCCTRL_STATUS_DPLLTO_Pos 10 /**< \brief (OSCCTRL_STATUS) DPLL Timeout */ 192 #define OSCCTRL_STATUS_DPLLTO (_U_(0x1) << OSCCTRL_STATUS_DPLLTO_Pos) 193 #define OSCCTRL_STATUS_DPLLLDRTO_Pos 11 /**< \brief (OSCCTRL_STATUS) DPLL Ratio Ready */ 194 #define OSCCTRL_STATUS_DPLLLDRTO (_U_(0x1) << OSCCTRL_STATUS_DPLLLDRTO_Pos) 195 #define OSCCTRL_STATUS_MASK _U_(0x00000F17) /**< \brief (OSCCTRL_STATUS) MASK Register */ 196 197 /* -------- OSCCTRL_XOSCCTRL : (OSCCTRL Offset: 0x10) (R/W 16) External Multipurpose Crystal Oscillator (XOSC) Control -------- */ 198 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 199 typedef union { 200 struct { 201 uint16_t :1; /*!< bit: 0 Reserved */ 202 uint16_t ENABLE:1; /*!< bit: 1 Oscillator Enable */ 203 uint16_t XTALEN:1; /*!< bit: 2 Crystal Oscillator Enable */ 204 uint16_t CFDEN:1; /*!< bit: 3 Xosc Clock Failure Detecteor Enable */ 205 uint16_t SWBEN:1; /*!< bit: 4 Xosc Clock Switch Enable */ 206 uint16_t :1; /*!< bit: 5 Reserved */ 207 uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ 208 uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ 209 uint16_t GAIN:3; /*!< bit: 8..10 Oscillator Gain */ 210 uint16_t AMPGC:1; /*!< bit: 11 Automatic Amplitude Gain Control */ 211 uint16_t STARTUP:4; /*!< bit: 12..15 Start-Up Time */ 212 } bit; /*!< Structure used for bit access */ 213 uint16_t reg; /*!< Type used for register access */ 214 } OSCCTRL_XOSCCTRL_Type; 215 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 216 217 #define OSCCTRL_XOSCCTRL_OFFSET 0x10 /**< \brief (OSCCTRL_XOSCCTRL offset) External Multipurpose Crystal Oscillator (XOSC) Control */ 218 #define OSCCTRL_XOSCCTRL_RESETVALUE _U_(0x0080) /**< \brief (OSCCTRL_XOSCCTRL reset_value) External Multipurpose Crystal Oscillator (XOSC) Control */ 219 220 #define OSCCTRL_XOSCCTRL_ENABLE_Pos 1 /**< \brief (OSCCTRL_XOSCCTRL) Oscillator Enable */ 221 #define OSCCTRL_XOSCCTRL_ENABLE (_U_(0x1) << OSCCTRL_XOSCCTRL_ENABLE_Pos) 222 #define OSCCTRL_XOSCCTRL_XTALEN_Pos 2 /**< \brief (OSCCTRL_XOSCCTRL) Crystal Oscillator Enable */ 223 #define OSCCTRL_XOSCCTRL_XTALEN (_U_(0x1) << OSCCTRL_XOSCCTRL_XTALEN_Pos) 224 #define OSCCTRL_XOSCCTRL_CFDEN_Pos 3 /**< \brief (OSCCTRL_XOSCCTRL) Xosc Clock Failure Detecteor Enable */ 225 #define OSCCTRL_XOSCCTRL_CFDEN (_U_(0x1) << OSCCTRL_XOSCCTRL_CFDEN_Pos) 226 #define OSCCTRL_XOSCCTRL_SWBEN_Pos 4 /**< \brief (OSCCTRL_XOSCCTRL) Xosc Clock Switch Enable */ 227 #define OSCCTRL_XOSCCTRL_SWBEN (_U_(0x1) << OSCCTRL_XOSCCTRL_SWBEN_Pos) 228 #define OSCCTRL_XOSCCTRL_RUNSTDBY_Pos 6 /**< \brief (OSCCTRL_XOSCCTRL) Run in Standby */ 229 #define OSCCTRL_XOSCCTRL_RUNSTDBY (_U_(0x1) << OSCCTRL_XOSCCTRL_RUNSTDBY_Pos) 230 #define OSCCTRL_XOSCCTRL_ONDEMAND_Pos 7 /**< \brief (OSCCTRL_XOSCCTRL) On Demand Control */ 231 #define OSCCTRL_XOSCCTRL_ONDEMAND (_U_(0x1) << OSCCTRL_XOSCCTRL_ONDEMAND_Pos) 232 #define OSCCTRL_XOSCCTRL_GAIN_Pos 8 /**< \brief (OSCCTRL_XOSCCTRL) Oscillator Gain */ 233 #define OSCCTRL_XOSCCTRL_GAIN_Msk (_U_(0x7) << OSCCTRL_XOSCCTRL_GAIN_Pos) 234 #define OSCCTRL_XOSCCTRL_GAIN(value) (OSCCTRL_XOSCCTRL_GAIN_Msk & ((value) << OSCCTRL_XOSCCTRL_GAIN_Pos)) 235 #define OSCCTRL_XOSCCTRL_AMPGC_Pos 11 /**< \brief (OSCCTRL_XOSCCTRL) Automatic Amplitude Gain Control */ 236 #define OSCCTRL_XOSCCTRL_AMPGC (_U_(0x1) << OSCCTRL_XOSCCTRL_AMPGC_Pos) 237 #define OSCCTRL_XOSCCTRL_STARTUP_Pos 12 /**< \brief (OSCCTRL_XOSCCTRL) Start-Up Time */ 238 #define OSCCTRL_XOSCCTRL_STARTUP_Msk (_U_(0xF) << OSCCTRL_XOSCCTRL_STARTUP_Pos) 239 #define OSCCTRL_XOSCCTRL_STARTUP(value) (OSCCTRL_XOSCCTRL_STARTUP_Msk & ((value) << OSCCTRL_XOSCCTRL_STARTUP_Pos)) 240 #define OSCCTRL_XOSCCTRL_MASK _U_(0xFFDE) /**< \brief (OSCCTRL_XOSCCTRL) MASK Register */ 241 242 /* -------- OSCCTRL_CFDPRESC : (OSCCTRL Offset: 0x12) (R/W 8) Clock Failure Detector Prescaler -------- */ 243 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 244 typedef union { 245 struct { 246 uint8_t CFDPRESC:3; /*!< bit: 0.. 2 Clock Failure Detector Prescaler */ 247 uint8_t :5; /*!< bit: 3.. 7 Reserved */ 248 } bit; /*!< Structure used for bit access */ 249 uint8_t reg; /*!< Type used for register access */ 250 } OSCCTRL_CFDPRESC_Type; 251 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 252 253 #define OSCCTRL_CFDPRESC_OFFSET 0x12 /**< \brief (OSCCTRL_CFDPRESC offset) Clock Failure Detector Prescaler */ 254 #define OSCCTRL_CFDPRESC_RESETVALUE _U_(0x00) /**< \brief (OSCCTRL_CFDPRESC reset_value) Clock Failure Detector Prescaler */ 255 256 #define OSCCTRL_CFDPRESC_CFDPRESC_Pos 0 /**< \brief (OSCCTRL_CFDPRESC) Clock Failure Detector Prescaler */ 257 #define OSCCTRL_CFDPRESC_CFDPRESC_Msk (_U_(0x7) << OSCCTRL_CFDPRESC_CFDPRESC_Pos) 258 #define OSCCTRL_CFDPRESC_CFDPRESC(value) (OSCCTRL_CFDPRESC_CFDPRESC_Msk & ((value) << OSCCTRL_CFDPRESC_CFDPRESC_Pos)) 259 #define OSCCTRL_CFDPRESC_MASK _U_(0x07) /**< \brief (OSCCTRL_CFDPRESC) MASK Register */ 260 261 /* -------- OSCCTRL_EVCTRL : (OSCCTRL Offset: 0x13) (R/W 8) Event Control -------- */ 262 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 263 typedef union { 264 struct { 265 uint8_t CFDEO:1; /*!< bit: 0 Clock Failure Detector Event Output Enable */ 266 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 267 } bit; /*!< Structure used for bit access */ 268 uint8_t reg; /*!< Type used for register access */ 269 } OSCCTRL_EVCTRL_Type; 270 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 271 272 #define OSCCTRL_EVCTRL_OFFSET 0x13 /**< \brief (OSCCTRL_EVCTRL offset) Event Control */ 273 #define OSCCTRL_EVCTRL_RESETVALUE _U_(0x00) /**< \brief (OSCCTRL_EVCTRL reset_value) Event Control */ 274 275 #define OSCCTRL_EVCTRL_CFDEO_Pos 0 /**< \brief (OSCCTRL_EVCTRL) Clock Failure Detector Event Output Enable */ 276 #define OSCCTRL_EVCTRL_CFDEO (_U_(0x1) << OSCCTRL_EVCTRL_CFDEO_Pos) 277 #define OSCCTRL_EVCTRL_MASK _U_(0x01) /**< \brief (OSCCTRL_EVCTRL) MASK Register */ 278 279 /* -------- OSCCTRL_OSC48MCTRL : (OSCCTRL Offset: 0x14) (R/W 8) 48MHz Internal Oscillator (OSC48M) Control -------- */ 280 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 281 typedef union { 282 struct { 283 uint8_t :1; /*!< bit: 0 Reserved */ 284 uint8_t ENABLE:1; /*!< bit: 1 Oscillator Enable */ 285 uint8_t :4; /*!< bit: 2.. 5 Reserved */ 286 uint8_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ 287 uint8_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ 288 } bit; /*!< Structure used for bit access */ 289 uint8_t reg; /*!< Type used for register access */ 290 } OSCCTRL_OSC48MCTRL_Type; 291 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 292 293 #define OSCCTRL_OSC48MCTRL_OFFSET 0x14 /**< \brief (OSCCTRL_OSC48MCTRL offset) 48MHz Internal Oscillator (OSC48M) Control */ 294 #define OSCCTRL_OSC48MCTRL_RESETVALUE _U_(0x82) /**< \brief (OSCCTRL_OSC48MCTRL reset_value) 48MHz Internal Oscillator (OSC48M) Control */ 295 296 #define OSCCTRL_OSC48MCTRL_ENABLE_Pos 1 /**< \brief (OSCCTRL_OSC48MCTRL) Oscillator Enable */ 297 #define OSCCTRL_OSC48MCTRL_ENABLE (_U_(0x1) << OSCCTRL_OSC48MCTRL_ENABLE_Pos) 298 #define OSCCTRL_OSC48MCTRL_RUNSTDBY_Pos 6 /**< \brief (OSCCTRL_OSC48MCTRL) Run in Standby */ 299 #define OSCCTRL_OSC48MCTRL_RUNSTDBY (_U_(0x1) << OSCCTRL_OSC48MCTRL_RUNSTDBY_Pos) 300 #define OSCCTRL_OSC48MCTRL_ONDEMAND_Pos 7 /**< \brief (OSCCTRL_OSC48MCTRL) On Demand Control */ 301 #define OSCCTRL_OSC48MCTRL_ONDEMAND (_U_(0x1) << OSCCTRL_OSC48MCTRL_ONDEMAND_Pos) 302 #define OSCCTRL_OSC48MCTRL_MASK _U_(0xC2) /**< \brief (OSCCTRL_OSC48MCTRL) MASK Register */ 303 304 /* -------- OSCCTRL_OSC48MDIV : (OSCCTRL Offset: 0x15) (R/W 8) OSC48M Divider -------- */ 305 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 306 typedef union { 307 struct { 308 uint8_t DIV:4; /*!< bit: 0.. 3 OSC48M Division Factor */ 309 uint8_t :4; /*!< bit: 4.. 7 Reserved */ 310 } bit; /*!< Structure used for bit access */ 311 uint8_t reg; /*!< Type used for register access */ 312 } OSCCTRL_OSC48MDIV_Type; 313 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 314 315 #define OSCCTRL_OSC48MDIV_OFFSET 0x15 /**< \brief (OSCCTRL_OSC48MDIV offset) OSC48M Divider */ 316 #define OSCCTRL_OSC48MDIV_RESETVALUE _U_(0x0B) /**< \brief (OSCCTRL_OSC48MDIV reset_value) OSC48M Divider */ 317 318 #define OSCCTRL_OSC48MDIV_DIV_Pos 0 /**< \brief (OSCCTRL_OSC48MDIV) OSC48M Division Factor */ 319 #define OSCCTRL_OSC48MDIV_DIV_Msk (_U_(0xF) << OSCCTRL_OSC48MDIV_DIV_Pos) 320 #define OSCCTRL_OSC48MDIV_DIV(value) (OSCCTRL_OSC48MDIV_DIV_Msk & ((value) << OSCCTRL_OSC48MDIV_DIV_Pos)) 321 #define OSCCTRL_OSC48MDIV_MASK _U_(0x0F) /**< \brief (OSCCTRL_OSC48MDIV) MASK Register */ 322 323 /* -------- OSCCTRL_OSC48MSTUP : (OSCCTRL Offset: 0x16) (R/W 8) OSC48M Startup Time -------- */ 324 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 325 typedef union { 326 struct { 327 uint8_t STARTUP:3; /*!< bit: 0.. 2 Startup Time */ 328 uint8_t :5; /*!< bit: 3.. 7 Reserved */ 329 } bit; /*!< Structure used for bit access */ 330 uint8_t reg; /*!< Type used for register access */ 331 } OSCCTRL_OSC48MSTUP_Type; 332 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 333 334 #define OSCCTRL_OSC48MSTUP_OFFSET 0x16 /**< \brief (OSCCTRL_OSC48MSTUP offset) OSC48M Startup Time */ 335 #define OSCCTRL_OSC48MSTUP_RESETVALUE _U_(0x07) /**< \brief (OSCCTRL_OSC48MSTUP reset_value) OSC48M Startup Time */ 336 337 #define OSCCTRL_OSC48MSTUP_STARTUP_Pos 0 /**< \brief (OSCCTRL_OSC48MSTUP) Startup Time */ 338 #define OSCCTRL_OSC48MSTUP_STARTUP_Msk (_U_(0x7) << OSCCTRL_OSC48MSTUP_STARTUP_Pos) 339 #define OSCCTRL_OSC48MSTUP_STARTUP(value) (OSCCTRL_OSC48MSTUP_STARTUP_Msk & ((value) << OSCCTRL_OSC48MSTUP_STARTUP_Pos)) 340 #define OSCCTRL_OSC48MSTUP_MASK _U_(0x07) /**< \brief (OSCCTRL_OSC48MSTUP) MASK Register */ 341 342 /* -------- OSCCTRL_OSC48MSYNCBUSY : (OSCCTRL Offset: 0x18) (R/ 32) OSC48M Synchronization Busy -------- */ 343 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 344 typedef union { 345 struct { 346 uint32_t :2; /*!< bit: 0.. 1 Reserved */ 347 uint32_t OSC48MDIV:1; /*!< bit: 2 OSC48MDIV Synchronization Status */ 348 uint32_t :29; /*!< bit: 3..31 Reserved */ 349 } bit; /*!< Structure used for bit access */ 350 uint32_t reg; /*!< Type used for register access */ 351 } OSCCTRL_OSC48MSYNCBUSY_Type; 352 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 353 354 #define OSCCTRL_OSC48MSYNCBUSY_OFFSET 0x18 /**< \brief (OSCCTRL_OSC48MSYNCBUSY offset) OSC48M Synchronization Busy */ 355 #define OSCCTRL_OSC48MSYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (OSCCTRL_OSC48MSYNCBUSY reset_value) OSC48M Synchronization Busy */ 356 357 #define OSCCTRL_OSC48MSYNCBUSY_OSC48MDIV_Pos 2 /**< \brief (OSCCTRL_OSC48MSYNCBUSY) OSC48MDIV Synchronization Status */ 358 #define OSCCTRL_OSC48MSYNCBUSY_OSC48MDIV (_U_(0x1) << OSCCTRL_OSC48MSYNCBUSY_OSC48MDIV_Pos) 359 #define OSCCTRL_OSC48MSYNCBUSY_MASK _U_(0x00000004) /**< \brief (OSCCTRL_OSC48MSYNCBUSY) MASK Register */ 360 361 /* -------- OSCCTRL_DPLLCTRLA : (OSCCTRL Offset: 0x1C) (R/W 8) DPLL Control -------- */ 362 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 363 typedef union { 364 struct { 365 uint8_t :1; /*!< bit: 0 Reserved */ 366 uint8_t ENABLE:1; /*!< bit: 1 Enable */ 367 uint8_t :4; /*!< bit: 2.. 5 Reserved */ 368 uint8_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ 369 uint8_t ONDEMAND:1; /*!< bit: 7 On Demand */ 370 } bit; /*!< Structure used for bit access */ 371 uint8_t reg; /*!< Type used for register access */ 372 } OSCCTRL_DPLLCTRLA_Type; 373 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 374 375 #define OSCCTRL_DPLLCTRLA_OFFSET 0x1C /**< \brief (OSCCTRL_DPLLCTRLA offset) DPLL Control */ 376 #define OSCCTRL_DPLLCTRLA_RESETVALUE _U_(0x80) /**< \brief (OSCCTRL_DPLLCTRLA reset_value) DPLL Control */ 377 378 #define OSCCTRL_DPLLCTRLA_ENABLE_Pos 1 /**< \brief (OSCCTRL_DPLLCTRLA) Enable */ 379 #define OSCCTRL_DPLLCTRLA_ENABLE (_U_(0x1) << OSCCTRL_DPLLCTRLA_ENABLE_Pos) 380 #define OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos 6 /**< \brief (OSCCTRL_DPLLCTRLA) Run in Standby */ 381 #define OSCCTRL_DPLLCTRLA_RUNSTDBY (_U_(0x1) << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos) 382 #define OSCCTRL_DPLLCTRLA_ONDEMAND_Pos 7 /**< \brief (OSCCTRL_DPLLCTRLA) On Demand */ 383 #define OSCCTRL_DPLLCTRLA_ONDEMAND (_U_(0x1) << OSCCTRL_DPLLCTRLA_ONDEMAND_Pos) 384 #define OSCCTRL_DPLLCTRLA_MASK _U_(0xC2) /**< \brief (OSCCTRL_DPLLCTRLA) MASK Register */ 385 386 /* -------- OSCCTRL_DPLLRATIO : (OSCCTRL Offset: 0x20) (R/W 32) DPLL Ratio Control -------- */ 387 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 388 typedef union { 389 struct { 390 uint32_t LDR:12; /*!< bit: 0..11 Loop Divider Ratio */ 391 uint32_t :4; /*!< bit: 12..15 Reserved */ 392 uint32_t LDRFRAC:4; /*!< bit: 16..19 Loop Divider Ratio Fractional Part */ 393 uint32_t :12; /*!< bit: 20..31 Reserved */ 394 } bit; /*!< Structure used for bit access */ 395 uint32_t reg; /*!< Type used for register access */ 396 } OSCCTRL_DPLLRATIO_Type; 397 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 398 399 #define OSCCTRL_DPLLRATIO_OFFSET 0x20 /**< \brief (OSCCTRL_DPLLRATIO offset) DPLL Ratio Control */ 400 #define OSCCTRL_DPLLRATIO_RESETVALUE _U_(0x00000000) /**< \brief (OSCCTRL_DPLLRATIO reset_value) DPLL Ratio Control */ 401 402 #define OSCCTRL_DPLLRATIO_LDR_Pos 0 /**< \brief (OSCCTRL_DPLLRATIO) Loop Divider Ratio */ 403 #define OSCCTRL_DPLLRATIO_LDR_Msk (_U_(0xFFF) << OSCCTRL_DPLLRATIO_LDR_Pos) 404 #define OSCCTRL_DPLLRATIO_LDR(value) (OSCCTRL_DPLLRATIO_LDR_Msk & ((value) << OSCCTRL_DPLLRATIO_LDR_Pos)) 405 #define OSCCTRL_DPLLRATIO_LDRFRAC_Pos 16 /**< \brief (OSCCTRL_DPLLRATIO) Loop Divider Ratio Fractional Part */ 406 #define OSCCTRL_DPLLRATIO_LDRFRAC_Msk (_U_(0xF) << OSCCTRL_DPLLRATIO_LDRFRAC_Pos) 407 #define OSCCTRL_DPLLRATIO_LDRFRAC(value) (OSCCTRL_DPLLRATIO_LDRFRAC_Msk & ((value) << OSCCTRL_DPLLRATIO_LDRFRAC_Pos)) 408 #define OSCCTRL_DPLLRATIO_MASK _U_(0x000F0FFF) /**< \brief (OSCCTRL_DPLLRATIO) MASK Register */ 409 410 /* -------- OSCCTRL_DPLLCTRLB : (OSCCTRL Offset: 0x24) (R/W 32) Digital Core Configuration -------- */ 411 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 412 typedef union { 413 struct { 414 uint32_t FILTER:2; /*!< bit: 0.. 1 Proportional Integral Filter Selection */ 415 uint32_t LPEN:1; /*!< bit: 2 Low-Power Enable */ 416 uint32_t WUF:1; /*!< bit: 3 Wake Up Fast */ 417 uint32_t REFCLK:2; /*!< bit: 4.. 5 Reference Clock Selection */ 418 uint32_t :2; /*!< bit: 6.. 7 Reserved */ 419 uint32_t LTIME:3; /*!< bit: 8..10 Lock Time */ 420 uint32_t :1; /*!< bit: 11 Reserved */ 421 uint32_t LBYPASS:1; /*!< bit: 12 Lock Bypass */ 422 uint32_t :3; /*!< bit: 13..15 Reserved */ 423 uint32_t DIV:11; /*!< bit: 16..26 Clock Divider */ 424 uint32_t :5; /*!< bit: 27..31 Reserved */ 425 } bit; /*!< Structure used for bit access */ 426 uint32_t reg; /*!< Type used for register access */ 427 } OSCCTRL_DPLLCTRLB_Type; 428 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 429 430 #define OSCCTRL_DPLLCTRLB_OFFSET 0x24 /**< \brief (OSCCTRL_DPLLCTRLB offset) Digital Core Configuration */ 431 #define OSCCTRL_DPLLCTRLB_RESETVALUE _U_(0x00000000) /**< \brief (OSCCTRL_DPLLCTRLB reset_value) Digital Core Configuration */ 432 433 #define OSCCTRL_DPLLCTRLB_FILTER_Pos 0 /**< \brief (OSCCTRL_DPLLCTRLB) Proportional Integral Filter Selection */ 434 #define OSCCTRL_DPLLCTRLB_FILTER_Msk (_U_(0x3) << OSCCTRL_DPLLCTRLB_FILTER_Pos) 435 #define OSCCTRL_DPLLCTRLB_FILTER(value) (OSCCTRL_DPLLCTRLB_FILTER_Msk & ((value) << OSCCTRL_DPLLCTRLB_FILTER_Pos)) 436 #define OSCCTRL_DPLLCTRLB_LPEN_Pos 2 /**< \brief (OSCCTRL_DPLLCTRLB) Low-Power Enable */ 437 #define OSCCTRL_DPLLCTRLB_LPEN (_U_(0x1) << OSCCTRL_DPLLCTRLB_LPEN_Pos) 438 #define OSCCTRL_DPLLCTRLB_WUF_Pos 3 /**< \brief (OSCCTRL_DPLLCTRLB) Wake Up Fast */ 439 #define OSCCTRL_DPLLCTRLB_WUF (_U_(0x1) << OSCCTRL_DPLLCTRLB_WUF_Pos) 440 #define OSCCTRL_DPLLCTRLB_REFCLK_Pos 4 /**< \brief (OSCCTRL_DPLLCTRLB) Reference Clock Selection */ 441 #define OSCCTRL_DPLLCTRLB_REFCLK_Msk (_U_(0x3) << OSCCTRL_DPLLCTRLB_REFCLK_Pos) 442 #define OSCCTRL_DPLLCTRLB_REFCLK(value) (OSCCTRL_DPLLCTRLB_REFCLK_Msk & ((value) << OSCCTRL_DPLLCTRLB_REFCLK_Pos)) 443 #define OSCCTRL_DPLLCTRLB_LTIME_Pos 8 /**< \brief (OSCCTRL_DPLLCTRLB) Lock Time */ 444 #define OSCCTRL_DPLLCTRLB_LTIME_Msk (_U_(0x7) << OSCCTRL_DPLLCTRLB_LTIME_Pos) 445 #define OSCCTRL_DPLLCTRLB_LTIME(value) (OSCCTRL_DPLLCTRLB_LTIME_Msk & ((value) << OSCCTRL_DPLLCTRLB_LTIME_Pos)) 446 #define OSCCTRL_DPLLCTRLB_LBYPASS_Pos 12 /**< \brief (OSCCTRL_DPLLCTRLB) Lock Bypass */ 447 #define OSCCTRL_DPLLCTRLB_LBYPASS (_U_(0x1) << OSCCTRL_DPLLCTRLB_LBYPASS_Pos) 448 #define OSCCTRL_DPLLCTRLB_DIV_Pos 16 /**< \brief (OSCCTRL_DPLLCTRLB) Clock Divider */ 449 #define OSCCTRL_DPLLCTRLB_DIV_Msk (_U_(0x7FF) << OSCCTRL_DPLLCTRLB_DIV_Pos) 450 #define OSCCTRL_DPLLCTRLB_DIV(value) (OSCCTRL_DPLLCTRLB_DIV_Msk & ((value) << OSCCTRL_DPLLCTRLB_DIV_Pos)) 451 #define OSCCTRL_DPLLCTRLB_MASK _U_(0x07FF173F) /**< \brief (OSCCTRL_DPLLCTRLB) MASK Register */ 452 453 /* -------- OSCCTRL_DPLLPRESC : (OSCCTRL Offset: 0x28) (R/W 8) DPLL Prescaler -------- */ 454 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 455 typedef union { 456 struct { 457 uint8_t PRESC:2; /*!< bit: 0.. 1 Output Clock Prescaler */ 458 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 459 } bit; /*!< Structure used for bit access */ 460 uint8_t reg; /*!< Type used for register access */ 461 } OSCCTRL_DPLLPRESC_Type; 462 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 463 464 #define OSCCTRL_DPLLPRESC_OFFSET 0x28 /**< \brief (OSCCTRL_DPLLPRESC offset) DPLL Prescaler */ 465 #define OSCCTRL_DPLLPRESC_RESETVALUE _U_(0x00) /**< \brief (OSCCTRL_DPLLPRESC reset_value) DPLL Prescaler */ 466 467 #define OSCCTRL_DPLLPRESC_PRESC_Pos 0 /**< \brief (OSCCTRL_DPLLPRESC) Output Clock Prescaler */ 468 #define OSCCTRL_DPLLPRESC_PRESC_Msk (_U_(0x3) << OSCCTRL_DPLLPRESC_PRESC_Pos) 469 #define OSCCTRL_DPLLPRESC_PRESC(value) (OSCCTRL_DPLLPRESC_PRESC_Msk & ((value) << OSCCTRL_DPLLPRESC_PRESC_Pos)) 470 #define OSCCTRL_DPLLPRESC_PRESC_DIV1_Val _U_(0x0) /**< \brief (OSCCTRL_DPLLPRESC) DPLL output is divided by 1 */ 471 #define OSCCTRL_DPLLPRESC_PRESC_DIV2_Val _U_(0x1) /**< \brief (OSCCTRL_DPLLPRESC) DPLL output is divided by 2 */ 472 #define OSCCTRL_DPLLPRESC_PRESC_DIV4_Val _U_(0x2) /**< \brief (OSCCTRL_DPLLPRESC) DPLL output is divided by 4 */ 473 #define OSCCTRL_DPLLPRESC_PRESC_DIV1 (OSCCTRL_DPLLPRESC_PRESC_DIV1_Val << OSCCTRL_DPLLPRESC_PRESC_Pos) 474 #define OSCCTRL_DPLLPRESC_PRESC_DIV2 (OSCCTRL_DPLLPRESC_PRESC_DIV2_Val << OSCCTRL_DPLLPRESC_PRESC_Pos) 475 #define OSCCTRL_DPLLPRESC_PRESC_DIV4 (OSCCTRL_DPLLPRESC_PRESC_DIV4_Val << OSCCTRL_DPLLPRESC_PRESC_Pos) 476 #define OSCCTRL_DPLLPRESC_MASK _U_(0x03) /**< \brief (OSCCTRL_DPLLPRESC) MASK Register */ 477 478 /* -------- OSCCTRL_DPLLSYNCBUSY : (OSCCTRL Offset: 0x2C) (R/ 8) DPLL Synchronization Busy -------- */ 479 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 480 typedef union { 481 struct { 482 uint8_t :1; /*!< bit: 0 Reserved */ 483 uint8_t ENABLE:1; /*!< bit: 1 DPLL Enable Synchronization Status */ 484 uint8_t DPLLRATIO:1; /*!< bit: 2 DPLL Ratio Synchronization Status */ 485 uint8_t DPLLPRESC:1; /*!< bit: 3 DPLL Prescaler Synchronization Status */ 486 uint8_t :4; /*!< bit: 4.. 7 Reserved */ 487 } bit; /*!< Structure used for bit access */ 488 uint8_t reg; /*!< Type used for register access */ 489 } OSCCTRL_DPLLSYNCBUSY_Type; 490 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 491 492 #define OSCCTRL_DPLLSYNCBUSY_OFFSET 0x2C /**< \brief (OSCCTRL_DPLLSYNCBUSY offset) DPLL Synchronization Busy */ 493 #define OSCCTRL_DPLLSYNCBUSY_RESETVALUE _U_(0x00) /**< \brief (OSCCTRL_DPLLSYNCBUSY reset_value) DPLL Synchronization Busy */ 494 495 #define OSCCTRL_DPLLSYNCBUSY_ENABLE_Pos 1 /**< \brief (OSCCTRL_DPLLSYNCBUSY) DPLL Enable Synchronization Status */ 496 #define OSCCTRL_DPLLSYNCBUSY_ENABLE (_U_(0x1) << OSCCTRL_DPLLSYNCBUSY_ENABLE_Pos) 497 #define OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Pos 2 /**< \brief (OSCCTRL_DPLLSYNCBUSY) DPLL Ratio Synchronization Status */ 498 #define OSCCTRL_DPLLSYNCBUSY_DPLLRATIO (_U_(0x1) << OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Pos) 499 #define OSCCTRL_DPLLSYNCBUSY_DPLLPRESC_Pos 3 /**< \brief (OSCCTRL_DPLLSYNCBUSY) DPLL Prescaler Synchronization Status */ 500 #define OSCCTRL_DPLLSYNCBUSY_DPLLPRESC (_U_(0x1) << OSCCTRL_DPLLSYNCBUSY_DPLLPRESC_Pos) 501 #define OSCCTRL_DPLLSYNCBUSY_MASK _U_(0x0E) /**< \brief (OSCCTRL_DPLLSYNCBUSY) MASK Register */ 502 503 /* -------- OSCCTRL_DPLLSTATUS : (OSCCTRL Offset: 0x30) (R/ 8) DPLL Status -------- */ 504 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 505 typedef union { 506 struct { 507 uint8_t LOCK:1; /*!< bit: 0 DPLL Lock Status */ 508 uint8_t CLKRDY:1; /*!< bit: 1 DPLL Clock Ready */ 509 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 510 } bit; /*!< Structure used for bit access */ 511 uint8_t reg; /*!< Type used for register access */ 512 } OSCCTRL_DPLLSTATUS_Type; 513 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 514 515 #define OSCCTRL_DPLLSTATUS_OFFSET 0x30 /**< \brief (OSCCTRL_DPLLSTATUS offset) DPLL Status */ 516 #define OSCCTRL_DPLLSTATUS_RESETVALUE _U_(0x00) /**< \brief (OSCCTRL_DPLLSTATUS reset_value) DPLL Status */ 517 518 #define OSCCTRL_DPLLSTATUS_LOCK_Pos 0 /**< \brief (OSCCTRL_DPLLSTATUS) DPLL Lock Status */ 519 #define OSCCTRL_DPLLSTATUS_LOCK (_U_(0x1) << OSCCTRL_DPLLSTATUS_LOCK_Pos) 520 #define OSCCTRL_DPLLSTATUS_CLKRDY_Pos 1 /**< \brief (OSCCTRL_DPLLSTATUS) DPLL Clock Ready */ 521 #define OSCCTRL_DPLLSTATUS_CLKRDY (_U_(0x1) << OSCCTRL_DPLLSTATUS_CLKRDY_Pos) 522 #define OSCCTRL_DPLLSTATUS_MASK _U_(0x03) /**< \brief (OSCCTRL_DPLLSTATUS) MASK Register */ 523 524 /* -------- OSCCTRL_CAL48M : (OSCCTRL Offset: 0x38) (R/W 32) 48MHz Oscillator Calibration -------- */ 525 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 526 typedef union { 527 struct { 528 uint32_t FCAL:6; /*!< bit: 0.. 5 Frequency Calibration (48MHz) */ 529 uint32_t :2; /*!< bit: 6.. 7 Reserved */ 530 uint32_t FRANGE:2; /*!< bit: 8.. 9 Frequency Range (48MHz) */ 531 uint32_t :6; /*!< bit: 10..15 Reserved */ 532 uint32_t TCAL:6; /*!< bit: 16..21 Temperature Calibration (48MHz) */ 533 uint32_t :10; /*!< bit: 22..31 Reserved */ 534 } bit; /*!< Structure used for bit access */ 535 uint32_t reg; /*!< Type used for register access */ 536 } OSCCTRL_CAL48M_Type; 537 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 538 539 #define OSCCTRL_CAL48M_OFFSET 0x38 /**< \brief (OSCCTRL_CAL48M offset) 48MHz Oscillator Calibration */ 540 #define OSCCTRL_CAL48M_RESETVALUE _U_(0x00000000) /**< \brief (OSCCTRL_CAL48M reset_value) 48MHz Oscillator Calibration */ 541 542 #define OSCCTRL_CAL48M_FCAL_Pos 0 /**< \brief (OSCCTRL_CAL48M) Frequency Calibration (48MHz) */ 543 #define OSCCTRL_CAL48M_FCAL_Msk (_U_(0x3F) << OSCCTRL_CAL48M_FCAL_Pos) 544 #define OSCCTRL_CAL48M_FCAL(value) (OSCCTRL_CAL48M_FCAL_Msk & ((value) << OSCCTRL_CAL48M_FCAL_Pos)) 545 #define OSCCTRL_CAL48M_FRANGE_Pos 8 /**< \brief (OSCCTRL_CAL48M) Frequency Range (48MHz) */ 546 #define OSCCTRL_CAL48M_FRANGE_Msk (_U_(0x3) << OSCCTRL_CAL48M_FRANGE_Pos) 547 #define OSCCTRL_CAL48M_FRANGE(value) (OSCCTRL_CAL48M_FRANGE_Msk & ((value) << OSCCTRL_CAL48M_FRANGE_Pos)) 548 #define OSCCTRL_CAL48M_TCAL_Pos 16 /**< \brief (OSCCTRL_CAL48M) Temperature Calibration (48MHz) */ 549 #define OSCCTRL_CAL48M_TCAL_Msk (_U_(0x3F) << OSCCTRL_CAL48M_TCAL_Pos) 550 #define OSCCTRL_CAL48M_TCAL(value) (OSCCTRL_CAL48M_TCAL_Msk & ((value) << OSCCTRL_CAL48M_TCAL_Pos)) 551 #define OSCCTRL_CAL48M_MASK _U_(0x003F033F) /**< \brief (OSCCTRL_CAL48M) MASK Register */ 552 553 /** \brief OSCCTRL hardware registers */ 554 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 555 typedef struct { 556 __IO OSCCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x00 (R/W 32) Interrupt Enable Clear */ 557 __IO OSCCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x04 (R/W 32) Interrupt Enable Set */ 558 __IO OSCCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 32) Interrupt Flag Status and Clear */ 559 __I OSCCTRL_STATUS_Type STATUS; /**< \brief Offset: 0x0C (R/ 32) Power and Clocks Status */ 560 __IO OSCCTRL_XOSCCTRL_Type XOSCCTRL; /**< \brief Offset: 0x10 (R/W 16) External Multipurpose Crystal Oscillator (XOSC) Control */ 561 __IO OSCCTRL_CFDPRESC_Type CFDPRESC; /**< \brief Offset: 0x12 (R/W 8) Clock Failure Detector Prescaler */ 562 __IO OSCCTRL_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x13 (R/W 8) Event Control */ 563 __IO OSCCTRL_OSC48MCTRL_Type OSC48MCTRL; /**< \brief Offset: 0x14 (R/W 8) 48MHz Internal Oscillator (OSC48M) Control */ 564 __IO OSCCTRL_OSC48MDIV_Type OSC48MDIV; /**< \brief Offset: 0x15 (R/W 8) OSC48M Divider */ 565 __IO OSCCTRL_OSC48MSTUP_Type OSC48MSTUP; /**< \brief Offset: 0x16 (R/W 8) OSC48M Startup Time */ 566 RoReg8 Reserved1[0x1]; 567 __I OSCCTRL_OSC48MSYNCBUSY_Type OSC48MSYNCBUSY; /**< \brief Offset: 0x18 (R/ 32) OSC48M Synchronization Busy */ 568 __IO OSCCTRL_DPLLCTRLA_Type DPLLCTRLA; /**< \brief Offset: 0x1C (R/W 8) DPLL Control */ 569 RoReg8 Reserved2[0x3]; 570 __IO OSCCTRL_DPLLRATIO_Type DPLLRATIO; /**< \brief Offset: 0x20 (R/W 32) DPLL Ratio Control */ 571 __IO OSCCTRL_DPLLCTRLB_Type DPLLCTRLB; /**< \brief Offset: 0x24 (R/W 32) Digital Core Configuration */ 572 __IO OSCCTRL_DPLLPRESC_Type DPLLPRESC; /**< \brief Offset: 0x28 (R/W 8) DPLL Prescaler */ 573 RoReg8 Reserved3[0x3]; 574 __I OSCCTRL_DPLLSYNCBUSY_Type DPLLSYNCBUSY; /**< \brief Offset: 0x2C (R/ 8) DPLL Synchronization Busy */ 575 RoReg8 Reserved4[0x3]; 576 __I OSCCTRL_DPLLSTATUS_Type DPLLSTATUS; /**< \brief Offset: 0x30 (R/ 8) DPLL Status */ 577 RoReg8 Reserved5[0x7]; 578 __IO OSCCTRL_CAL48M_Type CAL48M; /**< \brief Offset: 0x38 (R/W 32) 48MHz Oscillator Calibration */ 579 } Oscctrl; 580 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 581 582 /*@}*/ 583 584 #endif /* _SAMC20_OSCCTRL_COMPONENT_ */ 585
