1 /** 2 * \file 3 * 4 * \brief Instance description for ACC 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \license_stop 27 * 28 */ 29 30 /* file generated from device description version 2019-01-18T21:21:15Z */ 31 #ifndef _SAMV71_ACC_INSTANCE_H_ 32 #define _SAMV71_ACC_INSTANCE_H_ 33 34 /* ========== Register definition for ACC peripheral ========== */ 35 #if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 36 37 #define REG_ACC_CR (0x40044000) /**< (ACC) Control Register */ 38 #define REG_ACC_MR (0x40044004) /**< (ACC) Mode Register */ 39 #define REG_ACC_IER (0x40044024) /**< (ACC) Interrupt Enable Register */ 40 #define REG_ACC_IDR (0x40044028) /**< (ACC) Interrupt Disable Register */ 41 #define REG_ACC_IMR (0x4004402C) /**< (ACC) Interrupt Mask Register */ 42 #define REG_ACC_ISR (0x40044030) /**< (ACC) Interrupt Status Register */ 43 #define REG_ACC_ACR (0x40044094) /**< (ACC) Analog Control Register */ 44 #define REG_ACC_WPMR (0x400440E4) /**< (ACC) Write Protection Mode Register */ 45 #define REG_ACC_WPSR (0x400440E8) /**< (ACC) Write Protection Status Register */ 46 47 #else 48 49 #define REG_ACC_CR (*(__O uint32_t*)0x40044000U) /**< (ACC) Control Register */ 50 #define REG_ACC_MR (*(__IO uint32_t*)0x40044004U) /**< (ACC) Mode Register */ 51 #define REG_ACC_IER (*(__O uint32_t*)0x40044024U) /**< (ACC) Interrupt Enable Register */ 52 #define REG_ACC_IDR (*(__O uint32_t*)0x40044028U) /**< (ACC) Interrupt Disable Register */ 53 #define REG_ACC_IMR (*(__I uint32_t*)0x4004402CU) /**< (ACC) Interrupt Mask Register */ 54 #define REG_ACC_ISR (*(__I uint32_t*)0x40044030U) /**< (ACC) Interrupt Status Register */ 55 #define REG_ACC_ACR (*(__IO uint32_t*)0x40044094U) /**< (ACC) Analog Control Register */ 56 #define REG_ACC_WPMR (*(__IO uint32_t*)0x400440E4U) /**< (ACC) Write Protection Mode Register */ 57 #define REG_ACC_WPSR (*(__I uint32_t*)0x400440E8U) /**< (ACC) Write Protection Status Register */ 58 59 #endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 60 61 /* ========== Instance Parameter definitions for ACC peripheral ========== */ 62 #define ACC_INSTANCE_ID 33 63 #define ACC_CLOCK_ID 33 64 #define ACC_HAS_PLUS_COMPARATOR_SELECTION 1 65 #define ACC_HAS_MINUS_COMPARATOR_SELECTION 1 66 #define ACC_HAS_INVERTED_COMPARATOR 1 67 #define ACC_HAS_EDGETYPE_SELECTION 1 68 #define ACC_HAS_INTERRUPTS 1 69 #define ACC_HAS_CURRENT_SELECTION 1 70 #define ACC_HAS_HYSTERESIS 1 71 #define ACC_HAS_FAULT_ENABLE 1 72 73 #endif /* _SAMV71_ACC_INSTANCE_ */ 74
