1 /** 2 * \file 3 * 4 * \brief Component description for MATRIX 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \license_stop 27 * 28 */ 29 30 /* file generated from device description version 2019-01-18T21:21:15Z */ 31 #ifndef _SAMV71_MATRIX_COMPONENT_H_ 32 #define _SAMV71_MATRIX_COMPONENT_H_ 33 #define _SAMV71_MATRIX_COMPONENT_ /**< \deprecated Backward compatibility for ASF */ 34 35 /** \addtogroup SAMV_SAMV71 AHB Bus Matrix 36 * @{ 37 */ 38 /* ========================================================================== */ 39 /** SOFTWARE API DEFINITION FOR MATRIX */ 40 /* ========================================================================== */ 41 #ifndef COMPONENT_TYPEDEF_STYLE 42 #define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/ 43 #endif 44 45 #define MATRIX_11282 /**< (MATRIX) Module ID */ 46 #define REV_MATRIX L /**< (MATRIX) Module revision */ 47 48 /* -------- MATRIX_PRAS : (MATRIX Offset: 0x00) (R/W 32) Priority Register A for Slave 0 -------- */ 49 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 50 #if COMPONENT_TYPEDEF_STYLE == 'N' 51 typedef union { 52 struct { 53 uint32_t M0PR:2; /**< bit: 0..1 Master 0 Priority */ 54 uint32_t :2; /**< bit: 2..3 Reserved */ 55 uint32_t M1PR:2; /**< bit: 4..5 Master 1 Priority */ 56 uint32_t :2; /**< bit: 6..7 Reserved */ 57 uint32_t M2PR:2; /**< bit: 8..9 Master 2 Priority */ 58 uint32_t :2; /**< bit: 10..11 Reserved */ 59 uint32_t M3PR:2; /**< bit: 12..13 Master 3 Priority */ 60 uint32_t :2; /**< bit: 14..15 Reserved */ 61 uint32_t M4PR:2; /**< bit: 16..17 Master 4 Priority */ 62 uint32_t :2; /**< bit: 18..19 Reserved */ 63 uint32_t M5PR:2; /**< bit: 20..21 Master 5 Priority */ 64 uint32_t :2; /**< bit: 22..23 Reserved */ 65 uint32_t M6PR:2; /**< bit: 24..25 Master 6 Priority */ 66 uint32_t :2; /**< bit: 26..27 Reserved */ 67 uint32_t M7PR:2; /**< bit: 28..29 Master 7 Priority */ 68 uint32_t :2; /**< bit: 30..31 Reserved */ 69 } bit; /**< Structure used for bit access */ 70 uint32_t reg; /**< Type used for register access */ 71 } MATRIX_PRAS_Type; 72 #endif 73 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 74 75 #define MATRIX_PRAS_OFFSET (0x00) /**< (MATRIX_PRAS) Priority Register A for Slave 0 Offset */ 76 77 #define MATRIX_PRAS_M0PR_Pos 0 /**< (MATRIX_PRAS) Master 0 Priority Position */ 78 #define MATRIX_PRAS_M0PR_Msk (_U_(0x3) << MATRIX_PRAS_M0PR_Pos) /**< (MATRIX_PRAS) Master 0 Priority Mask */ 79 #define MATRIX_PRAS_M0PR(value) (MATRIX_PRAS_M0PR_Msk & ((value) << MATRIX_PRAS_M0PR_Pos)) 80 #define MATRIX_PRAS_M1PR_Pos 4 /**< (MATRIX_PRAS) Master 1 Priority Position */ 81 #define MATRIX_PRAS_M1PR_Msk (_U_(0x3) << MATRIX_PRAS_M1PR_Pos) /**< (MATRIX_PRAS) Master 1 Priority Mask */ 82 #define MATRIX_PRAS_M1PR(value) (MATRIX_PRAS_M1PR_Msk & ((value) << MATRIX_PRAS_M1PR_Pos)) 83 #define MATRIX_PRAS_M2PR_Pos 8 /**< (MATRIX_PRAS) Master 2 Priority Position */ 84 #define MATRIX_PRAS_M2PR_Msk (_U_(0x3) << MATRIX_PRAS_M2PR_Pos) /**< (MATRIX_PRAS) Master 2 Priority Mask */ 85 #define MATRIX_PRAS_M2PR(value) (MATRIX_PRAS_M2PR_Msk & ((value) << MATRIX_PRAS_M2PR_Pos)) 86 #define MATRIX_PRAS_M3PR_Pos 12 /**< (MATRIX_PRAS) Master 3 Priority Position */ 87 #define MATRIX_PRAS_M3PR_Msk (_U_(0x3) << MATRIX_PRAS_M3PR_Pos) /**< (MATRIX_PRAS) Master 3 Priority Mask */ 88 #define MATRIX_PRAS_M3PR(value) (MATRIX_PRAS_M3PR_Msk & ((value) << MATRIX_PRAS_M3PR_Pos)) 89 #define MATRIX_PRAS_M4PR_Pos 16 /**< (MATRIX_PRAS) Master 4 Priority Position */ 90 #define MATRIX_PRAS_M4PR_Msk (_U_(0x3) << MATRIX_PRAS_M4PR_Pos) /**< (MATRIX_PRAS) Master 4 Priority Mask */ 91 #define MATRIX_PRAS_M4PR(value) (MATRIX_PRAS_M4PR_Msk & ((value) << MATRIX_PRAS_M4PR_Pos)) 92 #define MATRIX_PRAS_M5PR_Pos 20 /**< (MATRIX_PRAS) Master 5 Priority Position */ 93 #define MATRIX_PRAS_M5PR_Msk (_U_(0x3) << MATRIX_PRAS_M5PR_Pos) /**< (MATRIX_PRAS) Master 5 Priority Mask */ 94 #define MATRIX_PRAS_M5PR(value) (MATRIX_PRAS_M5PR_Msk & ((value) << MATRIX_PRAS_M5PR_Pos)) 95 #define MATRIX_PRAS_M6PR_Pos 24 /**< (MATRIX_PRAS) Master 6 Priority Position */ 96 #define MATRIX_PRAS_M6PR_Msk (_U_(0x3) << MATRIX_PRAS_M6PR_Pos) /**< (MATRIX_PRAS) Master 6 Priority Mask */ 97 #define MATRIX_PRAS_M6PR(value) (MATRIX_PRAS_M6PR_Msk & ((value) << MATRIX_PRAS_M6PR_Pos)) 98 #define MATRIX_PRAS_M7PR_Pos 28 /**< (MATRIX_PRAS) Master 7 Priority Position */ 99 #define MATRIX_PRAS_M7PR_Msk (_U_(0x3) << MATRIX_PRAS_M7PR_Pos) /**< (MATRIX_PRAS) Master 7 Priority Mask */ 100 #define MATRIX_PRAS_M7PR(value) (MATRIX_PRAS_M7PR_Msk & ((value) << MATRIX_PRAS_M7PR_Pos)) 101 #define MATRIX_PRAS_MASK _U_(0x33333333) /**< \deprecated (MATRIX_PRAS) Register MASK (Use MATRIX_PRAS_Msk instead) */ 102 #define MATRIX_PRAS_Msk _U_(0x33333333) /**< (MATRIX_PRAS) Register Mask */ 103 104 105 /* -------- MATRIX_PRBS : (MATRIX Offset: 0x04) (R/W 32) Priority Register B for Slave 0 -------- */ 106 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 107 #if COMPONENT_TYPEDEF_STYLE == 'N' 108 typedef union { 109 struct { 110 uint32_t M8PR:2; /**< bit: 0..1 Master 8 Priority */ 111 uint32_t :2; /**< bit: 2..3 Reserved */ 112 uint32_t M9PR:2; /**< bit: 4..5 Master 9 Priority */ 113 uint32_t :2; /**< bit: 6..7 Reserved */ 114 uint32_t M10PR:2; /**< bit: 8..9 Master 10 Priority */ 115 uint32_t :2; /**< bit: 10..11 Reserved */ 116 uint32_t M11PR:2; /**< bit: 12..13 Master 11 Priority */ 117 uint32_t :2; /**< bit: 14..15 Reserved */ 118 uint32_t M12PR:2; /**< bit: 16..17 Master 12 Priority */ 119 uint32_t :14; /**< bit: 18..31 Reserved */ 120 } bit; /**< Structure used for bit access */ 121 uint32_t reg; /**< Type used for register access */ 122 } MATRIX_PRBS_Type; 123 #endif 124 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 125 126 #define MATRIX_PRBS_OFFSET (0x04) /**< (MATRIX_PRBS) Priority Register B for Slave 0 Offset */ 127 128 #define MATRIX_PRBS_M8PR_Pos 0 /**< (MATRIX_PRBS) Master 8 Priority Position */ 129 #define MATRIX_PRBS_M8PR_Msk (_U_(0x3) << MATRIX_PRBS_M8PR_Pos) /**< (MATRIX_PRBS) Master 8 Priority Mask */ 130 #define MATRIX_PRBS_M8PR(value) (MATRIX_PRBS_M8PR_Msk & ((value) << MATRIX_PRBS_M8PR_Pos)) 131 #define MATRIX_PRBS_M9PR_Pos 4 /**< (MATRIX_PRBS) Master 9 Priority Position */ 132 #define MATRIX_PRBS_M9PR_Msk (_U_(0x3) << MATRIX_PRBS_M9PR_Pos) /**< (MATRIX_PRBS) Master 9 Priority Mask */ 133 #define MATRIX_PRBS_M9PR(value) (MATRIX_PRBS_M9PR_Msk & ((value) << MATRIX_PRBS_M9PR_Pos)) 134 #define MATRIX_PRBS_M10PR_Pos 8 /**< (MATRIX_PRBS) Master 10 Priority Position */ 135 #define MATRIX_PRBS_M10PR_Msk (_U_(0x3) << MATRIX_PRBS_M10PR_Pos) /**< (MATRIX_PRBS) Master 10 Priority Mask */ 136 #define MATRIX_PRBS_M10PR(value) (MATRIX_PRBS_M10PR_Msk & ((value) << MATRIX_PRBS_M10PR_Pos)) 137 #define MATRIX_PRBS_M11PR_Pos 12 /**< (MATRIX_PRBS) Master 11 Priority Position */ 138 #define MATRIX_PRBS_M11PR_Msk (_U_(0x3) << MATRIX_PRBS_M11PR_Pos) /**< (MATRIX_PRBS) Master 11 Priority Mask */ 139 #define MATRIX_PRBS_M11PR(value) (MATRIX_PRBS_M11PR_Msk & ((value) << MATRIX_PRBS_M11PR_Pos)) 140 #define MATRIX_PRBS_M12PR_Pos 16 /**< (MATRIX_PRBS) Master 12 Priority Position */ 141 #define MATRIX_PRBS_M12PR_Msk (_U_(0x3) << MATRIX_PRBS_M12PR_Pos) /**< (MATRIX_PRBS) Master 12 Priority Mask */ 142 #define MATRIX_PRBS_M12PR(value) (MATRIX_PRBS_M12PR_Msk & ((value) << MATRIX_PRBS_M12PR_Pos)) 143 #define MATRIX_PRBS_MASK _U_(0x33333) /**< \deprecated (MATRIX_PRBS) Register MASK (Use MATRIX_PRBS_Msk instead) */ 144 #define MATRIX_PRBS_Msk _U_(0x33333) /**< (MATRIX_PRBS) Register Mask */ 145 146 147 /* -------- MATRIX_MCFG : (MATRIX Offset: 0x00) (R/W 32) Master Configuration Register 0 -------- */ 148 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 149 #if COMPONENT_TYPEDEF_STYLE == 'N' 150 typedef union { 151 struct { 152 uint32_t ULBT:3; /**< bit: 0..2 Undefined Length Burst Type */ 153 uint32_t :29; /**< bit: 3..31 Reserved */ 154 } bit; /**< Structure used for bit access */ 155 uint32_t reg; /**< Type used for register access */ 156 } MATRIX_MCFG_Type; 157 #endif 158 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 159 160 #define MATRIX_MCFG_OFFSET (0x00) /**< (MATRIX_MCFG) Master Configuration Register 0 Offset */ 161 162 #define MATRIX_MCFG_ULBT_Pos 0 /**< (MATRIX_MCFG) Undefined Length Burst Type Position */ 163 #define MATRIX_MCFG_ULBT_Msk (_U_(0x7) << MATRIX_MCFG_ULBT_Pos) /**< (MATRIX_MCFG) Undefined Length Burst Type Mask */ 164 #define MATRIX_MCFG_ULBT(value) (MATRIX_MCFG_ULBT_Msk & ((value) << MATRIX_MCFG_ULBT_Pos)) 165 #define MATRIX_MCFG_ULBT_UNLTD_LENGTH_Val _U_(0x0) /**< (MATRIX_MCFG) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */ 166 #define MATRIX_MCFG_ULBT_SINGLE_ACCESS_Val _U_(0x1) /**< (MATRIX_MCFG) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */ 167 #define MATRIX_MCFG_ULBT_4BEAT_BURST_Val _U_(0x2) /**< (MATRIX_MCFG) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */ 168 #define MATRIX_MCFG_ULBT_8BEAT_BURST_Val _U_(0x3) /**< (MATRIX_MCFG) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */ 169 #define MATRIX_MCFG_ULBT_16BEAT_BURST_Val _U_(0x4) /**< (MATRIX_MCFG) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */ 170 #define MATRIX_MCFG_ULBT_32BEAT_BURST_Val _U_(0x5) /**< (MATRIX_MCFG) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */ 171 #define MATRIX_MCFG_ULBT_64BEAT_BURST_Val _U_(0x6) /**< (MATRIX_MCFG) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */ 172 #define MATRIX_MCFG_ULBT_128BEAT_BURST_Val _U_(0x7) /**< (MATRIX_MCFG) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. */ 173 #define MATRIX_MCFG_ULBT_UNLTD_LENGTH (MATRIX_MCFG_ULBT_UNLTD_LENGTH_Val << MATRIX_MCFG_ULBT_Pos) /**< (MATRIX_MCFG) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. Position */ 174 #define MATRIX_MCFG_ULBT_SINGLE_ACCESS (MATRIX_MCFG_ULBT_SINGLE_ACCESS_Val << MATRIX_MCFG_ULBT_Pos) /**< (MATRIX_MCFG) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. Position */ 175 #define MATRIX_MCFG_ULBT_4BEAT_BURST (MATRIX_MCFG_ULBT_4BEAT_BURST_Val << MATRIX_MCFG_ULBT_Pos) /**< (MATRIX_MCFG) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. Position */ 176 #define MATRIX_MCFG_ULBT_8BEAT_BURST (MATRIX_MCFG_ULBT_8BEAT_BURST_Val << MATRIX_MCFG_ULBT_Pos) /**< (MATRIX_MCFG) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. Position */ 177 #define MATRIX_MCFG_ULBT_16BEAT_BURST (MATRIX_MCFG_ULBT_16BEAT_BURST_Val << MATRIX_MCFG_ULBT_Pos) /**< (MATRIX_MCFG) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. Position */ 178 #define MATRIX_MCFG_ULBT_32BEAT_BURST (MATRIX_MCFG_ULBT_32BEAT_BURST_Val << MATRIX_MCFG_ULBT_Pos) /**< (MATRIX_MCFG) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. Position */ 179 #define MATRIX_MCFG_ULBT_64BEAT_BURST (MATRIX_MCFG_ULBT_64BEAT_BURST_Val << MATRIX_MCFG_ULBT_Pos) /**< (MATRIX_MCFG) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. Position */ 180 #define MATRIX_MCFG_ULBT_128BEAT_BURST (MATRIX_MCFG_ULBT_128BEAT_BURST_Val << MATRIX_MCFG_ULBT_Pos) /**< (MATRIX_MCFG) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. Position */ 181 #define MATRIX_MCFG_MASK _U_(0x07) /**< \deprecated (MATRIX_MCFG) Register MASK (Use MATRIX_MCFG_Msk instead) */ 182 #define MATRIX_MCFG_Msk _U_(0x07) /**< (MATRIX_MCFG) Register Mask */ 183 184 185 /* -------- MATRIX_SCFG : (MATRIX Offset: 0x40) (R/W 32) Slave Configuration Register 0 -------- */ 186 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 187 #if COMPONENT_TYPEDEF_STYLE == 'N' 188 typedef union { 189 struct { 190 uint32_t SLOT_CYCLE:9; /**< bit: 0..8 Maximum Bus Grant Duration for Masters */ 191 uint32_t :7; /**< bit: 9..15 Reserved */ 192 uint32_t DEFMSTR_TYPE:2; /**< bit: 16..17 Default Master Type */ 193 uint32_t FIXED_DEFMSTR:4; /**< bit: 18..21 Fixed Default Master */ 194 uint32_t :10; /**< bit: 22..31 Reserved */ 195 } bit; /**< Structure used for bit access */ 196 uint32_t reg; /**< Type used for register access */ 197 } MATRIX_SCFG_Type; 198 #endif 199 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 200 201 #define MATRIX_SCFG_OFFSET (0x40) /**< (MATRIX_SCFG) Slave Configuration Register 0 Offset */ 202 203 #define MATRIX_SCFG_SLOT_CYCLE_Pos 0 /**< (MATRIX_SCFG) Maximum Bus Grant Duration for Masters Position */ 204 #define MATRIX_SCFG_SLOT_CYCLE_Msk (_U_(0x1FF) << MATRIX_SCFG_SLOT_CYCLE_Pos) /**< (MATRIX_SCFG) Maximum Bus Grant Duration for Masters Mask */ 205 #define MATRIX_SCFG_SLOT_CYCLE(value) (MATRIX_SCFG_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG_SLOT_CYCLE_Pos)) 206 #define MATRIX_SCFG_DEFMSTR_TYPE_Pos 16 /**< (MATRIX_SCFG) Default Master Type Position */ 207 #define MATRIX_SCFG_DEFMSTR_TYPE_Msk (_U_(0x3) << MATRIX_SCFG_DEFMSTR_TYPE_Pos) /**< (MATRIX_SCFG) Default Master Type Mask */ 208 #define MATRIX_SCFG_DEFMSTR_TYPE(value) (MATRIX_SCFG_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG_DEFMSTR_TYPE_Pos)) 209 #define MATRIX_SCFG_DEFMSTR_TYPE_NONE_Val _U_(0x0) /**< (MATRIX_SCFG) No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. */ 210 #define MATRIX_SCFG_DEFMSTR_TYPE_LAST_Val _U_(0x1) /**< (MATRIX_SCFG) Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. */ 211 #define MATRIX_SCFG_DEFMSTR_TYPE_FIXED_Val _U_(0x2) /**< (MATRIX_SCFG) Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. */ 212 #define MATRIX_SCFG_DEFMSTR_TYPE_NONE (MATRIX_SCFG_DEFMSTR_TYPE_NONE_Val << MATRIX_SCFG_DEFMSTR_TYPE_Pos) /**< (MATRIX_SCFG) No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. Position */ 213 #define MATRIX_SCFG_DEFMSTR_TYPE_LAST (MATRIX_SCFG_DEFMSTR_TYPE_LAST_Val << MATRIX_SCFG_DEFMSTR_TYPE_Pos) /**< (MATRIX_SCFG) Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. Position */ 214 #define MATRIX_SCFG_DEFMSTR_TYPE_FIXED (MATRIX_SCFG_DEFMSTR_TYPE_FIXED_Val << MATRIX_SCFG_DEFMSTR_TYPE_Pos) /**< (MATRIX_SCFG) Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. Position */ 215 #define MATRIX_SCFG_FIXED_DEFMSTR_Pos 18 /**< (MATRIX_SCFG) Fixed Default Master Position */ 216 #define MATRIX_SCFG_FIXED_DEFMSTR_Msk (_U_(0xF) << MATRIX_SCFG_FIXED_DEFMSTR_Pos) /**< (MATRIX_SCFG) Fixed Default Master Mask */ 217 #define MATRIX_SCFG_FIXED_DEFMSTR(value) (MATRIX_SCFG_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG_FIXED_DEFMSTR_Pos)) 218 #define MATRIX_SCFG_MASK _U_(0x3F01FF) /**< \deprecated (MATRIX_SCFG) Register MASK (Use MATRIX_SCFG_Msk instead) */ 219 #define MATRIX_SCFG_Msk _U_(0x3F01FF) /**< (MATRIX_SCFG) Register Mask */ 220 221 222 /* -------- MATRIX_MRCR : (MATRIX Offset: 0x100) (R/W 32) Master Remap Control Register -------- */ 223 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 224 #if COMPONENT_TYPEDEF_STYLE == 'N' 225 typedef union { 226 struct { 227 uint32_t RCB0:1; /**< bit: 0 Remap Command Bit for Master 0 */ 228 uint32_t RCB1:1; /**< bit: 1 Remap Command Bit for Master 1 */ 229 uint32_t RCB2:1; /**< bit: 2 Remap Command Bit for Master 2 */ 230 uint32_t RCB3:1; /**< bit: 3 Remap Command Bit for Master 3 */ 231 uint32_t RCB4:1; /**< bit: 4 Remap Command Bit for Master 4 */ 232 uint32_t RCB5:1; /**< bit: 5 Remap Command Bit for Master 5 */ 233 uint32_t RCB6:1; /**< bit: 6 Remap Command Bit for Master 6 */ 234 uint32_t RCB7:1; /**< bit: 7 Remap Command Bit for Master 7 */ 235 uint32_t RCB8:1; /**< bit: 8 Remap Command Bit for Master 8 */ 236 uint32_t RCB9:1; /**< bit: 9 Remap Command Bit for Master 9 */ 237 uint32_t RCB10:1; /**< bit: 10 Remap Command Bit for Master 10 */ 238 uint32_t RCB11:1; /**< bit: 11 Remap Command Bit for Master 11 */ 239 uint32_t RCB12:1; /**< bit: 12 Remap Command Bit for Master 12 */ 240 uint32_t :19; /**< bit: 13..31 Reserved */ 241 } bit; /**< Structure used for bit access */ 242 struct { 243 uint32_t RCB:13; /**< bit: 0..12 Remap Command Bit for Master x2 */ 244 uint32_t :19; /**< bit: 13..31 Reserved */ 245 } vec; /**< Structure used for vec access */ 246 uint32_t reg; /**< Type used for register access */ 247 } MATRIX_MRCR_Type; 248 #endif 249 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 250 251 #define MATRIX_MRCR_OFFSET (0x100) /**< (MATRIX_MRCR) Master Remap Control Register Offset */ 252 253 #define MATRIX_MRCR_RCB0_Pos 0 /**< (MATRIX_MRCR) Remap Command Bit for Master 0 Position */ 254 #define MATRIX_MRCR_RCB0_Msk (_U_(0x1) << MATRIX_MRCR_RCB0_Pos) /**< (MATRIX_MRCR) Remap Command Bit for Master 0 Mask */ 255 #define MATRIX_MRCR_RCB0 MATRIX_MRCR_RCB0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MATRIX_MRCR_RCB0_Msk instead */ 256 #define MATRIX_MRCR_RCB1_Pos 1 /**< (MATRIX_MRCR) Remap Command Bit for Master 1 Position */ 257 #define MATRIX_MRCR_RCB1_Msk (_U_(0x1) << MATRIX_MRCR_RCB1_Pos) /**< (MATRIX_MRCR) Remap Command Bit for Master 1 Mask */ 258 #define MATRIX_MRCR_RCB1 MATRIX_MRCR_RCB1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MATRIX_MRCR_RCB1_Msk instead */ 259 #define MATRIX_MRCR_RCB2_Pos 2 /**< (MATRIX_MRCR) Remap Command Bit for Master 2 Position */ 260 #define MATRIX_MRCR_RCB2_Msk (_U_(0x1) << MATRIX_MRCR_RCB2_Pos) /**< (MATRIX_MRCR) Remap Command Bit for Master 2 Mask */ 261 #define MATRIX_MRCR_RCB2 MATRIX_MRCR_RCB2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MATRIX_MRCR_RCB2_Msk instead */ 262 #define MATRIX_MRCR_RCB3_Pos 3 /**< (MATRIX_MRCR) Remap Command Bit for Master 3 Position */ 263 #define MATRIX_MRCR_RCB3_Msk (_U_(0x1) << MATRIX_MRCR_RCB3_Pos) /**< (MATRIX_MRCR) Remap Command Bit for Master 3 Mask */ 264 #define MATRIX_MRCR_RCB3 MATRIX_MRCR_RCB3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MATRIX_MRCR_RCB3_Msk instead */ 265 #define MATRIX_MRCR_RCB4_Pos 4 /**< (MATRIX_MRCR) Remap Command Bit for Master 4 Position */ 266 #define MATRIX_MRCR_RCB4_Msk (_U_(0x1) << MATRIX_MRCR_RCB4_Pos) /**< (MATRIX_MRCR) Remap Command Bit for Master 4 Mask */ 267 #define MATRIX_MRCR_RCB4 MATRIX_MRCR_RCB4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MATRIX_MRCR_RCB4_Msk instead */ 268 #define MATRIX_MRCR_RCB5_Pos 5 /**< (MATRIX_MRCR) Remap Command Bit for Master 5 Position */ 269 #define MATRIX_MRCR_RCB5_Msk (_U_(0x1) << MATRIX_MRCR_RCB5_Pos) /**< (MATRIX_MRCR) Remap Command Bit for Master 5 Mask */ 270 #define MATRIX_MRCR_RCB5 MATRIX_MRCR_RCB5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MATRIX_MRCR_RCB5_Msk instead */ 271 #define MATRIX_MRCR_RCB6_Pos 6 /**< (MATRIX_MRCR) Remap Command Bit for Master 6 Position */ 272 #define MATRIX_MRCR_RCB6_Msk (_U_(0x1) << MATRIX_MRCR_RCB6_Pos) /**< (MATRIX_MRCR) Remap Command Bit for Master 6 Mask */ 273 #define MATRIX_MRCR_RCB6 MATRIX_MRCR_RCB6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MATRIX_MRCR_RCB6_Msk instead */ 274 #define MATRIX_MRCR_RCB7_Pos 7 /**< (MATRIX_MRCR) Remap Command Bit for Master 7 Position */ 275 #define MATRIX_MRCR_RCB7_Msk (_U_(0x1) << MATRIX_MRCR_RCB7_Pos) /**< (MATRIX_MRCR) Remap Command Bit for Master 7 Mask */ 276 #define MATRIX_MRCR_RCB7 MATRIX_MRCR_RCB7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MATRIX_MRCR_RCB7_Msk instead */ 277 #define MATRIX_MRCR_RCB8_Pos 8 /**< (MATRIX_MRCR) Remap Command Bit for Master 8 Position */ 278 #define MATRIX_MRCR_RCB8_Msk (_U_(0x1) << MATRIX_MRCR_RCB8_Pos) /**< (MATRIX_MRCR) Remap Command Bit for Master 8 Mask */ 279 #define MATRIX_MRCR_RCB8 MATRIX_MRCR_RCB8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MATRIX_MRCR_RCB8_Msk instead */ 280 #define MATRIX_MRCR_RCB9_Pos 9 /**< (MATRIX_MRCR) Remap Command Bit for Master 9 Position */ 281 #define MATRIX_MRCR_RCB9_Msk (_U_(0x1) << MATRIX_MRCR_RCB9_Pos) /**< (MATRIX_MRCR) Remap Command Bit for Master 9 Mask */ 282 #define MATRIX_MRCR_RCB9 MATRIX_MRCR_RCB9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MATRIX_MRCR_RCB9_Msk instead */ 283 #define MATRIX_MRCR_RCB10_Pos 10 /**< (MATRIX_MRCR) Remap Command Bit for Master 10 Position */ 284 #define MATRIX_MRCR_RCB10_Msk (_U_(0x1) << MATRIX_MRCR_RCB10_Pos) /**< (MATRIX_MRCR) Remap Command Bit for Master 10 Mask */ 285 #define MATRIX_MRCR_RCB10 MATRIX_MRCR_RCB10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MATRIX_MRCR_RCB10_Msk instead */ 286 #define MATRIX_MRCR_RCB11_Pos 11 /**< (MATRIX_MRCR) Remap Command Bit for Master 11 Position */ 287 #define MATRIX_MRCR_RCB11_Msk (_U_(0x1) << MATRIX_MRCR_RCB11_Pos) /**< (MATRIX_MRCR) Remap Command Bit for Master 11 Mask */ 288 #define MATRIX_MRCR_RCB11 MATRIX_MRCR_RCB11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MATRIX_MRCR_RCB11_Msk instead */ 289 #define MATRIX_MRCR_RCB12_Pos 12 /**< (MATRIX_MRCR) Remap Command Bit for Master 12 Position */ 290 #define MATRIX_MRCR_RCB12_Msk (_U_(0x1) << MATRIX_MRCR_RCB12_Pos) /**< (MATRIX_MRCR) Remap Command Bit for Master 12 Mask */ 291 #define MATRIX_MRCR_RCB12 MATRIX_MRCR_RCB12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MATRIX_MRCR_RCB12_Msk instead */ 292 #define MATRIX_MRCR_MASK _U_(0x1FFF) /**< \deprecated (MATRIX_MRCR) Register MASK (Use MATRIX_MRCR_Msk instead) */ 293 #define MATRIX_MRCR_Msk _U_(0x1FFF) /**< (MATRIX_MRCR) Register Mask */ 294 295 #define MATRIX_MRCR_RCB_Pos 0 /**< (MATRIX_MRCR Position) Remap Command Bit for Master x2 */ 296 #define MATRIX_MRCR_RCB_Msk (_U_(0x1FFF) << MATRIX_MRCR_RCB_Pos) /**< (MATRIX_MRCR Mask) RCB */ 297 #define MATRIX_MRCR_RCB(value) (MATRIX_MRCR_RCB_Msk & ((value) << MATRIX_MRCR_RCB_Pos)) 298 299 /* -------- CCFG_CAN0 : (MATRIX Offset: 0x110) (R/W 32) CAN0 Configuration Register -------- */ 300 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 301 #if COMPONENT_TYPEDEF_STYLE == 'N' 302 typedef union { 303 struct { 304 uint32_t :16; /**< bit: 0..15 Reserved */ 305 uint32_t CAN0DMABA:16; /**< bit: 16..31 CAN0 DMA Base Address */ 306 } bit; /**< Structure used for bit access */ 307 uint32_t reg; /**< Type used for register access */ 308 } CCFG_CAN0_Type; 309 #endif 310 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 311 312 #define CCFG_CAN0_OFFSET (0x110) /**< (CCFG_CAN0) CAN0 Configuration Register Offset */ 313 314 #define CCFG_CAN0_CAN0DMABA_Pos 16 /**< (CCFG_CAN0) CAN0 DMA Base Address Position */ 315 #define CCFG_CAN0_CAN0DMABA_Msk (_U_(0xFFFF) << CCFG_CAN0_CAN0DMABA_Pos) /**< (CCFG_CAN0) CAN0 DMA Base Address Mask */ 316 #define CCFG_CAN0_CAN0DMABA(value) (CCFG_CAN0_CAN0DMABA_Msk & ((value) << CCFG_CAN0_CAN0DMABA_Pos)) 317 #define CCFG_CAN0_MASK _U_(0xFFFF0000) /**< \deprecated (CCFG_CAN0) Register MASK (Use CCFG_CAN0_Msk instead) */ 318 #define CCFG_CAN0_Msk _U_(0xFFFF0000) /**< (CCFG_CAN0) Register Mask */ 319 320 321 /* -------- CCFG_SYSIO : (MATRIX Offset: 0x114) (R/W 32) System I/O and CAN1 Configuration Register -------- */ 322 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 323 #if COMPONENT_TYPEDEF_STYLE == 'N' 324 typedef union { 325 struct { 326 uint32_t :4; /**< bit: 0..3 Reserved */ 327 uint32_t SYSIO4:1; /**< bit: 4 PB4 or TDI Assignment */ 328 uint32_t SYSIO5:1; /**< bit: 5 PB5 or TDO/TRACESWO Assignment */ 329 uint32_t SYSIO6:1; /**< bit: 6 PB6 or TMS/SWDIO Assignment */ 330 uint32_t SYSIO7:1; /**< bit: 7 PB7 or TCK/SWCLK Assignment */ 331 uint32_t :4; /**< bit: 8..11 Reserved */ 332 uint32_t SYSIO12:1; /**< bit: 12 PB12 or ERASE Assignment */ 333 uint32_t :3; /**< bit: 13..15 Reserved */ 334 uint32_t CAN1DMABA:16; /**< bit: 16..31 CAN1 DMA Base Address */ 335 } bit; /**< Structure used for bit access */ 336 struct { 337 uint32_t :4; /**< bit: 0..3 Reserved */ 338 uint32_t SYSIO:5; /**< bit: 4..8 PB4 or TDI Assignment */ 339 uint32_t :23; /**< bit: 9..31 Reserved */ 340 } vec; /**< Structure used for vec access */ 341 uint32_t reg; /**< Type used for register access */ 342 } CCFG_SYSIO_Type; 343 #endif 344 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 345 346 #define CCFG_SYSIO_OFFSET (0x114) /**< (CCFG_SYSIO) System I/O and CAN1 Configuration Register Offset */ 347 348 #define CCFG_SYSIO_SYSIO4_Pos 4 /**< (CCFG_SYSIO) PB4 or TDI Assignment Position */ 349 #define CCFG_SYSIO_SYSIO4_Msk (_U_(0x1) << CCFG_SYSIO_SYSIO4_Pos) /**< (CCFG_SYSIO) PB4 or TDI Assignment Mask */ 350 #define CCFG_SYSIO_SYSIO4 CCFG_SYSIO_SYSIO4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CCFG_SYSIO_SYSIO4_Msk instead */ 351 #define CCFG_SYSIO_SYSIO5_Pos 5 /**< (CCFG_SYSIO) PB5 or TDO/TRACESWO Assignment Position */ 352 #define CCFG_SYSIO_SYSIO5_Msk (_U_(0x1) << CCFG_SYSIO_SYSIO5_Pos) /**< (CCFG_SYSIO) PB5 or TDO/TRACESWO Assignment Mask */ 353 #define CCFG_SYSIO_SYSIO5 CCFG_SYSIO_SYSIO5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CCFG_SYSIO_SYSIO5_Msk instead */ 354 #define CCFG_SYSIO_SYSIO6_Pos 6 /**< (CCFG_SYSIO) PB6 or TMS/SWDIO Assignment Position */ 355 #define CCFG_SYSIO_SYSIO6_Msk (_U_(0x1) << CCFG_SYSIO_SYSIO6_Pos) /**< (CCFG_SYSIO) PB6 or TMS/SWDIO Assignment Mask */ 356 #define CCFG_SYSIO_SYSIO6 CCFG_SYSIO_SYSIO6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CCFG_SYSIO_SYSIO6_Msk instead */ 357 #define CCFG_SYSIO_SYSIO7_Pos 7 /**< (CCFG_SYSIO) PB7 or TCK/SWCLK Assignment Position */ 358 #define CCFG_SYSIO_SYSIO7_Msk (_U_(0x1) << CCFG_SYSIO_SYSIO7_Pos) /**< (CCFG_SYSIO) PB7 or TCK/SWCLK Assignment Mask */ 359 #define CCFG_SYSIO_SYSIO7 CCFG_SYSIO_SYSIO7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CCFG_SYSIO_SYSIO7_Msk instead */ 360 #define CCFG_SYSIO_SYSIO12_Pos 12 /**< (CCFG_SYSIO) PB12 or ERASE Assignment Position */ 361 #define CCFG_SYSIO_SYSIO12_Msk (_U_(0x1) << CCFG_SYSIO_SYSIO12_Pos) /**< (CCFG_SYSIO) PB12 or ERASE Assignment Mask */ 362 #define CCFG_SYSIO_SYSIO12 CCFG_SYSIO_SYSIO12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CCFG_SYSIO_SYSIO12_Msk instead */ 363 #define CCFG_SYSIO_CAN1DMABA_Pos 16 /**< (CCFG_SYSIO) CAN1 DMA Base Address Position */ 364 #define CCFG_SYSIO_CAN1DMABA_Msk (_U_(0xFFFF) << CCFG_SYSIO_CAN1DMABA_Pos) /**< (CCFG_SYSIO) CAN1 DMA Base Address Mask */ 365 #define CCFG_SYSIO_CAN1DMABA(value) (CCFG_SYSIO_CAN1DMABA_Msk & ((value) << CCFG_SYSIO_CAN1DMABA_Pos)) 366 #define CCFG_SYSIO_MASK _U_(0xFFFF10F0) /**< \deprecated (CCFG_SYSIO) Register MASK (Use CCFG_SYSIO_Msk instead) */ 367 #define CCFG_SYSIO_Msk _U_(0xFFFF10F0) /**< (CCFG_SYSIO) Register Mask */ 368 369 #define CCFG_SYSIO_SYSIO_Pos 4 /**< (CCFG_SYSIO Position) PB4 or TDI Assignment */ 370 #define CCFG_SYSIO_SYSIO_Msk (_U_(0x1F) << CCFG_SYSIO_SYSIO_Pos) /**< (CCFG_SYSIO Mask) SYSIO */ 371 #define CCFG_SYSIO_SYSIO(value) (CCFG_SYSIO_SYSIO_Msk & ((value) << CCFG_SYSIO_SYSIO_Pos)) 372 373 /* -------- CCFG_PCCR : (MATRIX Offset: 0x118) (R/W 32) Peripheral Clock Configuration Register -------- */ 374 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 375 #if COMPONENT_TYPEDEF_STYLE == 'N' 376 typedef union { 377 struct { 378 uint32_t :20; /**< bit: 0..19 Reserved */ 379 uint32_t TC0CC:1; /**< bit: 20 TC0 Clock Configuration */ 380 uint32_t I2SC0CC:1; /**< bit: 21 I2SC0 Clock Configuration */ 381 uint32_t I2SC1CC:1; /**< bit: 22 I2SC1 Clock Configuration */ 382 uint32_t :9; /**< bit: 23..31 Reserved */ 383 } bit; /**< Structure used for bit access */ 384 uint32_t reg; /**< Type used for register access */ 385 } CCFG_PCCR_Type; 386 #endif 387 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 388 389 #define CCFG_PCCR_OFFSET (0x118) /**< (CCFG_PCCR) Peripheral Clock Configuration Register Offset */ 390 391 #define CCFG_PCCR_TC0CC_Pos 20 /**< (CCFG_PCCR) TC0 Clock Configuration Position */ 392 #define CCFG_PCCR_TC0CC_Msk (_U_(0x1) << CCFG_PCCR_TC0CC_Pos) /**< (CCFG_PCCR) TC0 Clock Configuration Mask */ 393 #define CCFG_PCCR_TC0CC CCFG_PCCR_TC0CC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CCFG_PCCR_TC0CC_Msk instead */ 394 #define CCFG_PCCR_I2SC0CC_Pos 21 /**< (CCFG_PCCR) I2SC0 Clock Configuration Position */ 395 #define CCFG_PCCR_I2SC0CC_Msk (_U_(0x1) << CCFG_PCCR_I2SC0CC_Pos) /**< (CCFG_PCCR) I2SC0 Clock Configuration Mask */ 396 #define CCFG_PCCR_I2SC0CC CCFG_PCCR_I2SC0CC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CCFG_PCCR_I2SC0CC_Msk instead */ 397 #define CCFG_PCCR_I2SC1CC_Pos 22 /**< (CCFG_PCCR) I2SC1 Clock Configuration Position */ 398 #define CCFG_PCCR_I2SC1CC_Msk (_U_(0x1) << CCFG_PCCR_I2SC1CC_Pos) /**< (CCFG_PCCR) I2SC1 Clock Configuration Mask */ 399 #define CCFG_PCCR_I2SC1CC CCFG_PCCR_I2SC1CC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CCFG_PCCR_I2SC1CC_Msk instead */ 400 #define CCFG_PCCR_MASK _U_(0x700000) /**< \deprecated (CCFG_PCCR) Register MASK (Use CCFG_PCCR_Msk instead) */ 401 #define CCFG_PCCR_Msk _U_(0x700000) /**< (CCFG_PCCR) Register Mask */ 402 403 404 /* -------- CCFG_DYNCKG : (MATRIX Offset: 0x11c) (R/W 32) Dynamic Clock Gating Register -------- */ 405 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 406 #if COMPONENT_TYPEDEF_STYLE == 'N' 407 typedef union { 408 struct { 409 uint32_t MATCKG:1; /**< bit: 0 MATRIX Dynamic Clock Gating */ 410 uint32_t BRIDCKG:1; /**< bit: 1 Bridge Dynamic Clock Gating Enable */ 411 uint32_t EFCCKG:1; /**< bit: 2 EFC Dynamic Clock Gating Enable */ 412 uint32_t :29; /**< bit: 3..31 Reserved */ 413 } bit; /**< Structure used for bit access */ 414 uint32_t reg; /**< Type used for register access */ 415 } CCFG_DYNCKG_Type; 416 #endif 417 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 418 419 #define CCFG_DYNCKG_OFFSET (0x11C) /**< (CCFG_DYNCKG) Dynamic Clock Gating Register Offset */ 420 421 #define CCFG_DYNCKG_MATCKG_Pos 0 /**< (CCFG_DYNCKG) MATRIX Dynamic Clock Gating Position */ 422 #define CCFG_DYNCKG_MATCKG_Msk (_U_(0x1) << CCFG_DYNCKG_MATCKG_Pos) /**< (CCFG_DYNCKG) MATRIX Dynamic Clock Gating Mask */ 423 #define CCFG_DYNCKG_MATCKG CCFG_DYNCKG_MATCKG_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CCFG_DYNCKG_MATCKG_Msk instead */ 424 #define CCFG_DYNCKG_BRIDCKG_Pos 1 /**< (CCFG_DYNCKG) Bridge Dynamic Clock Gating Enable Position */ 425 #define CCFG_DYNCKG_BRIDCKG_Msk (_U_(0x1) << CCFG_DYNCKG_BRIDCKG_Pos) /**< (CCFG_DYNCKG) Bridge Dynamic Clock Gating Enable Mask */ 426 #define CCFG_DYNCKG_BRIDCKG CCFG_DYNCKG_BRIDCKG_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CCFG_DYNCKG_BRIDCKG_Msk instead */ 427 #define CCFG_DYNCKG_EFCCKG_Pos 2 /**< (CCFG_DYNCKG) EFC Dynamic Clock Gating Enable Position */ 428 #define CCFG_DYNCKG_EFCCKG_Msk (_U_(0x1) << CCFG_DYNCKG_EFCCKG_Pos) /**< (CCFG_DYNCKG) EFC Dynamic Clock Gating Enable Mask */ 429 #define CCFG_DYNCKG_EFCCKG CCFG_DYNCKG_EFCCKG_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CCFG_DYNCKG_EFCCKG_Msk instead */ 430 #define CCFG_DYNCKG_MASK _U_(0x07) /**< \deprecated (CCFG_DYNCKG) Register MASK (Use CCFG_DYNCKG_Msk instead) */ 431 #define CCFG_DYNCKG_Msk _U_(0x07) /**< (CCFG_DYNCKG) Register Mask */ 432 433 434 /* -------- CCFG_SMCNFCS : (MATRIX Offset: 0x124) (R/W 32) SMC NAND Flash Chip Select Configuration Register -------- */ 435 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 436 #if COMPONENT_TYPEDEF_STYLE == 'N' 437 typedef union { 438 struct { 439 uint32_t SMC_NFCS0:1; /**< bit: 0 SMC NAND Flash Chip Select 0 Assignment */ 440 uint32_t SMC_NFCS1:1; /**< bit: 1 SMC NAND Flash Chip Select 1 Assignment */ 441 uint32_t SMC_NFCS2:1; /**< bit: 2 SMC NAND Flash Chip Select 2 Assignment */ 442 uint32_t SMC_NFCS3:1; /**< bit: 3 SMC NAND Flash Chip Select 3 Assignment */ 443 uint32_t SDRAMEN:1; /**< bit: 4 SDRAM Enable */ 444 uint32_t :27; /**< bit: 5..31 Reserved */ 445 } bit; /**< Structure used for bit access */ 446 struct { 447 uint32_t SMC_NFCS:4; /**< bit: 0..3 SMC NAND Flash Chip Select x Assignment */ 448 uint32_t :28; /**< bit: 4..31 Reserved */ 449 } vec; /**< Structure used for vec access */ 450 uint32_t reg; /**< Type used for register access */ 451 } CCFG_SMCNFCS_Type; 452 #endif 453 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 454 455 #define CCFG_SMCNFCS_OFFSET (0x124) /**< (CCFG_SMCNFCS) SMC NAND Flash Chip Select Configuration Register Offset */ 456 457 #define CCFG_SMCNFCS_SMC_NFCS0_Pos 0 /**< (CCFG_SMCNFCS) SMC NAND Flash Chip Select 0 Assignment Position */ 458 #define CCFG_SMCNFCS_SMC_NFCS0_Msk (_U_(0x1) << CCFG_SMCNFCS_SMC_NFCS0_Pos) /**< (CCFG_SMCNFCS) SMC NAND Flash Chip Select 0 Assignment Mask */ 459 #define CCFG_SMCNFCS_SMC_NFCS0 CCFG_SMCNFCS_SMC_NFCS0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CCFG_SMCNFCS_SMC_NFCS0_Msk instead */ 460 #define CCFG_SMCNFCS_SMC_NFCS1_Pos 1 /**< (CCFG_SMCNFCS) SMC NAND Flash Chip Select 1 Assignment Position */ 461 #define CCFG_SMCNFCS_SMC_NFCS1_Msk (_U_(0x1) << CCFG_SMCNFCS_SMC_NFCS1_Pos) /**< (CCFG_SMCNFCS) SMC NAND Flash Chip Select 1 Assignment Mask */ 462 #define CCFG_SMCNFCS_SMC_NFCS1 CCFG_SMCNFCS_SMC_NFCS1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CCFG_SMCNFCS_SMC_NFCS1_Msk instead */ 463 #define CCFG_SMCNFCS_SMC_NFCS2_Pos 2 /**< (CCFG_SMCNFCS) SMC NAND Flash Chip Select 2 Assignment Position */ 464 #define CCFG_SMCNFCS_SMC_NFCS2_Msk (_U_(0x1) << CCFG_SMCNFCS_SMC_NFCS2_Pos) /**< (CCFG_SMCNFCS) SMC NAND Flash Chip Select 2 Assignment Mask */ 465 #define CCFG_SMCNFCS_SMC_NFCS2 CCFG_SMCNFCS_SMC_NFCS2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CCFG_SMCNFCS_SMC_NFCS2_Msk instead */ 466 #define CCFG_SMCNFCS_SMC_NFCS3_Pos 3 /**< (CCFG_SMCNFCS) SMC NAND Flash Chip Select 3 Assignment Position */ 467 #define CCFG_SMCNFCS_SMC_NFCS3_Msk (_U_(0x1) << CCFG_SMCNFCS_SMC_NFCS3_Pos) /**< (CCFG_SMCNFCS) SMC NAND Flash Chip Select 3 Assignment Mask */ 468 #define CCFG_SMCNFCS_SMC_NFCS3 CCFG_SMCNFCS_SMC_NFCS3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CCFG_SMCNFCS_SMC_NFCS3_Msk instead */ 469 #define CCFG_SMCNFCS_SDRAMEN_Pos 4 /**< (CCFG_SMCNFCS) SDRAM Enable Position */ 470 #define CCFG_SMCNFCS_SDRAMEN_Msk (_U_(0x1) << CCFG_SMCNFCS_SDRAMEN_Pos) /**< (CCFG_SMCNFCS) SDRAM Enable Mask */ 471 #define CCFG_SMCNFCS_SDRAMEN CCFG_SMCNFCS_SDRAMEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CCFG_SMCNFCS_SDRAMEN_Msk instead */ 472 #define CCFG_SMCNFCS_MASK _U_(0x1F) /**< \deprecated (CCFG_SMCNFCS) Register MASK (Use CCFG_SMCNFCS_Msk instead) */ 473 #define CCFG_SMCNFCS_Msk _U_(0x1F) /**< (CCFG_SMCNFCS) Register Mask */ 474 475 #define CCFG_SMCNFCS_SMC_NFCS_Pos 0 /**< (CCFG_SMCNFCS Position) SMC NAND Flash Chip Select x Assignment */ 476 #define CCFG_SMCNFCS_SMC_NFCS_Msk (_U_(0xF) << CCFG_SMCNFCS_SMC_NFCS_Pos) /**< (CCFG_SMCNFCS Mask) SMC_NFCS */ 477 #define CCFG_SMCNFCS_SMC_NFCS(value) (CCFG_SMCNFCS_SMC_NFCS_Msk & ((value) << CCFG_SMCNFCS_SMC_NFCS_Pos)) 478 479 /* -------- MATRIX_WPMR : (MATRIX Offset: 0x1e4) (R/W 32) Write Protection Mode Register -------- */ 480 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 481 #if COMPONENT_TYPEDEF_STYLE == 'N' 482 typedef union { 483 struct { 484 uint32_t WPEN:1; /**< bit: 0 Write Protection Enable */ 485 uint32_t :7; /**< bit: 1..7 Reserved */ 486 uint32_t WPKEY:24; /**< bit: 8..31 Write Protection Key */ 487 } bit; /**< Structure used for bit access */ 488 uint32_t reg; /**< Type used for register access */ 489 } MATRIX_WPMR_Type; 490 #endif 491 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 492 493 #define MATRIX_WPMR_OFFSET (0x1E4) /**< (MATRIX_WPMR) Write Protection Mode Register Offset */ 494 495 #define MATRIX_WPMR_WPEN_Pos 0 /**< (MATRIX_WPMR) Write Protection Enable Position */ 496 #define MATRIX_WPMR_WPEN_Msk (_U_(0x1) << MATRIX_WPMR_WPEN_Pos) /**< (MATRIX_WPMR) Write Protection Enable Mask */ 497 #define MATRIX_WPMR_WPEN MATRIX_WPMR_WPEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MATRIX_WPMR_WPEN_Msk instead */ 498 #define MATRIX_WPMR_WPKEY_Pos 8 /**< (MATRIX_WPMR) Write Protection Key Position */ 499 #define MATRIX_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << MATRIX_WPMR_WPKEY_Pos) /**< (MATRIX_WPMR) Write Protection Key Mask */ 500 #define MATRIX_WPMR_WPKEY(value) (MATRIX_WPMR_WPKEY_Msk & ((value) << MATRIX_WPMR_WPKEY_Pos)) 501 #define MATRIX_WPMR_WPKEY_PASSWD_Val _U_(0x4D4154) /**< (MATRIX_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ 502 #define MATRIX_WPMR_WPKEY_PASSWD (MATRIX_WPMR_WPKEY_PASSWD_Val << MATRIX_WPMR_WPKEY_Pos) /**< (MATRIX_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. Position */ 503 #define MATRIX_WPMR_MASK _U_(0xFFFFFF01) /**< \deprecated (MATRIX_WPMR) Register MASK (Use MATRIX_WPMR_Msk instead) */ 504 #define MATRIX_WPMR_Msk _U_(0xFFFFFF01) /**< (MATRIX_WPMR) Register Mask */ 505 506 507 /* -------- MATRIX_WPSR : (MATRIX Offset: 0x1e8) (R/ 32) Write Protection Status Register -------- */ 508 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 509 #if COMPONENT_TYPEDEF_STYLE == 'N' 510 typedef union { 511 struct { 512 uint32_t WPVS:1; /**< bit: 0 Write Protection Violation Status */ 513 uint32_t :7; /**< bit: 1..7 Reserved */ 514 uint32_t WPVSRC:16; /**< bit: 8..23 Write Protection Violation Source */ 515 uint32_t :8; /**< bit: 24..31 Reserved */ 516 } bit; /**< Structure used for bit access */ 517 uint32_t reg; /**< Type used for register access */ 518 } MATRIX_WPSR_Type; 519 #endif 520 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 521 522 #define MATRIX_WPSR_OFFSET (0x1E8) /**< (MATRIX_WPSR) Write Protection Status Register Offset */ 523 524 #define MATRIX_WPSR_WPVS_Pos 0 /**< (MATRIX_WPSR) Write Protection Violation Status Position */ 525 #define MATRIX_WPSR_WPVS_Msk (_U_(0x1) << MATRIX_WPSR_WPVS_Pos) /**< (MATRIX_WPSR) Write Protection Violation Status Mask */ 526 #define MATRIX_WPSR_WPVS MATRIX_WPSR_WPVS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MATRIX_WPSR_WPVS_Msk instead */ 527 #define MATRIX_WPSR_WPVSRC_Pos 8 /**< (MATRIX_WPSR) Write Protection Violation Source Position */ 528 #define MATRIX_WPSR_WPVSRC_Msk (_U_(0xFFFF) << MATRIX_WPSR_WPVSRC_Pos) /**< (MATRIX_WPSR) Write Protection Violation Source Mask */ 529 #define MATRIX_WPSR_WPVSRC(value) (MATRIX_WPSR_WPVSRC_Msk & ((value) << MATRIX_WPSR_WPVSRC_Pos)) 530 #define MATRIX_WPSR_MASK _U_(0xFFFF01) /**< \deprecated (MATRIX_WPSR) Register MASK (Use MATRIX_WPSR_Msk instead) */ 531 #define MATRIX_WPSR_Msk _U_(0xFFFF01) /**< (MATRIX_WPSR) Register Mask */ 532 533 534 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 535 #if COMPONENT_TYPEDEF_STYLE == 'R' 536 /** \brief MATRIX_PR hardware registers */ 537 typedef struct { 538 __IO uint32_t MATRIX_PRAS; /**< (MATRIX_PR Offset: 0x00) Priority Register A for Slave 0 */ 539 __IO uint32_t MATRIX_PRBS; /**< (MATRIX_PR Offset: 0x04) Priority Register B for Slave 0 */ 540 } MatrixPr; 541 542 #define MATRIXPR_NUMBER 9 543 /** \brief MATRIX hardware registers */ 544 typedef struct { 545 __IO uint32_t MATRIX_MCFG[13]; /**< (MATRIX Offset: 0x00) Master Configuration Register 0 */ 546 __I uint8_t Reserved1[12]; 547 __IO uint32_t MATRIX_SCFG[9]; /**< (MATRIX Offset: 0x40) Slave Configuration Register 0 */ 548 __I uint8_t Reserved2[28]; 549 MatrixPr MatrixPr[MATRIXPR_NUMBER]; /**< Offset: 0x80 Priority Register A for Slave 0 */ 550 __I uint8_t Reserved3[56]; 551 __IO uint32_t MATRIX_MRCR; /**< (MATRIX Offset: 0x100) Master Remap Control Register */ 552 __I uint8_t Reserved4[12]; 553 __IO uint32_t CCFG_CAN0; /**< (MATRIX Offset: 0x110) CAN0 Configuration Register */ 554 __IO uint32_t CCFG_SYSIO; /**< (MATRIX Offset: 0x114) System I/O and CAN1 Configuration Register */ 555 __IO uint32_t CCFG_PCCR; /**< (MATRIX Offset: 0x118) Peripheral Clock Configuration Register */ 556 __IO uint32_t CCFG_DYNCKG; /**< (MATRIX Offset: 0x11C) Dynamic Clock Gating Register */ 557 __I uint8_t Reserved5[4]; 558 __IO uint32_t CCFG_SMCNFCS; /**< (MATRIX Offset: 0x124) SMC NAND Flash Chip Select Configuration Register */ 559 __I uint8_t Reserved6[188]; 560 __IO uint32_t MATRIX_WPMR; /**< (MATRIX Offset: 0x1E4) Write Protection Mode Register */ 561 __I uint32_t MATRIX_WPSR; /**< (MATRIX Offset: 0x1E8) Write Protection Status Register */ 562 } Matrix; 563 564 #elif COMPONENT_TYPEDEF_STYLE == 'N' 565 /** \brief MATRIX_PR hardware registers */ 566 typedef struct { 567 __IO MATRIX_PRAS_Type MATRIX_PRAS; /**< Offset: 0x00 (R/W 32) Priority Register A for Slave 0 */ 568 __IO MATRIX_PRBS_Type MATRIX_PRBS; /**< Offset: 0x04 (R/W 32) Priority Register B for Slave 0 */ 569 } MatrixPr; 570 571 /** \brief MATRIX hardware registers */ 572 typedef struct { 573 __IO MATRIX_MCFG_Type MATRIX_MCFG[13]; /**< Offset: 0x00 (R/W 32) Master Configuration Register 0 */ 574 __I uint8_t Reserved1[12]; 575 __IO MATRIX_SCFG_Type MATRIX_SCFG[9]; /**< Offset: 0x40 (R/W 32) Slave Configuration Register 0 */ 576 __I uint8_t Reserved2[28]; 577 MatrixPr MatrixPr[9]; /**< Offset: 0x80 Priority Register A for Slave 0 */ 578 __I uint8_t Reserved3[56]; 579 __IO MATRIX_MRCR_Type MATRIX_MRCR; /**< Offset: 0x100 (R/W 32) Master Remap Control Register */ 580 __I uint8_t Reserved4[12]; 581 __IO CCFG_CAN0_Type CCFG_CAN0; /**< Offset: 0x110 (R/W 32) CAN0 Configuration Register */ 582 __IO CCFG_SYSIO_Type CCFG_SYSIO; /**< Offset: 0x114 (R/W 32) System I/O and CAN1 Configuration Register */ 583 __IO CCFG_PCCR_Type CCFG_PCCR; /**< Offset: 0x118 (R/W 32) Peripheral Clock Configuration Register */ 584 __IO CCFG_DYNCKG_Type CCFG_DYNCKG; /**< Offset: 0x11C (R/W 32) Dynamic Clock Gating Register */ 585 __I uint8_t Reserved5[4]; 586 __IO CCFG_SMCNFCS_Type CCFG_SMCNFCS; /**< Offset: 0x124 (R/W 32) SMC NAND Flash Chip Select Configuration Register */ 587 __I uint8_t Reserved6[188]; 588 __IO MATRIX_WPMR_Type MATRIX_WPMR; /**< Offset: 0x1E4 (R/W 32) Write Protection Mode Register */ 589 __I MATRIX_WPSR_Type MATRIX_WPSR; /**< Offset: 0x1E8 (R/ 32) Write Protection Status Register */ 590 } Matrix; 591 592 #else /* COMPONENT_TYPEDEF_STYLE */ 593 #error Unknown component typedef style 594 #endif /* COMPONENT_TYPEDEF_STYLE */ 595 596 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 597 /** @} end of AHB Bus Matrix */ 598 599 #endif /* _SAMV71_MATRIX_COMPONENT_H_ */ 600
