1 /** 2 * \file 3 * 4 * \brief Component description for GMAC 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \license_stop 27 * 28 */ 29 30 /* file generated from device description version 2019-01-18T21:21:15Z */ 31 #ifndef _SAMV71_GMAC_COMPONENT_H_ 32 #define _SAMV71_GMAC_COMPONENT_H_ 33 #define _SAMV71_GMAC_COMPONENT_ /**< \deprecated Backward compatibility for ASF */ 34 35 /** \addtogroup SAMV_SAMV71 Gigabit Ethernet MAC 36 * @{ 37 */ 38 /* ========================================================================== */ 39 /** SOFTWARE API DEFINITION FOR GMAC */ 40 /* ========================================================================== */ 41 #ifndef COMPONENT_TYPEDEF_STYLE 42 #define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/ 43 #endif 44 45 #define GMAC_11046 /**< (GMAC) Module ID */ 46 #define REV_GMAC S /**< (GMAC) Module revision */ 47 48 /* -------- GMAC_SAB : (GMAC Offset: 0x00) (R/W 32) Specific Address 1 Bottom Register -------- */ 49 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 50 #if COMPONENT_TYPEDEF_STYLE == 'N' 51 typedef union { 52 struct { 53 uint32_t ADDR:32; /**< bit: 0..31 Specific Address 1 */ 54 } bit; /**< Structure used for bit access */ 55 uint32_t reg; /**< Type used for register access */ 56 } GMAC_SAB_Type; 57 #endif 58 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 59 60 #define GMAC_SAB_OFFSET (0x00) /**< (GMAC_SAB) Specific Address 1 Bottom Register Offset */ 61 62 #define GMAC_SAB_ADDR_Pos 0 /**< (GMAC_SAB) Specific Address 1 Position */ 63 #define GMAC_SAB_ADDR_Msk (_U_(0xFFFFFFFF) << GMAC_SAB_ADDR_Pos) /**< (GMAC_SAB) Specific Address 1 Mask */ 64 #define GMAC_SAB_ADDR(value) (GMAC_SAB_ADDR_Msk & ((value) << GMAC_SAB_ADDR_Pos)) 65 #define GMAC_SAB_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_SAB) Register MASK (Use GMAC_SAB_Msk instead) */ 66 #define GMAC_SAB_Msk _U_(0xFFFFFFFF) /**< (GMAC_SAB) Register Mask */ 67 68 69 /* -------- GMAC_SAT : (GMAC Offset: 0x04) (R/W 32) Specific Address 1 Top Register -------- */ 70 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 71 #if COMPONENT_TYPEDEF_STYLE == 'N' 72 typedef union { 73 struct { 74 uint32_t ADDR:16; /**< bit: 0..15 Specific Address 1 */ 75 uint32_t :16; /**< bit: 16..31 Reserved */ 76 } bit; /**< Structure used for bit access */ 77 uint32_t reg; /**< Type used for register access */ 78 } GMAC_SAT_Type; 79 #endif 80 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 81 82 #define GMAC_SAT_OFFSET (0x04) /**< (GMAC_SAT) Specific Address 1 Top Register Offset */ 83 84 #define GMAC_SAT_ADDR_Pos 0 /**< (GMAC_SAT) Specific Address 1 Position */ 85 #define GMAC_SAT_ADDR_Msk (_U_(0xFFFF) << GMAC_SAT_ADDR_Pos) /**< (GMAC_SAT) Specific Address 1 Mask */ 86 #define GMAC_SAT_ADDR(value) (GMAC_SAT_ADDR_Msk & ((value) << GMAC_SAT_ADDR_Pos)) 87 #define GMAC_SAT_MASK _U_(0xFFFF) /**< \deprecated (GMAC_SAT) Register MASK (Use GMAC_SAT_Msk instead) */ 88 #define GMAC_SAT_Msk _U_(0xFFFF) /**< (GMAC_SAT) Register Mask */ 89 90 91 /* -------- GMAC_ST2CW0 : (GMAC Offset: 0x00) (R/W 32) Screening Type 2 Compare Word 0 Register -------- */ 92 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 93 #if COMPONENT_TYPEDEF_STYLE == 'N' 94 typedef union { 95 struct { 96 uint32_t MASKVAL:16; /**< bit: 0..15 Mask Value */ 97 uint32_t COMPVAL:16; /**< bit: 16..31 Compare Value */ 98 } bit; /**< Structure used for bit access */ 99 uint32_t reg; /**< Type used for register access */ 100 } GMAC_ST2CW0_Type; 101 #endif 102 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 103 104 #define GMAC_ST2CW0_OFFSET (0x00) /**< (GMAC_ST2CW0) Screening Type 2 Compare Word 0 Register Offset */ 105 106 #define GMAC_ST2CW0_MASKVAL_Pos 0 /**< (GMAC_ST2CW0) Mask Value Position */ 107 #define GMAC_ST2CW0_MASKVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW0_MASKVAL_Pos) /**< (GMAC_ST2CW0) Mask Value Mask */ 108 #define GMAC_ST2CW0_MASKVAL(value) (GMAC_ST2CW0_MASKVAL_Msk & ((value) << GMAC_ST2CW0_MASKVAL_Pos)) 109 #define GMAC_ST2CW0_COMPVAL_Pos 16 /**< (GMAC_ST2CW0) Compare Value Position */ 110 #define GMAC_ST2CW0_COMPVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW0_COMPVAL_Pos) /**< (GMAC_ST2CW0) Compare Value Mask */ 111 #define GMAC_ST2CW0_COMPVAL(value) (GMAC_ST2CW0_COMPVAL_Msk & ((value) << GMAC_ST2CW0_COMPVAL_Pos)) 112 #define GMAC_ST2CW0_Msk _U_(0xFFFFFFFF) /**< (GMAC_ST2CW0) Register Mask */ 113 114 115 /* -------- GMAC_ST2CW1 : (GMAC Offset: 0x04) (R/W 32) Screening Type 2 Compare Word 1 Register -------- */ 116 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 117 #if COMPONENT_TYPEDEF_STYLE == 'N' 118 typedef union { 119 struct { 120 uint32_t OFFSVAL:7; /**< bit: 0..6 Offset Value in Bytes */ 121 uint32_t OFFSSTRT:2; /**< bit: 7..8 Ethernet Frame Offset Start */ 122 uint32_t :23; /**< bit: 9..31 Reserved */ 123 } bit; /**< Structure used for bit access */ 124 uint32_t reg; /**< Type used for register access */ 125 } GMAC_ST2CW1_Type; 126 #endif 127 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 128 129 #define GMAC_ST2CW1_OFFSET (0x04) /**< (GMAC_ST2CW1) Screening Type 2 Compare Word 1 Register Offset */ 130 131 #define GMAC_ST2CW1_OFFSVAL_Pos 0 /**< (GMAC_ST2CW1) Offset Value in Bytes Position */ 132 #define GMAC_ST2CW1_OFFSVAL_Msk (_U_(0x7F) << GMAC_ST2CW1_OFFSVAL_Pos) /**< (GMAC_ST2CW1) Offset Value in Bytes Mask */ 133 #define GMAC_ST2CW1_OFFSVAL(value) (GMAC_ST2CW1_OFFSVAL_Msk & ((value) << GMAC_ST2CW1_OFFSVAL_Pos)) 134 #define GMAC_ST2CW1_OFFSSTRT_Pos 7 /**< (GMAC_ST2CW1) Ethernet Frame Offset Start Position */ 135 #define GMAC_ST2CW1_OFFSSTRT_Msk (_U_(0x3) << GMAC_ST2CW1_OFFSSTRT_Pos) /**< (GMAC_ST2CW1) Ethernet Frame Offset Start Mask */ 136 #define GMAC_ST2CW1_OFFSSTRT(value) (GMAC_ST2CW1_OFFSSTRT_Msk & ((value) << GMAC_ST2CW1_OFFSSTRT_Pos)) 137 #define GMAC_ST2CW1_OFFSSTRT_FRAMESTART_Val _U_(0x0) /**< (GMAC_ST2CW1) Offset from the start of the frame */ 138 #define GMAC_ST2CW1_OFFSSTRT_ETHERTYPE_Val _U_(0x1) /**< (GMAC_ST2CW1) Offset from the byte after the EtherType field */ 139 #define GMAC_ST2CW1_OFFSSTRT_IP_Val _U_(0x2) /**< (GMAC_ST2CW1) Offset from the byte after the IP header field */ 140 #define GMAC_ST2CW1_OFFSSTRT_TCP_UDP_Val _U_(0x3) /**< (GMAC_ST2CW1) Offset from the byte after the TCP/UDP header field */ 141 #define GMAC_ST2CW1_OFFSSTRT_FRAMESTART (GMAC_ST2CW1_OFFSSTRT_FRAMESTART_Val << GMAC_ST2CW1_OFFSSTRT_Pos) /**< (GMAC_ST2CW1) Offset from the start of the frame Position */ 142 #define GMAC_ST2CW1_OFFSSTRT_ETHERTYPE (GMAC_ST2CW1_OFFSSTRT_ETHERTYPE_Val << GMAC_ST2CW1_OFFSSTRT_Pos) /**< (GMAC_ST2CW1) Offset from the byte after the EtherType field Position */ 143 #define GMAC_ST2CW1_OFFSSTRT_IP (GMAC_ST2CW1_OFFSSTRT_IP_Val << GMAC_ST2CW1_OFFSSTRT_Pos) /**< (GMAC_ST2CW1) Offset from the byte after the IP header field Position */ 144 #define GMAC_ST2CW1_OFFSSTRT_TCP_UDP (GMAC_ST2CW1_OFFSSTRT_TCP_UDP_Val << GMAC_ST2CW1_OFFSSTRT_Pos) /**< (GMAC_ST2CW1) Offset from the byte after the TCP/UDP header field Position */ 145 #define GMAC_ST2CW1_MASK _U_(0x1FF) /**< \deprecated (GMAC_ST2CW1) Register MASK (Use GMAC_ST2CW1_Msk instead) */ 146 #define GMAC_ST2CW1_Msk _U_(0x1FF) /**< (GMAC_ST2CW1) Register Mask */ 147 148 149 /* -------- GMAC_NCR : (GMAC Offset: 0x00) (R/W 32) Network Control Register -------- */ 150 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 151 #if COMPONENT_TYPEDEF_STYLE == 'N' 152 typedef union { 153 struct { 154 uint32_t :1; /**< bit: 0 Reserved */ 155 uint32_t LBL:1; /**< bit: 1 Loop Back Local */ 156 uint32_t RXEN:1; /**< bit: 2 Receive Enable */ 157 uint32_t TXEN:1; /**< bit: 3 Transmit Enable */ 158 uint32_t MPE:1; /**< bit: 4 Management Port Enable */ 159 uint32_t CLRSTAT:1; /**< bit: 5 Clear Statistics Registers */ 160 uint32_t INCSTAT:1; /**< bit: 6 Increment Statistics Registers */ 161 uint32_t WESTAT:1; /**< bit: 7 Write Enable for Statistics Registers */ 162 uint32_t BP:1; /**< bit: 8 Back pressure */ 163 uint32_t TSTART:1; /**< bit: 9 Start Transmission */ 164 uint32_t THALT:1; /**< bit: 10 Transmit Halt */ 165 uint32_t TXPF:1; /**< bit: 11 Transmit Pause Frame */ 166 uint32_t TXZQPF:1; /**< bit: 12 Transmit Zero Quantum Pause Frame */ 167 uint32_t :2; /**< bit: 13..14 Reserved */ 168 uint32_t SRTSM:1; /**< bit: 15 Store Receive Time Stamp to Memory */ 169 uint32_t ENPBPR:1; /**< bit: 16 Enable PFC Priority-based Pause Reception */ 170 uint32_t TXPBPF:1; /**< bit: 17 Transmit PFC Priority-based Pause Frame */ 171 uint32_t FNP:1; /**< bit: 18 Flush Next Packet */ 172 uint32_t TXLPIEN:1; /**< bit: 19 Enable LPI Transmission */ 173 uint32_t :12; /**< bit: 20..31 Reserved */ 174 } bit; /**< Structure used for bit access */ 175 uint32_t reg; /**< Type used for register access */ 176 } GMAC_NCR_Type; 177 #endif 178 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 179 180 #define GMAC_NCR_OFFSET (0x00) /**< (GMAC_NCR) Network Control Register Offset */ 181 182 #define GMAC_NCR_LBL_Pos 1 /**< (GMAC_NCR) Loop Back Local Position */ 183 #define GMAC_NCR_LBL_Msk (_U_(0x1) << GMAC_NCR_LBL_Pos) /**< (GMAC_NCR) Loop Back Local Mask */ 184 #define GMAC_NCR_LBL GMAC_NCR_LBL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCR_LBL_Msk instead */ 185 #define GMAC_NCR_RXEN_Pos 2 /**< (GMAC_NCR) Receive Enable Position */ 186 #define GMAC_NCR_RXEN_Msk (_U_(0x1) << GMAC_NCR_RXEN_Pos) /**< (GMAC_NCR) Receive Enable Mask */ 187 #define GMAC_NCR_RXEN GMAC_NCR_RXEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCR_RXEN_Msk instead */ 188 #define GMAC_NCR_TXEN_Pos 3 /**< (GMAC_NCR) Transmit Enable Position */ 189 #define GMAC_NCR_TXEN_Msk (_U_(0x1) << GMAC_NCR_TXEN_Pos) /**< (GMAC_NCR) Transmit Enable Mask */ 190 #define GMAC_NCR_TXEN GMAC_NCR_TXEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCR_TXEN_Msk instead */ 191 #define GMAC_NCR_MPE_Pos 4 /**< (GMAC_NCR) Management Port Enable Position */ 192 #define GMAC_NCR_MPE_Msk (_U_(0x1) << GMAC_NCR_MPE_Pos) /**< (GMAC_NCR) Management Port Enable Mask */ 193 #define GMAC_NCR_MPE GMAC_NCR_MPE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCR_MPE_Msk instead */ 194 #define GMAC_NCR_CLRSTAT_Pos 5 /**< (GMAC_NCR) Clear Statistics Registers Position */ 195 #define GMAC_NCR_CLRSTAT_Msk (_U_(0x1) << GMAC_NCR_CLRSTAT_Pos) /**< (GMAC_NCR) Clear Statistics Registers Mask */ 196 #define GMAC_NCR_CLRSTAT GMAC_NCR_CLRSTAT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCR_CLRSTAT_Msk instead */ 197 #define GMAC_NCR_INCSTAT_Pos 6 /**< (GMAC_NCR) Increment Statistics Registers Position */ 198 #define GMAC_NCR_INCSTAT_Msk (_U_(0x1) << GMAC_NCR_INCSTAT_Pos) /**< (GMAC_NCR) Increment Statistics Registers Mask */ 199 #define GMAC_NCR_INCSTAT GMAC_NCR_INCSTAT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCR_INCSTAT_Msk instead */ 200 #define GMAC_NCR_WESTAT_Pos 7 /**< (GMAC_NCR) Write Enable for Statistics Registers Position */ 201 #define GMAC_NCR_WESTAT_Msk (_U_(0x1) << GMAC_NCR_WESTAT_Pos) /**< (GMAC_NCR) Write Enable for Statistics Registers Mask */ 202 #define GMAC_NCR_WESTAT GMAC_NCR_WESTAT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCR_WESTAT_Msk instead */ 203 #define GMAC_NCR_BP_Pos 8 /**< (GMAC_NCR) Back pressure Position */ 204 #define GMAC_NCR_BP_Msk (_U_(0x1) << GMAC_NCR_BP_Pos) /**< (GMAC_NCR) Back pressure Mask */ 205 #define GMAC_NCR_BP GMAC_NCR_BP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCR_BP_Msk instead */ 206 #define GMAC_NCR_TSTART_Pos 9 /**< (GMAC_NCR) Start Transmission Position */ 207 #define GMAC_NCR_TSTART_Msk (_U_(0x1) << GMAC_NCR_TSTART_Pos) /**< (GMAC_NCR) Start Transmission Mask */ 208 #define GMAC_NCR_TSTART GMAC_NCR_TSTART_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCR_TSTART_Msk instead */ 209 #define GMAC_NCR_THALT_Pos 10 /**< (GMAC_NCR) Transmit Halt Position */ 210 #define GMAC_NCR_THALT_Msk (_U_(0x1) << GMAC_NCR_THALT_Pos) /**< (GMAC_NCR) Transmit Halt Mask */ 211 #define GMAC_NCR_THALT GMAC_NCR_THALT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCR_THALT_Msk instead */ 212 #define GMAC_NCR_TXPF_Pos 11 /**< (GMAC_NCR) Transmit Pause Frame Position */ 213 #define GMAC_NCR_TXPF_Msk (_U_(0x1) << GMAC_NCR_TXPF_Pos) /**< (GMAC_NCR) Transmit Pause Frame Mask */ 214 #define GMAC_NCR_TXPF GMAC_NCR_TXPF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCR_TXPF_Msk instead */ 215 #define GMAC_NCR_TXZQPF_Pos 12 /**< (GMAC_NCR) Transmit Zero Quantum Pause Frame Position */ 216 #define GMAC_NCR_TXZQPF_Msk (_U_(0x1) << GMAC_NCR_TXZQPF_Pos) /**< (GMAC_NCR) Transmit Zero Quantum Pause Frame Mask */ 217 #define GMAC_NCR_TXZQPF GMAC_NCR_TXZQPF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCR_TXZQPF_Msk instead */ 218 #define GMAC_NCR_SRTSM_Pos 15 /**< (GMAC_NCR) Store Receive Time Stamp to Memory Position */ 219 #define GMAC_NCR_SRTSM_Msk (_U_(0x1) << GMAC_NCR_SRTSM_Pos) /**< (GMAC_NCR) Store Receive Time Stamp to Memory Mask */ 220 #define GMAC_NCR_SRTSM GMAC_NCR_SRTSM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCR_SRTSM_Msk instead */ 221 #define GMAC_NCR_ENPBPR_Pos 16 /**< (GMAC_NCR) Enable PFC Priority-based Pause Reception Position */ 222 #define GMAC_NCR_ENPBPR_Msk (_U_(0x1) << GMAC_NCR_ENPBPR_Pos) /**< (GMAC_NCR) Enable PFC Priority-based Pause Reception Mask */ 223 #define GMAC_NCR_ENPBPR GMAC_NCR_ENPBPR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCR_ENPBPR_Msk instead */ 224 #define GMAC_NCR_TXPBPF_Pos 17 /**< (GMAC_NCR) Transmit PFC Priority-based Pause Frame Position */ 225 #define GMAC_NCR_TXPBPF_Msk (_U_(0x1) << GMAC_NCR_TXPBPF_Pos) /**< (GMAC_NCR) Transmit PFC Priority-based Pause Frame Mask */ 226 #define GMAC_NCR_TXPBPF GMAC_NCR_TXPBPF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCR_TXPBPF_Msk instead */ 227 #define GMAC_NCR_FNP_Pos 18 /**< (GMAC_NCR) Flush Next Packet Position */ 228 #define GMAC_NCR_FNP_Msk (_U_(0x1) << GMAC_NCR_FNP_Pos) /**< (GMAC_NCR) Flush Next Packet Mask */ 229 #define GMAC_NCR_FNP GMAC_NCR_FNP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCR_FNP_Msk instead */ 230 #define GMAC_NCR_TXLPIEN_Pos 19 /**< (GMAC_NCR) Enable LPI Transmission Position */ 231 #define GMAC_NCR_TXLPIEN_Msk (_U_(0x1) << GMAC_NCR_TXLPIEN_Pos) /**< (GMAC_NCR) Enable LPI Transmission Mask */ 232 #define GMAC_NCR_TXLPIEN GMAC_NCR_TXLPIEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCR_TXLPIEN_Msk instead */ 233 #define GMAC_NCR_MASK _U_(0xF9FFE) /**< \deprecated (GMAC_NCR) Register MASK (Use GMAC_NCR_Msk instead) */ 234 #define GMAC_NCR_Msk _U_(0xF9FFE) /**< (GMAC_NCR) Register Mask */ 235 236 237 /* -------- GMAC_NCFGR : (GMAC Offset: 0x04) (R/W 32) Network Configuration Register -------- */ 238 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 239 #if COMPONENT_TYPEDEF_STYLE == 'N' 240 typedef union { 241 struct { 242 uint32_t SPD:1; /**< bit: 0 Speed */ 243 uint32_t FD:1; /**< bit: 1 Full Duplex */ 244 uint32_t DNVLAN:1; /**< bit: 2 Discard Non-VLAN FRAMES */ 245 uint32_t JFRAME:1; /**< bit: 3 Jumbo Frame Size */ 246 uint32_t CAF:1; /**< bit: 4 Copy All Frames */ 247 uint32_t NBC:1; /**< bit: 5 No Broadcast */ 248 uint32_t MTIHEN:1; /**< bit: 6 Multicast Hash Enable */ 249 uint32_t UNIHEN:1; /**< bit: 7 Unicast Hash Enable */ 250 uint32_t MAXFS:1; /**< bit: 8 1536 Maximum Frame Size */ 251 uint32_t :3; /**< bit: 9..11 Reserved */ 252 uint32_t RTY:1; /**< bit: 12 Retry Test */ 253 uint32_t PEN:1; /**< bit: 13 Pause Enable */ 254 uint32_t RXBUFO:2; /**< bit: 14..15 Receive Buffer Offset */ 255 uint32_t LFERD:1; /**< bit: 16 Length Field Error Frame Discard */ 256 uint32_t RFCS:1; /**< bit: 17 Remove FCS */ 257 uint32_t CLK:3; /**< bit: 18..20 MDC CLock Division */ 258 uint32_t DBW:2; /**< bit: 21..22 Data Bus Width */ 259 uint32_t DCPF:1; /**< bit: 23 Disable Copy of Pause Frames */ 260 uint32_t RXCOEN:1; /**< bit: 24 Receive Checksum Offload Enable */ 261 uint32_t EFRHD:1; /**< bit: 25 Enable Frames Received in Half Duplex */ 262 uint32_t IRXFCS:1; /**< bit: 26 Ignore RX FCS */ 263 uint32_t :1; /**< bit: 27 Reserved */ 264 uint32_t IPGSEN:1; /**< bit: 28 IP Stretch Enable */ 265 uint32_t RXBP:1; /**< bit: 29 Receive Bad Preamble */ 266 uint32_t IRXER:1; /**< bit: 30 Ignore IPG GRXER */ 267 uint32_t :1; /**< bit: 31 Reserved */ 268 } bit; /**< Structure used for bit access */ 269 uint32_t reg; /**< Type used for register access */ 270 } GMAC_NCFGR_Type; 271 #endif 272 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 273 274 #define GMAC_NCFGR_OFFSET (0x04) /**< (GMAC_NCFGR) Network Configuration Register Offset */ 275 276 #define GMAC_NCFGR_SPD_Pos 0 /**< (GMAC_NCFGR) Speed Position */ 277 #define GMAC_NCFGR_SPD_Msk (_U_(0x1) << GMAC_NCFGR_SPD_Pos) /**< (GMAC_NCFGR) Speed Mask */ 278 #define GMAC_NCFGR_SPD GMAC_NCFGR_SPD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCFGR_SPD_Msk instead */ 279 #define GMAC_NCFGR_FD_Pos 1 /**< (GMAC_NCFGR) Full Duplex Position */ 280 #define GMAC_NCFGR_FD_Msk (_U_(0x1) << GMAC_NCFGR_FD_Pos) /**< (GMAC_NCFGR) Full Duplex Mask */ 281 #define GMAC_NCFGR_FD GMAC_NCFGR_FD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCFGR_FD_Msk instead */ 282 #define GMAC_NCFGR_DNVLAN_Pos 2 /**< (GMAC_NCFGR) Discard Non-VLAN FRAMES Position */ 283 #define GMAC_NCFGR_DNVLAN_Msk (_U_(0x1) << GMAC_NCFGR_DNVLAN_Pos) /**< (GMAC_NCFGR) Discard Non-VLAN FRAMES Mask */ 284 #define GMAC_NCFGR_DNVLAN GMAC_NCFGR_DNVLAN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCFGR_DNVLAN_Msk instead */ 285 #define GMAC_NCFGR_JFRAME_Pos 3 /**< (GMAC_NCFGR) Jumbo Frame Size Position */ 286 #define GMAC_NCFGR_JFRAME_Msk (_U_(0x1) << GMAC_NCFGR_JFRAME_Pos) /**< (GMAC_NCFGR) Jumbo Frame Size Mask */ 287 #define GMAC_NCFGR_JFRAME GMAC_NCFGR_JFRAME_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCFGR_JFRAME_Msk instead */ 288 #define GMAC_NCFGR_CAF_Pos 4 /**< (GMAC_NCFGR) Copy All Frames Position */ 289 #define GMAC_NCFGR_CAF_Msk (_U_(0x1) << GMAC_NCFGR_CAF_Pos) /**< (GMAC_NCFGR) Copy All Frames Mask */ 290 #define GMAC_NCFGR_CAF GMAC_NCFGR_CAF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCFGR_CAF_Msk instead */ 291 #define GMAC_NCFGR_NBC_Pos 5 /**< (GMAC_NCFGR) No Broadcast Position */ 292 #define GMAC_NCFGR_NBC_Msk (_U_(0x1) << GMAC_NCFGR_NBC_Pos) /**< (GMAC_NCFGR) No Broadcast Mask */ 293 #define GMAC_NCFGR_NBC GMAC_NCFGR_NBC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCFGR_NBC_Msk instead */ 294 #define GMAC_NCFGR_MTIHEN_Pos 6 /**< (GMAC_NCFGR) Multicast Hash Enable Position */ 295 #define GMAC_NCFGR_MTIHEN_Msk (_U_(0x1) << GMAC_NCFGR_MTIHEN_Pos) /**< (GMAC_NCFGR) Multicast Hash Enable Mask */ 296 #define GMAC_NCFGR_MTIHEN GMAC_NCFGR_MTIHEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCFGR_MTIHEN_Msk instead */ 297 #define GMAC_NCFGR_UNIHEN_Pos 7 /**< (GMAC_NCFGR) Unicast Hash Enable Position */ 298 #define GMAC_NCFGR_UNIHEN_Msk (_U_(0x1) << GMAC_NCFGR_UNIHEN_Pos) /**< (GMAC_NCFGR) Unicast Hash Enable Mask */ 299 #define GMAC_NCFGR_UNIHEN GMAC_NCFGR_UNIHEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCFGR_UNIHEN_Msk instead */ 300 #define GMAC_NCFGR_MAXFS_Pos 8 /**< (GMAC_NCFGR) 1536 Maximum Frame Size Position */ 301 #define GMAC_NCFGR_MAXFS_Msk (_U_(0x1) << GMAC_NCFGR_MAXFS_Pos) /**< (GMAC_NCFGR) 1536 Maximum Frame Size Mask */ 302 #define GMAC_NCFGR_MAXFS GMAC_NCFGR_MAXFS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCFGR_MAXFS_Msk instead */ 303 #define GMAC_NCFGR_RTY_Pos 12 /**< (GMAC_NCFGR) Retry Test Position */ 304 #define GMAC_NCFGR_RTY_Msk (_U_(0x1) << GMAC_NCFGR_RTY_Pos) /**< (GMAC_NCFGR) Retry Test Mask */ 305 #define GMAC_NCFGR_RTY GMAC_NCFGR_RTY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCFGR_RTY_Msk instead */ 306 #define GMAC_NCFGR_PEN_Pos 13 /**< (GMAC_NCFGR) Pause Enable Position */ 307 #define GMAC_NCFGR_PEN_Msk (_U_(0x1) << GMAC_NCFGR_PEN_Pos) /**< (GMAC_NCFGR) Pause Enable Mask */ 308 #define GMAC_NCFGR_PEN GMAC_NCFGR_PEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCFGR_PEN_Msk instead */ 309 #define GMAC_NCFGR_RXBUFO_Pos 14 /**< (GMAC_NCFGR) Receive Buffer Offset Position */ 310 #define GMAC_NCFGR_RXBUFO_Msk (_U_(0x3) << GMAC_NCFGR_RXBUFO_Pos) /**< (GMAC_NCFGR) Receive Buffer Offset Mask */ 311 #define GMAC_NCFGR_RXBUFO(value) (GMAC_NCFGR_RXBUFO_Msk & ((value) << GMAC_NCFGR_RXBUFO_Pos)) 312 #define GMAC_NCFGR_LFERD_Pos 16 /**< (GMAC_NCFGR) Length Field Error Frame Discard Position */ 313 #define GMAC_NCFGR_LFERD_Msk (_U_(0x1) << GMAC_NCFGR_LFERD_Pos) /**< (GMAC_NCFGR) Length Field Error Frame Discard Mask */ 314 #define GMAC_NCFGR_LFERD GMAC_NCFGR_LFERD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCFGR_LFERD_Msk instead */ 315 #define GMAC_NCFGR_RFCS_Pos 17 /**< (GMAC_NCFGR) Remove FCS Position */ 316 #define GMAC_NCFGR_RFCS_Msk (_U_(0x1) << GMAC_NCFGR_RFCS_Pos) /**< (GMAC_NCFGR) Remove FCS Mask */ 317 #define GMAC_NCFGR_RFCS GMAC_NCFGR_RFCS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCFGR_RFCS_Msk instead */ 318 #define GMAC_NCFGR_CLK_Pos 18 /**< (GMAC_NCFGR) MDC CLock Division Position */ 319 #define GMAC_NCFGR_CLK_Msk (_U_(0x7) << GMAC_NCFGR_CLK_Pos) /**< (GMAC_NCFGR) MDC CLock Division Mask */ 320 #define GMAC_NCFGR_CLK(value) (GMAC_NCFGR_CLK_Msk & ((value) << GMAC_NCFGR_CLK_Pos)) 321 #define GMAC_NCFGR_CLK_MCK_8_Val _U_(0x0) /**< (GMAC_NCFGR) MCK divided by 8 (MCK up to 20 MHz) */ 322 #define GMAC_NCFGR_CLK_MCK_16_Val _U_(0x1) /**< (GMAC_NCFGR) MCK divided by 16 (MCK up to 40 MHz) */ 323 #define GMAC_NCFGR_CLK_MCK_32_Val _U_(0x2) /**< (GMAC_NCFGR) MCK divided by 32 (MCK up to 80 MHz) */ 324 #define GMAC_NCFGR_CLK_MCK_48_Val _U_(0x3) /**< (GMAC_NCFGR) MCK divided by 48 (MCK up to 120 MHz) */ 325 #define GMAC_NCFGR_CLK_MCK_64_Val _U_(0x4) /**< (GMAC_NCFGR) MCK divided by 64 (MCK up to 160 MHz) */ 326 #define GMAC_NCFGR_CLK_MCK_96_Val _U_(0x5) /**< (GMAC_NCFGR) MCK divided by 96 (MCK up to 240 MHz) */ 327 #define GMAC_NCFGR_CLK_MCK_8 (GMAC_NCFGR_CLK_MCK_8_Val << GMAC_NCFGR_CLK_Pos) /**< (GMAC_NCFGR) MCK divided by 8 (MCK up to 20 MHz) Position */ 328 #define GMAC_NCFGR_CLK_MCK_16 (GMAC_NCFGR_CLK_MCK_16_Val << GMAC_NCFGR_CLK_Pos) /**< (GMAC_NCFGR) MCK divided by 16 (MCK up to 40 MHz) Position */ 329 #define GMAC_NCFGR_CLK_MCK_32 (GMAC_NCFGR_CLK_MCK_32_Val << GMAC_NCFGR_CLK_Pos) /**< (GMAC_NCFGR) MCK divided by 32 (MCK up to 80 MHz) Position */ 330 #define GMAC_NCFGR_CLK_MCK_48 (GMAC_NCFGR_CLK_MCK_48_Val << GMAC_NCFGR_CLK_Pos) /**< (GMAC_NCFGR) MCK divided by 48 (MCK up to 120 MHz) Position */ 331 #define GMAC_NCFGR_CLK_MCK_64 (GMAC_NCFGR_CLK_MCK_64_Val << GMAC_NCFGR_CLK_Pos) /**< (GMAC_NCFGR) MCK divided by 64 (MCK up to 160 MHz) Position */ 332 #define GMAC_NCFGR_CLK_MCK_96 (GMAC_NCFGR_CLK_MCK_96_Val << GMAC_NCFGR_CLK_Pos) /**< (GMAC_NCFGR) MCK divided by 96 (MCK up to 240 MHz) Position */ 333 #define GMAC_NCFGR_DBW_Pos 21 /**< (GMAC_NCFGR) Data Bus Width Position */ 334 #define GMAC_NCFGR_DBW_Msk (_U_(0x3) << GMAC_NCFGR_DBW_Pos) /**< (GMAC_NCFGR) Data Bus Width Mask */ 335 #define GMAC_NCFGR_DBW(value) (GMAC_NCFGR_DBW_Msk & ((value) << GMAC_NCFGR_DBW_Pos)) 336 #define GMAC_NCFGR_DCPF_Pos 23 /**< (GMAC_NCFGR) Disable Copy of Pause Frames Position */ 337 #define GMAC_NCFGR_DCPF_Msk (_U_(0x1) << GMAC_NCFGR_DCPF_Pos) /**< (GMAC_NCFGR) Disable Copy of Pause Frames Mask */ 338 #define GMAC_NCFGR_DCPF GMAC_NCFGR_DCPF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCFGR_DCPF_Msk instead */ 339 #define GMAC_NCFGR_RXCOEN_Pos 24 /**< (GMAC_NCFGR) Receive Checksum Offload Enable Position */ 340 #define GMAC_NCFGR_RXCOEN_Msk (_U_(0x1) << GMAC_NCFGR_RXCOEN_Pos) /**< (GMAC_NCFGR) Receive Checksum Offload Enable Mask */ 341 #define GMAC_NCFGR_RXCOEN GMAC_NCFGR_RXCOEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCFGR_RXCOEN_Msk instead */ 342 #define GMAC_NCFGR_EFRHD_Pos 25 /**< (GMAC_NCFGR) Enable Frames Received in Half Duplex Position */ 343 #define GMAC_NCFGR_EFRHD_Msk (_U_(0x1) << GMAC_NCFGR_EFRHD_Pos) /**< (GMAC_NCFGR) Enable Frames Received in Half Duplex Mask */ 344 #define GMAC_NCFGR_EFRHD GMAC_NCFGR_EFRHD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCFGR_EFRHD_Msk instead */ 345 #define GMAC_NCFGR_IRXFCS_Pos 26 /**< (GMAC_NCFGR) Ignore RX FCS Position */ 346 #define GMAC_NCFGR_IRXFCS_Msk (_U_(0x1) << GMAC_NCFGR_IRXFCS_Pos) /**< (GMAC_NCFGR) Ignore RX FCS Mask */ 347 #define GMAC_NCFGR_IRXFCS GMAC_NCFGR_IRXFCS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCFGR_IRXFCS_Msk instead */ 348 #define GMAC_NCFGR_IPGSEN_Pos 28 /**< (GMAC_NCFGR) IP Stretch Enable Position */ 349 #define GMAC_NCFGR_IPGSEN_Msk (_U_(0x1) << GMAC_NCFGR_IPGSEN_Pos) /**< (GMAC_NCFGR) IP Stretch Enable Mask */ 350 #define GMAC_NCFGR_IPGSEN GMAC_NCFGR_IPGSEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCFGR_IPGSEN_Msk instead */ 351 #define GMAC_NCFGR_RXBP_Pos 29 /**< (GMAC_NCFGR) Receive Bad Preamble Position */ 352 #define GMAC_NCFGR_RXBP_Msk (_U_(0x1) << GMAC_NCFGR_RXBP_Pos) /**< (GMAC_NCFGR) Receive Bad Preamble Mask */ 353 #define GMAC_NCFGR_RXBP GMAC_NCFGR_RXBP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCFGR_RXBP_Msk instead */ 354 #define GMAC_NCFGR_IRXER_Pos 30 /**< (GMAC_NCFGR) Ignore IPG GRXER Position */ 355 #define GMAC_NCFGR_IRXER_Msk (_U_(0x1) << GMAC_NCFGR_IRXER_Pos) /**< (GMAC_NCFGR) Ignore IPG GRXER Mask */ 356 #define GMAC_NCFGR_IRXER GMAC_NCFGR_IRXER_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCFGR_IRXER_Msk instead */ 357 #define GMAC_NCFGR_MASK _U_(0x77FFF1FF) /**< \deprecated (GMAC_NCFGR) Register MASK (Use GMAC_NCFGR_Msk instead) */ 358 #define GMAC_NCFGR_Msk _U_(0x77FFF1FF) /**< (GMAC_NCFGR) Register Mask */ 359 360 361 /* -------- GMAC_NSR : (GMAC Offset: 0x08) (R/ 32) Network Status Register -------- */ 362 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 363 #if COMPONENT_TYPEDEF_STYLE == 'N' 364 typedef union { 365 struct { 366 uint32_t :1; /**< bit: 0 Reserved */ 367 uint32_t MDIO:1; /**< bit: 1 MDIO Input Status */ 368 uint32_t IDLE:1; /**< bit: 2 PHY Management Logic Idle */ 369 uint32_t :4; /**< bit: 3..6 Reserved */ 370 uint32_t RXLPIS:1; /**< bit: 7 LPI Indication */ 371 uint32_t :24; /**< bit: 8..31 Reserved */ 372 } bit; /**< Structure used for bit access */ 373 uint32_t reg; /**< Type used for register access */ 374 } GMAC_NSR_Type; 375 #endif 376 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 377 378 #define GMAC_NSR_OFFSET (0x08) /**< (GMAC_NSR) Network Status Register Offset */ 379 380 #define GMAC_NSR_MDIO_Pos 1 /**< (GMAC_NSR) MDIO Input Status Position */ 381 #define GMAC_NSR_MDIO_Msk (_U_(0x1) << GMAC_NSR_MDIO_Pos) /**< (GMAC_NSR) MDIO Input Status Mask */ 382 #define GMAC_NSR_MDIO GMAC_NSR_MDIO_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NSR_MDIO_Msk instead */ 383 #define GMAC_NSR_IDLE_Pos 2 /**< (GMAC_NSR) PHY Management Logic Idle Position */ 384 #define GMAC_NSR_IDLE_Msk (_U_(0x1) << GMAC_NSR_IDLE_Pos) /**< (GMAC_NSR) PHY Management Logic Idle Mask */ 385 #define GMAC_NSR_IDLE GMAC_NSR_IDLE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NSR_IDLE_Msk instead */ 386 #define GMAC_NSR_RXLPIS_Pos 7 /**< (GMAC_NSR) LPI Indication Position */ 387 #define GMAC_NSR_RXLPIS_Msk (_U_(0x1) << GMAC_NSR_RXLPIS_Pos) /**< (GMAC_NSR) LPI Indication Mask */ 388 #define GMAC_NSR_RXLPIS GMAC_NSR_RXLPIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NSR_RXLPIS_Msk instead */ 389 #define GMAC_NSR_MASK _U_(0x86) /**< \deprecated (GMAC_NSR) Register MASK (Use GMAC_NSR_Msk instead) */ 390 #define GMAC_NSR_Msk _U_(0x86) /**< (GMAC_NSR) Register Mask */ 391 392 393 /* -------- GMAC_UR : (GMAC Offset: 0x0c) (R/W 32) User Register -------- */ 394 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 395 #if COMPONENT_TYPEDEF_STYLE == 'N' 396 typedef union { 397 struct { 398 uint32_t RMII:1; /**< bit: 0 Reduced MII Mode */ 399 uint32_t :31; /**< bit: 1..31 Reserved */ 400 } bit; /**< Structure used for bit access */ 401 uint32_t reg; /**< Type used for register access */ 402 } GMAC_UR_Type; 403 #endif 404 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 405 406 #define GMAC_UR_OFFSET (0x0C) /**< (GMAC_UR) User Register Offset */ 407 408 #define GMAC_UR_RMII_Pos 0 /**< (GMAC_UR) Reduced MII Mode Position */ 409 #define GMAC_UR_RMII_Msk (_U_(0x1) << GMAC_UR_RMII_Pos) /**< (GMAC_UR) Reduced MII Mode Mask */ 410 #define GMAC_UR_RMII GMAC_UR_RMII_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_UR_RMII_Msk instead */ 411 #define GMAC_UR_MASK _U_(0x01) /**< \deprecated (GMAC_UR) Register MASK (Use GMAC_UR_Msk instead) */ 412 #define GMAC_UR_Msk _U_(0x01) /**< (GMAC_UR) Register Mask */ 413 414 415 /* -------- GMAC_DCFGR : (GMAC Offset: 0x10) (R/W 32) DMA Configuration Register -------- */ 416 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 417 #if COMPONENT_TYPEDEF_STYLE == 'N' 418 typedef union { 419 struct { 420 uint32_t FBLDO:5; /**< bit: 0..4 Fixed Burst Length for DMA Data Operations: */ 421 uint32_t :1; /**< bit: 5 Reserved */ 422 uint32_t ESMA:1; /**< bit: 6 Endian Swap Mode Enable for Management Descriptor Accesses */ 423 uint32_t ESPA:1; /**< bit: 7 Endian Swap Mode Enable for Packet Data Accesses */ 424 uint32_t RXBMS:2; /**< bit: 8..9 Receiver Packet Buffer Memory Size Select */ 425 uint32_t TXPBMS:1; /**< bit: 10 Transmitter Packet Buffer Memory Size Select */ 426 uint32_t TXCOEN:1; /**< bit: 11 Transmitter Checksum Generation Offload Enable */ 427 uint32_t :4; /**< bit: 12..15 Reserved */ 428 uint32_t DRBS:8; /**< bit: 16..23 DMA Receive Buffer Size */ 429 uint32_t DDRP:1; /**< bit: 24 DMA Discard Receive Packets */ 430 uint32_t :7; /**< bit: 25..31 Reserved */ 431 } bit; /**< Structure used for bit access */ 432 uint32_t reg; /**< Type used for register access */ 433 } GMAC_DCFGR_Type; 434 #endif 435 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 436 437 #define GMAC_DCFGR_OFFSET (0x10) /**< (GMAC_DCFGR) DMA Configuration Register Offset */ 438 439 #define GMAC_DCFGR_FBLDO_Pos 0 /**< (GMAC_DCFGR) Fixed Burst Length for DMA Data Operations: Position */ 440 #define GMAC_DCFGR_FBLDO_Msk (_U_(0x1F) << GMAC_DCFGR_FBLDO_Pos) /**< (GMAC_DCFGR) Fixed Burst Length for DMA Data Operations: Mask */ 441 #define GMAC_DCFGR_FBLDO(value) (GMAC_DCFGR_FBLDO_Msk & ((value) << GMAC_DCFGR_FBLDO_Pos)) 442 #define GMAC_DCFGR_FBLDO_SINGLE_Val _U_(0x1) /**< (GMAC_DCFGR) 00001: Always use SINGLE AHB bursts */ 443 #define GMAC_DCFGR_FBLDO_INCR4_Val _U_(0x4) /**< (GMAC_DCFGR) 001xx: Attempt to use INCR4 AHB bursts (Default) */ 444 #define GMAC_DCFGR_FBLDO_INCR8_Val _U_(0x8) /**< (GMAC_DCFGR) 01xxx: Attempt to use INCR8 AHB bursts */ 445 #define GMAC_DCFGR_FBLDO_INCR16_Val _U_(0x10) /**< (GMAC_DCFGR) 1xxxx: Attempt to use INCR16 AHB bursts */ 446 #define GMAC_DCFGR_FBLDO_SINGLE (GMAC_DCFGR_FBLDO_SINGLE_Val << GMAC_DCFGR_FBLDO_Pos) /**< (GMAC_DCFGR) 00001: Always use SINGLE AHB bursts Position */ 447 #define GMAC_DCFGR_FBLDO_INCR4 (GMAC_DCFGR_FBLDO_INCR4_Val << GMAC_DCFGR_FBLDO_Pos) /**< (GMAC_DCFGR) 001xx: Attempt to use INCR4 AHB bursts (Default) Position */ 448 #define GMAC_DCFGR_FBLDO_INCR8 (GMAC_DCFGR_FBLDO_INCR8_Val << GMAC_DCFGR_FBLDO_Pos) /**< (GMAC_DCFGR) 01xxx: Attempt to use INCR8 AHB bursts Position */ 449 #define GMAC_DCFGR_FBLDO_INCR16 (GMAC_DCFGR_FBLDO_INCR16_Val << GMAC_DCFGR_FBLDO_Pos) /**< (GMAC_DCFGR) 1xxxx: Attempt to use INCR16 AHB bursts Position */ 450 #define GMAC_DCFGR_ESMA_Pos 6 /**< (GMAC_DCFGR) Endian Swap Mode Enable for Management Descriptor Accesses Position */ 451 #define GMAC_DCFGR_ESMA_Msk (_U_(0x1) << GMAC_DCFGR_ESMA_Pos) /**< (GMAC_DCFGR) Endian Swap Mode Enable for Management Descriptor Accesses Mask */ 452 #define GMAC_DCFGR_ESMA GMAC_DCFGR_ESMA_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_DCFGR_ESMA_Msk instead */ 453 #define GMAC_DCFGR_ESPA_Pos 7 /**< (GMAC_DCFGR) Endian Swap Mode Enable for Packet Data Accesses Position */ 454 #define GMAC_DCFGR_ESPA_Msk (_U_(0x1) << GMAC_DCFGR_ESPA_Pos) /**< (GMAC_DCFGR) Endian Swap Mode Enable for Packet Data Accesses Mask */ 455 #define GMAC_DCFGR_ESPA GMAC_DCFGR_ESPA_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_DCFGR_ESPA_Msk instead */ 456 #define GMAC_DCFGR_RXBMS_Pos 8 /**< (GMAC_DCFGR) Receiver Packet Buffer Memory Size Select Position */ 457 #define GMAC_DCFGR_RXBMS_Msk (_U_(0x3) << GMAC_DCFGR_RXBMS_Pos) /**< (GMAC_DCFGR) Receiver Packet Buffer Memory Size Select Mask */ 458 #define GMAC_DCFGR_RXBMS(value) (GMAC_DCFGR_RXBMS_Msk & ((value) << GMAC_DCFGR_RXBMS_Pos)) 459 #define GMAC_DCFGR_RXBMS_EIGHTH_Val _U_(0x0) /**< (GMAC_DCFGR) 4/8 Kbyte Memory Size */ 460 #define GMAC_DCFGR_RXBMS_QUARTER_Val _U_(0x1) /**< (GMAC_DCFGR) 4/4 Kbytes Memory Size */ 461 #define GMAC_DCFGR_RXBMS_HALF_Val _U_(0x2) /**< (GMAC_DCFGR) 4/2 Kbytes Memory Size */ 462 #define GMAC_DCFGR_RXBMS_FULL_Val _U_(0x3) /**< (GMAC_DCFGR) 4 Kbytes Memory Size */ 463 #define GMAC_DCFGR_RXBMS_EIGHTH (GMAC_DCFGR_RXBMS_EIGHTH_Val << GMAC_DCFGR_RXBMS_Pos) /**< (GMAC_DCFGR) 4/8 Kbyte Memory Size Position */ 464 #define GMAC_DCFGR_RXBMS_QUARTER (GMAC_DCFGR_RXBMS_QUARTER_Val << GMAC_DCFGR_RXBMS_Pos) /**< (GMAC_DCFGR) 4/4 Kbytes Memory Size Position */ 465 #define GMAC_DCFGR_RXBMS_HALF (GMAC_DCFGR_RXBMS_HALF_Val << GMAC_DCFGR_RXBMS_Pos) /**< (GMAC_DCFGR) 4/2 Kbytes Memory Size Position */ 466 #define GMAC_DCFGR_RXBMS_FULL (GMAC_DCFGR_RXBMS_FULL_Val << GMAC_DCFGR_RXBMS_Pos) /**< (GMAC_DCFGR) 4 Kbytes Memory Size Position */ 467 #define GMAC_DCFGR_TXPBMS_Pos 10 /**< (GMAC_DCFGR) Transmitter Packet Buffer Memory Size Select Position */ 468 #define GMAC_DCFGR_TXPBMS_Msk (_U_(0x1) << GMAC_DCFGR_TXPBMS_Pos) /**< (GMAC_DCFGR) Transmitter Packet Buffer Memory Size Select Mask */ 469 #define GMAC_DCFGR_TXPBMS GMAC_DCFGR_TXPBMS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_DCFGR_TXPBMS_Msk instead */ 470 #define GMAC_DCFGR_TXCOEN_Pos 11 /**< (GMAC_DCFGR) Transmitter Checksum Generation Offload Enable Position */ 471 #define GMAC_DCFGR_TXCOEN_Msk (_U_(0x1) << GMAC_DCFGR_TXCOEN_Pos) /**< (GMAC_DCFGR) Transmitter Checksum Generation Offload Enable Mask */ 472 #define GMAC_DCFGR_TXCOEN GMAC_DCFGR_TXCOEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_DCFGR_TXCOEN_Msk instead */ 473 #define GMAC_DCFGR_DRBS_Pos 16 /**< (GMAC_DCFGR) DMA Receive Buffer Size Position */ 474 #define GMAC_DCFGR_DRBS_Msk (_U_(0xFF) << GMAC_DCFGR_DRBS_Pos) /**< (GMAC_DCFGR) DMA Receive Buffer Size Mask */ 475 #define GMAC_DCFGR_DRBS(value) (GMAC_DCFGR_DRBS_Msk & ((value) << GMAC_DCFGR_DRBS_Pos)) 476 #define GMAC_DCFGR_DDRP_Pos 24 /**< (GMAC_DCFGR) DMA Discard Receive Packets Position */ 477 #define GMAC_DCFGR_DDRP_Msk (_U_(0x1) << GMAC_DCFGR_DDRP_Pos) /**< (GMAC_DCFGR) DMA Discard Receive Packets Mask */ 478 #define GMAC_DCFGR_DDRP GMAC_DCFGR_DDRP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_DCFGR_DDRP_Msk instead */ 479 #define GMAC_DCFGR_MASK _U_(0x1FF0FDF) /**< \deprecated (GMAC_DCFGR) Register MASK (Use GMAC_DCFGR_Msk instead) */ 480 #define GMAC_DCFGR_Msk _U_(0x1FF0FDF) /**< (GMAC_DCFGR) Register Mask */ 481 482 483 /* -------- GMAC_TSR : (GMAC Offset: 0x14) (R/W 32) Transmit Status Register -------- */ 484 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 485 #if COMPONENT_TYPEDEF_STYLE == 'N' 486 typedef union { 487 struct { 488 uint32_t UBR:1; /**< bit: 0 Used Bit Read */ 489 uint32_t COL:1; /**< bit: 1 Collision Occurred */ 490 uint32_t RLE:1; /**< bit: 2 Retry Limit Exceeded */ 491 uint32_t TXGO:1; /**< bit: 3 Transmit Go */ 492 uint32_t TFC:1; /**< bit: 4 Transmit Frame Corruption Due to AHB Error */ 493 uint32_t TXCOMP:1; /**< bit: 5 Transmit Complete */ 494 uint32_t :2; /**< bit: 6..7 Reserved */ 495 uint32_t HRESP:1; /**< bit: 8 HRESP Not OK */ 496 uint32_t :23; /**< bit: 9..31 Reserved */ 497 } bit; /**< Structure used for bit access */ 498 uint32_t reg; /**< Type used for register access */ 499 } GMAC_TSR_Type; 500 #endif 501 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 502 503 #define GMAC_TSR_OFFSET (0x14) /**< (GMAC_TSR) Transmit Status Register Offset */ 504 505 #define GMAC_TSR_UBR_Pos 0 /**< (GMAC_TSR) Used Bit Read Position */ 506 #define GMAC_TSR_UBR_Msk (_U_(0x1) << GMAC_TSR_UBR_Pos) /**< (GMAC_TSR) Used Bit Read Mask */ 507 #define GMAC_TSR_UBR GMAC_TSR_UBR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_TSR_UBR_Msk instead */ 508 #define GMAC_TSR_COL_Pos 1 /**< (GMAC_TSR) Collision Occurred Position */ 509 #define GMAC_TSR_COL_Msk (_U_(0x1) << GMAC_TSR_COL_Pos) /**< (GMAC_TSR) Collision Occurred Mask */ 510 #define GMAC_TSR_COL GMAC_TSR_COL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_TSR_COL_Msk instead */ 511 #define GMAC_TSR_RLE_Pos 2 /**< (GMAC_TSR) Retry Limit Exceeded Position */ 512 #define GMAC_TSR_RLE_Msk (_U_(0x1) << GMAC_TSR_RLE_Pos) /**< (GMAC_TSR) Retry Limit Exceeded Mask */ 513 #define GMAC_TSR_RLE GMAC_TSR_RLE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_TSR_RLE_Msk instead */ 514 #define GMAC_TSR_TXGO_Pos 3 /**< (GMAC_TSR) Transmit Go Position */ 515 #define GMAC_TSR_TXGO_Msk (_U_(0x1) << GMAC_TSR_TXGO_Pos) /**< (GMAC_TSR) Transmit Go Mask */ 516 #define GMAC_TSR_TXGO GMAC_TSR_TXGO_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_TSR_TXGO_Msk instead */ 517 #define GMAC_TSR_TFC_Pos 4 /**< (GMAC_TSR) Transmit Frame Corruption Due to AHB Error Position */ 518 #define GMAC_TSR_TFC_Msk (_U_(0x1) << GMAC_TSR_TFC_Pos) /**< (GMAC_TSR) Transmit Frame Corruption Due to AHB Error Mask */ 519 #define GMAC_TSR_TFC GMAC_TSR_TFC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_TSR_TFC_Msk instead */ 520 #define GMAC_TSR_TXCOMP_Pos 5 /**< (GMAC_TSR) Transmit Complete Position */ 521 #define GMAC_TSR_TXCOMP_Msk (_U_(0x1) << GMAC_TSR_TXCOMP_Pos) /**< (GMAC_TSR) Transmit Complete Mask */ 522 #define GMAC_TSR_TXCOMP GMAC_TSR_TXCOMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_TSR_TXCOMP_Msk instead */ 523 #define GMAC_TSR_HRESP_Pos 8 /**< (GMAC_TSR) HRESP Not OK Position */ 524 #define GMAC_TSR_HRESP_Msk (_U_(0x1) << GMAC_TSR_HRESP_Pos) /**< (GMAC_TSR) HRESP Not OK Mask */ 525 #define GMAC_TSR_HRESP GMAC_TSR_HRESP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_TSR_HRESP_Msk instead */ 526 #define GMAC_TSR_MASK _U_(0x13F) /**< \deprecated (GMAC_TSR) Register MASK (Use GMAC_TSR_Msk instead) */ 527 #define GMAC_TSR_Msk _U_(0x13F) /**< (GMAC_TSR) Register Mask */ 528 529 530 /* -------- GMAC_RBQB : (GMAC Offset: 0x18) (R/W 32) Receive Buffer Queue Base Address Register -------- */ 531 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 532 #if COMPONENT_TYPEDEF_STYLE == 'N' 533 typedef union { 534 struct { 535 uint32_t :2; /**< bit: 0..1 Reserved */ 536 uint32_t ADDR:30; /**< bit: 2..31 Receive Buffer Queue Base Address */ 537 } bit; /**< Structure used for bit access */ 538 uint32_t reg; /**< Type used for register access */ 539 } GMAC_RBQB_Type; 540 #endif 541 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 542 543 #define GMAC_RBQB_OFFSET (0x18) /**< (GMAC_RBQB) Receive Buffer Queue Base Address Register Offset */ 544 545 #define GMAC_RBQB_ADDR_Pos 2 /**< (GMAC_RBQB) Receive Buffer Queue Base Address Position */ 546 #define GMAC_RBQB_ADDR_Msk (_U_(0x3FFFFFFF) << GMAC_RBQB_ADDR_Pos) /**< (GMAC_RBQB) Receive Buffer Queue Base Address Mask */ 547 #define GMAC_RBQB_ADDR(value) (GMAC_RBQB_ADDR_Msk & ((value) << GMAC_RBQB_ADDR_Pos)) 548 #define GMAC_RBQB_MASK _U_(0xFFFFFFFC) /**< \deprecated (GMAC_RBQB) Register MASK (Use GMAC_RBQB_Msk instead) */ 549 #define GMAC_RBQB_Msk _U_(0xFFFFFFFC) /**< (GMAC_RBQB) Register Mask */ 550 551 552 /* -------- GMAC_TBQB : (GMAC Offset: 0x1c) (R/W 32) Transmit Buffer Queue Base Address Register -------- */ 553 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 554 #if COMPONENT_TYPEDEF_STYLE == 'N' 555 typedef union { 556 struct { 557 uint32_t :2; /**< bit: 0..1 Reserved */ 558 uint32_t ADDR:30; /**< bit: 2..31 Transmit Buffer Queue Base Address */ 559 } bit; /**< Structure used for bit access */ 560 uint32_t reg; /**< Type used for register access */ 561 } GMAC_TBQB_Type; 562 #endif 563 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 564 565 #define GMAC_TBQB_OFFSET (0x1C) /**< (GMAC_TBQB) Transmit Buffer Queue Base Address Register Offset */ 566 567 #define GMAC_TBQB_ADDR_Pos 2 /**< (GMAC_TBQB) Transmit Buffer Queue Base Address Position */ 568 #define GMAC_TBQB_ADDR_Msk (_U_(0x3FFFFFFF) << GMAC_TBQB_ADDR_Pos) /**< (GMAC_TBQB) Transmit Buffer Queue Base Address Mask */ 569 #define GMAC_TBQB_ADDR(value) (GMAC_TBQB_ADDR_Msk & ((value) << GMAC_TBQB_ADDR_Pos)) 570 #define GMAC_TBQB_MASK _U_(0xFFFFFFFC) /**< \deprecated (GMAC_TBQB) Register MASK (Use GMAC_TBQB_Msk instead) */ 571 #define GMAC_TBQB_Msk _U_(0xFFFFFFFC) /**< (GMAC_TBQB) Register Mask */ 572 573 574 /* -------- GMAC_RSR : (GMAC Offset: 0x20) (R/W 32) Receive Status Register -------- */ 575 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 576 #if COMPONENT_TYPEDEF_STYLE == 'N' 577 typedef union { 578 struct { 579 uint32_t BNA:1; /**< bit: 0 Buffer Not Available */ 580 uint32_t REC:1; /**< bit: 1 Frame Received */ 581 uint32_t RXOVR:1; /**< bit: 2 Receive Overrun */ 582 uint32_t HNO:1; /**< bit: 3 HRESP Not OK */ 583 uint32_t :28; /**< bit: 4..31 Reserved */ 584 } bit; /**< Structure used for bit access */ 585 uint32_t reg; /**< Type used for register access */ 586 } GMAC_RSR_Type; 587 #endif 588 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 589 590 #define GMAC_RSR_OFFSET (0x20) /**< (GMAC_RSR) Receive Status Register Offset */ 591 592 #define GMAC_RSR_BNA_Pos 0 /**< (GMAC_RSR) Buffer Not Available Position */ 593 #define GMAC_RSR_BNA_Msk (_U_(0x1) << GMAC_RSR_BNA_Pos) /**< (GMAC_RSR) Buffer Not Available Mask */ 594 #define GMAC_RSR_BNA GMAC_RSR_BNA_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_RSR_BNA_Msk instead */ 595 #define GMAC_RSR_REC_Pos 1 /**< (GMAC_RSR) Frame Received Position */ 596 #define GMAC_RSR_REC_Msk (_U_(0x1) << GMAC_RSR_REC_Pos) /**< (GMAC_RSR) Frame Received Mask */ 597 #define GMAC_RSR_REC GMAC_RSR_REC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_RSR_REC_Msk instead */ 598 #define GMAC_RSR_RXOVR_Pos 2 /**< (GMAC_RSR) Receive Overrun Position */ 599 #define GMAC_RSR_RXOVR_Msk (_U_(0x1) << GMAC_RSR_RXOVR_Pos) /**< (GMAC_RSR) Receive Overrun Mask */ 600 #define GMAC_RSR_RXOVR GMAC_RSR_RXOVR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_RSR_RXOVR_Msk instead */ 601 #define GMAC_RSR_HNO_Pos 3 /**< (GMAC_RSR) HRESP Not OK Position */ 602 #define GMAC_RSR_HNO_Msk (_U_(0x1) << GMAC_RSR_HNO_Pos) /**< (GMAC_RSR) HRESP Not OK Mask */ 603 #define GMAC_RSR_HNO GMAC_RSR_HNO_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_RSR_HNO_Msk instead */ 604 #define GMAC_RSR_MASK _U_(0x0F) /**< \deprecated (GMAC_RSR) Register MASK (Use GMAC_RSR_Msk instead) */ 605 #define GMAC_RSR_Msk _U_(0x0F) /**< (GMAC_RSR) Register Mask */ 606 607 608 /* -------- GMAC_ISR : (GMAC Offset: 0x24) (R/ 32) Interrupt Status Register -------- */ 609 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 610 #if COMPONENT_TYPEDEF_STYLE == 'N' 611 typedef union { 612 struct { 613 uint32_t MFS:1; /**< bit: 0 Management Frame Sent */ 614 uint32_t RCOMP:1; /**< bit: 1 Receive Complete */ 615 uint32_t RXUBR:1; /**< bit: 2 RX Used Bit Read */ 616 uint32_t TXUBR:1; /**< bit: 3 TX Used Bit Read */ 617 uint32_t TUR:1; /**< bit: 4 Transmit Underrun */ 618 uint32_t RLEX:1; /**< bit: 5 Retry Limit Exceeded */ 619 uint32_t TFC:1; /**< bit: 6 Transmit Frame Corruption Due to AHB Error */ 620 uint32_t TCOMP:1; /**< bit: 7 Transmit Complete */ 621 uint32_t :2; /**< bit: 8..9 Reserved */ 622 uint32_t ROVR:1; /**< bit: 10 Receive Overrun */ 623 uint32_t HRESP:1; /**< bit: 11 HRESP Not OK */ 624 uint32_t PFNZ:1; /**< bit: 12 Pause Frame with Non-zero Pause Quantum Received */ 625 uint32_t PTZ:1; /**< bit: 13 Pause Time Zero */ 626 uint32_t PFTR:1; /**< bit: 14 Pause Frame Transmitted */ 627 uint32_t :3; /**< bit: 15..17 Reserved */ 628 uint32_t DRQFR:1; /**< bit: 18 PTP Delay Request Frame Received */ 629 uint32_t SFR:1; /**< bit: 19 PTP Sync Frame Received */ 630 uint32_t DRQFT:1; /**< bit: 20 PTP Delay Request Frame Transmitted */ 631 uint32_t SFT:1; /**< bit: 21 PTP Sync Frame Transmitted */ 632 uint32_t PDRQFR:1; /**< bit: 22 PDelay Request Frame Received */ 633 uint32_t PDRSFR:1; /**< bit: 23 PDelay Response Frame Received */ 634 uint32_t PDRQFT:1; /**< bit: 24 PDelay Request Frame Transmitted */ 635 uint32_t PDRSFT:1; /**< bit: 25 PDelay Response Frame Transmitted */ 636 uint32_t SRI:1; /**< bit: 26 TSU Seconds Register Increment */ 637 uint32_t RXLPISBC:1; /**< bit: 27 Receive LPI indication Status Bit Change */ 638 uint32_t WOL:1; /**< bit: 28 Wake On LAN */ 639 uint32_t TSUTIMCOMP:1; /**< bit: 29 TSU Timer Comparison */ 640 uint32_t :2; /**< bit: 30..31 Reserved */ 641 } bit; /**< Structure used for bit access */ 642 uint32_t reg; /**< Type used for register access */ 643 } GMAC_ISR_Type; 644 #endif 645 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 646 647 #define GMAC_ISR_OFFSET (0x24) /**< (GMAC_ISR) Interrupt Status Register Offset */ 648 649 #define GMAC_ISR_MFS_Pos 0 /**< (GMAC_ISR) Management Frame Sent Position */ 650 #define GMAC_ISR_MFS_Msk (_U_(0x1) << GMAC_ISR_MFS_Pos) /**< (GMAC_ISR) Management Frame Sent Mask */ 651 #define GMAC_ISR_MFS GMAC_ISR_MFS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISR_MFS_Msk instead */ 652 #define GMAC_ISR_RCOMP_Pos 1 /**< (GMAC_ISR) Receive Complete Position */ 653 #define GMAC_ISR_RCOMP_Msk (_U_(0x1) << GMAC_ISR_RCOMP_Pos) /**< (GMAC_ISR) Receive Complete Mask */ 654 #define GMAC_ISR_RCOMP GMAC_ISR_RCOMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISR_RCOMP_Msk instead */ 655 #define GMAC_ISR_RXUBR_Pos 2 /**< (GMAC_ISR) RX Used Bit Read Position */ 656 #define GMAC_ISR_RXUBR_Msk (_U_(0x1) << GMAC_ISR_RXUBR_Pos) /**< (GMAC_ISR) RX Used Bit Read Mask */ 657 #define GMAC_ISR_RXUBR GMAC_ISR_RXUBR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISR_RXUBR_Msk instead */ 658 #define GMAC_ISR_TXUBR_Pos 3 /**< (GMAC_ISR) TX Used Bit Read Position */ 659 #define GMAC_ISR_TXUBR_Msk (_U_(0x1) << GMAC_ISR_TXUBR_Pos) /**< (GMAC_ISR) TX Used Bit Read Mask */ 660 #define GMAC_ISR_TXUBR GMAC_ISR_TXUBR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISR_TXUBR_Msk instead */ 661 #define GMAC_ISR_TUR_Pos 4 /**< (GMAC_ISR) Transmit Underrun Position */ 662 #define GMAC_ISR_TUR_Msk (_U_(0x1) << GMAC_ISR_TUR_Pos) /**< (GMAC_ISR) Transmit Underrun Mask */ 663 #define GMAC_ISR_TUR GMAC_ISR_TUR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISR_TUR_Msk instead */ 664 #define GMAC_ISR_RLEX_Pos 5 /**< (GMAC_ISR) Retry Limit Exceeded Position */ 665 #define GMAC_ISR_RLEX_Msk (_U_(0x1) << GMAC_ISR_RLEX_Pos) /**< (GMAC_ISR) Retry Limit Exceeded Mask */ 666 #define GMAC_ISR_RLEX GMAC_ISR_RLEX_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISR_RLEX_Msk instead */ 667 #define GMAC_ISR_TFC_Pos 6 /**< (GMAC_ISR) Transmit Frame Corruption Due to AHB Error Position */ 668 #define GMAC_ISR_TFC_Msk (_U_(0x1) << GMAC_ISR_TFC_Pos) /**< (GMAC_ISR) Transmit Frame Corruption Due to AHB Error Mask */ 669 #define GMAC_ISR_TFC GMAC_ISR_TFC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISR_TFC_Msk instead */ 670 #define GMAC_ISR_TCOMP_Pos 7 /**< (GMAC_ISR) Transmit Complete Position */ 671 #define GMAC_ISR_TCOMP_Msk (_U_(0x1) << GMAC_ISR_TCOMP_Pos) /**< (GMAC_ISR) Transmit Complete Mask */ 672 #define GMAC_ISR_TCOMP GMAC_ISR_TCOMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISR_TCOMP_Msk instead */ 673 #define GMAC_ISR_ROVR_Pos 10 /**< (GMAC_ISR) Receive Overrun Position */ 674 #define GMAC_ISR_ROVR_Msk (_U_(0x1) << GMAC_ISR_ROVR_Pos) /**< (GMAC_ISR) Receive Overrun Mask */ 675 #define GMAC_ISR_ROVR GMAC_ISR_ROVR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISR_ROVR_Msk instead */ 676 #define GMAC_ISR_HRESP_Pos 11 /**< (GMAC_ISR) HRESP Not OK Position */ 677 #define GMAC_ISR_HRESP_Msk (_U_(0x1) << GMAC_ISR_HRESP_Pos) /**< (GMAC_ISR) HRESP Not OK Mask */ 678 #define GMAC_ISR_HRESP GMAC_ISR_HRESP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISR_HRESP_Msk instead */ 679 #define GMAC_ISR_PFNZ_Pos 12 /**< (GMAC_ISR) Pause Frame with Non-zero Pause Quantum Received Position */ 680 #define GMAC_ISR_PFNZ_Msk (_U_(0x1) << GMAC_ISR_PFNZ_Pos) /**< (GMAC_ISR) Pause Frame with Non-zero Pause Quantum Received Mask */ 681 #define GMAC_ISR_PFNZ GMAC_ISR_PFNZ_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISR_PFNZ_Msk instead */ 682 #define GMAC_ISR_PTZ_Pos 13 /**< (GMAC_ISR) Pause Time Zero Position */ 683 #define GMAC_ISR_PTZ_Msk (_U_(0x1) << GMAC_ISR_PTZ_Pos) /**< (GMAC_ISR) Pause Time Zero Mask */ 684 #define GMAC_ISR_PTZ GMAC_ISR_PTZ_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISR_PTZ_Msk instead */ 685 #define GMAC_ISR_PFTR_Pos 14 /**< (GMAC_ISR) Pause Frame Transmitted Position */ 686 #define GMAC_ISR_PFTR_Msk (_U_(0x1) << GMAC_ISR_PFTR_Pos) /**< (GMAC_ISR) Pause Frame Transmitted Mask */ 687 #define GMAC_ISR_PFTR GMAC_ISR_PFTR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISR_PFTR_Msk instead */ 688 #define GMAC_ISR_DRQFR_Pos 18 /**< (GMAC_ISR) PTP Delay Request Frame Received Position */ 689 #define GMAC_ISR_DRQFR_Msk (_U_(0x1) << GMAC_ISR_DRQFR_Pos) /**< (GMAC_ISR) PTP Delay Request Frame Received Mask */ 690 #define GMAC_ISR_DRQFR GMAC_ISR_DRQFR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISR_DRQFR_Msk instead */ 691 #define GMAC_ISR_SFR_Pos 19 /**< (GMAC_ISR) PTP Sync Frame Received Position */ 692 #define GMAC_ISR_SFR_Msk (_U_(0x1) << GMAC_ISR_SFR_Pos) /**< (GMAC_ISR) PTP Sync Frame Received Mask */ 693 #define GMAC_ISR_SFR GMAC_ISR_SFR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISR_SFR_Msk instead */ 694 #define GMAC_ISR_DRQFT_Pos 20 /**< (GMAC_ISR) PTP Delay Request Frame Transmitted Position */ 695 #define GMAC_ISR_DRQFT_Msk (_U_(0x1) << GMAC_ISR_DRQFT_Pos) /**< (GMAC_ISR) PTP Delay Request Frame Transmitted Mask */ 696 #define GMAC_ISR_DRQFT GMAC_ISR_DRQFT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISR_DRQFT_Msk instead */ 697 #define GMAC_ISR_SFT_Pos 21 /**< (GMAC_ISR) PTP Sync Frame Transmitted Position */ 698 #define GMAC_ISR_SFT_Msk (_U_(0x1) << GMAC_ISR_SFT_Pos) /**< (GMAC_ISR) PTP Sync Frame Transmitted Mask */ 699 #define GMAC_ISR_SFT GMAC_ISR_SFT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISR_SFT_Msk instead */ 700 #define GMAC_ISR_PDRQFR_Pos 22 /**< (GMAC_ISR) PDelay Request Frame Received Position */ 701 #define GMAC_ISR_PDRQFR_Msk (_U_(0x1) << GMAC_ISR_PDRQFR_Pos) /**< (GMAC_ISR) PDelay Request Frame Received Mask */ 702 #define GMAC_ISR_PDRQFR GMAC_ISR_PDRQFR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISR_PDRQFR_Msk instead */ 703 #define GMAC_ISR_PDRSFR_Pos 23 /**< (GMAC_ISR) PDelay Response Frame Received Position */ 704 #define GMAC_ISR_PDRSFR_Msk (_U_(0x1) << GMAC_ISR_PDRSFR_Pos) /**< (GMAC_ISR) PDelay Response Frame Received Mask */ 705 #define GMAC_ISR_PDRSFR GMAC_ISR_PDRSFR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISR_PDRSFR_Msk instead */ 706 #define GMAC_ISR_PDRQFT_Pos 24 /**< (GMAC_ISR) PDelay Request Frame Transmitted Position */ 707 #define GMAC_ISR_PDRQFT_Msk (_U_(0x1) << GMAC_ISR_PDRQFT_Pos) /**< (GMAC_ISR) PDelay Request Frame Transmitted Mask */ 708 #define GMAC_ISR_PDRQFT GMAC_ISR_PDRQFT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISR_PDRQFT_Msk instead */ 709 #define GMAC_ISR_PDRSFT_Pos 25 /**< (GMAC_ISR) PDelay Response Frame Transmitted Position */ 710 #define GMAC_ISR_PDRSFT_Msk (_U_(0x1) << GMAC_ISR_PDRSFT_Pos) /**< (GMAC_ISR) PDelay Response Frame Transmitted Mask */ 711 #define GMAC_ISR_PDRSFT GMAC_ISR_PDRSFT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISR_PDRSFT_Msk instead */ 712 #define GMAC_ISR_SRI_Pos 26 /**< (GMAC_ISR) TSU Seconds Register Increment Position */ 713 #define GMAC_ISR_SRI_Msk (_U_(0x1) << GMAC_ISR_SRI_Pos) /**< (GMAC_ISR) TSU Seconds Register Increment Mask */ 714 #define GMAC_ISR_SRI GMAC_ISR_SRI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISR_SRI_Msk instead */ 715 #define GMAC_ISR_RXLPISBC_Pos 27 /**< (GMAC_ISR) Receive LPI indication Status Bit Change Position */ 716 #define GMAC_ISR_RXLPISBC_Msk (_U_(0x1) << GMAC_ISR_RXLPISBC_Pos) /**< (GMAC_ISR) Receive LPI indication Status Bit Change Mask */ 717 #define GMAC_ISR_RXLPISBC GMAC_ISR_RXLPISBC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISR_RXLPISBC_Msk instead */ 718 #define GMAC_ISR_WOL_Pos 28 /**< (GMAC_ISR) Wake On LAN Position */ 719 #define GMAC_ISR_WOL_Msk (_U_(0x1) << GMAC_ISR_WOL_Pos) /**< (GMAC_ISR) Wake On LAN Mask */ 720 #define GMAC_ISR_WOL GMAC_ISR_WOL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISR_WOL_Msk instead */ 721 #define GMAC_ISR_TSUTIMCOMP_Pos 29 /**< (GMAC_ISR) TSU Timer Comparison Position */ 722 #define GMAC_ISR_TSUTIMCOMP_Msk (_U_(0x1) << GMAC_ISR_TSUTIMCOMP_Pos) /**< (GMAC_ISR) TSU Timer Comparison Mask */ 723 #define GMAC_ISR_TSUTIMCOMP GMAC_ISR_TSUTIMCOMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISR_TSUTIMCOMP_Msk instead */ 724 #define GMAC_ISR_MASK _U_(0x3FFC7CFF) /**< \deprecated (GMAC_ISR) Register MASK (Use GMAC_ISR_Msk instead) */ 725 #define GMAC_ISR_Msk _U_(0x3FFC7CFF) /**< (GMAC_ISR) Register Mask */ 726 727 728 /* -------- GMAC_IER : (GMAC Offset: 0x28) (/W 32) Interrupt Enable Register -------- */ 729 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 730 #if COMPONENT_TYPEDEF_STYLE == 'N' 731 typedef union { 732 struct { 733 uint32_t MFS:1; /**< bit: 0 Management Frame Sent */ 734 uint32_t RCOMP:1; /**< bit: 1 Receive Complete */ 735 uint32_t RXUBR:1; /**< bit: 2 RX Used Bit Read */ 736 uint32_t TXUBR:1; /**< bit: 3 TX Used Bit Read */ 737 uint32_t TUR:1; /**< bit: 4 Transmit Underrun */ 738 uint32_t RLEX:1; /**< bit: 5 Retry Limit Exceeded or Late Collision */ 739 uint32_t TFC:1; /**< bit: 6 Transmit Frame Corruption Due to AHB Error */ 740 uint32_t TCOMP:1; /**< bit: 7 Transmit Complete */ 741 uint32_t :2; /**< bit: 8..9 Reserved */ 742 uint32_t ROVR:1; /**< bit: 10 Receive Overrun */ 743 uint32_t HRESP:1; /**< bit: 11 HRESP Not OK */ 744 uint32_t PFNZ:1; /**< bit: 12 Pause Frame with Non-zero Pause Quantum Received */ 745 uint32_t PTZ:1; /**< bit: 13 Pause Time Zero */ 746 uint32_t PFTR:1; /**< bit: 14 Pause Frame Transmitted */ 747 uint32_t EXINT:1; /**< bit: 15 External Interrupt */ 748 uint32_t :2; /**< bit: 16..17 Reserved */ 749 uint32_t DRQFR:1; /**< bit: 18 PTP Delay Request Frame Received */ 750 uint32_t SFR:1; /**< bit: 19 PTP Sync Frame Received */ 751 uint32_t DRQFT:1; /**< bit: 20 PTP Delay Request Frame Transmitted */ 752 uint32_t SFT:1; /**< bit: 21 PTP Sync Frame Transmitted */ 753 uint32_t PDRQFR:1; /**< bit: 22 PDelay Request Frame Received */ 754 uint32_t PDRSFR:1; /**< bit: 23 PDelay Response Frame Received */ 755 uint32_t PDRQFT:1; /**< bit: 24 PDelay Request Frame Transmitted */ 756 uint32_t PDRSFT:1; /**< bit: 25 PDelay Response Frame Transmitted */ 757 uint32_t SRI:1; /**< bit: 26 TSU Seconds Register Increment */ 758 uint32_t RXLPISBC:1; /**< bit: 27 Enable RX LPI Indication */ 759 uint32_t WOL:1; /**< bit: 28 Wake On LAN */ 760 uint32_t TSUTIMCOMP:1; /**< bit: 29 TSU Timer Comparison */ 761 uint32_t :2; /**< bit: 30..31 Reserved */ 762 } bit; /**< Structure used for bit access */ 763 uint32_t reg; /**< Type used for register access */ 764 } GMAC_IER_Type; 765 #endif 766 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 767 768 #define GMAC_IER_OFFSET (0x28) /**< (GMAC_IER) Interrupt Enable Register Offset */ 769 770 #define GMAC_IER_MFS_Pos 0 /**< (GMAC_IER) Management Frame Sent Position */ 771 #define GMAC_IER_MFS_Msk (_U_(0x1) << GMAC_IER_MFS_Pos) /**< (GMAC_IER) Management Frame Sent Mask */ 772 #define GMAC_IER_MFS GMAC_IER_MFS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IER_MFS_Msk instead */ 773 #define GMAC_IER_RCOMP_Pos 1 /**< (GMAC_IER) Receive Complete Position */ 774 #define GMAC_IER_RCOMP_Msk (_U_(0x1) << GMAC_IER_RCOMP_Pos) /**< (GMAC_IER) Receive Complete Mask */ 775 #define GMAC_IER_RCOMP GMAC_IER_RCOMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IER_RCOMP_Msk instead */ 776 #define GMAC_IER_RXUBR_Pos 2 /**< (GMAC_IER) RX Used Bit Read Position */ 777 #define GMAC_IER_RXUBR_Msk (_U_(0x1) << GMAC_IER_RXUBR_Pos) /**< (GMAC_IER) RX Used Bit Read Mask */ 778 #define GMAC_IER_RXUBR GMAC_IER_RXUBR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IER_RXUBR_Msk instead */ 779 #define GMAC_IER_TXUBR_Pos 3 /**< (GMAC_IER) TX Used Bit Read Position */ 780 #define GMAC_IER_TXUBR_Msk (_U_(0x1) << GMAC_IER_TXUBR_Pos) /**< (GMAC_IER) TX Used Bit Read Mask */ 781 #define GMAC_IER_TXUBR GMAC_IER_TXUBR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IER_TXUBR_Msk instead */ 782 #define GMAC_IER_TUR_Pos 4 /**< (GMAC_IER) Transmit Underrun Position */ 783 #define GMAC_IER_TUR_Msk (_U_(0x1) << GMAC_IER_TUR_Pos) /**< (GMAC_IER) Transmit Underrun Mask */ 784 #define GMAC_IER_TUR GMAC_IER_TUR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IER_TUR_Msk instead */ 785 #define GMAC_IER_RLEX_Pos 5 /**< (GMAC_IER) Retry Limit Exceeded or Late Collision Position */ 786 #define GMAC_IER_RLEX_Msk (_U_(0x1) << GMAC_IER_RLEX_Pos) /**< (GMAC_IER) Retry Limit Exceeded or Late Collision Mask */ 787 #define GMAC_IER_RLEX GMAC_IER_RLEX_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IER_RLEX_Msk instead */ 788 #define GMAC_IER_TFC_Pos 6 /**< (GMAC_IER) Transmit Frame Corruption Due to AHB Error Position */ 789 #define GMAC_IER_TFC_Msk (_U_(0x1) << GMAC_IER_TFC_Pos) /**< (GMAC_IER) Transmit Frame Corruption Due to AHB Error Mask */ 790 #define GMAC_IER_TFC GMAC_IER_TFC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IER_TFC_Msk instead */ 791 #define GMAC_IER_TCOMP_Pos 7 /**< (GMAC_IER) Transmit Complete Position */ 792 #define GMAC_IER_TCOMP_Msk (_U_(0x1) << GMAC_IER_TCOMP_Pos) /**< (GMAC_IER) Transmit Complete Mask */ 793 #define GMAC_IER_TCOMP GMAC_IER_TCOMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IER_TCOMP_Msk instead */ 794 #define GMAC_IER_ROVR_Pos 10 /**< (GMAC_IER) Receive Overrun Position */ 795 #define GMAC_IER_ROVR_Msk (_U_(0x1) << GMAC_IER_ROVR_Pos) /**< (GMAC_IER) Receive Overrun Mask */ 796 #define GMAC_IER_ROVR GMAC_IER_ROVR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IER_ROVR_Msk instead */ 797 #define GMAC_IER_HRESP_Pos 11 /**< (GMAC_IER) HRESP Not OK Position */ 798 #define GMAC_IER_HRESP_Msk (_U_(0x1) << GMAC_IER_HRESP_Pos) /**< (GMAC_IER) HRESP Not OK Mask */ 799 #define GMAC_IER_HRESP GMAC_IER_HRESP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IER_HRESP_Msk instead */ 800 #define GMAC_IER_PFNZ_Pos 12 /**< (GMAC_IER) Pause Frame with Non-zero Pause Quantum Received Position */ 801 #define GMAC_IER_PFNZ_Msk (_U_(0x1) << GMAC_IER_PFNZ_Pos) /**< (GMAC_IER) Pause Frame with Non-zero Pause Quantum Received Mask */ 802 #define GMAC_IER_PFNZ GMAC_IER_PFNZ_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IER_PFNZ_Msk instead */ 803 #define GMAC_IER_PTZ_Pos 13 /**< (GMAC_IER) Pause Time Zero Position */ 804 #define GMAC_IER_PTZ_Msk (_U_(0x1) << GMAC_IER_PTZ_Pos) /**< (GMAC_IER) Pause Time Zero Mask */ 805 #define GMAC_IER_PTZ GMAC_IER_PTZ_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IER_PTZ_Msk instead */ 806 #define GMAC_IER_PFTR_Pos 14 /**< (GMAC_IER) Pause Frame Transmitted Position */ 807 #define GMAC_IER_PFTR_Msk (_U_(0x1) << GMAC_IER_PFTR_Pos) /**< (GMAC_IER) Pause Frame Transmitted Mask */ 808 #define GMAC_IER_PFTR GMAC_IER_PFTR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IER_PFTR_Msk instead */ 809 #define GMAC_IER_EXINT_Pos 15 /**< (GMAC_IER) External Interrupt Position */ 810 #define GMAC_IER_EXINT_Msk (_U_(0x1) << GMAC_IER_EXINT_Pos) /**< (GMAC_IER) External Interrupt Mask */ 811 #define GMAC_IER_EXINT GMAC_IER_EXINT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IER_EXINT_Msk instead */ 812 #define GMAC_IER_DRQFR_Pos 18 /**< (GMAC_IER) PTP Delay Request Frame Received Position */ 813 #define GMAC_IER_DRQFR_Msk (_U_(0x1) << GMAC_IER_DRQFR_Pos) /**< (GMAC_IER) PTP Delay Request Frame Received Mask */ 814 #define GMAC_IER_DRQFR GMAC_IER_DRQFR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IER_DRQFR_Msk instead */ 815 #define GMAC_IER_SFR_Pos 19 /**< (GMAC_IER) PTP Sync Frame Received Position */ 816 #define GMAC_IER_SFR_Msk (_U_(0x1) << GMAC_IER_SFR_Pos) /**< (GMAC_IER) PTP Sync Frame Received Mask */ 817 #define GMAC_IER_SFR GMAC_IER_SFR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IER_SFR_Msk instead */ 818 #define GMAC_IER_DRQFT_Pos 20 /**< (GMAC_IER) PTP Delay Request Frame Transmitted Position */ 819 #define GMAC_IER_DRQFT_Msk (_U_(0x1) << GMAC_IER_DRQFT_Pos) /**< (GMAC_IER) PTP Delay Request Frame Transmitted Mask */ 820 #define GMAC_IER_DRQFT GMAC_IER_DRQFT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IER_DRQFT_Msk instead */ 821 #define GMAC_IER_SFT_Pos 21 /**< (GMAC_IER) PTP Sync Frame Transmitted Position */ 822 #define GMAC_IER_SFT_Msk (_U_(0x1) << GMAC_IER_SFT_Pos) /**< (GMAC_IER) PTP Sync Frame Transmitted Mask */ 823 #define GMAC_IER_SFT GMAC_IER_SFT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IER_SFT_Msk instead */ 824 #define GMAC_IER_PDRQFR_Pos 22 /**< (GMAC_IER) PDelay Request Frame Received Position */ 825 #define GMAC_IER_PDRQFR_Msk (_U_(0x1) << GMAC_IER_PDRQFR_Pos) /**< (GMAC_IER) PDelay Request Frame Received Mask */ 826 #define GMAC_IER_PDRQFR GMAC_IER_PDRQFR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IER_PDRQFR_Msk instead */ 827 #define GMAC_IER_PDRSFR_Pos 23 /**< (GMAC_IER) PDelay Response Frame Received Position */ 828 #define GMAC_IER_PDRSFR_Msk (_U_(0x1) << GMAC_IER_PDRSFR_Pos) /**< (GMAC_IER) PDelay Response Frame Received Mask */ 829 #define GMAC_IER_PDRSFR GMAC_IER_PDRSFR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IER_PDRSFR_Msk instead */ 830 #define GMAC_IER_PDRQFT_Pos 24 /**< (GMAC_IER) PDelay Request Frame Transmitted Position */ 831 #define GMAC_IER_PDRQFT_Msk (_U_(0x1) << GMAC_IER_PDRQFT_Pos) /**< (GMAC_IER) PDelay Request Frame Transmitted Mask */ 832 #define GMAC_IER_PDRQFT GMAC_IER_PDRQFT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IER_PDRQFT_Msk instead */ 833 #define GMAC_IER_PDRSFT_Pos 25 /**< (GMAC_IER) PDelay Response Frame Transmitted Position */ 834 #define GMAC_IER_PDRSFT_Msk (_U_(0x1) << GMAC_IER_PDRSFT_Pos) /**< (GMAC_IER) PDelay Response Frame Transmitted Mask */ 835 #define GMAC_IER_PDRSFT GMAC_IER_PDRSFT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IER_PDRSFT_Msk instead */ 836 #define GMAC_IER_SRI_Pos 26 /**< (GMAC_IER) TSU Seconds Register Increment Position */ 837 #define GMAC_IER_SRI_Msk (_U_(0x1) << GMAC_IER_SRI_Pos) /**< (GMAC_IER) TSU Seconds Register Increment Mask */ 838 #define GMAC_IER_SRI GMAC_IER_SRI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IER_SRI_Msk instead */ 839 #define GMAC_IER_RXLPISBC_Pos 27 /**< (GMAC_IER) Enable RX LPI Indication Position */ 840 #define GMAC_IER_RXLPISBC_Msk (_U_(0x1) << GMAC_IER_RXLPISBC_Pos) /**< (GMAC_IER) Enable RX LPI Indication Mask */ 841 #define GMAC_IER_RXLPISBC GMAC_IER_RXLPISBC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IER_RXLPISBC_Msk instead */ 842 #define GMAC_IER_WOL_Pos 28 /**< (GMAC_IER) Wake On LAN Position */ 843 #define GMAC_IER_WOL_Msk (_U_(0x1) << GMAC_IER_WOL_Pos) /**< (GMAC_IER) Wake On LAN Mask */ 844 #define GMAC_IER_WOL GMAC_IER_WOL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IER_WOL_Msk instead */ 845 #define GMAC_IER_TSUTIMCOMP_Pos 29 /**< (GMAC_IER) TSU Timer Comparison Position */ 846 #define GMAC_IER_TSUTIMCOMP_Msk (_U_(0x1) << GMAC_IER_TSUTIMCOMP_Pos) /**< (GMAC_IER) TSU Timer Comparison Mask */ 847 #define GMAC_IER_TSUTIMCOMP GMAC_IER_TSUTIMCOMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IER_TSUTIMCOMP_Msk instead */ 848 #define GMAC_IER_MASK _U_(0x3FFCFCFF) /**< \deprecated (GMAC_IER) Register MASK (Use GMAC_IER_Msk instead) */ 849 #define GMAC_IER_Msk _U_(0x3FFCFCFF) /**< (GMAC_IER) Register Mask */ 850 851 852 /* -------- GMAC_IDR : (GMAC Offset: 0x2c) (/W 32) Interrupt Disable Register -------- */ 853 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 854 #if COMPONENT_TYPEDEF_STYLE == 'N' 855 typedef union { 856 struct { 857 uint32_t MFS:1; /**< bit: 0 Management Frame Sent */ 858 uint32_t RCOMP:1; /**< bit: 1 Receive Complete */ 859 uint32_t RXUBR:1; /**< bit: 2 RX Used Bit Read */ 860 uint32_t TXUBR:1; /**< bit: 3 TX Used Bit Read */ 861 uint32_t TUR:1; /**< bit: 4 Transmit Underrun */ 862 uint32_t RLEX:1; /**< bit: 5 Retry Limit Exceeded or Late Collision */ 863 uint32_t TFC:1; /**< bit: 6 Transmit Frame Corruption Due to AHB Error */ 864 uint32_t TCOMP:1; /**< bit: 7 Transmit Complete */ 865 uint32_t :2; /**< bit: 8..9 Reserved */ 866 uint32_t ROVR:1; /**< bit: 10 Receive Overrun */ 867 uint32_t HRESP:1; /**< bit: 11 HRESP Not OK */ 868 uint32_t PFNZ:1; /**< bit: 12 Pause Frame with Non-zero Pause Quantum Received */ 869 uint32_t PTZ:1; /**< bit: 13 Pause Time Zero */ 870 uint32_t PFTR:1; /**< bit: 14 Pause Frame Transmitted */ 871 uint32_t EXINT:1; /**< bit: 15 External Interrupt */ 872 uint32_t :2; /**< bit: 16..17 Reserved */ 873 uint32_t DRQFR:1; /**< bit: 18 PTP Delay Request Frame Received */ 874 uint32_t SFR:1; /**< bit: 19 PTP Sync Frame Received */ 875 uint32_t DRQFT:1; /**< bit: 20 PTP Delay Request Frame Transmitted */ 876 uint32_t SFT:1; /**< bit: 21 PTP Sync Frame Transmitted */ 877 uint32_t PDRQFR:1; /**< bit: 22 PDelay Request Frame Received */ 878 uint32_t PDRSFR:1; /**< bit: 23 PDelay Response Frame Received */ 879 uint32_t PDRQFT:1; /**< bit: 24 PDelay Request Frame Transmitted */ 880 uint32_t PDRSFT:1; /**< bit: 25 PDelay Response Frame Transmitted */ 881 uint32_t SRI:1; /**< bit: 26 TSU Seconds Register Increment */ 882 uint32_t RXLPISBC:1; /**< bit: 27 Enable RX LPI Indication */ 883 uint32_t WOL:1; /**< bit: 28 Wake On LAN */ 884 uint32_t TSUTIMCOMP:1; /**< bit: 29 TSU Timer Comparison */ 885 uint32_t :2; /**< bit: 30..31 Reserved */ 886 } bit; /**< Structure used for bit access */ 887 uint32_t reg; /**< Type used for register access */ 888 } GMAC_IDR_Type; 889 #endif 890 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 891 892 #define GMAC_IDR_OFFSET (0x2C) /**< (GMAC_IDR) Interrupt Disable Register Offset */ 893 894 #define GMAC_IDR_MFS_Pos 0 /**< (GMAC_IDR) Management Frame Sent Position */ 895 #define GMAC_IDR_MFS_Msk (_U_(0x1) << GMAC_IDR_MFS_Pos) /**< (GMAC_IDR) Management Frame Sent Mask */ 896 #define GMAC_IDR_MFS GMAC_IDR_MFS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDR_MFS_Msk instead */ 897 #define GMAC_IDR_RCOMP_Pos 1 /**< (GMAC_IDR) Receive Complete Position */ 898 #define GMAC_IDR_RCOMP_Msk (_U_(0x1) << GMAC_IDR_RCOMP_Pos) /**< (GMAC_IDR) Receive Complete Mask */ 899 #define GMAC_IDR_RCOMP GMAC_IDR_RCOMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDR_RCOMP_Msk instead */ 900 #define GMAC_IDR_RXUBR_Pos 2 /**< (GMAC_IDR) RX Used Bit Read Position */ 901 #define GMAC_IDR_RXUBR_Msk (_U_(0x1) << GMAC_IDR_RXUBR_Pos) /**< (GMAC_IDR) RX Used Bit Read Mask */ 902 #define GMAC_IDR_RXUBR GMAC_IDR_RXUBR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDR_RXUBR_Msk instead */ 903 #define GMAC_IDR_TXUBR_Pos 3 /**< (GMAC_IDR) TX Used Bit Read Position */ 904 #define GMAC_IDR_TXUBR_Msk (_U_(0x1) << GMAC_IDR_TXUBR_Pos) /**< (GMAC_IDR) TX Used Bit Read Mask */ 905 #define GMAC_IDR_TXUBR GMAC_IDR_TXUBR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDR_TXUBR_Msk instead */ 906 #define GMAC_IDR_TUR_Pos 4 /**< (GMAC_IDR) Transmit Underrun Position */ 907 #define GMAC_IDR_TUR_Msk (_U_(0x1) << GMAC_IDR_TUR_Pos) /**< (GMAC_IDR) Transmit Underrun Mask */ 908 #define GMAC_IDR_TUR GMAC_IDR_TUR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDR_TUR_Msk instead */ 909 #define GMAC_IDR_RLEX_Pos 5 /**< (GMAC_IDR) Retry Limit Exceeded or Late Collision Position */ 910 #define GMAC_IDR_RLEX_Msk (_U_(0x1) << GMAC_IDR_RLEX_Pos) /**< (GMAC_IDR) Retry Limit Exceeded or Late Collision Mask */ 911 #define GMAC_IDR_RLEX GMAC_IDR_RLEX_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDR_RLEX_Msk instead */ 912 #define GMAC_IDR_TFC_Pos 6 /**< (GMAC_IDR) Transmit Frame Corruption Due to AHB Error Position */ 913 #define GMAC_IDR_TFC_Msk (_U_(0x1) << GMAC_IDR_TFC_Pos) /**< (GMAC_IDR) Transmit Frame Corruption Due to AHB Error Mask */ 914 #define GMAC_IDR_TFC GMAC_IDR_TFC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDR_TFC_Msk instead */ 915 #define GMAC_IDR_TCOMP_Pos 7 /**< (GMAC_IDR) Transmit Complete Position */ 916 #define GMAC_IDR_TCOMP_Msk (_U_(0x1) << GMAC_IDR_TCOMP_Pos) /**< (GMAC_IDR) Transmit Complete Mask */ 917 #define GMAC_IDR_TCOMP GMAC_IDR_TCOMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDR_TCOMP_Msk instead */ 918 #define GMAC_IDR_ROVR_Pos 10 /**< (GMAC_IDR) Receive Overrun Position */ 919 #define GMAC_IDR_ROVR_Msk (_U_(0x1) << GMAC_IDR_ROVR_Pos) /**< (GMAC_IDR) Receive Overrun Mask */ 920 #define GMAC_IDR_ROVR GMAC_IDR_ROVR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDR_ROVR_Msk instead */ 921 #define GMAC_IDR_HRESP_Pos 11 /**< (GMAC_IDR) HRESP Not OK Position */ 922 #define GMAC_IDR_HRESP_Msk (_U_(0x1) << GMAC_IDR_HRESP_Pos) /**< (GMAC_IDR) HRESP Not OK Mask */ 923 #define GMAC_IDR_HRESP GMAC_IDR_HRESP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDR_HRESP_Msk instead */ 924 #define GMAC_IDR_PFNZ_Pos 12 /**< (GMAC_IDR) Pause Frame with Non-zero Pause Quantum Received Position */ 925 #define GMAC_IDR_PFNZ_Msk (_U_(0x1) << GMAC_IDR_PFNZ_Pos) /**< (GMAC_IDR) Pause Frame with Non-zero Pause Quantum Received Mask */ 926 #define GMAC_IDR_PFNZ GMAC_IDR_PFNZ_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDR_PFNZ_Msk instead */ 927 #define GMAC_IDR_PTZ_Pos 13 /**< (GMAC_IDR) Pause Time Zero Position */ 928 #define GMAC_IDR_PTZ_Msk (_U_(0x1) << GMAC_IDR_PTZ_Pos) /**< (GMAC_IDR) Pause Time Zero Mask */ 929 #define GMAC_IDR_PTZ GMAC_IDR_PTZ_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDR_PTZ_Msk instead */ 930 #define GMAC_IDR_PFTR_Pos 14 /**< (GMAC_IDR) Pause Frame Transmitted Position */ 931 #define GMAC_IDR_PFTR_Msk (_U_(0x1) << GMAC_IDR_PFTR_Pos) /**< (GMAC_IDR) Pause Frame Transmitted Mask */ 932 #define GMAC_IDR_PFTR GMAC_IDR_PFTR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDR_PFTR_Msk instead */ 933 #define GMAC_IDR_EXINT_Pos 15 /**< (GMAC_IDR) External Interrupt Position */ 934 #define GMAC_IDR_EXINT_Msk (_U_(0x1) << GMAC_IDR_EXINT_Pos) /**< (GMAC_IDR) External Interrupt Mask */ 935 #define GMAC_IDR_EXINT GMAC_IDR_EXINT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDR_EXINT_Msk instead */ 936 #define GMAC_IDR_DRQFR_Pos 18 /**< (GMAC_IDR) PTP Delay Request Frame Received Position */ 937 #define GMAC_IDR_DRQFR_Msk (_U_(0x1) << GMAC_IDR_DRQFR_Pos) /**< (GMAC_IDR) PTP Delay Request Frame Received Mask */ 938 #define GMAC_IDR_DRQFR GMAC_IDR_DRQFR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDR_DRQFR_Msk instead */ 939 #define GMAC_IDR_SFR_Pos 19 /**< (GMAC_IDR) PTP Sync Frame Received Position */ 940 #define GMAC_IDR_SFR_Msk (_U_(0x1) << GMAC_IDR_SFR_Pos) /**< (GMAC_IDR) PTP Sync Frame Received Mask */ 941 #define GMAC_IDR_SFR GMAC_IDR_SFR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDR_SFR_Msk instead */ 942 #define GMAC_IDR_DRQFT_Pos 20 /**< (GMAC_IDR) PTP Delay Request Frame Transmitted Position */ 943 #define GMAC_IDR_DRQFT_Msk (_U_(0x1) << GMAC_IDR_DRQFT_Pos) /**< (GMAC_IDR) PTP Delay Request Frame Transmitted Mask */ 944 #define GMAC_IDR_DRQFT GMAC_IDR_DRQFT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDR_DRQFT_Msk instead */ 945 #define GMAC_IDR_SFT_Pos 21 /**< (GMAC_IDR) PTP Sync Frame Transmitted Position */ 946 #define GMAC_IDR_SFT_Msk (_U_(0x1) << GMAC_IDR_SFT_Pos) /**< (GMAC_IDR) PTP Sync Frame Transmitted Mask */ 947 #define GMAC_IDR_SFT GMAC_IDR_SFT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDR_SFT_Msk instead */ 948 #define GMAC_IDR_PDRQFR_Pos 22 /**< (GMAC_IDR) PDelay Request Frame Received Position */ 949 #define GMAC_IDR_PDRQFR_Msk (_U_(0x1) << GMAC_IDR_PDRQFR_Pos) /**< (GMAC_IDR) PDelay Request Frame Received Mask */ 950 #define GMAC_IDR_PDRQFR GMAC_IDR_PDRQFR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDR_PDRQFR_Msk instead */ 951 #define GMAC_IDR_PDRSFR_Pos 23 /**< (GMAC_IDR) PDelay Response Frame Received Position */ 952 #define GMAC_IDR_PDRSFR_Msk (_U_(0x1) << GMAC_IDR_PDRSFR_Pos) /**< (GMAC_IDR) PDelay Response Frame Received Mask */ 953 #define GMAC_IDR_PDRSFR GMAC_IDR_PDRSFR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDR_PDRSFR_Msk instead */ 954 #define GMAC_IDR_PDRQFT_Pos 24 /**< (GMAC_IDR) PDelay Request Frame Transmitted Position */ 955 #define GMAC_IDR_PDRQFT_Msk (_U_(0x1) << GMAC_IDR_PDRQFT_Pos) /**< (GMAC_IDR) PDelay Request Frame Transmitted Mask */ 956 #define GMAC_IDR_PDRQFT GMAC_IDR_PDRQFT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDR_PDRQFT_Msk instead */ 957 #define GMAC_IDR_PDRSFT_Pos 25 /**< (GMAC_IDR) PDelay Response Frame Transmitted Position */ 958 #define GMAC_IDR_PDRSFT_Msk (_U_(0x1) << GMAC_IDR_PDRSFT_Pos) /**< (GMAC_IDR) PDelay Response Frame Transmitted Mask */ 959 #define GMAC_IDR_PDRSFT GMAC_IDR_PDRSFT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDR_PDRSFT_Msk instead */ 960 #define GMAC_IDR_SRI_Pos 26 /**< (GMAC_IDR) TSU Seconds Register Increment Position */ 961 #define GMAC_IDR_SRI_Msk (_U_(0x1) << GMAC_IDR_SRI_Pos) /**< (GMAC_IDR) TSU Seconds Register Increment Mask */ 962 #define GMAC_IDR_SRI GMAC_IDR_SRI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDR_SRI_Msk instead */ 963 #define GMAC_IDR_RXLPISBC_Pos 27 /**< (GMAC_IDR) Enable RX LPI Indication Position */ 964 #define GMAC_IDR_RXLPISBC_Msk (_U_(0x1) << GMAC_IDR_RXLPISBC_Pos) /**< (GMAC_IDR) Enable RX LPI Indication Mask */ 965 #define GMAC_IDR_RXLPISBC GMAC_IDR_RXLPISBC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDR_RXLPISBC_Msk instead */ 966 #define GMAC_IDR_WOL_Pos 28 /**< (GMAC_IDR) Wake On LAN Position */ 967 #define GMAC_IDR_WOL_Msk (_U_(0x1) << GMAC_IDR_WOL_Pos) /**< (GMAC_IDR) Wake On LAN Mask */ 968 #define GMAC_IDR_WOL GMAC_IDR_WOL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDR_WOL_Msk instead */ 969 #define GMAC_IDR_TSUTIMCOMP_Pos 29 /**< (GMAC_IDR) TSU Timer Comparison Position */ 970 #define GMAC_IDR_TSUTIMCOMP_Msk (_U_(0x1) << GMAC_IDR_TSUTIMCOMP_Pos) /**< (GMAC_IDR) TSU Timer Comparison Mask */ 971 #define GMAC_IDR_TSUTIMCOMP GMAC_IDR_TSUTIMCOMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDR_TSUTIMCOMP_Msk instead */ 972 #define GMAC_IDR_MASK _U_(0x3FFCFCFF) /**< \deprecated (GMAC_IDR) Register MASK (Use GMAC_IDR_Msk instead) */ 973 #define GMAC_IDR_Msk _U_(0x3FFCFCFF) /**< (GMAC_IDR) Register Mask */ 974 975 976 /* -------- GMAC_IMR : (GMAC Offset: 0x30) (R/W 32) Interrupt Mask Register -------- */ 977 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 978 #if COMPONENT_TYPEDEF_STYLE == 'N' 979 typedef union { 980 struct { 981 uint32_t MFS:1; /**< bit: 0 Management Frame Sent */ 982 uint32_t RCOMP:1; /**< bit: 1 Receive Complete */ 983 uint32_t RXUBR:1; /**< bit: 2 RX Used Bit Read */ 984 uint32_t TXUBR:1; /**< bit: 3 TX Used Bit Read */ 985 uint32_t TUR:1; /**< bit: 4 Transmit Underrun */ 986 uint32_t RLEX:1; /**< bit: 5 Retry Limit Exceeded */ 987 uint32_t TFC:1; /**< bit: 6 Transmit Frame Corruption Due to AHB Error */ 988 uint32_t TCOMP:1; /**< bit: 7 Transmit Complete */ 989 uint32_t :2; /**< bit: 8..9 Reserved */ 990 uint32_t ROVR:1; /**< bit: 10 Receive Overrun */ 991 uint32_t HRESP:1; /**< bit: 11 HRESP Not OK */ 992 uint32_t PFNZ:1; /**< bit: 12 Pause Frame with Non-zero Pause Quantum Received */ 993 uint32_t PTZ:1; /**< bit: 13 Pause Time Zero */ 994 uint32_t PFTR:1; /**< bit: 14 Pause Frame Transmitted */ 995 uint32_t EXINT:1; /**< bit: 15 External Interrupt */ 996 uint32_t :2; /**< bit: 16..17 Reserved */ 997 uint32_t DRQFR:1; /**< bit: 18 PTP Delay Request Frame Received */ 998 uint32_t SFR:1; /**< bit: 19 PTP Sync Frame Received */ 999 uint32_t DRQFT:1; /**< bit: 20 PTP Delay Request Frame Transmitted */ 1000 uint32_t SFT:1; /**< bit: 21 PTP Sync Frame Transmitted */ 1001 uint32_t PDRQFR:1; /**< bit: 22 PDelay Request Frame Received */ 1002 uint32_t PDRSFR:1; /**< bit: 23 PDelay Response Frame Received */ 1003 uint32_t PDRQFT:1; /**< bit: 24 PDelay Request Frame Transmitted */ 1004 uint32_t PDRSFT:1; /**< bit: 25 PDelay Response Frame Transmitted */ 1005 uint32_t SRI:1; /**< bit: 26 TSU Seconds Register Increment */ 1006 uint32_t RXLPISBC:1; /**< bit: 27 Enable RX LPI Indication */ 1007 uint32_t WOL:1; /**< bit: 28 Wake On LAN */ 1008 uint32_t TSUTIMCOMP:1; /**< bit: 29 TSU Timer Comparison */ 1009 uint32_t :2; /**< bit: 30..31 Reserved */ 1010 } bit; /**< Structure used for bit access */ 1011 uint32_t reg; /**< Type used for register access */ 1012 } GMAC_IMR_Type; 1013 #endif 1014 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1015 1016 #define GMAC_IMR_OFFSET (0x30) /**< (GMAC_IMR) Interrupt Mask Register Offset */ 1017 1018 #define GMAC_IMR_MFS_Pos 0 /**< (GMAC_IMR) Management Frame Sent Position */ 1019 #define GMAC_IMR_MFS_Msk (_U_(0x1) << GMAC_IMR_MFS_Pos) /**< (GMAC_IMR) Management Frame Sent Mask */ 1020 #define GMAC_IMR_MFS GMAC_IMR_MFS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMR_MFS_Msk instead */ 1021 #define GMAC_IMR_RCOMP_Pos 1 /**< (GMAC_IMR) Receive Complete Position */ 1022 #define GMAC_IMR_RCOMP_Msk (_U_(0x1) << GMAC_IMR_RCOMP_Pos) /**< (GMAC_IMR) Receive Complete Mask */ 1023 #define GMAC_IMR_RCOMP GMAC_IMR_RCOMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMR_RCOMP_Msk instead */ 1024 #define GMAC_IMR_RXUBR_Pos 2 /**< (GMAC_IMR) RX Used Bit Read Position */ 1025 #define GMAC_IMR_RXUBR_Msk (_U_(0x1) << GMAC_IMR_RXUBR_Pos) /**< (GMAC_IMR) RX Used Bit Read Mask */ 1026 #define GMAC_IMR_RXUBR GMAC_IMR_RXUBR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMR_RXUBR_Msk instead */ 1027 #define GMAC_IMR_TXUBR_Pos 3 /**< (GMAC_IMR) TX Used Bit Read Position */ 1028 #define GMAC_IMR_TXUBR_Msk (_U_(0x1) << GMAC_IMR_TXUBR_Pos) /**< (GMAC_IMR) TX Used Bit Read Mask */ 1029 #define GMAC_IMR_TXUBR GMAC_IMR_TXUBR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMR_TXUBR_Msk instead */ 1030 #define GMAC_IMR_TUR_Pos 4 /**< (GMAC_IMR) Transmit Underrun Position */ 1031 #define GMAC_IMR_TUR_Msk (_U_(0x1) << GMAC_IMR_TUR_Pos) /**< (GMAC_IMR) Transmit Underrun Mask */ 1032 #define GMAC_IMR_TUR GMAC_IMR_TUR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMR_TUR_Msk instead */ 1033 #define GMAC_IMR_RLEX_Pos 5 /**< (GMAC_IMR) Retry Limit Exceeded Position */ 1034 #define GMAC_IMR_RLEX_Msk (_U_(0x1) << GMAC_IMR_RLEX_Pos) /**< (GMAC_IMR) Retry Limit Exceeded Mask */ 1035 #define GMAC_IMR_RLEX GMAC_IMR_RLEX_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMR_RLEX_Msk instead */ 1036 #define GMAC_IMR_TFC_Pos 6 /**< (GMAC_IMR) Transmit Frame Corruption Due to AHB Error Position */ 1037 #define GMAC_IMR_TFC_Msk (_U_(0x1) << GMAC_IMR_TFC_Pos) /**< (GMAC_IMR) Transmit Frame Corruption Due to AHB Error Mask */ 1038 #define GMAC_IMR_TFC GMAC_IMR_TFC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMR_TFC_Msk instead */ 1039 #define GMAC_IMR_TCOMP_Pos 7 /**< (GMAC_IMR) Transmit Complete Position */ 1040 #define GMAC_IMR_TCOMP_Msk (_U_(0x1) << GMAC_IMR_TCOMP_Pos) /**< (GMAC_IMR) Transmit Complete Mask */ 1041 #define GMAC_IMR_TCOMP GMAC_IMR_TCOMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMR_TCOMP_Msk instead */ 1042 #define GMAC_IMR_ROVR_Pos 10 /**< (GMAC_IMR) Receive Overrun Position */ 1043 #define GMAC_IMR_ROVR_Msk (_U_(0x1) << GMAC_IMR_ROVR_Pos) /**< (GMAC_IMR) Receive Overrun Mask */ 1044 #define GMAC_IMR_ROVR GMAC_IMR_ROVR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMR_ROVR_Msk instead */ 1045 #define GMAC_IMR_HRESP_Pos 11 /**< (GMAC_IMR) HRESP Not OK Position */ 1046 #define GMAC_IMR_HRESP_Msk (_U_(0x1) << GMAC_IMR_HRESP_Pos) /**< (GMAC_IMR) HRESP Not OK Mask */ 1047 #define GMAC_IMR_HRESP GMAC_IMR_HRESP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMR_HRESP_Msk instead */ 1048 #define GMAC_IMR_PFNZ_Pos 12 /**< (GMAC_IMR) Pause Frame with Non-zero Pause Quantum Received Position */ 1049 #define GMAC_IMR_PFNZ_Msk (_U_(0x1) << GMAC_IMR_PFNZ_Pos) /**< (GMAC_IMR) Pause Frame with Non-zero Pause Quantum Received Mask */ 1050 #define GMAC_IMR_PFNZ GMAC_IMR_PFNZ_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMR_PFNZ_Msk instead */ 1051 #define GMAC_IMR_PTZ_Pos 13 /**< (GMAC_IMR) Pause Time Zero Position */ 1052 #define GMAC_IMR_PTZ_Msk (_U_(0x1) << GMAC_IMR_PTZ_Pos) /**< (GMAC_IMR) Pause Time Zero Mask */ 1053 #define GMAC_IMR_PTZ GMAC_IMR_PTZ_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMR_PTZ_Msk instead */ 1054 #define GMAC_IMR_PFTR_Pos 14 /**< (GMAC_IMR) Pause Frame Transmitted Position */ 1055 #define GMAC_IMR_PFTR_Msk (_U_(0x1) << GMAC_IMR_PFTR_Pos) /**< (GMAC_IMR) Pause Frame Transmitted Mask */ 1056 #define GMAC_IMR_PFTR GMAC_IMR_PFTR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMR_PFTR_Msk instead */ 1057 #define GMAC_IMR_EXINT_Pos 15 /**< (GMAC_IMR) External Interrupt Position */ 1058 #define GMAC_IMR_EXINT_Msk (_U_(0x1) << GMAC_IMR_EXINT_Pos) /**< (GMAC_IMR) External Interrupt Mask */ 1059 #define GMAC_IMR_EXINT GMAC_IMR_EXINT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMR_EXINT_Msk instead */ 1060 #define GMAC_IMR_DRQFR_Pos 18 /**< (GMAC_IMR) PTP Delay Request Frame Received Position */ 1061 #define GMAC_IMR_DRQFR_Msk (_U_(0x1) << GMAC_IMR_DRQFR_Pos) /**< (GMAC_IMR) PTP Delay Request Frame Received Mask */ 1062 #define GMAC_IMR_DRQFR GMAC_IMR_DRQFR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMR_DRQFR_Msk instead */ 1063 #define GMAC_IMR_SFR_Pos 19 /**< (GMAC_IMR) PTP Sync Frame Received Position */ 1064 #define GMAC_IMR_SFR_Msk (_U_(0x1) << GMAC_IMR_SFR_Pos) /**< (GMAC_IMR) PTP Sync Frame Received Mask */ 1065 #define GMAC_IMR_SFR GMAC_IMR_SFR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMR_SFR_Msk instead */ 1066 #define GMAC_IMR_DRQFT_Pos 20 /**< (GMAC_IMR) PTP Delay Request Frame Transmitted Position */ 1067 #define GMAC_IMR_DRQFT_Msk (_U_(0x1) << GMAC_IMR_DRQFT_Pos) /**< (GMAC_IMR) PTP Delay Request Frame Transmitted Mask */ 1068 #define GMAC_IMR_DRQFT GMAC_IMR_DRQFT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMR_DRQFT_Msk instead */ 1069 #define GMAC_IMR_SFT_Pos 21 /**< (GMAC_IMR) PTP Sync Frame Transmitted Position */ 1070 #define GMAC_IMR_SFT_Msk (_U_(0x1) << GMAC_IMR_SFT_Pos) /**< (GMAC_IMR) PTP Sync Frame Transmitted Mask */ 1071 #define GMAC_IMR_SFT GMAC_IMR_SFT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMR_SFT_Msk instead */ 1072 #define GMAC_IMR_PDRQFR_Pos 22 /**< (GMAC_IMR) PDelay Request Frame Received Position */ 1073 #define GMAC_IMR_PDRQFR_Msk (_U_(0x1) << GMAC_IMR_PDRQFR_Pos) /**< (GMAC_IMR) PDelay Request Frame Received Mask */ 1074 #define GMAC_IMR_PDRQFR GMAC_IMR_PDRQFR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMR_PDRQFR_Msk instead */ 1075 #define GMAC_IMR_PDRSFR_Pos 23 /**< (GMAC_IMR) PDelay Response Frame Received Position */ 1076 #define GMAC_IMR_PDRSFR_Msk (_U_(0x1) << GMAC_IMR_PDRSFR_Pos) /**< (GMAC_IMR) PDelay Response Frame Received Mask */ 1077 #define GMAC_IMR_PDRSFR GMAC_IMR_PDRSFR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMR_PDRSFR_Msk instead */ 1078 #define GMAC_IMR_PDRQFT_Pos 24 /**< (GMAC_IMR) PDelay Request Frame Transmitted Position */ 1079 #define GMAC_IMR_PDRQFT_Msk (_U_(0x1) << GMAC_IMR_PDRQFT_Pos) /**< (GMAC_IMR) PDelay Request Frame Transmitted Mask */ 1080 #define GMAC_IMR_PDRQFT GMAC_IMR_PDRQFT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMR_PDRQFT_Msk instead */ 1081 #define GMAC_IMR_PDRSFT_Pos 25 /**< (GMAC_IMR) PDelay Response Frame Transmitted Position */ 1082 #define GMAC_IMR_PDRSFT_Msk (_U_(0x1) << GMAC_IMR_PDRSFT_Pos) /**< (GMAC_IMR) PDelay Response Frame Transmitted Mask */ 1083 #define GMAC_IMR_PDRSFT GMAC_IMR_PDRSFT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMR_PDRSFT_Msk instead */ 1084 #define GMAC_IMR_SRI_Pos 26 /**< (GMAC_IMR) TSU Seconds Register Increment Position */ 1085 #define GMAC_IMR_SRI_Msk (_U_(0x1) << GMAC_IMR_SRI_Pos) /**< (GMAC_IMR) TSU Seconds Register Increment Mask */ 1086 #define GMAC_IMR_SRI GMAC_IMR_SRI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMR_SRI_Msk instead */ 1087 #define GMAC_IMR_RXLPISBC_Pos 27 /**< (GMAC_IMR) Enable RX LPI Indication Position */ 1088 #define GMAC_IMR_RXLPISBC_Msk (_U_(0x1) << GMAC_IMR_RXLPISBC_Pos) /**< (GMAC_IMR) Enable RX LPI Indication Mask */ 1089 #define GMAC_IMR_RXLPISBC GMAC_IMR_RXLPISBC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMR_RXLPISBC_Msk instead */ 1090 #define GMAC_IMR_WOL_Pos 28 /**< (GMAC_IMR) Wake On LAN Position */ 1091 #define GMAC_IMR_WOL_Msk (_U_(0x1) << GMAC_IMR_WOL_Pos) /**< (GMAC_IMR) Wake On LAN Mask */ 1092 #define GMAC_IMR_WOL GMAC_IMR_WOL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMR_WOL_Msk instead */ 1093 #define GMAC_IMR_TSUTIMCOMP_Pos 29 /**< (GMAC_IMR) TSU Timer Comparison Position */ 1094 #define GMAC_IMR_TSUTIMCOMP_Msk (_U_(0x1) << GMAC_IMR_TSUTIMCOMP_Pos) /**< (GMAC_IMR) TSU Timer Comparison Mask */ 1095 #define GMAC_IMR_TSUTIMCOMP GMAC_IMR_TSUTIMCOMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMR_TSUTIMCOMP_Msk instead */ 1096 #define GMAC_IMR_MASK _U_(0x3FFCFCFF) /**< \deprecated (GMAC_IMR) Register MASK (Use GMAC_IMR_Msk instead) */ 1097 #define GMAC_IMR_Msk _U_(0x3FFCFCFF) /**< (GMAC_IMR) Register Mask */ 1098 1099 1100 /* -------- GMAC_MAN : (GMAC Offset: 0x34) (R/W 32) PHY Maintenance Register -------- */ 1101 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1102 #if COMPONENT_TYPEDEF_STYLE == 'N' 1103 typedef union { 1104 struct { 1105 uint32_t DATA:16; /**< bit: 0..15 PHY Data */ 1106 uint32_t WTN:2; /**< bit: 16..17 Write Ten */ 1107 uint32_t REGA:5; /**< bit: 18..22 Register Address */ 1108 uint32_t PHYA:5; /**< bit: 23..27 PHY Address */ 1109 uint32_t OP:2; /**< bit: 28..29 Operation */ 1110 uint32_t CLTTO:1; /**< bit: 30 Clause 22 Operation */ 1111 uint32_t WZO:1; /**< bit: 31 Write ZERO */ 1112 } bit; /**< Structure used for bit access */ 1113 uint32_t reg; /**< Type used for register access */ 1114 } GMAC_MAN_Type; 1115 #endif 1116 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1117 1118 #define GMAC_MAN_OFFSET (0x34) /**< (GMAC_MAN) PHY Maintenance Register Offset */ 1119 1120 #define GMAC_MAN_DATA_Pos 0 /**< (GMAC_MAN) PHY Data Position */ 1121 #define GMAC_MAN_DATA_Msk (_U_(0xFFFF) << GMAC_MAN_DATA_Pos) /**< (GMAC_MAN) PHY Data Mask */ 1122 #define GMAC_MAN_DATA(value) (GMAC_MAN_DATA_Msk & ((value) << GMAC_MAN_DATA_Pos)) 1123 #define GMAC_MAN_WTN_Pos 16 /**< (GMAC_MAN) Write Ten Position */ 1124 #define GMAC_MAN_WTN_Msk (_U_(0x3) << GMAC_MAN_WTN_Pos) /**< (GMAC_MAN) Write Ten Mask */ 1125 #define GMAC_MAN_WTN(value) (GMAC_MAN_WTN_Msk & ((value) << GMAC_MAN_WTN_Pos)) 1126 #define GMAC_MAN_REGA_Pos 18 /**< (GMAC_MAN) Register Address Position */ 1127 #define GMAC_MAN_REGA_Msk (_U_(0x1F) << GMAC_MAN_REGA_Pos) /**< (GMAC_MAN) Register Address Mask */ 1128 #define GMAC_MAN_REGA(value) (GMAC_MAN_REGA_Msk & ((value) << GMAC_MAN_REGA_Pos)) 1129 #define GMAC_MAN_PHYA_Pos 23 /**< (GMAC_MAN) PHY Address Position */ 1130 #define GMAC_MAN_PHYA_Msk (_U_(0x1F) << GMAC_MAN_PHYA_Pos) /**< (GMAC_MAN) PHY Address Mask */ 1131 #define GMAC_MAN_PHYA(value) (GMAC_MAN_PHYA_Msk & ((value) << GMAC_MAN_PHYA_Pos)) 1132 #define GMAC_MAN_OP_Pos 28 /**< (GMAC_MAN) Operation Position */ 1133 #define GMAC_MAN_OP_Msk (_U_(0x3) << GMAC_MAN_OP_Pos) /**< (GMAC_MAN) Operation Mask */ 1134 #define GMAC_MAN_OP(value) (GMAC_MAN_OP_Msk & ((value) << GMAC_MAN_OP_Pos)) 1135 #define GMAC_MAN_CLTTO_Pos 30 /**< (GMAC_MAN) Clause 22 Operation Position */ 1136 #define GMAC_MAN_CLTTO_Msk (_U_(0x1) << GMAC_MAN_CLTTO_Pos) /**< (GMAC_MAN) Clause 22 Operation Mask */ 1137 #define GMAC_MAN_CLTTO GMAC_MAN_CLTTO_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_MAN_CLTTO_Msk instead */ 1138 #define GMAC_MAN_WZO_Pos 31 /**< (GMAC_MAN) Write ZERO Position */ 1139 #define GMAC_MAN_WZO_Msk (_U_(0x1) << GMAC_MAN_WZO_Pos) /**< (GMAC_MAN) Write ZERO Mask */ 1140 #define GMAC_MAN_WZO GMAC_MAN_WZO_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_MAN_WZO_Msk instead */ 1141 #define GMAC_MAN_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_MAN) Register MASK (Use GMAC_MAN_Msk instead) */ 1142 #define GMAC_MAN_Msk _U_(0xFFFFFFFF) /**< (GMAC_MAN) Register Mask */ 1143 1144 1145 /* -------- GMAC_RPQ : (GMAC Offset: 0x38) (R/ 32) Received Pause Quantum Register -------- */ 1146 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1147 #if COMPONENT_TYPEDEF_STYLE == 'N' 1148 typedef union { 1149 struct { 1150 uint32_t RPQ:16; /**< bit: 0..15 Received Pause Quantum */ 1151 uint32_t :16; /**< bit: 16..31 Reserved */ 1152 } bit; /**< Structure used for bit access */ 1153 uint32_t reg; /**< Type used for register access */ 1154 } GMAC_RPQ_Type; 1155 #endif 1156 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1157 1158 #define GMAC_RPQ_OFFSET (0x38) /**< (GMAC_RPQ) Received Pause Quantum Register Offset */ 1159 1160 #define GMAC_RPQ_RPQ_Pos 0 /**< (GMAC_RPQ) Received Pause Quantum Position */ 1161 #define GMAC_RPQ_RPQ_Msk (_U_(0xFFFF) << GMAC_RPQ_RPQ_Pos) /**< (GMAC_RPQ) Received Pause Quantum Mask */ 1162 #define GMAC_RPQ_RPQ(value) (GMAC_RPQ_RPQ_Msk & ((value) << GMAC_RPQ_RPQ_Pos)) 1163 #define GMAC_RPQ_MASK _U_(0xFFFF) /**< \deprecated (GMAC_RPQ) Register MASK (Use GMAC_RPQ_Msk instead) */ 1164 #define GMAC_RPQ_Msk _U_(0xFFFF) /**< (GMAC_RPQ) Register Mask */ 1165 1166 1167 /* -------- GMAC_TPQ : (GMAC Offset: 0x3c) (R/W 32) Transmit Pause Quantum Register -------- */ 1168 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1169 #if COMPONENT_TYPEDEF_STYLE == 'N' 1170 typedef union { 1171 struct { 1172 uint32_t TPQ:16; /**< bit: 0..15 Transmit Pause Quantum */ 1173 uint32_t :16; /**< bit: 16..31 Reserved */ 1174 } bit; /**< Structure used for bit access */ 1175 uint32_t reg; /**< Type used for register access */ 1176 } GMAC_TPQ_Type; 1177 #endif 1178 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1179 1180 #define GMAC_TPQ_OFFSET (0x3C) /**< (GMAC_TPQ) Transmit Pause Quantum Register Offset */ 1181 1182 #define GMAC_TPQ_TPQ_Pos 0 /**< (GMAC_TPQ) Transmit Pause Quantum Position */ 1183 #define GMAC_TPQ_TPQ_Msk (_U_(0xFFFF) << GMAC_TPQ_TPQ_Pos) /**< (GMAC_TPQ) Transmit Pause Quantum Mask */ 1184 #define GMAC_TPQ_TPQ(value) (GMAC_TPQ_TPQ_Msk & ((value) << GMAC_TPQ_TPQ_Pos)) 1185 #define GMAC_TPQ_MASK _U_(0xFFFF) /**< \deprecated (GMAC_TPQ) Register MASK (Use GMAC_TPQ_Msk instead) */ 1186 #define GMAC_TPQ_Msk _U_(0xFFFF) /**< (GMAC_TPQ) Register Mask */ 1187 1188 1189 /* -------- GMAC_TPSF : (GMAC Offset: 0x40) (R/W 32) TX Partial Store and Forward Register -------- */ 1190 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1191 #if COMPONENT_TYPEDEF_STYLE == 'N' 1192 typedef union { 1193 struct { 1194 uint32_t TPB1ADR:12; /**< bit: 0..11 Transmit Partial Store and Forward Address */ 1195 uint32_t :19; /**< bit: 12..30 Reserved */ 1196 uint32_t ENTXP:1; /**< bit: 31 Enable TX Partial Store and Forward Operation */ 1197 } bit; /**< Structure used for bit access */ 1198 uint32_t reg; /**< Type used for register access */ 1199 } GMAC_TPSF_Type; 1200 #endif 1201 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1202 1203 #define GMAC_TPSF_OFFSET (0x40) /**< (GMAC_TPSF) TX Partial Store and Forward Register Offset */ 1204 1205 #define GMAC_TPSF_TPB1ADR_Pos 0 /**< (GMAC_TPSF) Transmit Partial Store and Forward Address Position */ 1206 #define GMAC_TPSF_TPB1ADR_Msk (_U_(0xFFF) << GMAC_TPSF_TPB1ADR_Pos) /**< (GMAC_TPSF) Transmit Partial Store and Forward Address Mask */ 1207 #define GMAC_TPSF_TPB1ADR(value) (GMAC_TPSF_TPB1ADR_Msk & ((value) << GMAC_TPSF_TPB1ADR_Pos)) 1208 #define GMAC_TPSF_ENTXP_Pos 31 /**< (GMAC_TPSF) Enable TX Partial Store and Forward Operation Position */ 1209 #define GMAC_TPSF_ENTXP_Msk (_U_(0x1) << GMAC_TPSF_ENTXP_Pos) /**< (GMAC_TPSF) Enable TX Partial Store and Forward Operation Mask */ 1210 #define GMAC_TPSF_ENTXP GMAC_TPSF_ENTXP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_TPSF_ENTXP_Msk instead */ 1211 #define GMAC_TPSF_MASK _U_(0x80000FFF) /**< \deprecated (GMAC_TPSF) Register MASK (Use GMAC_TPSF_Msk instead) */ 1212 #define GMAC_TPSF_Msk _U_(0x80000FFF) /**< (GMAC_TPSF) Register Mask */ 1213 1214 1215 /* -------- GMAC_RPSF : (GMAC Offset: 0x44) (R/W 32) RX Partial Store and Forward Register -------- */ 1216 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1217 #if COMPONENT_TYPEDEF_STYLE == 'N' 1218 typedef union { 1219 struct { 1220 uint32_t RPB1ADR:12; /**< bit: 0..11 Receive Partial Store and Forward Address */ 1221 uint32_t :19; /**< bit: 12..30 Reserved */ 1222 uint32_t ENRXP:1; /**< bit: 31 Enable RX Partial Store and Forward Operation */ 1223 } bit; /**< Structure used for bit access */ 1224 uint32_t reg; /**< Type used for register access */ 1225 } GMAC_RPSF_Type; 1226 #endif 1227 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1228 1229 #define GMAC_RPSF_OFFSET (0x44) /**< (GMAC_RPSF) RX Partial Store and Forward Register Offset */ 1230 1231 #define GMAC_RPSF_RPB1ADR_Pos 0 /**< (GMAC_RPSF) Receive Partial Store and Forward Address Position */ 1232 #define GMAC_RPSF_RPB1ADR_Msk (_U_(0xFFF) << GMAC_RPSF_RPB1ADR_Pos) /**< (GMAC_RPSF) Receive Partial Store and Forward Address Mask */ 1233 #define GMAC_RPSF_RPB1ADR(value) (GMAC_RPSF_RPB1ADR_Msk & ((value) << GMAC_RPSF_RPB1ADR_Pos)) 1234 #define GMAC_RPSF_ENRXP_Pos 31 /**< (GMAC_RPSF) Enable RX Partial Store and Forward Operation Position */ 1235 #define GMAC_RPSF_ENRXP_Msk (_U_(0x1) << GMAC_RPSF_ENRXP_Pos) /**< (GMAC_RPSF) Enable RX Partial Store and Forward Operation Mask */ 1236 #define GMAC_RPSF_ENRXP GMAC_RPSF_ENRXP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_RPSF_ENRXP_Msk instead */ 1237 #define GMAC_RPSF_MASK _U_(0x80000FFF) /**< \deprecated (GMAC_RPSF) Register MASK (Use GMAC_RPSF_Msk instead) */ 1238 #define GMAC_RPSF_Msk _U_(0x80000FFF) /**< (GMAC_RPSF) Register Mask */ 1239 1240 1241 /* -------- GMAC_RJFML : (GMAC Offset: 0x48) (R/W 32) RX Jumbo Frame Max Length Register -------- */ 1242 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1243 #if COMPONENT_TYPEDEF_STYLE == 'N' 1244 typedef union { 1245 struct { 1246 uint32_t FML:14; /**< bit: 0..13 Frame Max Length */ 1247 uint32_t :18; /**< bit: 14..31 Reserved */ 1248 } bit; /**< Structure used for bit access */ 1249 uint32_t reg; /**< Type used for register access */ 1250 } GMAC_RJFML_Type; 1251 #endif 1252 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1253 1254 #define GMAC_RJFML_OFFSET (0x48) /**< (GMAC_RJFML) RX Jumbo Frame Max Length Register Offset */ 1255 1256 #define GMAC_RJFML_FML_Pos 0 /**< (GMAC_RJFML) Frame Max Length Position */ 1257 #define GMAC_RJFML_FML_Msk (_U_(0x3FFF) << GMAC_RJFML_FML_Pos) /**< (GMAC_RJFML) Frame Max Length Mask */ 1258 #define GMAC_RJFML_FML(value) (GMAC_RJFML_FML_Msk & ((value) << GMAC_RJFML_FML_Pos)) 1259 #define GMAC_RJFML_MASK _U_(0x3FFF) /**< \deprecated (GMAC_RJFML) Register MASK (Use GMAC_RJFML_Msk instead) */ 1260 #define GMAC_RJFML_Msk _U_(0x3FFF) /**< (GMAC_RJFML) Register Mask */ 1261 1262 1263 /* -------- GMAC_HRB : (GMAC Offset: 0x80) (R/W 32) Hash Register Bottom -------- */ 1264 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1265 #if COMPONENT_TYPEDEF_STYLE == 'N' 1266 typedef union { 1267 struct { 1268 uint32_t ADDR:32; /**< bit: 0..31 Hash Address */ 1269 } bit; /**< Structure used for bit access */ 1270 uint32_t reg; /**< Type used for register access */ 1271 } GMAC_HRB_Type; 1272 #endif 1273 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1274 1275 #define GMAC_HRB_OFFSET (0x80) /**< (GMAC_HRB) Hash Register Bottom Offset */ 1276 1277 #define GMAC_HRB_ADDR_Pos 0 /**< (GMAC_HRB) Hash Address Position */ 1278 #define GMAC_HRB_ADDR_Msk (_U_(0xFFFFFFFF) << GMAC_HRB_ADDR_Pos) /**< (GMAC_HRB) Hash Address Mask */ 1279 #define GMAC_HRB_ADDR(value) (GMAC_HRB_ADDR_Msk & ((value) << GMAC_HRB_ADDR_Pos)) 1280 #define GMAC_HRB_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_HRB) Register MASK (Use GMAC_HRB_Msk instead) */ 1281 #define GMAC_HRB_Msk _U_(0xFFFFFFFF) /**< (GMAC_HRB) Register Mask */ 1282 1283 1284 /* -------- GMAC_HRT : (GMAC Offset: 0x84) (R/W 32) Hash Register Top -------- */ 1285 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1286 #if COMPONENT_TYPEDEF_STYLE == 'N' 1287 typedef union { 1288 struct { 1289 uint32_t ADDR:32; /**< bit: 0..31 Hash Address */ 1290 } bit; /**< Structure used for bit access */ 1291 uint32_t reg; /**< Type used for register access */ 1292 } GMAC_HRT_Type; 1293 #endif 1294 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1295 1296 #define GMAC_HRT_OFFSET (0x84) /**< (GMAC_HRT) Hash Register Top Offset */ 1297 1298 #define GMAC_HRT_ADDR_Pos 0 /**< (GMAC_HRT) Hash Address Position */ 1299 #define GMAC_HRT_ADDR_Msk (_U_(0xFFFFFFFF) << GMAC_HRT_ADDR_Pos) /**< (GMAC_HRT) Hash Address Mask */ 1300 #define GMAC_HRT_ADDR(value) (GMAC_HRT_ADDR_Msk & ((value) << GMAC_HRT_ADDR_Pos)) 1301 #define GMAC_HRT_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_HRT) Register MASK (Use GMAC_HRT_Msk instead) */ 1302 #define GMAC_HRT_Msk _U_(0xFFFFFFFF) /**< (GMAC_HRT) Register Mask */ 1303 1304 1305 /* -------- GMAC_TIDM1 : (GMAC Offset: 0xa8) (R/W 32) Type ID Match 1 Register -------- */ 1306 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1307 #if COMPONENT_TYPEDEF_STYLE == 'N' 1308 typedef union { 1309 struct { 1310 uint32_t TID:16; /**< bit: 0..15 Type ID Match 1 */ 1311 uint32_t :15; /**< bit: 16..30 Reserved */ 1312 uint32_t ENID1:1; /**< bit: 31 Enable Copying of TID Matched Frames */ 1313 } bit; /**< Structure used for bit access */ 1314 struct { 1315 uint32_t :31; /**< bit: 0..30 Reserved */ 1316 uint32_t ENID:1; /**< bit: 31 Enable Copying of TID Matched Frames */ 1317 } vec; /**< Structure used for vec access */ 1318 uint32_t reg; /**< Type used for register access */ 1319 } GMAC_TIDM1_Type; 1320 #endif 1321 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1322 1323 #define GMAC_TIDM1_OFFSET (0xA8) /**< (GMAC_TIDM1) Type ID Match 1 Register Offset */ 1324 1325 #define GMAC_TIDM1_TID_Pos 0 /**< (GMAC_TIDM1) Type ID Match 1 Position */ 1326 #define GMAC_TIDM1_TID_Msk (_U_(0xFFFF) << GMAC_TIDM1_TID_Pos) /**< (GMAC_TIDM1) Type ID Match 1 Mask */ 1327 #define GMAC_TIDM1_TID(value) (GMAC_TIDM1_TID_Msk & ((value) << GMAC_TIDM1_TID_Pos)) 1328 #define GMAC_TIDM1_ENID1_Pos 31 /**< (GMAC_TIDM1) Enable Copying of TID Matched Frames Position */ 1329 #define GMAC_TIDM1_ENID1_Msk (_U_(0x1) << GMAC_TIDM1_ENID1_Pos) /**< (GMAC_TIDM1) Enable Copying of TID Matched Frames Mask */ 1330 #define GMAC_TIDM1_ENID1 GMAC_TIDM1_ENID1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_TIDM1_ENID1_Msk instead */ 1331 #define GMAC_TIDM1_MASK _U_(0x8000FFFF) /**< \deprecated (GMAC_TIDM1) Register MASK (Use GMAC_TIDM1_Msk instead) */ 1332 #define GMAC_TIDM1_Msk _U_(0x8000FFFF) /**< (GMAC_TIDM1) Register Mask */ 1333 1334 #define GMAC_TIDM1_ENID_Pos 31 /**< (GMAC_TIDM1 Position) Enable Copying of TID Matched Frames */ 1335 #define GMAC_TIDM1_ENID_Msk (_U_(0x1) << GMAC_TIDM1_ENID_Pos) /**< (GMAC_TIDM1 Mask) ENID */ 1336 #define GMAC_TIDM1_ENID(value) (GMAC_TIDM1_ENID_Msk & ((value) << GMAC_TIDM1_ENID_Pos)) 1337 1338 /* -------- GMAC_TIDM2 : (GMAC Offset: 0xac) (R/W 32) Type ID Match 2 Register -------- */ 1339 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1340 #if COMPONENT_TYPEDEF_STYLE == 'N' 1341 typedef union { 1342 struct { 1343 uint32_t TID:16; /**< bit: 0..15 Type ID Match 2 */ 1344 uint32_t :15; /**< bit: 16..30 Reserved */ 1345 uint32_t ENID2:1; /**< bit: 31 Enable Copying of TID Matched Frames */ 1346 } bit; /**< Structure used for bit access */ 1347 struct { 1348 uint32_t :31; /**< bit: 0..30 Reserved */ 1349 uint32_t ENID:1; /**< bit: 31 Enable Copying of TID Matched Frames */ 1350 } vec; /**< Structure used for vec access */ 1351 uint32_t reg; /**< Type used for register access */ 1352 } GMAC_TIDM2_Type; 1353 #endif 1354 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1355 1356 #define GMAC_TIDM2_OFFSET (0xAC) /**< (GMAC_TIDM2) Type ID Match 2 Register Offset */ 1357 1358 #define GMAC_TIDM2_TID_Pos 0 /**< (GMAC_TIDM2) Type ID Match 2 Position */ 1359 #define GMAC_TIDM2_TID_Msk (_U_(0xFFFF) << GMAC_TIDM2_TID_Pos) /**< (GMAC_TIDM2) Type ID Match 2 Mask */ 1360 #define GMAC_TIDM2_TID(value) (GMAC_TIDM2_TID_Msk & ((value) << GMAC_TIDM2_TID_Pos)) 1361 #define GMAC_TIDM2_ENID2_Pos 31 /**< (GMAC_TIDM2) Enable Copying of TID Matched Frames Position */ 1362 #define GMAC_TIDM2_ENID2_Msk (_U_(0x1) << GMAC_TIDM2_ENID2_Pos) /**< (GMAC_TIDM2) Enable Copying of TID Matched Frames Mask */ 1363 #define GMAC_TIDM2_ENID2 GMAC_TIDM2_ENID2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_TIDM2_ENID2_Msk instead */ 1364 #define GMAC_TIDM2_MASK _U_(0x8000FFFF) /**< \deprecated (GMAC_TIDM2) Register MASK (Use GMAC_TIDM2_Msk instead) */ 1365 #define GMAC_TIDM2_Msk _U_(0x8000FFFF) /**< (GMAC_TIDM2) Register Mask */ 1366 1367 #define GMAC_TIDM2_ENID_Pos 31 /**< (GMAC_TIDM2 Position) Enable Copying of TID Matched Frames */ 1368 #define GMAC_TIDM2_ENID_Msk (_U_(0x1) << GMAC_TIDM2_ENID_Pos) /**< (GMAC_TIDM2 Mask) ENID */ 1369 #define GMAC_TIDM2_ENID(value) (GMAC_TIDM2_ENID_Msk & ((value) << GMAC_TIDM2_ENID_Pos)) 1370 1371 /* -------- GMAC_TIDM3 : (GMAC Offset: 0xb0) (R/W 32) Type ID Match 3 Register -------- */ 1372 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1373 #if COMPONENT_TYPEDEF_STYLE == 'N' 1374 typedef union { 1375 struct { 1376 uint32_t TID:16; /**< bit: 0..15 Type ID Match 3 */ 1377 uint32_t :15; /**< bit: 16..30 Reserved */ 1378 uint32_t ENID3:1; /**< bit: 31 Enable Copying of TID Matched Frames */ 1379 } bit; /**< Structure used for bit access */ 1380 struct { 1381 uint32_t :31; /**< bit: 0..30 Reserved */ 1382 uint32_t ENID:1; /**< bit: 31 Enable Copying of TID Matched Frames */ 1383 } vec; /**< Structure used for vec access */ 1384 uint32_t reg; /**< Type used for register access */ 1385 } GMAC_TIDM3_Type; 1386 #endif 1387 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1388 1389 #define GMAC_TIDM3_OFFSET (0xB0) /**< (GMAC_TIDM3) Type ID Match 3 Register Offset */ 1390 1391 #define GMAC_TIDM3_TID_Pos 0 /**< (GMAC_TIDM3) Type ID Match 3 Position */ 1392 #define GMAC_TIDM3_TID_Msk (_U_(0xFFFF) << GMAC_TIDM3_TID_Pos) /**< (GMAC_TIDM3) Type ID Match 3 Mask */ 1393 #define GMAC_TIDM3_TID(value) (GMAC_TIDM3_TID_Msk & ((value) << GMAC_TIDM3_TID_Pos)) 1394 #define GMAC_TIDM3_ENID3_Pos 31 /**< (GMAC_TIDM3) Enable Copying of TID Matched Frames Position */ 1395 #define GMAC_TIDM3_ENID3_Msk (_U_(0x1) << GMAC_TIDM3_ENID3_Pos) /**< (GMAC_TIDM3) Enable Copying of TID Matched Frames Mask */ 1396 #define GMAC_TIDM3_ENID3 GMAC_TIDM3_ENID3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_TIDM3_ENID3_Msk instead */ 1397 #define GMAC_TIDM3_MASK _U_(0x8000FFFF) /**< \deprecated (GMAC_TIDM3) Register MASK (Use GMAC_TIDM3_Msk instead) */ 1398 #define GMAC_TIDM3_Msk _U_(0x8000FFFF) /**< (GMAC_TIDM3) Register Mask */ 1399 1400 #define GMAC_TIDM3_ENID_Pos 31 /**< (GMAC_TIDM3 Position) Enable Copying of TID Matched Frames */ 1401 #define GMAC_TIDM3_ENID_Msk (_U_(0x1) << GMAC_TIDM3_ENID_Pos) /**< (GMAC_TIDM3 Mask) ENID */ 1402 #define GMAC_TIDM3_ENID(value) (GMAC_TIDM3_ENID_Msk & ((value) << GMAC_TIDM3_ENID_Pos)) 1403 1404 /* -------- GMAC_TIDM4 : (GMAC Offset: 0xb4) (R/W 32) Type ID Match 4 Register -------- */ 1405 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1406 #if COMPONENT_TYPEDEF_STYLE == 'N' 1407 typedef union { 1408 struct { 1409 uint32_t TID:16; /**< bit: 0..15 Type ID Match 4 */ 1410 uint32_t :15; /**< bit: 16..30 Reserved */ 1411 uint32_t ENID4:1; /**< bit: 31 Enable Copying of TID Matched Frames */ 1412 } bit; /**< Structure used for bit access */ 1413 struct { 1414 uint32_t :31; /**< bit: 0..30 Reserved */ 1415 uint32_t ENID:1; /**< bit: 31 Enable Copying of TID Matched Frames */ 1416 } vec; /**< Structure used for vec access */ 1417 uint32_t reg; /**< Type used for register access */ 1418 } GMAC_TIDM4_Type; 1419 #endif 1420 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1421 1422 #define GMAC_TIDM4_OFFSET (0xB4) /**< (GMAC_TIDM4) Type ID Match 4 Register Offset */ 1423 1424 #define GMAC_TIDM4_TID_Pos 0 /**< (GMAC_TIDM4) Type ID Match 4 Position */ 1425 #define GMAC_TIDM4_TID_Msk (_U_(0xFFFF) << GMAC_TIDM4_TID_Pos) /**< (GMAC_TIDM4) Type ID Match 4 Mask */ 1426 #define GMAC_TIDM4_TID(value) (GMAC_TIDM4_TID_Msk & ((value) << GMAC_TIDM4_TID_Pos)) 1427 #define GMAC_TIDM4_ENID4_Pos 31 /**< (GMAC_TIDM4) Enable Copying of TID Matched Frames Position */ 1428 #define GMAC_TIDM4_ENID4_Msk (_U_(0x1) << GMAC_TIDM4_ENID4_Pos) /**< (GMAC_TIDM4) Enable Copying of TID Matched Frames Mask */ 1429 #define GMAC_TIDM4_ENID4 GMAC_TIDM4_ENID4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_TIDM4_ENID4_Msk instead */ 1430 #define GMAC_TIDM4_MASK _U_(0x8000FFFF) /**< \deprecated (GMAC_TIDM4) Register MASK (Use GMAC_TIDM4_Msk instead) */ 1431 #define GMAC_TIDM4_Msk _U_(0x8000FFFF) /**< (GMAC_TIDM4) Register Mask */ 1432 1433 #define GMAC_TIDM4_ENID_Pos 31 /**< (GMAC_TIDM4 Position) Enable Copying of TID Matched Frames */ 1434 #define GMAC_TIDM4_ENID_Msk (_U_(0x1) << GMAC_TIDM4_ENID_Pos) /**< (GMAC_TIDM4 Mask) ENID */ 1435 #define GMAC_TIDM4_ENID(value) (GMAC_TIDM4_ENID_Msk & ((value) << GMAC_TIDM4_ENID_Pos)) 1436 1437 /* -------- GMAC_WOL : (GMAC Offset: 0xb8) (R/W 32) Wake on LAN Register -------- */ 1438 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1439 #if COMPONENT_TYPEDEF_STYLE == 'N' 1440 typedef union { 1441 struct { 1442 uint32_t IP:16; /**< bit: 0..15 ARP Request IP Address */ 1443 uint32_t MAG:1; /**< bit: 16 Magic Packet Event Enable */ 1444 uint32_t ARP:1; /**< bit: 17 ARP Request IP Address */ 1445 uint32_t SA1:1; /**< bit: 18 Specific Address Register 1 Event Enable */ 1446 uint32_t MTI:1; /**< bit: 19 Multicast Hash Event Enable */ 1447 uint32_t :12; /**< bit: 20..31 Reserved */ 1448 } bit; /**< Structure used for bit access */ 1449 struct { 1450 uint32_t :18; /**< bit: 0..17 Reserved */ 1451 uint32_t SA:1; /**< bit: 18 Specific Address Register x Event Enable */ 1452 uint32_t :13; /**< bit: 19..31 Reserved */ 1453 } vec; /**< Structure used for vec access */ 1454 uint32_t reg; /**< Type used for register access */ 1455 } GMAC_WOL_Type; 1456 #endif 1457 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1458 1459 #define GMAC_WOL_OFFSET (0xB8) /**< (GMAC_WOL) Wake on LAN Register Offset */ 1460 1461 #define GMAC_WOL_IP_Pos 0 /**< (GMAC_WOL) ARP Request IP Address Position */ 1462 #define GMAC_WOL_IP_Msk (_U_(0xFFFF) << GMAC_WOL_IP_Pos) /**< (GMAC_WOL) ARP Request IP Address Mask */ 1463 #define GMAC_WOL_IP(value) (GMAC_WOL_IP_Msk & ((value) << GMAC_WOL_IP_Pos)) 1464 #define GMAC_WOL_MAG_Pos 16 /**< (GMAC_WOL) Magic Packet Event Enable Position */ 1465 #define GMAC_WOL_MAG_Msk (_U_(0x1) << GMAC_WOL_MAG_Pos) /**< (GMAC_WOL) Magic Packet Event Enable Mask */ 1466 #define GMAC_WOL_MAG GMAC_WOL_MAG_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_WOL_MAG_Msk instead */ 1467 #define GMAC_WOL_ARP_Pos 17 /**< (GMAC_WOL) ARP Request IP Address Position */ 1468 #define GMAC_WOL_ARP_Msk (_U_(0x1) << GMAC_WOL_ARP_Pos) /**< (GMAC_WOL) ARP Request IP Address Mask */ 1469 #define GMAC_WOL_ARP GMAC_WOL_ARP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_WOL_ARP_Msk instead */ 1470 #define GMAC_WOL_SA1_Pos 18 /**< (GMAC_WOL) Specific Address Register 1 Event Enable Position */ 1471 #define GMAC_WOL_SA1_Msk (_U_(0x1) << GMAC_WOL_SA1_Pos) /**< (GMAC_WOL) Specific Address Register 1 Event Enable Mask */ 1472 #define GMAC_WOL_SA1 GMAC_WOL_SA1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_WOL_SA1_Msk instead */ 1473 #define GMAC_WOL_MTI_Pos 19 /**< (GMAC_WOL) Multicast Hash Event Enable Position */ 1474 #define GMAC_WOL_MTI_Msk (_U_(0x1) << GMAC_WOL_MTI_Pos) /**< (GMAC_WOL) Multicast Hash Event Enable Mask */ 1475 #define GMAC_WOL_MTI GMAC_WOL_MTI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_WOL_MTI_Msk instead */ 1476 #define GMAC_WOL_MASK _U_(0xFFFFF) /**< \deprecated (GMAC_WOL) Register MASK (Use GMAC_WOL_Msk instead) */ 1477 #define GMAC_WOL_Msk _U_(0xFFFFF) /**< (GMAC_WOL) Register Mask */ 1478 1479 #define GMAC_WOL_SA_Pos 18 /**< (GMAC_WOL Position) Specific Address Register x Event Enable */ 1480 #define GMAC_WOL_SA_Msk (_U_(0x1) << GMAC_WOL_SA_Pos) /**< (GMAC_WOL Mask) SA */ 1481 #define GMAC_WOL_SA(value) (GMAC_WOL_SA_Msk & ((value) << GMAC_WOL_SA_Pos)) 1482 1483 /* -------- GMAC_IPGS : (GMAC Offset: 0xbc) (R/W 32) IPG Stretch Register -------- */ 1484 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1485 #if COMPONENT_TYPEDEF_STYLE == 'N' 1486 typedef union { 1487 struct { 1488 uint32_t FL:16; /**< bit: 0..15 Frame Length */ 1489 uint32_t :16; /**< bit: 16..31 Reserved */ 1490 } bit; /**< Structure used for bit access */ 1491 uint32_t reg; /**< Type used for register access */ 1492 } GMAC_IPGS_Type; 1493 #endif 1494 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1495 1496 #define GMAC_IPGS_OFFSET (0xBC) /**< (GMAC_IPGS) IPG Stretch Register Offset */ 1497 1498 #define GMAC_IPGS_FL_Pos 0 /**< (GMAC_IPGS) Frame Length Position */ 1499 #define GMAC_IPGS_FL_Msk (_U_(0xFFFF) << GMAC_IPGS_FL_Pos) /**< (GMAC_IPGS) Frame Length Mask */ 1500 #define GMAC_IPGS_FL(value) (GMAC_IPGS_FL_Msk & ((value) << GMAC_IPGS_FL_Pos)) 1501 #define GMAC_IPGS_MASK _U_(0xFFFF) /**< \deprecated (GMAC_IPGS) Register MASK (Use GMAC_IPGS_Msk instead) */ 1502 #define GMAC_IPGS_Msk _U_(0xFFFF) /**< (GMAC_IPGS) Register Mask */ 1503 1504 1505 /* -------- GMAC_SVLAN : (GMAC Offset: 0xc0) (R/W 32) Stacked VLAN Register -------- */ 1506 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1507 #if COMPONENT_TYPEDEF_STYLE == 'N' 1508 typedef union { 1509 struct { 1510 uint32_t VLAN_TYPE:16; /**< bit: 0..15 User Defined VLAN_TYPE Field */ 1511 uint32_t :15; /**< bit: 16..30 Reserved */ 1512 uint32_t ESVLAN:1; /**< bit: 31 Enable Stacked VLAN Processing Mode */ 1513 } bit; /**< Structure used for bit access */ 1514 uint32_t reg; /**< Type used for register access */ 1515 } GMAC_SVLAN_Type; 1516 #endif 1517 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1518 1519 #define GMAC_SVLAN_OFFSET (0xC0) /**< (GMAC_SVLAN) Stacked VLAN Register Offset */ 1520 1521 #define GMAC_SVLAN_VLAN_TYPE_Pos 0 /**< (GMAC_SVLAN) User Defined VLAN_TYPE Field Position */ 1522 #define GMAC_SVLAN_VLAN_TYPE_Msk (_U_(0xFFFF) << GMAC_SVLAN_VLAN_TYPE_Pos) /**< (GMAC_SVLAN) User Defined VLAN_TYPE Field Mask */ 1523 #define GMAC_SVLAN_VLAN_TYPE(value) (GMAC_SVLAN_VLAN_TYPE_Msk & ((value) << GMAC_SVLAN_VLAN_TYPE_Pos)) 1524 #define GMAC_SVLAN_ESVLAN_Pos 31 /**< (GMAC_SVLAN) Enable Stacked VLAN Processing Mode Position */ 1525 #define GMAC_SVLAN_ESVLAN_Msk (_U_(0x1) << GMAC_SVLAN_ESVLAN_Pos) /**< (GMAC_SVLAN) Enable Stacked VLAN Processing Mode Mask */ 1526 #define GMAC_SVLAN_ESVLAN GMAC_SVLAN_ESVLAN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_SVLAN_ESVLAN_Msk instead */ 1527 #define GMAC_SVLAN_MASK _U_(0x8000FFFF) /**< \deprecated (GMAC_SVLAN) Register MASK (Use GMAC_SVLAN_Msk instead) */ 1528 #define GMAC_SVLAN_Msk _U_(0x8000FFFF) /**< (GMAC_SVLAN) Register Mask */ 1529 1530 1531 /* -------- GMAC_TPFCP : (GMAC Offset: 0xc4) (R/W 32) Transmit PFC Pause Register -------- */ 1532 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1533 #if COMPONENT_TYPEDEF_STYLE == 'N' 1534 typedef union { 1535 struct { 1536 uint32_t PEV:8; /**< bit: 0..7 Priority Enable Vector */ 1537 uint32_t PQ:8; /**< bit: 8..15 Pause Quantum */ 1538 uint32_t :16; /**< bit: 16..31 Reserved */ 1539 } bit; /**< Structure used for bit access */ 1540 uint32_t reg; /**< Type used for register access */ 1541 } GMAC_TPFCP_Type; 1542 #endif 1543 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1544 1545 #define GMAC_TPFCP_OFFSET (0xC4) /**< (GMAC_TPFCP) Transmit PFC Pause Register Offset */ 1546 1547 #define GMAC_TPFCP_PEV_Pos 0 /**< (GMAC_TPFCP) Priority Enable Vector Position */ 1548 #define GMAC_TPFCP_PEV_Msk (_U_(0xFF) << GMAC_TPFCP_PEV_Pos) /**< (GMAC_TPFCP) Priority Enable Vector Mask */ 1549 #define GMAC_TPFCP_PEV(value) (GMAC_TPFCP_PEV_Msk & ((value) << GMAC_TPFCP_PEV_Pos)) 1550 #define GMAC_TPFCP_PQ_Pos 8 /**< (GMAC_TPFCP) Pause Quantum Position */ 1551 #define GMAC_TPFCP_PQ_Msk (_U_(0xFF) << GMAC_TPFCP_PQ_Pos) /**< (GMAC_TPFCP) Pause Quantum Mask */ 1552 #define GMAC_TPFCP_PQ(value) (GMAC_TPFCP_PQ_Msk & ((value) << GMAC_TPFCP_PQ_Pos)) 1553 #define GMAC_TPFCP_MASK _U_(0xFFFF) /**< \deprecated (GMAC_TPFCP) Register MASK (Use GMAC_TPFCP_Msk instead) */ 1554 #define GMAC_TPFCP_Msk _U_(0xFFFF) /**< (GMAC_TPFCP) Register Mask */ 1555 1556 1557 /* -------- GMAC_SAMB1 : (GMAC Offset: 0xc8) (R/W 32) Specific Address 1 Mask Bottom Register -------- */ 1558 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1559 #if COMPONENT_TYPEDEF_STYLE == 'N' 1560 typedef union { 1561 struct { 1562 uint32_t ADDR:32; /**< bit: 0..31 Specific Address 1 Mask */ 1563 } bit; /**< Structure used for bit access */ 1564 uint32_t reg; /**< Type used for register access */ 1565 } GMAC_SAMB1_Type; 1566 #endif 1567 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1568 1569 #define GMAC_SAMB1_OFFSET (0xC8) /**< (GMAC_SAMB1) Specific Address 1 Mask Bottom Register Offset */ 1570 1571 #define GMAC_SAMB1_ADDR_Pos 0 /**< (GMAC_SAMB1) Specific Address 1 Mask Position */ 1572 #define GMAC_SAMB1_ADDR_Msk (_U_(0xFFFFFFFF) << GMAC_SAMB1_ADDR_Pos) /**< (GMAC_SAMB1) Specific Address 1 Mask Mask */ 1573 #define GMAC_SAMB1_ADDR(value) (GMAC_SAMB1_ADDR_Msk & ((value) << GMAC_SAMB1_ADDR_Pos)) 1574 #define GMAC_SAMB1_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_SAMB1) Register MASK (Use GMAC_SAMB1_Msk instead) */ 1575 #define GMAC_SAMB1_Msk _U_(0xFFFFFFFF) /**< (GMAC_SAMB1) Register Mask */ 1576 1577 1578 /* -------- GMAC_SAMT1 : (GMAC Offset: 0xcc) (R/W 32) Specific Address 1 Mask Top Register -------- */ 1579 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1580 #if COMPONENT_TYPEDEF_STYLE == 'N' 1581 typedef union { 1582 struct { 1583 uint32_t ADDR:16; /**< bit: 0..15 Specific Address 1 Mask */ 1584 uint32_t :16; /**< bit: 16..31 Reserved */ 1585 } bit; /**< Structure used for bit access */ 1586 uint32_t reg; /**< Type used for register access */ 1587 } GMAC_SAMT1_Type; 1588 #endif 1589 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1590 1591 #define GMAC_SAMT1_OFFSET (0xCC) /**< (GMAC_SAMT1) Specific Address 1 Mask Top Register Offset */ 1592 1593 #define GMAC_SAMT1_ADDR_Pos 0 /**< (GMAC_SAMT1) Specific Address 1 Mask Position */ 1594 #define GMAC_SAMT1_ADDR_Msk (_U_(0xFFFF) << GMAC_SAMT1_ADDR_Pos) /**< (GMAC_SAMT1) Specific Address 1 Mask Mask */ 1595 #define GMAC_SAMT1_ADDR(value) (GMAC_SAMT1_ADDR_Msk & ((value) << GMAC_SAMT1_ADDR_Pos)) 1596 #define GMAC_SAMT1_MASK _U_(0xFFFF) /**< \deprecated (GMAC_SAMT1) Register MASK (Use GMAC_SAMT1_Msk instead) */ 1597 #define GMAC_SAMT1_Msk _U_(0xFFFF) /**< (GMAC_SAMT1) Register Mask */ 1598 1599 1600 /* -------- GMAC_NSC : (GMAC Offset: 0xdc) (R/W 32) 1588 Timer Nanosecond Comparison Register -------- */ 1601 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1602 #if COMPONENT_TYPEDEF_STYLE == 'N' 1603 typedef union { 1604 struct { 1605 uint32_t NANOSEC:22; /**< bit: 0..21 1588 Timer Nanosecond Comparison Value */ 1606 uint32_t :10; /**< bit: 22..31 Reserved */ 1607 } bit; /**< Structure used for bit access */ 1608 uint32_t reg; /**< Type used for register access */ 1609 } GMAC_NSC_Type; 1610 #endif 1611 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1612 1613 #define GMAC_NSC_OFFSET (0xDC) /**< (GMAC_NSC) 1588 Timer Nanosecond Comparison Register Offset */ 1614 1615 #define GMAC_NSC_NANOSEC_Pos 0 /**< (GMAC_NSC) 1588 Timer Nanosecond Comparison Value Position */ 1616 #define GMAC_NSC_NANOSEC_Msk (_U_(0x3FFFFF) << GMAC_NSC_NANOSEC_Pos) /**< (GMAC_NSC) 1588 Timer Nanosecond Comparison Value Mask */ 1617 #define GMAC_NSC_NANOSEC(value) (GMAC_NSC_NANOSEC_Msk & ((value) << GMAC_NSC_NANOSEC_Pos)) 1618 #define GMAC_NSC_MASK _U_(0x3FFFFF) /**< \deprecated (GMAC_NSC) Register MASK (Use GMAC_NSC_Msk instead) */ 1619 #define GMAC_NSC_Msk _U_(0x3FFFFF) /**< (GMAC_NSC) Register Mask */ 1620 1621 1622 /* -------- GMAC_SCL : (GMAC Offset: 0xe0) (R/W 32) 1588 Timer Second Comparison Low Register -------- */ 1623 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1624 #if COMPONENT_TYPEDEF_STYLE == 'N' 1625 typedef union { 1626 struct { 1627 uint32_t SEC:32; /**< bit: 0..31 1588 Timer Second Comparison Value */ 1628 } bit; /**< Structure used for bit access */ 1629 uint32_t reg; /**< Type used for register access */ 1630 } GMAC_SCL_Type; 1631 #endif 1632 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1633 1634 #define GMAC_SCL_OFFSET (0xE0) /**< (GMAC_SCL) 1588 Timer Second Comparison Low Register Offset */ 1635 1636 #define GMAC_SCL_SEC_Pos 0 /**< (GMAC_SCL) 1588 Timer Second Comparison Value Position */ 1637 #define GMAC_SCL_SEC_Msk (_U_(0xFFFFFFFF) << GMAC_SCL_SEC_Pos) /**< (GMAC_SCL) 1588 Timer Second Comparison Value Mask */ 1638 #define GMAC_SCL_SEC(value) (GMAC_SCL_SEC_Msk & ((value) << GMAC_SCL_SEC_Pos)) 1639 #define GMAC_SCL_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_SCL) Register MASK (Use GMAC_SCL_Msk instead) */ 1640 #define GMAC_SCL_Msk _U_(0xFFFFFFFF) /**< (GMAC_SCL) Register Mask */ 1641 1642 1643 /* -------- GMAC_SCH : (GMAC Offset: 0xe4) (R/W 32) 1588 Timer Second Comparison High Register -------- */ 1644 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1645 #if COMPONENT_TYPEDEF_STYLE == 'N' 1646 typedef union { 1647 struct { 1648 uint32_t SEC:16; /**< bit: 0..15 1588 Timer Second Comparison Value */ 1649 uint32_t :16; /**< bit: 16..31 Reserved */ 1650 } bit; /**< Structure used for bit access */ 1651 uint32_t reg; /**< Type used for register access */ 1652 } GMAC_SCH_Type; 1653 #endif 1654 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1655 1656 #define GMAC_SCH_OFFSET (0xE4) /**< (GMAC_SCH) 1588 Timer Second Comparison High Register Offset */ 1657 1658 #define GMAC_SCH_SEC_Pos 0 /**< (GMAC_SCH) 1588 Timer Second Comparison Value Position */ 1659 #define GMAC_SCH_SEC_Msk (_U_(0xFFFF) << GMAC_SCH_SEC_Pos) /**< (GMAC_SCH) 1588 Timer Second Comparison Value Mask */ 1660 #define GMAC_SCH_SEC(value) (GMAC_SCH_SEC_Msk & ((value) << GMAC_SCH_SEC_Pos)) 1661 #define GMAC_SCH_MASK _U_(0xFFFF) /**< \deprecated (GMAC_SCH) Register MASK (Use GMAC_SCH_Msk instead) */ 1662 #define GMAC_SCH_Msk _U_(0xFFFF) /**< (GMAC_SCH) Register Mask */ 1663 1664 1665 /* -------- GMAC_EFTSH : (GMAC Offset: 0xe8) (R/ 32) PTP Event Frame Transmitted Seconds High Register -------- */ 1666 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1667 #if COMPONENT_TYPEDEF_STYLE == 'N' 1668 typedef union { 1669 struct { 1670 uint32_t RUD:16; /**< bit: 0..15 Register Update */ 1671 uint32_t :16; /**< bit: 16..31 Reserved */ 1672 } bit; /**< Structure used for bit access */ 1673 uint32_t reg; /**< Type used for register access */ 1674 } GMAC_EFTSH_Type; 1675 #endif 1676 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1677 1678 #define GMAC_EFTSH_OFFSET (0xE8) /**< (GMAC_EFTSH) PTP Event Frame Transmitted Seconds High Register Offset */ 1679 1680 #define GMAC_EFTSH_RUD_Pos 0 /**< (GMAC_EFTSH) Register Update Position */ 1681 #define GMAC_EFTSH_RUD_Msk (_U_(0xFFFF) << GMAC_EFTSH_RUD_Pos) /**< (GMAC_EFTSH) Register Update Mask */ 1682 #define GMAC_EFTSH_RUD(value) (GMAC_EFTSH_RUD_Msk & ((value) << GMAC_EFTSH_RUD_Pos)) 1683 #define GMAC_EFTSH_MASK _U_(0xFFFF) /**< \deprecated (GMAC_EFTSH) Register MASK (Use GMAC_EFTSH_Msk instead) */ 1684 #define GMAC_EFTSH_Msk _U_(0xFFFF) /**< (GMAC_EFTSH) Register Mask */ 1685 1686 1687 /* -------- GMAC_EFRSH : (GMAC Offset: 0xec) (R/ 32) PTP Event Frame Received Seconds High Register -------- */ 1688 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1689 #if COMPONENT_TYPEDEF_STYLE == 'N' 1690 typedef union { 1691 struct { 1692 uint32_t RUD:16; /**< bit: 0..15 Register Update */ 1693 uint32_t :16; /**< bit: 16..31 Reserved */ 1694 } bit; /**< Structure used for bit access */ 1695 uint32_t reg; /**< Type used for register access */ 1696 } GMAC_EFRSH_Type; 1697 #endif 1698 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1699 1700 #define GMAC_EFRSH_OFFSET (0xEC) /**< (GMAC_EFRSH) PTP Event Frame Received Seconds High Register Offset */ 1701 1702 #define GMAC_EFRSH_RUD_Pos 0 /**< (GMAC_EFRSH) Register Update Position */ 1703 #define GMAC_EFRSH_RUD_Msk (_U_(0xFFFF) << GMAC_EFRSH_RUD_Pos) /**< (GMAC_EFRSH) Register Update Mask */ 1704 #define GMAC_EFRSH_RUD(value) (GMAC_EFRSH_RUD_Msk & ((value) << GMAC_EFRSH_RUD_Pos)) 1705 #define GMAC_EFRSH_MASK _U_(0xFFFF) /**< \deprecated (GMAC_EFRSH) Register MASK (Use GMAC_EFRSH_Msk instead) */ 1706 #define GMAC_EFRSH_Msk _U_(0xFFFF) /**< (GMAC_EFRSH) Register Mask */ 1707 1708 1709 /* -------- GMAC_PEFTSH : (GMAC Offset: 0xf0) (R/ 32) PTP Peer Event Frame Transmitted Seconds High Register -------- */ 1710 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1711 #if COMPONENT_TYPEDEF_STYLE == 'N' 1712 typedef union { 1713 struct { 1714 uint32_t RUD:16; /**< bit: 0..15 Register Update */ 1715 uint32_t :16; /**< bit: 16..31 Reserved */ 1716 } bit; /**< Structure used for bit access */ 1717 uint32_t reg; /**< Type used for register access */ 1718 } GMAC_PEFTSH_Type; 1719 #endif 1720 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1721 1722 #define GMAC_PEFTSH_OFFSET (0xF0) /**< (GMAC_PEFTSH) PTP Peer Event Frame Transmitted Seconds High Register Offset */ 1723 1724 #define GMAC_PEFTSH_RUD_Pos 0 /**< (GMAC_PEFTSH) Register Update Position */ 1725 #define GMAC_PEFTSH_RUD_Msk (_U_(0xFFFF) << GMAC_PEFTSH_RUD_Pos) /**< (GMAC_PEFTSH) Register Update Mask */ 1726 #define GMAC_PEFTSH_RUD(value) (GMAC_PEFTSH_RUD_Msk & ((value) << GMAC_PEFTSH_RUD_Pos)) 1727 #define GMAC_PEFTSH_MASK _U_(0xFFFF) /**< \deprecated (GMAC_PEFTSH) Register MASK (Use GMAC_PEFTSH_Msk instead) */ 1728 #define GMAC_PEFTSH_Msk _U_(0xFFFF) /**< (GMAC_PEFTSH) Register Mask */ 1729 1730 1731 /* -------- GMAC_PEFRSH : (GMAC Offset: 0xf4) (R/ 32) PTP Peer Event Frame Received Seconds High Register -------- */ 1732 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1733 #if COMPONENT_TYPEDEF_STYLE == 'N' 1734 typedef union { 1735 struct { 1736 uint32_t RUD:16; /**< bit: 0..15 Register Update */ 1737 uint32_t :16; /**< bit: 16..31 Reserved */ 1738 } bit; /**< Structure used for bit access */ 1739 uint32_t reg; /**< Type used for register access */ 1740 } GMAC_PEFRSH_Type; 1741 #endif 1742 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1743 1744 #define GMAC_PEFRSH_OFFSET (0xF4) /**< (GMAC_PEFRSH) PTP Peer Event Frame Received Seconds High Register Offset */ 1745 1746 #define GMAC_PEFRSH_RUD_Pos 0 /**< (GMAC_PEFRSH) Register Update Position */ 1747 #define GMAC_PEFRSH_RUD_Msk (_U_(0xFFFF) << GMAC_PEFRSH_RUD_Pos) /**< (GMAC_PEFRSH) Register Update Mask */ 1748 #define GMAC_PEFRSH_RUD(value) (GMAC_PEFRSH_RUD_Msk & ((value) << GMAC_PEFRSH_RUD_Pos)) 1749 #define GMAC_PEFRSH_MASK _U_(0xFFFF) /**< \deprecated (GMAC_PEFRSH) Register MASK (Use GMAC_PEFRSH_Msk instead) */ 1750 #define GMAC_PEFRSH_Msk _U_(0xFFFF) /**< (GMAC_PEFRSH) Register Mask */ 1751 1752 1753 /* -------- GMAC_OTLO : (GMAC Offset: 0x100) (R/ 32) Octets Transmitted Low Register -------- */ 1754 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1755 #if COMPONENT_TYPEDEF_STYLE == 'N' 1756 typedef union { 1757 struct { 1758 uint32_t TXO:32; /**< bit: 0..31 Transmitted Octets */ 1759 } bit; /**< Structure used for bit access */ 1760 uint32_t reg; /**< Type used for register access */ 1761 } GMAC_OTLO_Type; 1762 #endif 1763 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1764 1765 #define GMAC_OTLO_OFFSET (0x100) /**< (GMAC_OTLO) Octets Transmitted Low Register Offset */ 1766 1767 #define GMAC_OTLO_TXO_Pos 0 /**< (GMAC_OTLO) Transmitted Octets Position */ 1768 #define GMAC_OTLO_TXO_Msk (_U_(0xFFFFFFFF) << GMAC_OTLO_TXO_Pos) /**< (GMAC_OTLO) Transmitted Octets Mask */ 1769 #define GMAC_OTLO_TXO(value) (GMAC_OTLO_TXO_Msk & ((value) << GMAC_OTLO_TXO_Pos)) 1770 #define GMAC_OTLO_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_OTLO) Register MASK (Use GMAC_OTLO_Msk instead) */ 1771 #define GMAC_OTLO_Msk _U_(0xFFFFFFFF) /**< (GMAC_OTLO) Register Mask */ 1772 1773 1774 /* -------- GMAC_OTHI : (GMAC Offset: 0x104) (R/ 32) Octets Transmitted High Register -------- */ 1775 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1776 #if COMPONENT_TYPEDEF_STYLE == 'N' 1777 typedef union { 1778 struct { 1779 uint32_t TXO:16; /**< bit: 0..15 Transmitted Octets */ 1780 uint32_t :16; /**< bit: 16..31 Reserved */ 1781 } bit; /**< Structure used for bit access */ 1782 uint32_t reg; /**< Type used for register access */ 1783 } GMAC_OTHI_Type; 1784 #endif 1785 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1786 1787 #define GMAC_OTHI_OFFSET (0x104) /**< (GMAC_OTHI) Octets Transmitted High Register Offset */ 1788 1789 #define GMAC_OTHI_TXO_Pos 0 /**< (GMAC_OTHI) Transmitted Octets Position */ 1790 #define GMAC_OTHI_TXO_Msk (_U_(0xFFFF) << GMAC_OTHI_TXO_Pos) /**< (GMAC_OTHI) Transmitted Octets Mask */ 1791 #define GMAC_OTHI_TXO(value) (GMAC_OTHI_TXO_Msk & ((value) << GMAC_OTHI_TXO_Pos)) 1792 #define GMAC_OTHI_MASK _U_(0xFFFF) /**< \deprecated (GMAC_OTHI) Register MASK (Use GMAC_OTHI_Msk instead) */ 1793 #define GMAC_OTHI_Msk _U_(0xFFFF) /**< (GMAC_OTHI) Register Mask */ 1794 1795 1796 /* -------- GMAC_FT : (GMAC Offset: 0x108) (R/ 32) Frames Transmitted Register -------- */ 1797 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1798 #if COMPONENT_TYPEDEF_STYLE == 'N' 1799 typedef union { 1800 struct { 1801 uint32_t FTX:32; /**< bit: 0..31 Frames Transmitted without Error */ 1802 } bit; /**< Structure used for bit access */ 1803 uint32_t reg; /**< Type used for register access */ 1804 } GMAC_FT_Type; 1805 #endif 1806 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1807 1808 #define GMAC_FT_OFFSET (0x108) /**< (GMAC_FT) Frames Transmitted Register Offset */ 1809 1810 #define GMAC_FT_FTX_Pos 0 /**< (GMAC_FT) Frames Transmitted without Error Position */ 1811 #define GMAC_FT_FTX_Msk (_U_(0xFFFFFFFF) << GMAC_FT_FTX_Pos) /**< (GMAC_FT) Frames Transmitted without Error Mask */ 1812 #define GMAC_FT_FTX(value) (GMAC_FT_FTX_Msk & ((value) << GMAC_FT_FTX_Pos)) 1813 #define GMAC_FT_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_FT) Register MASK (Use GMAC_FT_Msk instead) */ 1814 #define GMAC_FT_Msk _U_(0xFFFFFFFF) /**< (GMAC_FT) Register Mask */ 1815 1816 1817 /* -------- GMAC_BCFT : (GMAC Offset: 0x10c) (R/ 32) Broadcast Frames Transmitted Register -------- */ 1818 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1819 #if COMPONENT_TYPEDEF_STYLE == 'N' 1820 typedef union { 1821 struct { 1822 uint32_t BFTX:32; /**< bit: 0..31 Broadcast Frames Transmitted without Error */ 1823 } bit; /**< Structure used for bit access */ 1824 uint32_t reg; /**< Type used for register access */ 1825 } GMAC_BCFT_Type; 1826 #endif 1827 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1828 1829 #define GMAC_BCFT_OFFSET (0x10C) /**< (GMAC_BCFT) Broadcast Frames Transmitted Register Offset */ 1830 1831 #define GMAC_BCFT_BFTX_Pos 0 /**< (GMAC_BCFT) Broadcast Frames Transmitted without Error Position */ 1832 #define GMAC_BCFT_BFTX_Msk (_U_(0xFFFFFFFF) << GMAC_BCFT_BFTX_Pos) /**< (GMAC_BCFT) Broadcast Frames Transmitted without Error Mask */ 1833 #define GMAC_BCFT_BFTX(value) (GMAC_BCFT_BFTX_Msk & ((value) << GMAC_BCFT_BFTX_Pos)) 1834 #define GMAC_BCFT_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_BCFT) Register MASK (Use GMAC_BCFT_Msk instead) */ 1835 #define GMAC_BCFT_Msk _U_(0xFFFFFFFF) /**< (GMAC_BCFT) Register Mask */ 1836 1837 1838 /* -------- GMAC_MFT : (GMAC Offset: 0x110) (R/ 32) Multicast Frames Transmitted Register -------- */ 1839 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1840 #if COMPONENT_TYPEDEF_STYLE == 'N' 1841 typedef union { 1842 struct { 1843 uint32_t MFTX:32; /**< bit: 0..31 Multicast Frames Transmitted without Error */ 1844 } bit; /**< Structure used for bit access */ 1845 uint32_t reg; /**< Type used for register access */ 1846 } GMAC_MFT_Type; 1847 #endif 1848 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1849 1850 #define GMAC_MFT_OFFSET (0x110) /**< (GMAC_MFT) Multicast Frames Transmitted Register Offset */ 1851 1852 #define GMAC_MFT_MFTX_Pos 0 /**< (GMAC_MFT) Multicast Frames Transmitted without Error Position */ 1853 #define GMAC_MFT_MFTX_Msk (_U_(0xFFFFFFFF) << GMAC_MFT_MFTX_Pos) /**< (GMAC_MFT) Multicast Frames Transmitted without Error Mask */ 1854 #define GMAC_MFT_MFTX(value) (GMAC_MFT_MFTX_Msk & ((value) << GMAC_MFT_MFTX_Pos)) 1855 #define GMAC_MFT_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_MFT) Register MASK (Use GMAC_MFT_Msk instead) */ 1856 #define GMAC_MFT_Msk _U_(0xFFFFFFFF) /**< (GMAC_MFT) Register Mask */ 1857 1858 1859 /* -------- GMAC_PFT : (GMAC Offset: 0x114) (R/ 32) Pause Frames Transmitted Register -------- */ 1860 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1861 #if COMPONENT_TYPEDEF_STYLE == 'N' 1862 typedef union { 1863 struct { 1864 uint32_t PFTX:16; /**< bit: 0..15 Pause Frames Transmitted Register */ 1865 uint32_t :16; /**< bit: 16..31 Reserved */ 1866 } bit; /**< Structure used for bit access */ 1867 uint32_t reg; /**< Type used for register access */ 1868 } GMAC_PFT_Type; 1869 #endif 1870 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1871 1872 #define GMAC_PFT_OFFSET (0x114) /**< (GMAC_PFT) Pause Frames Transmitted Register Offset */ 1873 1874 #define GMAC_PFT_PFTX_Pos 0 /**< (GMAC_PFT) Pause Frames Transmitted Register Position */ 1875 #define GMAC_PFT_PFTX_Msk (_U_(0xFFFF) << GMAC_PFT_PFTX_Pos) /**< (GMAC_PFT) Pause Frames Transmitted Register Mask */ 1876 #define GMAC_PFT_PFTX(value) (GMAC_PFT_PFTX_Msk & ((value) << GMAC_PFT_PFTX_Pos)) 1877 #define GMAC_PFT_MASK _U_(0xFFFF) /**< \deprecated (GMAC_PFT) Register MASK (Use GMAC_PFT_Msk instead) */ 1878 #define GMAC_PFT_Msk _U_(0xFFFF) /**< (GMAC_PFT) Register Mask */ 1879 1880 1881 /* -------- GMAC_BFT64 : (GMAC Offset: 0x118) (R/ 32) 64 Byte Frames Transmitted Register -------- */ 1882 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1883 #if COMPONENT_TYPEDEF_STYLE == 'N' 1884 typedef union { 1885 struct { 1886 uint32_t NFTX:32; /**< bit: 0..31 64 Byte Frames Transmitted without Error */ 1887 } bit; /**< Structure used for bit access */ 1888 uint32_t reg; /**< Type used for register access */ 1889 } GMAC_BFT64_Type; 1890 #endif 1891 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1892 1893 #define GMAC_BFT64_OFFSET (0x118) /**< (GMAC_BFT64) 64 Byte Frames Transmitted Register Offset */ 1894 1895 #define GMAC_BFT64_NFTX_Pos 0 /**< (GMAC_BFT64) 64 Byte Frames Transmitted without Error Position */ 1896 #define GMAC_BFT64_NFTX_Msk (_U_(0xFFFFFFFF) << GMAC_BFT64_NFTX_Pos) /**< (GMAC_BFT64) 64 Byte Frames Transmitted without Error Mask */ 1897 #define GMAC_BFT64_NFTX(value) (GMAC_BFT64_NFTX_Msk & ((value) << GMAC_BFT64_NFTX_Pos)) 1898 #define GMAC_BFT64_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_BFT64) Register MASK (Use GMAC_BFT64_Msk instead) */ 1899 #define GMAC_BFT64_Msk _U_(0xFFFFFFFF) /**< (GMAC_BFT64) Register Mask */ 1900 1901 1902 /* -------- GMAC_TBFT127 : (GMAC Offset: 0x11c) (R/ 32) 65 to 127 Byte Frames Transmitted Register -------- */ 1903 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1904 #if COMPONENT_TYPEDEF_STYLE == 'N' 1905 typedef union { 1906 struct { 1907 uint32_t NFTX:32; /**< bit: 0..31 65 to 127 Byte Frames Transmitted without Error */ 1908 } bit; /**< Structure used for bit access */ 1909 uint32_t reg; /**< Type used for register access */ 1910 } GMAC_TBFT127_Type; 1911 #endif 1912 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1913 1914 #define GMAC_TBFT127_OFFSET (0x11C) /**< (GMAC_TBFT127) 65 to 127 Byte Frames Transmitted Register Offset */ 1915 1916 #define GMAC_TBFT127_NFTX_Pos 0 /**< (GMAC_TBFT127) 65 to 127 Byte Frames Transmitted without Error Position */ 1917 #define GMAC_TBFT127_NFTX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFT127_NFTX_Pos) /**< (GMAC_TBFT127) 65 to 127 Byte Frames Transmitted without Error Mask */ 1918 #define GMAC_TBFT127_NFTX(value) (GMAC_TBFT127_NFTX_Msk & ((value) << GMAC_TBFT127_NFTX_Pos)) 1919 #define GMAC_TBFT127_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_TBFT127) Register MASK (Use GMAC_TBFT127_Msk instead) */ 1920 #define GMAC_TBFT127_Msk _U_(0xFFFFFFFF) /**< (GMAC_TBFT127) Register Mask */ 1921 1922 1923 /* -------- GMAC_TBFT255 : (GMAC Offset: 0x120) (R/ 32) 128 to 255 Byte Frames Transmitted Register -------- */ 1924 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1925 #if COMPONENT_TYPEDEF_STYLE == 'N' 1926 typedef union { 1927 struct { 1928 uint32_t NFTX:32; /**< bit: 0..31 128 to 255 Byte Frames Transmitted without Error */ 1929 } bit; /**< Structure used for bit access */ 1930 uint32_t reg; /**< Type used for register access */ 1931 } GMAC_TBFT255_Type; 1932 #endif 1933 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1934 1935 #define GMAC_TBFT255_OFFSET (0x120) /**< (GMAC_TBFT255) 128 to 255 Byte Frames Transmitted Register Offset */ 1936 1937 #define GMAC_TBFT255_NFTX_Pos 0 /**< (GMAC_TBFT255) 128 to 255 Byte Frames Transmitted without Error Position */ 1938 #define GMAC_TBFT255_NFTX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFT255_NFTX_Pos) /**< (GMAC_TBFT255) 128 to 255 Byte Frames Transmitted without Error Mask */ 1939 #define GMAC_TBFT255_NFTX(value) (GMAC_TBFT255_NFTX_Msk & ((value) << GMAC_TBFT255_NFTX_Pos)) 1940 #define GMAC_TBFT255_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_TBFT255) Register MASK (Use GMAC_TBFT255_Msk instead) */ 1941 #define GMAC_TBFT255_Msk _U_(0xFFFFFFFF) /**< (GMAC_TBFT255) Register Mask */ 1942 1943 1944 /* -------- GMAC_TBFT511 : (GMAC Offset: 0x124) (R/ 32) 256 to 511 Byte Frames Transmitted Register -------- */ 1945 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1946 #if COMPONENT_TYPEDEF_STYLE == 'N' 1947 typedef union { 1948 struct { 1949 uint32_t NFTX:32; /**< bit: 0..31 256 to 511 Byte Frames Transmitted without Error */ 1950 } bit; /**< Structure used for bit access */ 1951 uint32_t reg; /**< Type used for register access */ 1952 } GMAC_TBFT511_Type; 1953 #endif 1954 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1955 1956 #define GMAC_TBFT511_OFFSET (0x124) /**< (GMAC_TBFT511) 256 to 511 Byte Frames Transmitted Register Offset */ 1957 1958 #define GMAC_TBFT511_NFTX_Pos 0 /**< (GMAC_TBFT511) 256 to 511 Byte Frames Transmitted without Error Position */ 1959 #define GMAC_TBFT511_NFTX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFT511_NFTX_Pos) /**< (GMAC_TBFT511) 256 to 511 Byte Frames Transmitted without Error Mask */ 1960 #define GMAC_TBFT511_NFTX(value) (GMAC_TBFT511_NFTX_Msk & ((value) << GMAC_TBFT511_NFTX_Pos)) 1961 #define GMAC_TBFT511_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_TBFT511) Register MASK (Use GMAC_TBFT511_Msk instead) */ 1962 #define GMAC_TBFT511_Msk _U_(0xFFFFFFFF) /**< (GMAC_TBFT511) Register Mask */ 1963 1964 1965 /* -------- GMAC_TBFT1023 : (GMAC Offset: 0x128) (R/ 32) 512 to 1023 Byte Frames Transmitted Register -------- */ 1966 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1967 #if COMPONENT_TYPEDEF_STYLE == 'N' 1968 typedef union { 1969 struct { 1970 uint32_t NFTX:32; /**< bit: 0..31 512 to 1023 Byte Frames Transmitted without Error */ 1971 } bit; /**< Structure used for bit access */ 1972 uint32_t reg; /**< Type used for register access */ 1973 } GMAC_TBFT1023_Type; 1974 #endif 1975 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1976 1977 #define GMAC_TBFT1023_OFFSET (0x128) /**< (GMAC_TBFT1023) 512 to 1023 Byte Frames Transmitted Register Offset */ 1978 1979 #define GMAC_TBFT1023_NFTX_Pos 0 /**< (GMAC_TBFT1023) 512 to 1023 Byte Frames Transmitted without Error Position */ 1980 #define GMAC_TBFT1023_NFTX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFT1023_NFTX_Pos) /**< (GMAC_TBFT1023) 512 to 1023 Byte Frames Transmitted without Error Mask */ 1981 #define GMAC_TBFT1023_NFTX(value) (GMAC_TBFT1023_NFTX_Msk & ((value) << GMAC_TBFT1023_NFTX_Pos)) 1982 #define GMAC_TBFT1023_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_TBFT1023) Register MASK (Use GMAC_TBFT1023_Msk instead) */ 1983 #define GMAC_TBFT1023_Msk _U_(0xFFFFFFFF) /**< (GMAC_TBFT1023) Register Mask */ 1984 1985 1986 /* -------- GMAC_TBFT1518 : (GMAC Offset: 0x12c) (R/ 32) 1024 to 1518 Byte Frames Transmitted Register -------- */ 1987 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1988 #if COMPONENT_TYPEDEF_STYLE == 'N' 1989 typedef union { 1990 struct { 1991 uint32_t NFTX:32; /**< bit: 0..31 1024 to 1518 Byte Frames Transmitted without Error */ 1992 } bit; /**< Structure used for bit access */ 1993 uint32_t reg; /**< Type used for register access */ 1994 } GMAC_TBFT1518_Type; 1995 #endif 1996 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1997 1998 #define GMAC_TBFT1518_OFFSET (0x12C) /**< (GMAC_TBFT1518) 1024 to 1518 Byte Frames Transmitted Register Offset */ 1999 2000 #define GMAC_TBFT1518_NFTX_Pos 0 /**< (GMAC_TBFT1518) 1024 to 1518 Byte Frames Transmitted without Error Position */ 2001 #define GMAC_TBFT1518_NFTX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFT1518_NFTX_Pos) /**< (GMAC_TBFT1518) 1024 to 1518 Byte Frames Transmitted without Error Mask */ 2002 #define GMAC_TBFT1518_NFTX(value) (GMAC_TBFT1518_NFTX_Msk & ((value) << GMAC_TBFT1518_NFTX_Pos)) 2003 #define GMAC_TBFT1518_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_TBFT1518) Register MASK (Use GMAC_TBFT1518_Msk instead) */ 2004 #define GMAC_TBFT1518_Msk _U_(0xFFFFFFFF) /**< (GMAC_TBFT1518) Register Mask */ 2005 2006 2007 /* -------- GMAC_GTBFT1518 : (GMAC Offset: 0x130) (R/ 32) Greater Than 1518 Byte Frames Transmitted Register -------- */ 2008 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2009 #if COMPONENT_TYPEDEF_STYLE == 'N' 2010 typedef union { 2011 struct { 2012 uint32_t NFTX:32; /**< bit: 0..31 Greater than 1518 Byte Frames Transmitted without Error */ 2013 } bit; /**< Structure used for bit access */ 2014 uint32_t reg; /**< Type used for register access */ 2015 } GMAC_GTBFT1518_Type; 2016 #endif 2017 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2018 2019 #define GMAC_GTBFT1518_OFFSET (0x130) /**< (GMAC_GTBFT1518) Greater Than 1518 Byte Frames Transmitted Register Offset */ 2020 2021 #define GMAC_GTBFT1518_NFTX_Pos 0 /**< (GMAC_GTBFT1518) Greater than 1518 Byte Frames Transmitted without Error Position */ 2022 #define GMAC_GTBFT1518_NFTX_Msk (_U_(0xFFFFFFFF) << GMAC_GTBFT1518_NFTX_Pos) /**< (GMAC_GTBFT1518) Greater than 1518 Byte Frames Transmitted without Error Mask */ 2023 #define GMAC_GTBFT1518_NFTX(value) (GMAC_GTBFT1518_NFTX_Msk & ((value) << GMAC_GTBFT1518_NFTX_Pos)) 2024 #define GMAC_GTBFT1518_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_GTBFT1518) Register MASK (Use GMAC_GTBFT1518_Msk instead) */ 2025 #define GMAC_GTBFT1518_Msk _U_(0xFFFFFFFF) /**< (GMAC_GTBFT1518) Register Mask */ 2026 2027 2028 /* -------- GMAC_TUR : (GMAC Offset: 0x134) (R/ 32) Transmit Underruns Register -------- */ 2029 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2030 #if COMPONENT_TYPEDEF_STYLE == 'N' 2031 typedef union { 2032 struct { 2033 uint32_t TXUNR:10; /**< bit: 0..9 Transmit Underruns */ 2034 uint32_t :22; /**< bit: 10..31 Reserved */ 2035 } bit; /**< Structure used for bit access */ 2036 uint32_t reg; /**< Type used for register access */ 2037 } GMAC_TUR_Type; 2038 #endif 2039 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2040 2041 #define GMAC_TUR_OFFSET (0x134) /**< (GMAC_TUR) Transmit Underruns Register Offset */ 2042 2043 #define GMAC_TUR_TXUNR_Pos 0 /**< (GMAC_TUR) Transmit Underruns Position */ 2044 #define GMAC_TUR_TXUNR_Msk (_U_(0x3FF) << GMAC_TUR_TXUNR_Pos) /**< (GMAC_TUR) Transmit Underruns Mask */ 2045 #define GMAC_TUR_TXUNR(value) (GMAC_TUR_TXUNR_Msk & ((value) << GMAC_TUR_TXUNR_Pos)) 2046 #define GMAC_TUR_MASK _U_(0x3FF) /**< \deprecated (GMAC_TUR) Register MASK (Use GMAC_TUR_Msk instead) */ 2047 #define GMAC_TUR_Msk _U_(0x3FF) /**< (GMAC_TUR) Register Mask */ 2048 2049 2050 /* -------- GMAC_SCF : (GMAC Offset: 0x138) (R/ 32) Single Collision Frames Register -------- */ 2051 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2052 #if COMPONENT_TYPEDEF_STYLE == 'N' 2053 typedef union { 2054 struct { 2055 uint32_t SCOL:18; /**< bit: 0..17 Single Collision */ 2056 uint32_t :14; /**< bit: 18..31 Reserved */ 2057 } bit; /**< Structure used for bit access */ 2058 uint32_t reg; /**< Type used for register access */ 2059 } GMAC_SCF_Type; 2060 #endif 2061 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2062 2063 #define GMAC_SCF_OFFSET (0x138) /**< (GMAC_SCF) Single Collision Frames Register Offset */ 2064 2065 #define GMAC_SCF_SCOL_Pos 0 /**< (GMAC_SCF) Single Collision Position */ 2066 #define GMAC_SCF_SCOL_Msk (_U_(0x3FFFF) << GMAC_SCF_SCOL_Pos) /**< (GMAC_SCF) Single Collision Mask */ 2067 #define GMAC_SCF_SCOL(value) (GMAC_SCF_SCOL_Msk & ((value) << GMAC_SCF_SCOL_Pos)) 2068 #define GMAC_SCF_MASK _U_(0x3FFFF) /**< \deprecated (GMAC_SCF) Register MASK (Use GMAC_SCF_Msk instead) */ 2069 #define GMAC_SCF_Msk _U_(0x3FFFF) /**< (GMAC_SCF) Register Mask */ 2070 2071 2072 /* -------- GMAC_MCF : (GMAC Offset: 0x13c) (R/ 32) Multiple Collision Frames Register -------- */ 2073 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2074 #if COMPONENT_TYPEDEF_STYLE == 'N' 2075 typedef union { 2076 struct { 2077 uint32_t MCOL:18; /**< bit: 0..17 Multiple Collision */ 2078 uint32_t :14; /**< bit: 18..31 Reserved */ 2079 } bit; /**< Structure used for bit access */ 2080 uint32_t reg; /**< Type used for register access */ 2081 } GMAC_MCF_Type; 2082 #endif 2083 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2084 2085 #define GMAC_MCF_OFFSET (0x13C) /**< (GMAC_MCF) Multiple Collision Frames Register Offset */ 2086 2087 #define GMAC_MCF_MCOL_Pos 0 /**< (GMAC_MCF) Multiple Collision Position */ 2088 #define GMAC_MCF_MCOL_Msk (_U_(0x3FFFF) << GMAC_MCF_MCOL_Pos) /**< (GMAC_MCF) Multiple Collision Mask */ 2089 #define GMAC_MCF_MCOL(value) (GMAC_MCF_MCOL_Msk & ((value) << GMAC_MCF_MCOL_Pos)) 2090 #define GMAC_MCF_MASK _U_(0x3FFFF) /**< \deprecated (GMAC_MCF) Register MASK (Use GMAC_MCF_Msk instead) */ 2091 #define GMAC_MCF_Msk _U_(0x3FFFF) /**< (GMAC_MCF) Register Mask */ 2092 2093 2094 /* -------- GMAC_EC : (GMAC Offset: 0x140) (R/ 32) Excessive Collisions Register -------- */ 2095 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2096 #if COMPONENT_TYPEDEF_STYLE == 'N' 2097 typedef union { 2098 struct { 2099 uint32_t XCOL:10; /**< bit: 0..9 Excessive Collisions */ 2100 uint32_t :22; /**< bit: 10..31 Reserved */ 2101 } bit; /**< Structure used for bit access */ 2102 uint32_t reg; /**< Type used for register access */ 2103 } GMAC_EC_Type; 2104 #endif 2105 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2106 2107 #define GMAC_EC_OFFSET (0x140) /**< (GMAC_EC) Excessive Collisions Register Offset */ 2108 2109 #define GMAC_EC_XCOL_Pos 0 /**< (GMAC_EC) Excessive Collisions Position */ 2110 #define GMAC_EC_XCOL_Msk (_U_(0x3FF) << GMAC_EC_XCOL_Pos) /**< (GMAC_EC) Excessive Collisions Mask */ 2111 #define GMAC_EC_XCOL(value) (GMAC_EC_XCOL_Msk & ((value) << GMAC_EC_XCOL_Pos)) 2112 #define GMAC_EC_MASK _U_(0x3FF) /**< \deprecated (GMAC_EC) Register MASK (Use GMAC_EC_Msk instead) */ 2113 #define GMAC_EC_Msk _U_(0x3FF) /**< (GMAC_EC) Register Mask */ 2114 2115 2116 /* -------- GMAC_LC : (GMAC Offset: 0x144) (R/ 32) Late Collisions Register -------- */ 2117 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2118 #if COMPONENT_TYPEDEF_STYLE == 'N' 2119 typedef union { 2120 struct { 2121 uint32_t LCOL:10; /**< bit: 0..9 Late Collisions */ 2122 uint32_t :22; /**< bit: 10..31 Reserved */ 2123 } bit; /**< Structure used for bit access */ 2124 uint32_t reg; /**< Type used for register access */ 2125 } GMAC_LC_Type; 2126 #endif 2127 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2128 2129 #define GMAC_LC_OFFSET (0x144) /**< (GMAC_LC) Late Collisions Register Offset */ 2130 2131 #define GMAC_LC_LCOL_Pos 0 /**< (GMAC_LC) Late Collisions Position */ 2132 #define GMAC_LC_LCOL_Msk (_U_(0x3FF) << GMAC_LC_LCOL_Pos) /**< (GMAC_LC) Late Collisions Mask */ 2133 #define GMAC_LC_LCOL(value) (GMAC_LC_LCOL_Msk & ((value) << GMAC_LC_LCOL_Pos)) 2134 #define GMAC_LC_MASK _U_(0x3FF) /**< \deprecated (GMAC_LC) Register MASK (Use GMAC_LC_Msk instead) */ 2135 #define GMAC_LC_Msk _U_(0x3FF) /**< (GMAC_LC) Register Mask */ 2136 2137 2138 /* -------- GMAC_DTF : (GMAC Offset: 0x148) (R/ 32) Deferred Transmission Frames Register -------- */ 2139 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2140 #if COMPONENT_TYPEDEF_STYLE == 'N' 2141 typedef union { 2142 struct { 2143 uint32_t DEFT:18; /**< bit: 0..17 Deferred Transmission */ 2144 uint32_t :14; /**< bit: 18..31 Reserved */ 2145 } bit; /**< Structure used for bit access */ 2146 uint32_t reg; /**< Type used for register access */ 2147 } GMAC_DTF_Type; 2148 #endif 2149 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2150 2151 #define GMAC_DTF_OFFSET (0x148) /**< (GMAC_DTF) Deferred Transmission Frames Register Offset */ 2152 2153 #define GMAC_DTF_DEFT_Pos 0 /**< (GMAC_DTF) Deferred Transmission Position */ 2154 #define GMAC_DTF_DEFT_Msk (_U_(0x3FFFF) << GMAC_DTF_DEFT_Pos) /**< (GMAC_DTF) Deferred Transmission Mask */ 2155 #define GMAC_DTF_DEFT(value) (GMAC_DTF_DEFT_Msk & ((value) << GMAC_DTF_DEFT_Pos)) 2156 #define GMAC_DTF_MASK _U_(0x3FFFF) /**< \deprecated (GMAC_DTF) Register MASK (Use GMAC_DTF_Msk instead) */ 2157 #define GMAC_DTF_Msk _U_(0x3FFFF) /**< (GMAC_DTF) Register Mask */ 2158 2159 2160 /* -------- GMAC_CSE : (GMAC Offset: 0x14c) (R/ 32) Carrier Sense Errors Register -------- */ 2161 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2162 #if COMPONENT_TYPEDEF_STYLE == 'N' 2163 typedef union { 2164 struct { 2165 uint32_t CSR:10; /**< bit: 0..9 Carrier Sense Error */ 2166 uint32_t :22; /**< bit: 10..31 Reserved */ 2167 } bit; /**< Structure used for bit access */ 2168 uint32_t reg; /**< Type used for register access */ 2169 } GMAC_CSE_Type; 2170 #endif 2171 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2172 2173 #define GMAC_CSE_OFFSET (0x14C) /**< (GMAC_CSE) Carrier Sense Errors Register Offset */ 2174 2175 #define GMAC_CSE_CSR_Pos 0 /**< (GMAC_CSE) Carrier Sense Error Position */ 2176 #define GMAC_CSE_CSR_Msk (_U_(0x3FF) << GMAC_CSE_CSR_Pos) /**< (GMAC_CSE) Carrier Sense Error Mask */ 2177 #define GMAC_CSE_CSR(value) (GMAC_CSE_CSR_Msk & ((value) << GMAC_CSE_CSR_Pos)) 2178 #define GMAC_CSE_MASK _U_(0x3FF) /**< \deprecated (GMAC_CSE) Register MASK (Use GMAC_CSE_Msk instead) */ 2179 #define GMAC_CSE_Msk _U_(0x3FF) /**< (GMAC_CSE) Register Mask */ 2180 2181 2182 /* -------- GMAC_ORLO : (GMAC Offset: 0x150) (R/ 32) Octets Received Low Received Register -------- */ 2183 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2184 #if COMPONENT_TYPEDEF_STYLE == 'N' 2185 typedef union { 2186 struct { 2187 uint32_t RXO:32; /**< bit: 0..31 Received Octets */ 2188 } bit; /**< Structure used for bit access */ 2189 uint32_t reg; /**< Type used for register access */ 2190 } GMAC_ORLO_Type; 2191 #endif 2192 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2193 2194 #define GMAC_ORLO_OFFSET (0x150) /**< (GMAC_ORLO) Octets Received Low Received Register Offset */ 2195 2196 #define GMAC_ORLO_RXO_Pos 0 /**< (GMAC_ORLO) Received Octets Position */ 2197 #define GMAC_ORLO_RXO_Msk (_U_(0xFFFFFFFF) << GMAC_ORLO_RXO_Pos) /**< (GMAC_ORLO) Received Octets Mask */ 2198 #define GMAC_ORLO_RXO(value) (GMAC_ORLO_RXO_Msk & ((value) << GMAC_ORLO_RXO_Pos)) 2199 #define GMAC_ORLO_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_ORLO) Register MASK (Use GMAC_ORLO_Msk instead) */ 2200 #define GMAC_ORLO_Msk _U_(0xFFFFFFFF) /**< (GMAC_ORLO) Register Mask */ 2201 2202 2203 /* -------- GMAC_ORHI : (GMAC Offset: 0x154) (R/ 32) Octets Received High Received Register -------- */ 2204 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2205 #if COMPONENT_TYPEDEF_STYLE == 'N' 2206 typedef union { 2207 struct { 2208 uint32_t RXO:16; /**< bit: 0..15 Received Octets */ 2209 uint32_t :16; /**< bit: 16..31 Reserved */ 2210 } bit; /**< Structure used for bit access */ 2211 uint32_t reg; /**< Type used for register access */ 2212 } GMAC_ORHI_Type; 2213 #endif 2214 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2215 2216 #define GMAC_ORHI_OFFSET (0x154) /**< (GMAC_ORHI) Octets Received High Received Register Offset */ 2217 2218 #define GMAC_ORHI_RXO_Pos 0 /**< (GMAC_ORHI) Received Octets Position */ 2219 #define GMAC_ORHI_RXO_Msk (_U_(0xFFFF) << GMAC_ORHI_RXO_Pos) /**< (GMAC_ORHI) Received Octets Mask */ 2220 #define GMAC_ORHI_RXO(value) (GMAC_ORHI_RXO_Msk & ((value) << GMAC_ORHI_RXO_Pos)) 2221 #define GMAC_ORHI_MASK _U_(0xFFFF) /**< \deprecated (GMAC_ORHI) Register MASK (Use GMAC_ORHI_Msk instead) */ 2222 #define GMAC_ORHI_Msk _U_(0xFFFF) /**< (GMAC_ORHI) Register Mask */ 2223 2224 2225 /* -------- GMAC_FR : (GMAC Offset: 0x158) (R/ 32) Frames Received Register -------- */ 2226 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2227 #if COMPONENT_TYPEDEF_STYLE == 'N' 2228 typedef union { 2229 struct { 2230 uint32_t FRX:32; /**< bit: 0..31 Frames Received without Error */ 2231 } bit; /**< Structure used for bit access */ 2232 uint32_t reg; /**< Type used for register access */ 2233 } GMAC_FR_Type; 2234 #endif 2235 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2236 2237 #define GMAC_FR_OFFSET (0x158) /**< (GMAC_FR) Frames Received Register Offset */ 2238 2239 #define GMAC_FR_FRX_Pos 0 /**< (GMAC_FR) Frames Received without Error Position */ 2240 #define GMAC_FR_FRX_Msk (_U_(0xFFFFFFFF) << GMAC_FR_FRX_Pos) /**< (GMAC_FR) Frames Received without Error Mask */ 2241 #define GMAC_FR_FRX(value) (GMAC_FR_FRX_Msk & ((value) << GMAC_FR_FRX_Pos)) 2242 #define GMAC_FR_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_FR) Register MASK (Use GMAC_FR_Msk instead) */ 2243 #define GMAC_FR_Msk _U_(0xFFFFFFFF) /**< (GMAC_FR) Register Mask */ 2244 2245 2246 /* -------- GMAC_BCFR : (GMAC Offset: 0x15c) (R/ 32) Broadcast Frames Received Register -------- */ 2247 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2248 #if COMPONENT_TYPEDEF_STYLE == 'N' 2249 typedef union { 2250 struct { 2251 uint32_t BFRX:32; /**< bit: 0..31 Broadcast Frames Received without Error */ 2252 } bit; /**< Structure used for bit access */ 2253 uint32_t reg; /**< Type used for register access */ 2254 } GMAC_BCFR_Type; 2255 #endif 2256 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2257 2258 #define GMAC_BCFR_OFFSET (0x15C) /**< (GMAC_BCFR) Broadcast Frames Received Register Offset */ 2259 2260 #define GMAC_BCFR_BFRX_Pos 0 /**< (GMAC_BCFR) Broadcast Frames Received without Error Position */ 2261 #define GMAC_BCFR_BFRX_Msk (_U_(0xFFFFFFFF) << GMAC_BCFR_BFRX_Pos) /**< (GMAC_BCFR) Broadcast Frames Received without Error Mask */ 2262 #define GMAC_BCFR_BFRX(value) (GMAC_BCFR_BFRX_Msk & ((value) << GMAC_BCFR_BFRX_Pos)) 2263 #define GMAC_BCFR_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_BCFR) Register MASK (Use GMAC_BCFR_Msk instead) */ 2264 #define GMAC_BCFR_Msk _U_(0xFFFFFFFF) /**< (GMAC_BCFR) Register Mask */ 2265 2266 2267 /* -------- GMAC_MFR : (GMAC Offset: 0x160) (R/ 32) Multicast Frames Received Register -------- */ 2268 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2269 #if COMPONENT_TYPEDEF_STYLE == 'N' 2270 typedef union { 2271 struct { 2272 uint32_t MFRX:32; /**< bit: 0..31 Multicast Frames Received without Error */ 2273 } bit; /**< Structure used for bit access */ 2274 uint32_t reg; /**< Type used for register access */ 2275 } GMAC_MFR_Type; 2276 #endif 2277 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2278 2279 #define GMAC_MFR_OFFSET (0x160) /**< (GMAC_MFR) Multicast Frames Received Register Offset */ 2280 2281 #define GMAC_MFR_MFRX_Pos 0 /**< (GMAC_MFR) Multicast Frames Received without Error Position */ 2282 #define GMAC_MFR_MFRX_Msk (_U_(0xFFFFFFFF) << GMAC_MFR_MFRX_Pos) /**< (GMAC_MFR) Multicast Frames Received without Error Mask */ 2283 #define GMAC_MFR_MFRX(value) (GMAC_MFR_MFRX_Msk & ((value) << GMAC_MFR_MFRX_Pos)) 2284 #define GMAC_MFR_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_MFR) Register MASK (Use GMAC_MFR_Msk instead) */ 2285 #define GMAC_MFR_Msk _U_(0xFFFFFFFF) /**< (GMAC_MFR) Register Mask */ 2286 2287 2288 /* -------- GMAC_PFR : (GMAC Offset: 0x164) (R/ 32) Pause Frames Received Register -------- */ 2289 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2290 #if COMPONENT_TYPEDEF_STYLE == 'N' 2291 typedef union { 2292 struct { 2293 uint32_t PFRX:16; /**< bit: 0..15 Pause Frames Received Register */ 2294 uint32_t :16; /**< bit: 16..31 Reserved */ 2295 } bit; /**< Structure used for bit access */ 2296 uint32_t reg; /**< Type used for register access */ 2297 } GMAC_PFR_Type; 2298 #endif 2299 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2300 2301 #define GMAC_PFR_OFFSET (0x164) /**< (GMAC_PFR) Pause Frames Received Register Offset */ 2302 2303 #define GMAC_PFR_PFRX_Pos 0 /**< (GMAC_PFR) Pause Frames Received Register Position */ 2304 #define GMAC_PFR_PFRX_Msk (_U_(0xFFFF) << GMAC_PFR_PFRX_Pos) /**< (GMAC_PFR) Pause Frames Received Register Mask */ 2305 #define GMAC_PFR_PFRX(value) (GMAC_PFR_PFRX_Msk & ((value) << GMAC_PFR_PFRX_Pos)) 2306 #define GMAC_PFR_MASK _U_(0xFFFF) /**< \deprecated (GMAC_PFR) Register MASK (Use GMAC_PFR_Msk instead) */ 2307 #define GMAC_PFR_Msk _U_(0xFFFF) /**< (GMAC_PFR) Register Mask */ 2308 2309 2310 /* -------- GMAC_BFR64 : (GMAC Offset: 0x168) (R/ 32) 64 Byte Frames Received Register -------- */ 2311 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2312 #if COMPONENT_TYPEDEF_STYLE == 'N' 2313 typedef union { 2314 struct { 2315 uint32_t NFRX:32; /**< bit: 0..31 64 Byte Frames Received without Error */ 2316 } bit; /**< Structure used for bit access */ 2317 uint32_t reg; /**< Type used for register access */ 2318 } GMAC_BFR64_Type; 2319 #endif 2320 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2321 2322 #define GMAC_BFR64_OFFSET (0x168) /**< (GMAC_BFR64) 64 Byte Frames Received Register Offset */ 2323 2324 #define GMAC_BFR64_NFRX_Pos 0 /**< (GMAC_BFR64) 64 Byte Frames Received without Error Position */ 2325 #define GMAC_BFR64_NFRX_Msk (_U_(0xFFFFFFFF) << GMAC_BFR64_NFRX_Pos) /**< (GMAC_BFR64) 64 Byte Frames Received without Error Mask */ 2326 #define GMAC_BFR64_NFRX(value) (GMAC_BFR64_NFRX_Msk & ((value) << GMAC_BFR64_NFRX_Pos)) 2327 #define GMAC_BFR64_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_BFR64) Register MASK (Use GMAC_BFR64_Msk instead) */ 2328 #define GMAC_BFR64_Msk _U_(0xFFFFFFFF) /**< (GMAC_BFR64) Register Mask */ 2329 2330 2331 /* -------- GMAC_TBFR127 : (GMAC Offset: 0x16c) (R/ 32) 65 to 127 Byte Frames Received Register -------- */ 2332 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2333 #if COMPONENT_TYPEDEF_STYLE == 'N' 2334 typedef union { 2335 struct { 2336 uint32_t NFRX:32; /**< bit: 0..31 65 to 127 Byte Frames Received without Error */ 2337 } bit; /**< Structure used for bit access */ 2338 uint32_t reg; /**< Type used for register access */ 2339 } GMAC_TBFR127_Type; 2340 #endif 2341 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2342 2343 #define GMAC_TBFR127_OFFSET (0x16C) /**< (GMAC_TBFR127) 65 to 127 Byte Frames Received Register Offset */ 2344 2345 #define GMAC_TBFR127_NFRX_Pos 0 /**< (GMAC_TBFR127) 65 to 127 Byte Frames Received without Error Position */ 2346 #define GMAC_TBFR127_NFRX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFR127_NFRX_Pos) /**< (GMAC_TBFR127) 65 to 127 Byte Frames Received without Error Mask */ 2347 #define GMAC_TBFR127_NFRX(value) (GMAC_TBFR127_NFRX_Msk & ((value) << GMAC_TBFR127_NFRX_Pos)) 2348 #define GMAC_TBFR127_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_TBFR127) Register MASK (Use GMAC_TBFR127_Msk instead) */ 2349 #define GMAC_TBFR127_Msk _U_(0xFFFFFFFF) /**< (GMAC_TBFR127) Register Mask */ 2350 2351 2352 /* -------- GMAC_TBFR255 : (GMAC Offset: 0x170) (R/ 32) 128 to 255 Byte Frames Received Register -------- */ 2353 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2354 #if COMPONENT_TYPEDEF_STYLE == 'N' 2355 typedef union { 2356 struct { 2357 uint32_t NFRX:32; /**< bit: 0..31 128 to 255 Byte Frames Received without Error */ 2358 } bit; /**< Structure used for bit access */ 2359 uint32_t reg; /**< Type used for register access */ 2360 } GMAC_TBFR255_Type; 2361 #endif 2362 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2363 2364 #define GMAC_TBFR255_OFFSET (0x170) /**< (GMAC_TBFR255) 128 to 255 Byte Frames Received Register Offset */ 2365 2366 #define GMAC_TBFR255_NFRX_Pos 0 /**< (GMAC_TBFR255) 128 to 255 Byte Frames Received without Error Position */ 2367 #define GMAC_TBFR255_NFRX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFR255_NFRX_Pos) /**< (GMAC_TBFR255) 128 to 255 Byte Frames Received without Error Mask */ 2368 #define GMAC_TBFR255_NFRX(value) (GMAC_TBFR255_NFRX_Msk & ((value) << GMAC_TBFR255_NFRX_Pos)) 2369 #define GMAC_TBFR255_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_TBFR255) Register MASK (Use GMAC_TBFR255_Msk instead) */ 2370 #define GMAC_TBFR255_Msk _U_(0xFFFFFFFF) /**< (GMAC_TBFR255) Register Mask */ 2371 2372 2373 /* -------- GMAC_TBFR511 : (GMAC Offset: 0x174) (R/ 32) 256 to 511 Byte Frames Received Register -------- */ 2374 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2375 #if COMPONENT_TYPEDEF_STYLE == 'N' 2376 typedef union { 2377 struct { 2378 uint32_t NFRX:32; /**< bit: 0..31 256 to 511 Byte Frames Received without Error */ 2379 } bit; /**< Structure used for bit access */ 2380 uint32_t reg; /**< Type used for register access */ 2381 } GMAC_TBFR511_Type; 2382 #endif 2383 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2384 2385 #define GMAC_TBFR511_OFFSET (0x174) /**< (GMAC_TBFR511) 256 to 511 Byte Frames Received Register Offset */ 2386 2387 #define GMAC_TBFR511_NFRX_Pos 0 /**< (GMAC_TBFR511) 256 to 511 Byte Frames Received without Error Position */ 2388 #define GMAC_TBFR511_NFRX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFR511_NFRX_Pos) /**< (GMAC_TBFR511) 256 to 511 Byte Frames Received without Error Mask */ 2389 #define GMAC_TBFR511_NFRX(value) (GMAC_TBFR511_NFRX_Msk & ((value) << GMAC_TBFR511_NFRX_Pos)) 2390 #define GMAC_TBFR511_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_TBFR511) Register MASK (Use GMAC_TBFR511_Msk instead) */ 2391 #define GMAC_TBFR511_Msk _U_(0xFFFFFFFF) /**< (GMAC_TBFR511) Register Mask */ 2392 2393 2394 /* -------- GMAC_TBFR1023 : (GMAC Offset: 0x178) (R/ 32) 512 to 1023 Byte Frames Received Register -------- */ 2395 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2396 #if COMPONENT_TYPEDEF_STYLE == 'N' 2397 typedef union { 2398 struct { 2399 uint32_t NFRX:32; /**< bit: 0..31 512 to 1023 Byte Frames Received without Error */ 2400 } bit; /**< Structure used for bit access */ 2401 uint32_t reg; /**< Type used for register access */ 2402 } GMAC_TBFR1023_Type; 2403 #endif 2404 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2405 2406 #define GMAC_TBFR1023_OFFSET (0x178) /**< (GMAC_TBFR1023) 512 to 1023 Byte Frames Received Register Offset */ 2407 2408 #define GMAC_TBFR1023_NFRX_Pos 0 /**< (GMAC_TBFR1023) 512 to 1023 Byte Frames Received without Error Position */ 2409 #define GMAC_TBFR1023_NFRX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFR1023_NFRX_Pos) /**< (GMAC_TBFR1023) 512 to 1023 Byte Frames Received without Error Mask */ 2410 #define GMAC_TBFR1023_NFRX(value) (GMAC_TBFR1023_NFRX_Msk & ((value) << GMAC_TBFR1023_NFRX_Pos)) 2411 #define GMAC_TBFR1023_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_TBFR1023) Register MASK (Use GMAC_TBFR1023_Msk instead) */ 2412 #define GMAC_TBFR1023_Msk _U_(0xFFFFFFFF) /**< (GMAC_TBFR1023) Register Mask */ 2413 2414 2415 /* -------- GMAC_TBFR1518 : (GMAC Offset: 0x17c) (R/ 32) 1024 to 1518 Byte Frames Received Register -------- */ 2416 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2417 #if COMPONENT_TYPEDEF_STYLE == 'N' 2418 typedef union { 2419 struct { 2420 uint32_t NFRX:32; /**< bit: 0..31 1024 to 1518 Byte Frames Received without Error */ 2421 } bit; /**< Structure used for bit access */ 2422 uint32_t reg; /**< Type used for register access */ 2423 } GMAC_TBFR1518_Type; 2424 #endif 2425 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2426 2427 #define GMAC_TBFR1518_OFFSET (0x17C) /**< (GMAC_TBFR1518) 1024 to 1518 Byte Frames Received Register Offset */ 2428 2429 #define GMAC_TBFR1518_NFRX_Pos 0 /**< (GMAC_TBFR1518) 1024 to 1518 Byte Frames Received without Error Position */ 2430 #define GMAC_TBFR1518_NFRX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFR1518_NFRX_Pos) /**< (GMAC_TBFR1518) 1024 to 1518 Byte Frames Received without Error Mask */ 2431 #define GMAC_TBFR1518_NFRX(value) (GMAC_TBFR1518_NFRX_Msk & ((value) << GMAC_TBFR1518_NFRX_Pos)) 2432 #define GMAC_TBFR1518_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_TBFR1518) Register MASK (Use GMAC_TBFR1518_Msk instead) */ 2433 #define GMAC_TBFR1518_Msk _U_(0xFFFFFFFF) /**< (GMAC_TBFR1518) Register Mask */ 2434 2435 2436 /* -------- GMAC_TMXBFR : (GMAC Offset: 0x180) (R/ 32) 1519 to Maximum Byte Frames Received Register -------- */ 2437 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2438 #if COMPONENT_TYPEDEF_STYLE == 'N' 2439 typedef union { 2440 struct { 2441 uint32_t NFRX:32; /**< bit: 0..31 1519 to Maximum Byte Frames Received without Error */ 2442 } bit; /**< Structure used for bit access */ 2443 uint32_t reg; /**< Type used for register access */ 2444 } GMAC_TMXBFR_Type; 2445 #endif 2446 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2447 2448 #define GMAC_TMXBFR_OFFSET (0x180) /**< (GMAC_TMXBFR) 1519 to Maximum Byte Frames Received Register Offset */ 2449 2450 #define GMAC_TMXBFR_NFRX_Pos 0 /**< (GMAC_TMXBFR) 1519 to Maximum Byte Frames Received without Error Position */ 2451 #define GMAC_TMXBFR_NFRX_Msk (_U_(0xFFFFFFFF) << GMAC_TMXBFR_NFRX_Pos) /**< (GMAC_TMXBFR) 1519 to Maximum Byte Frames Received without Error Mask */ 2452 #define GMAC_TMXBFR_NFRX(value) (GMAC_TMXBFR_NFRX_Msk & ((value) << GMAC_TMXBFR_NFRX_Pos)) 2453 #define GMAC_TMXBFR_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_TMXBFR) Register MASK (Use GMAC_TMXBFR_Msk instead) */ 2454 #define GMAC_TMXBFR_Msk _U_(0xFFFFFFFF) /**< (GMAC_TMXBFR) Register Mask */ 2455 2456 2457 /* -------- GMAC_UFR : (GMAC Offset: 0x184) (R/ 32) Undersize Frames Received Register -------- */ 2458 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2459 #if COMPONENT_TYPEDEF_STYLE == 'N' 2460 typedef union { 2461 struct { 2462 uint32_t UFRX:10; /**< bit: 0..9 Undersize Frames Received */ 2463 uint32_t :22; /**< bit: 10..31 Reserved */ 2464 } bit; /**< Structure used for bit access */ 2465 uint32_t reg; /**< Type used for register access */ 2466 } GMAC_UFR_Type; 2467 #endif 2468 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2469 2470 #define GMAC_UFR_OFFSET (0x184) /**< (GMAC_UFR) Undersize Frames Received Register Offset */ 2471 2472 #define GMAC_UFR_UFRX_Pos 0 /**< (GMAC_UFR) Undersize Frames Received Position */ 2473 #define GMAC_UFR_UFRX_Msk (_U_(0x3FF) << GMAC_UFR_UFRX_Pos) /**< (GMAC_UFR) Undersize Frames Received Mask */ 2474 #define GMAC_UFR_UFRX(value) (GMAC_UFR_UFRX_Msk & ((value) << GMAC_UFR_UFRX_Pos)) 2475 #define GMAC_UFR_MASK _U_(0x3FF) /**< \deprecated (GMAC_UFR) Register MASK (Use GMAC_UFR_Msk instead) */ 2476 #define GMAC_UFR_Msk _U_(0x3FF) /**< (GMAC_UFR) Register Mask */ 2477 2478 2479 /* -------- GMAC_OFR : (GMAC Offset: 0x188) (R/ 32) Oversize Frames Received Register -------- */ 2480 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2481 #if COMPONENT_TYPEDEF_STYLE == 'N' 2482 typedef union { 2483 struct { 2484 uint32_t OFRX:10; /**< bit: 0..9 Oversized Frames Received */ 2485 uint32_t :22; /**< bit: 10..31 Reserved */ 2486 } bit; /**< Structure used for bit access */ 2487 uint32_t reg; /**< Type used for register access */ 2488 } GMAC_OFR_Type; 2489 #endif 2490 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2491 2492 #define GMAC_OFR_OFFSET (0x188) /**< (GMAC_OFR) Oversize Frames Received Register Offset */ 2493 2494 #define GMAC_OFR_OFRX_Pos 0 /**< (GMAC_OFR) Oversized Frames Received Position */ 2495 #define GMAC_OFR_OFRX_Msk (_U_(0x3FF) << GMAC_OFR_OFRX_Pos) /**< (GMAC_OFR) Oversized Frames Received Mask */ 2496 #define GMAC_OFR_OFRX(value) (GMAC_OFR_OFRX_Msk & ((value) << GMAC_OFR_OFRX_Pos)) 2497 #define GMAC_OFR_MASK _U_(0x3FF) /**< \deprecated (GMAC_OFR) Register MASK (Use GMAC_OFR_Msk instead) */ 2498 #define GMAC_OFR_Msk _U_(0x3FF) /**< (GMAC_OFR) Register Mask */ 2499 2500 2501 /* -------- GMAC_JR : (GMAC Offset: 0x18c) (R/ 32) Jabbers Received Register -------- */ 2502 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2503 #if COMPONENT_TYPEDEF_STYLE == 'N' 2504 typedef union { 2505 struct { 2506 uint32_t JRX:10; /**< bit: 0..9 Jabbers Received */ 2507 uint32_t :22; /**< bit: 10..31 Reserved */ 2508 } bit; /**< Structure used for bit access */ 2509 uint32_t reg; /**< Type used for register access */ 2510 } GMAC_JR_Type; 2511 #endif 2512 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2513 2514 #define GMAC_JR_OFFSET (0x18C) /**< (GMAC_JR) Jabbers Received Register Offset */ 2515 2516 #define GMAC_JR_JRX_Pos 0 /**< (GMAC_JR) Jabbers Received Position */ 2517 #define GMAC_JR_JRX_Msk (_U_(0x3FF) << GMAC_JR_JRX_Pos) /**< (GMAC_JR) Jabbers Received Mask */ 2518 #define GMAC_JR_JRX(value) (GMAC_JR_JRX_Msk & ((value) << GMAC_JR_JRX_Pos)) 2519 #define GMAC_JR_MASK _U_(0x3FF) /**< \deprecated (GMAC_JR) Register MASK (Use GMAC_JR_Msk instead) */ 2520 #define GMAC_JR_Msk _U_(0x3FF) /**< (GMAC_JR) Register Mask */ 2521 2522 2523 /* -------- GMAC_FCSE : (GMAC Offset: 0x190) (R/ 32) Frame Check Sequence Errors Register -------- */ 2524 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2525 #if COMPONENT_TYPEDEF_STYLE == 'N' 2526 typedef union { 2527 struct { 2528 uint32_t FCKR:10; /**< bit: 0..9 Frame Check Sequence Errors */ 2529 uint32_t :22; /**< bit: 10..31 Reserved */ 2530 } bit; /**< Structure used for bit access */ 2531 uint32_t reg; /**< Type used for register access */ 2532 } GMAC_FCSE_Type; 2533 #endif 2534 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2535 2536 #define GMAC_FCSE_OFFSET (0x190) /**< (GMAC_FCSE) Frame Check Sequence Errors Register Offset */ 2537 2538 #define GMAC_FCSE_FCKR_Pos 0 /**< (GMAC_FCSE) Frame Check Sequence Errors Position */ 2539 #define GMAC_FCSE_FCKR_Msk (_U_(0x3FF) << GMAC_FCSE_FCKR_Pos) /**< (GMAC_FCSE) Frame Check Sequence Errors Mask */ 2540 #define GMAC_FCSE_FCKR(value) (GMAC_FCSE_FCKR_Msk & ((value) << GMAC_FCSE_FCKR_Pos)) 2541 #define GMAC_FCSE_MASK _U_(0x3FF) /**< \deprecated (GMAC_FCSE) Register MASK (Use GMAC_FCSE_Msk instead) */ 2542 #define GMAC_FCSE_Msk _U_(0x3FF) /**< (GMAC_FCSE) Register Mask */ 2543 2544 2545 /* -------- GMAC_LFFE : (GMAC Offset: 0x194) (R/ 32) Length Field Frame Errors Register -------- */ 2546 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2547 #if COMPONENT_TYPEDEF_STYLE == 'N' 2548 typedef union { 2549 struct { 2550 uint32_t LFER:10; /**< bit: 0..9 Length Field Frame Errors */ 2551 uint32_t :22; /**< bit: 10..31 Reserved */ 2552 } bit; /**< Structure used for bit access */ 2553 uint32_t reg; /**< Type used for register access */ 2554 } GMAC_LFFE_Type; 2555 #endif 2556 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2557 2558 #define GMAC_LFFE_OFFSET (0x194) /**< (GMAC_LFFE) Length Field Frame Errors Register Offset */ 2559 2560 #define GMAC_LFFE_LFER_Pos 0 /**< (GMAC_LFFE) Length Field Frame Errors Position */ 2561 #define GMAC_LFFE_LFER_Msk (_U_(0x3FF) << GMAC_LFFE_LFER_Pos) /**< (GMAC_LFFE) Length Field Frame Errors Mask */ 2562 #define GMAC_LFFE_LFER(value) (GMAC_LFFE_LFER_Msk & ((value) << GMAC_LFFE_LFER_Pos)) 2563 #define GMAC_LFFE_MASK _U_(0x3FF) /**< \deprecated (GMAC_LFFE) Register MASK (Use GMAC_LFFE_Msk instead) */ 2564 #define GMAC_LFFE_Msk _U_(0x3FF) /**< (GMAC_LFFE) Register Mask */ 2565 2566 2567 /* -------- GMAC_RSE : (GMAC Offset: 0x198) (R/ 32) Receive Symbol Errors Register -------- */ 2568 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2569 #if COMPONENT_TYPEDEF_STYLE == 'N' 2570 typedef union { 2571 struct { 2572 uint32_t RXSE:10; /**< bit: 0..9 Receive Symbol Errors */ 2573 uint32_t :22; /**< bit: 10..31 Reserved */ 2574 } bit; /**< Structure used for bit access */ 2575 uint32_t reg; /**< Type used for register access */ 2576 } GMAC_RSE_Type; 2577 #endif 2578 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2579 2580 #define GMAC_RSE_OFFSET (0x198) /**< (GMAC_RSE) Receive Symbol Errors Register Offset */ 2581 2582 #define GMAC_RSE_RXSE_Pos 0 /**< (GMAC_RSE) Receive Symbol Errors Position */ 2583 #define GMAC_RSE_RXSE_Msk (_U_(0x3FF) << GMAC_RSE_RXSE_Pos) /**< (GMAC_RSE) Receive Symbol Errors Mask */ 2584 #define GMAC_RSE_RXSE(value) (GMAC_RSE_RXSE_Msk & ((value) << GMAC_RSE_RXSE_Pos)) 2585 #define GMAC_RSE_MASK _U_(0x3FF) /**< \deprecated (GMAC_RSE) Register MASK (Use GMAC_RSE_Msk instead) */ 2586 #define GMAC_RSE_Msk _U_(0x3FF) /**< (GMAC_RSE) Register Mask */ 2587 2588 2589 /* -------- GMAC_AE : (GMAC Offset: 0x19c) (R/ 32) Alignment Errors Register -------- */ 2590 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2591 #if COMPONENT_TYPEDEF_STYLE == 'N' 2592 typedef union { 2593 struct { 2594 uint32_t AER:10; /**< bit: 0..9 Alignment Errors */ 2595 uint32_t :22; /**< bit: 10..31 Reserved */ 2596 } bit; /**< Structure used for bit access */ 2597 uint32_t reg; /**< Type used for register access */ 2598 } GMAC_AE_Type; 2599 #endif 2600 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2601 2602 #define GMAC_AE_OFFSET (0x19C) /**< (GMAC_AE) Alignment Errors Register Offset */ 2603 2604 #define GMAC_AE_AER_Pos 0 /**< (GMAC_AE) Alignment Errors Position */ 2605 #define GMAC_AE_AER_Msk (_U_(0x3FF) << GMAC_AE_AER_Pos) /**< (GMAC_AE) Alignment Errors Mask */ 2606 #define GMAC_AE_AER(value) (GMAC_AE_AER_Msk & ((value) << GMAC_AE_AER_Pos)) 2607 #define GMAC_AE_MASK _U_(0x3FF) /**< \deprecated (GMAC_AE) Register MASK (Use GMAC_AE_Msk instead) */ 2608 #define GMAC_AE_Msk _U_(0x3FF) /**< (GMAC_AE) Register Mask */ 2609 2610 2611 /* -------- GMAC_RRE : (GMAC Offset: 0x1a0) (R/ 32) Receive Resource Errors Register -------- */ 2612 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2613 #if COMPONENT_TYPEDEF_STYLE == 'N' 2614 typedef union { 2615 struct { 2616 uint32_t RXRER:18; /**< bit: 0..17 Receive Resource Errors */ 2617 uint32_t :14; /**< bit: 18..31 Reserved */ 2618 } bit; /**< Structure used for bit access */ 2619 uint32_t reg; /**< Type used for register access */ 2620 } GMAC_RRE_Type; 2621 #endif 2622 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2623 2624 #define GMAC_RRE_OFFSET (0x1A0) /**< (GMAC_RRE) Receive Resource Errors Register Offset */ 2625 2626 #define GMAC_RRE_RXRER_Pos 0 /**< (GMAC_RRE) Receive Resource Errors Position */ 2627 #define GMAC_RRE_RXRER_Msk (_U_(0x3FFFF) << GMAC_RRE_RXRER_Pos) /**< (GMAC_RRE) Receive Resource Errors Mask */ 2628 #define GMAC_RRE_RXRER(value) (GMAC_RRE_RXRER_Msk & ((value) << GMAC_RRE_RXRER_Pos)) 2629 #define GMAC_RRE_MASK _U_(0x3FFFF) /**< \deprecated (GMAC_RRE) Register MASK (Use GMAC_RRE_Msk instead) */ 2630 #define GMAC_RRE_Msk _U_(0x3FFFF) /**< (GMAC_RRE) Register Mask */ 2631 2632 2633 /* -------- GMAC_ROE : (GMAC Offset: 0x1a4) (R/ 32) Receive Overrun Register -------- */ 2634 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2635 #if COMPONENT_TYPEDEF_STYLE == 'N' 2636 typedef union { 2637 struct { 2638 uint32_t RXOVR:10; /**< bit: 0..9 Receive Overruns */ 2639 uint32_t :22; /**< bit: 10..31 Reserved */ 2640 } bit; /**< Structure used for bit access */ 2641 uint32_t reg; /**< Type used for register access */ 2642 } GMAC_ROE_Type; 2643 #endif 2644 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2645 2646 #define GMAC_ROE_OFFSET (0x1A4) /**< (GMAC_ROE) Receive Overrun Register Offset */ 2647 2648 #define GMAC_ROE_RXOVR_Pos 0 /**< (GMAC_ROE) Receive Overruns Position */ 2649 #define GMAC_ROE_RXOVR_Msk (_U_(0x3FF) << GMAC_ROE_RXOVR_Pos) /**< (GMAC_ROE) Receive Overruns Mask */ 2650 #define GMAC_ROE_RXOVR(value) (GMAC_ROE_RXOVR_Msk & ((value) << GMAC_ROE_RXOVR_Pos)) 2651 #define GMAC_ROE_MASK _U_(0x3FF) /**< \deprecated (GMAC_ROE) Register MASK (Use GMAC_ROE_Msk instead) */ 2652 #define GMAC_ROE_Msk _U_(0x3FF) /**< (GMAC_ROE) Register Mask */ 2653 2654 2655 /* -------- GMAC_IHCE : (GMAC Offset: 0x1a8) (R/ 32) IP Header Checksum Errors Register -------- */ 2656 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2657 #if COMPONENT_TYPEDEF_STYLE == 'N' 2658 typedef union { 2659 struct { 2660 uint32_t HCKER:8; /**< bit: 0..7 IP Header Checksum Errors */ 2661 uint32_t :24; /**< bit: 8..31 Reserved */ 2662 } bit; /**< Structure used for bit access */ 2663 uint32_t reg; /**< Type used for register access */ 2664 } GMAC_IHCE_Type; 2665 #endif 2666 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2667 2668 #define GMAC_IHCE_OFFSET (0x1A8) /**< (GMAC_IHCE) IP Header Checksum Errors Register Offset */ 2669 2670 #define GMAC_IHCE_HCKER_Pos 0 /**< (GMAC_IHCE) IP Header Checksum Errors Position */ 2671 #define GMAC_IHCE_HCKER_Msk (_U_(0xFF) << GMAC_IHCE_HCKER_Pos) /**< (GMAC_IHCE) IP Header Checksum Errors Mask */ 2672 #define GMAC_IHCE_HCKER(value) (GMAC_IHCE_HCKER_Msk & ((value) << GMAC_IHCE_HCKER_Pos)) 2673 #define GMAC_IHCE_MASK _U_(0xFF) /**< \deprecated (GMAC_IHCE) Register MASK (Use GMAC_IHCE_Msk instead) */ 2674 #define GMAC_IHCE_Msk _U_(0xFF) /**< (GMAC_IHCE) Register Mask */ 2675 2676 2677 /* -------- GMAC_TCE : (GMAC Offset: 0x1ac) (R/ 32) TCP Checksum Errors Register -------- */ 2678 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2679 #if COMPONENT_TYPEDEF_STYLE == 'N' 2680 typedef union { 2681 struct { 2682 uint32_t TCKER:8; /**< bit: 0..7 TCP Checksum Errors */ 2683 uint32_t :24; /**< bit: 8..31 Reserved */ 2684 } bit; /**< Structure used for bit access */ 2685 uint32_t reg; /**< Type used for register access */ 2686 } GMAC_TCE_Type; 2687 #endif 2688 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2689 2690 #define GMAC_TCE_OFFSET (0x1AC) /**< (GMAC_TCE) TCP Checksum Errors Register Offset */ 2691 2692 #define GMAC_TCE_TCKER_Pos 0 /**< (GMAC_TCE) TCP Checksum Errors Position */ 2693 #define GMAC_TCE_TCKER_Msk (_U_(0xFF) << GMAC_TCE_TCKER_Pos) /**< (GMAC_TCE) TCP Checksum Errors Mask */ 2694 #define GMAC_TCE_TCKER(value) (GMAC_TCE_TCKER_Msk & ((value) << GMAC_TCE_TCKER_Pos)) 2695 #define GMAC_TCE_MASK _U_(0xFF) /**< \deprecated (GMAC_TCE) Register MASK (Use GMAC_TCE_Msk instead) */ 2696 #define GMAC_TCE_Msk _U_(0xFF) /**< (GMAC_TCE) Register Mask */ 2697 2698 2699 /* -------- GMAC_UCE : (GMAC Offset: 0x1b0) (R/ 32) UDP Checksum Errors Register -------- */ 2700 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2701 #if COMPONENT_TYPEDEF_STYLE == 'N' 2702 typedef union { 2703 struct { 2704 uint32_t UCKER:8; /**< bit: 0..7 UDP Checksum Errors */ 2705 uint32_t :24; /**< bit: 8..31 Reserved */ 2706 } bit; /**< Structure used for bit access */ 2707 uint32_t reg; /**< Type used for register access */ 2708 } GMAC_UCE_Type; 2709 #endif 2710 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2711 2712 #define GMAC_UCE_OFFSET (0x1B0) /**< (GMAC_UCE) UDP Checksum Errors Register Offset */ 2713 2714 #define GMAC_UCE_UCKER_Pos 0 /**< (GMAC_UCE) UDP Checksum Errors Position */ 2715 #define GMAC_UCE_UCKER_Msk (_U_(0xFF) << GMAC_UCE_UCKER_Pos) /**< (GMAC_UCE) UDP Checksum Errors Mask */ 2716 #define GMAC_UCE_UCKER(value) (GMAC_UCE_UCKER_Msk & ((value) << GMAC_UCE_UCKER_Pos)) 2717 #define GMAC_UCE_MASK _U_(0xFF) /**< \deprecated (GMAC_UCE) Register MASK (Use GMAC_UCE_Msk instead) */ 2718 #define GMAC_UCE_Msk _U_(0xFF) /**< (GMAC_UCE) Register Mask */ 2719 2720 2721 /* -------- GMAC_TISUBN : (GMAC Offset: 0x1bc) (R/W 32) 1588 Timer Increment Sub-nanoseconds Register -------- */ 2722 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2723 #if COMPONENT_TYPEDEF_STYLE == 'N' 2724 typedef union { 2725 struct { 2726 uint32_t LSBTIR:16; /**< bit: 0..15 Lower Significant Bits of Timer Increment Register */ 2727 uint32_t :16; /**< bit: 16..31 Reserved */ 2728 } bit; /**< Structure used for bit access */ 2729 uint32_t reg; /**< Type used for register access */ 2730 } GMAC_TISUBN_Type; 2731 #endif 2732 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2733 2734 #define GMAC_TISUBN_OFFSET (0x1BC) /**< (GMAC_TISUBN) 1588 Timer Increment Sub-nanoseconds Register Offset */ 2735 2736 #define GMAC_TISUBN_LSBTIR_Pos 0 /**< (GMAC_TISUBN) Lower Significant Bits of Timer Increment Register Position */ 2737 #define GMAC_TISUBN_LSBTIR_Msk (_U_(0xFFFF) << GMAC_TISUBN_LSBTIR_Pos) /**< (GMAC_TISUBN) Lower Significant Bits of Timer Increment Register Mask */ 2738 #define GMAC_TISUBN_LSBTIR(value) (GMAC_TISUBN_LSBTIR_Msk & ((value) << GMAC_TISUBN_LSBTIR_Pos)) 2739 #define GMAC_TISUBN_MASK _U_(0xFFFF) /**< \deprecated (GMAC_TISUBN) Register MASK (Use GMAC_TISUBN_Msk instead) */ 2740 #define GMAC_TISUBN_Msk _U_(0xFFFF) /**< (GMAC_TISUBN) Register Mask */ 2741 2742 2743 /* -------- GMAC_TSH : (GMAC Offset: 0x1c0) (R/W 32) 1588 Timer Seconds High Register -------- */ 2744 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2745 #if COMPONENT_TYPEDEF_STYLE == 'N' 2746 typedef union { 2747 struct { 2748 uint32_t TCS:16; /**< bit: 0..15 Timer Count in Seconds */ 2749 uint32_t :16; /**< bit: 16..31 Reserved */ 2750 } bit; /**< Structure used for bit access */ 2751 uint32_t reg; /**< Type used for register access */ 2752 } GMAC_TSH_Type; 2753 #endif 2754 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2755 2756 #define GMAC_TSH_OFFSET (0x1C0) /**< (GMAC_TSH) 1588 Timer Seconds High Register Offset */ 2757 2758 #define GMAC_TSH_TCS_Pos 0 /**< (GMAC_TSH) Timer Count in Seconds Position */ 2759 #define GMAC_TSH_TCS_Msk (_U_(0xFFFF) << GMAC_TSH_TCS_Pos) /**< (GMAC_TSH) Timer Count in Seconds Mask */ 2760 #define GMAC_TSH_TCS(value) (GMAC_TSH_TCS_Msk & ((value) << GMAC_TSH_TCS_Pos)) 2761 #define GMAC_TSH_MASK _U_(0xFFFF) /**< \deprecated (GMAC_TSH) Register MASK (Use GMAC_TSH_Msk instead) */ 2762 #define GMAC_TSH_Msk _U_(0xFFFF) /**< (GMAC_TSH) Register Mask */ 2763 2764 2765 /* -------- GMAC_TSL : (GMAC Offset: 0x1d0) (R/W 32) 1588 Timer Seconds Low Register -------- */ 2766 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2767 #if COMPONENT_TYPEDEF_STYLE == 'N' 2768 typedef union { 2769 struct { 2770 uint32_t TCS:32; /**< bit: 0..31 Timer Count in Seconds */ 2771 } bit; /**< Structure used for bit access */ 2772 uint32_t reg; /**< Type used for register access */ 2773 } GMAC_TSL_Type; 2774 #endif 2775 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2776 2777 #define GMAC_TSL_OFFSET (0x1D0) /**< (GMAC_TSL) 1588 Timer Seconds Low Register Offset */ 2778 2779 #define GMAC_TSL_TCS_Pos 0 /**< (GMAC_TSL) Timer Count in Seconds Position */ 2780 #define GMAC_TSL_TCS_Msk (_U_(0xFFFFFFFF) << GMAC_TSL_TCS_Pos) /**< (GMAC_TSL) Timer Count in Seconds Mask */ 2781 #define GMAC_TSL_TCS(value) (GMAC_TSL_TCS_Msk & ((value) << GMAC_TSL_TCS_Pos)) 2782 #define GMAC_TSL_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_TSL) Register MASK (Use GMAC_TSL_Msk instead) */ 2783 #define GMAC_TSL_Msk _U_(0xFFFFFFFF) /**< (GMAC_TSL) Register Mask */ 2784 2785 2786 /* -------- GMAC_TN : (GMAC Offset: 0x1d4) (R/W 32) 1588 Timer Nanoseconds Register -------- */ 2787 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2788 #if COMPONENT_TYPEDEF_STYLE == 'N' 2789 typedef union { 2790 struct { 2791 uint32_t TNS:30; /**< bit: 0..29 Timer Count in Nanoseconds */ 2792 uint32_t :2; /**< bit: 30..31 Reserved */ 2793 } bit; /**< Structure used for bit access */ 2794 uint32_t reg; /**< Type used for register access */ 2795 } GMAC_TN_Type; 2796 #endif 2797 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2798 2799 #define GMAC_TN_OFFSET (0x1D4) /**< (GMAC_TN) 1588 Timer Nanoseconds Register Offset */ 2800 2801 #define GMAC_TN_TNS_Pos 0 /**< (GMAC_TN) Timer Count in Nanoseconds Position */ 2802 #define GMAC_TN_TNS_Msk (_U_(0x3FFFFFFF) << GMAC_TN_TNS_Pos) /**< (GMAC_TN) Timer Count in Nanoseconds Mask */ 2803 #define GMAC_TN_TNS(value) (GMAC_TN_TNS_Msk & ((value) << GMAC_TN_TNS_Pos)) 2804 #define GMAC_TN_MASK _U_(0x3FFFFFFF) /**< \deprecated (GMAC_TN) Register MASK (Use GMAC_TN_Msk instead) */ 2805 #define GMAC_TN_Msk _U_(0x3FFFFFFF) /**< (GMAC_TN) Register Mask */ 2806 2807 2808 /* -------- GMAC_TA : (GMAC Offset: 0x1d8) (/W 32) 1588 Timer Adjust Register -------- */ 2809 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2810 #if COMPONENT_TYPEDEF_STYLE == 'N' 2811 typedef union { 2812 struct { 2813 uint32_t ITDT:30; /**< bit: 0..29 Increment/Decrement */ 2814 uint32_t :1; /**< bit: 30 Reserved */ 2815 uint32_t ADJ:1; /**< bit: 31 Adjust 1588 Timer */ 2816 } bit; /**< Structure used for bit access */ 2817 uint32_t reg; /**< Type used for register access */ 2818 } GMAC_TA_Type; 2819 #endif 2820 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2821 2822 #define GMAC_TA_OFFSET (0x1D8) /**< (GMAC_TA) 1588 Timer Adjust Register Offset */ 2823 2824 #define GMAC_TA_ITDT_Pos 0 /**< (GMAC_TA) Increment/Decrement Position */ 2825 #define GMAC_TA_ITDT_Msk (_U_(0x3FFFFFFF) << GMAC_TA_ITDT_Pos) /**< (GMAC_TA) Increment/Decrement Mask */ 2826 #define GMAC_TA_ITDT(value) (GMAC_TA_ITDT_Msk & ((value) << GMAC_TA_ITDT_Pos)) 2827 #define GMAC_TA_ADJ_Pos 31 /**< (GMAC_TA) Adjust 1588 Timer Position */ 2828 #define GMAC_TA_ADJ_Msk (_U_(0x1) << GMAC_TA_ADJ_Pos) /**< (GMAC_TA) Adjust 1588 Timer Mask */ 2829 #define GMAC_TA_ADJ GMAC_TA_ADJ_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_TA_ADJ_Msk instead */ 2830 #define GMAC_TA_MASK _U_(0xBFFFFFFF) /**< \deprecated (GMAC_TA) Register MASK (Use GMAC_TA_Msk instead) */ 2831 #define GMAC_TA_Msk _U_(0xBFFFFFFF) /**< (GMAC_TA) Register Mask */ 2832 2833 2834 /* -------- GMAC_TI : (GMAC Offset: 0x1dc) (R/W 32) 1588 Timer Increment Register -------- */ 2835 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2836 #if COMPONENT_TYPEDEF_STYLE == 'N' 2837 typedef union { 2838 struct { 2839 uint32_t CNS:8; /**< bit: 0..7 Count Nanoseconds */ 2840 uint32_t ACNS:8; /**< bit: 8..15 Alternative Count Nanoseconds */ 2841 uint32_t NIT:8; /**< bit: 16..23 Number of Increments */ 2842 uint32_t :8; /**< bit: 24..31 Reserved */ 2843 } bit; /**< Structure used for bit access */ 2844 uint32_t reg; /**< Type used for register access */ 2845 } GMAC_TI_Type; 2846 #endif 2847 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2848 2849 #define GMAC_TI_OFFSET (0x1DC) /**< (GMAC_TI) 1588 Timer Increment Register Offset */ 2850 2851 #define GMAC_TI_CNS_Pos 0 /**< (GMAC_TI) Count Nanoseconds Position */ 2852 #define GMAC_TI_CNS_Msk (_U_(0xFF) << GMAC_TI_CNS_Pos) /**< (GMAC_TI) Count Nanoseconds Mask */ 2853 #define GMAC_TI_CNS(value) (GMAC_TI_CNS_Msk & ((value) << GMAC_TI_CNS_Pos)) 2854 #define GMAC_TI_ACNS_Pos 8 /**< (GMAC_TI) Alternative Count Nanoseconds Position */ 2855 #define GMAC_TI_ACNS_Msk (_U_(0xFF) << GMAC_TI_ACNS_Pos) /**< (GMAC_TI) Alternative Count Nanoseconds Mask */ 2856 #define GMAC_TI_ACNS(value) (GMAC_TI_ACNS_Msk & ((value) << GMAC_TI_ACNS_Pos)) 2857 #define GMAC_TI_NIT_Pos 16 /**< (GMAC_TI) Number of Increments Position */ 2858 #define GMAC_TI_NIT_Msk (_U_(0xFF) << GMAC_TI_NIT_Pos) /**< (GMAC_TI) Number of Increments Mask */ 2859 #define GMAC_TI_NIT(value) (GMAC_TI_NIT_Msk & ((value) << GMAC_TI_NIT_Pos)) 2860 #define GMAC_TI_MASK _U_(0xFFFFFF) /**< \deprecated (GMAC_TI) Register MASK (Use GMAC_TI_Msk instead) */ 2861 #define GMAC_TI_Msk _U_(0xFFFFFF) /**< (GMAC_TI) Register Mask */ 2862 2863 2864 /* -------- GMAC_EFTSL : (GMAC Offset: 0x1e0) (R/ 32) PTP Event Frame Transmitted Seconds Low Register -------- */ 2865 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2866 #if COMPONENT_TYPEDEF_STYLE == 'N' 2867 typedef union { 2868 struct { 2869 uint32_t RUD:32; /**< bit: 0..31 Register Update */ 2870 } bit; /**< Structure used for bit access */ 2871 uint32_t reg; /**< Type used for register access */ 2872 } GMAC_EFTSL_Type; 2873 #endif 2874 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2875 2876 #define GMAC_EFTSL_OFFSET (0x1E0) /**< (GMAC_EFTSL) PTP Event Frame Transmitted Seconds Low Register Offset */ 2877 2878 #define GMAC_EFTSL_RUD_Pos 0 /**< (GMAC_EFTSL) Register Update Position */ 2879 #define GMAC_EFTSL_RUD_Msk (_U_(0xFFFFFFFF) << GMAC_EFTSL_RUD_Pos) /**< (GMAC_EFTSL) Register Update Mask */ 2880 #define GMAC_EFTSL_RUD(value) (GMAC_EFTSL_RUD_Msk & ((value) << GMAC_EFTSL_RUD_Pos)) 2881 #define GMAC_EFTSL_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_EFTSL) Register MASK (Use GMAC_EFTSL_Msk instead) */ 2882 #define GMAC_EFTSL_Msk _U_(0xFFFFFFFF) /**< (GMAC_EFTSL) Register Mask */ 2883 2884 2885 /* -------- GMAC_EFTN : (GMAC Offset: 0x1e4) (R/ 32) PTP Event Frame Transmitted Nanoseconds Register -------- */ 2886 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2887 #if COMPONENT_TYPEDEF_STYLE == 'N' 2888 typedef union { 2889 struct { 2890 uint32_t RUD:30; /**< bit: 0..29 Register Update */ 2891 uint32_t :2; /**< bit: 30..31 Reserved */ 2892 } bit; /**< Structure used for bit access */ 2893 uint32_t reg; /**< Type used for register access */ 2894 } GMAC_EFTN_Type; 2895 #endif 2896 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2897 2898 #define GMAC_EFTN_OFFSET (0x1E4) /**< (GMAC_EFTN) PTP Event Frame Transmitted Nanoseconds Register Offset */ 2899 2900 #define GMAC_EFTN_RUD_Pos 0 /**< (GMAC_EFTN) Register Update Position */ 2901 #define GMAC_EFTN_RUD_Msk (_U_(0x3FFFFFFF) << GMAC_EFTN_RUD_Pos) /**< (GMAC_EFTN) Register Update Mask */ 2902 #define GMAC_EFTN_RUD(value) (GMAC_EFTN_RUD_Msk & ((value) << GMAC_EFTN_RUD_Pos)) 2903 #define GMAC_EFTN_MASK _U_(0x3FFFFFFF) /**< \deprecated (GMAC_EFTN) Register MASK (Use GMAC_EFTN_Msk instead) */ 2904 #define GMAC_EFTN_Msk _U_(0x3FFFFFFF) /**< (GMAC_EFTN) Register Mask */ 2905 2906 2907 /* -------- GMAC_EFRSL : (GMAC Offset: 0x1e8) (R/ 32) PTP Event Frame Received Seconds Low Register -------- */ 2908 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2909 #if COMPONENT_TYPEDEF_STYLE == 'N' 2910 typedef union { 2911 struct { 2912 uint32_t RUD:32; /**< bit: 0..31 Register Update */ 2913 } bit; /**< Structure used for bit access */ 2914 uint32_t reg; /**< Type used for register access */ 2915 } GMAC_EFRSL_Type; 2916 #endif 2917 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2918 2919 #define GMAC_EFRSL_OFFSET (0x1E8) /**< (GMAC_EFRSL) PTP Event Frame Received Seconds Low Register Offset */ 2920 2921 #define GMAC_EFRSL_RUD_Pos 0 /**< (GMAC_EFRSL) Register Update Position */ 2922 #define GMAC_EFRSL_RUD_Msk (_U_(0xFFFFFFFF) << GMAC_EFRSL_RUD_Pos) /**< (GMAC_EFRSL) Register Update Mask */ 2923 #define GMAC_EFRSL_RUD(value) (GMAC_EFRSL_RUD_Msk & ((value) << GMAC_EFRSL_RUD_Pos)) 2924 #define GMAC_EFRSL_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_EFRSL) Register MASK (Use GMAC_EFRSL_Msk instead) */ 2925 #define GMAC_EFRSL_Msk _U_(0xFFFFFFFF) /**< (GMAC_EFRSL) Register Mask */ 2926 2927 2928 /* -------- GMAC_EFRN : (GMAC Offset: 0x1ec) (R/ 32) PTP Event Frame Received Nanoseconds Register -------- */ 2929 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2930 #if COMPONENT_TYPEDEF_STYLE == 'N' 2931 typedef union { 2932 struct { 2933 uint32_t RUD:30; /**< bit: 0..29 Register Update */ 2934 uint32_t :2; /**< bit: 30..31 Reserved */ 2935 } bit; /**< Structure used for bit access */ 2936 uint32_t reg; /**< Type used for register access */ 2937 } GMAC_EFRN_Type; 2938 #endif 2939 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2940 2941 #define GMAC_EFRN_OFFSET (0x1EC) /**< (GMAC_EFRN) PTP Event Frame Received Nanoseconds Register Offset */ 2942 2943 #define GMAC_EFRN_RUD_Pos 0 /**< (GMAC_EFRN) Register Update Position */ 2944 #define GMAC_EFRN_RUD_Msk (_U_(0x3FFFFFFF) << GMAC_EFRN_RUD_Pos) /**< (GMAC_EFRN) Register Update Mask */ 2945 #define GMAC_EFRN_RUD(value) (GMAC_EFRN_RUD_Msk & ((value) << GMAC_EFRN_RUD_Pos)) 2946 #define GMAC_EFRN_MASK _U_(0x3FFFFFFF) /**< \deprecated (GMAC_EFRN) Register MASK (Use GMAC_EFRN_Msk instead) */ 2947 #define GMAC_EFRN_Msk _U_(0x3FFFFFFF) /**< (GMAC_EFRN) Register Mask */ 2948 2949 2950 /* -------- GMAC_PEFTSL : (GMAC Offset: 0x1f0) (R/ 32) PTP Peer Event Frame Transmitted Seconds Low Register -------- */ 2951 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2952 #if COMPONENT_TYPEDEF_STYLE == 'N' 2953 typedef union { 2954 struct { 2955 uint32_t RUD:32; /**< bit: 0..31 Register Update */ 2956 } bit; /**< Structure used for bit access */ 2957 uint32_t reg; /**< Type used for register access */ 2958 } GMAC_PEFTSL_Type; 2959 #endif 2960 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2961 2962 #define GMAC_PEFTSL_OFFSET (0x1F0) /**< (GMAC_PEFTSL) PTP Peer Event Frame Transmitted Seconds Low Register Offset */ 2963 2964 #define GMAC_PEFTSL_RUD_Pos 0 /**< (GMAC_PEFTSL) Register Update Position */ 2965 #define GMAC_PEFTSL_RUD_Msk (_U_(0xFFFFFFFF) << GMAC_PEFTSL_RUD_Pos) /**< (GMAC_PEFTSL) Register Update Mask */ 2966 #define GMAC_PEFTSL_RUD(value) (GMAC_PEFTSL_RUD_Msk & ((value) << GMAC_PEFTSL_RUD_Pos)) 2967 #define GMAC_PEFTSL_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_PEFTSL) Register MASK (Use GMAC_PEFTSL_Msk instead) */ 2968 #define GMAC_PEFTSL_Msk _U_(0xFFFFFFFF) /**< (GMAC_PEFTSL) Register Mask */ 2969 2970 2971 /* -------- GMAC_PEFTN : (GMAC Offset: 0x1f4) (R/ 32) PTP Peer Event Frame Transmitted Nanoseconds Register -------- */ 2972 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2973 #if COMPONENT_TYPEDEF_STYLE == 'N' 2974 typedef union { 2975 struct { 2976 uint32_t RUD:30; /**< bit: 0..29 Register Update */ 2977 uint32_t :2; /**< bit: 30..31 Reserved */ 2978 } bit; /**< Structure used for bit access */ 2979 uint32_t reg; /**< Type used for register access */ 2980 } GMAC_PEFTN_Type; 2981 #endif 2982 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2983 2984 #define GMAC_PEFTN_OFFSET (0x1F4) /**< (GMAC_PEFTN) PTP Peer Event Frame Transmitted Nanoseconds Register Offset */ 2985 2986 #define GMAC_PEFTN_RUD_Pos 0 /**< (GMAC_PEFTN) Register Update Position */ 2987 #define GMAC_PEFTN_RUD_Msk (_U_(0x3FFFFFFF) << GMAC_PEFTN_RUD_Pos) /**< (GMAC_PEFTN) Register Update Mask */ 2988 #define GMAC_PEFTN_RUD(value) (GMAC_PEFTN_RUD_Msk & ((value) << GMAC_PEFTN_RUD_Pos)) 2989 #define GMAC_PEFTN_MASK _U_(0x3FFFFFFF) /**< \deprecated (GMAC_PEFTN) Register MASK (Use GMAC_PEFTN_Msk instead) */ 2990 #define GMAC_PEFTN_Msk _U_(0x3FFFFFFF) /**< (GMAC_PEFTN) Register Mask */ 2991 2992 2993 /* -------- GMAC_PEFRSL : (GMAC Offset: 0x1f8) (R/ 32) PTP Peer Event Frame Received Seconds Low Register -------- */ 2994 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2995 #if COMPONENT_TYPEDEF_STYLE == 'N' 2996 typedef union { 2997 struct { 2998 uint32_t RUD:32; /**< bit: 0..31 Register Update */ 2999 } bit; /**< Structure used for bit access */ 3000 uint32_t reg; /**< Type used for register access */ 3001 } GMAC_PEFRSL_Type; 3002 #endif 3003 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 3004 3005 #define GMAC_PEFRSL_OFFSET (0x1F8) /**< (GMAC_PEFRSL) PTP Peer Event Frame Received Seconds Low Register Offset */ 3006 3007 #define GMAC_PEFRSL_RUD_Pos 0 /**< (GMAC_PEFRSL) Register Update Position */ 3008 #define GMAC_PEFRSL_RUD_Msk (_U_(0xFFFFFFFF) << GMAC_PEFRSL_RUD_Pos) /**< (GMAC_PEFRSL) Register Update Mask */ 3009 #define GMAC_PEFRSL_RUD(value) (GMAC_PEFRSL_RUD_Msk & ((value) << GMAC_PEFRSL_RUD_Pos)) 3010 #define GMAC_PEFRSL_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_PEFRSL) Register MASK (Use GMAC_PEFRSL_Msk instead) */ 3011 #define GMAC_PEFRSL_Msk _U_(0xFFFFFFFF) /**< (GMAC_PEFRSL) Register Mask */ 3012 3013 3014 /* -------- GMAC_PEFRN : (GMAC Offset: 0x1fc) (R/ 32) PTP Peer Event Frame Received Nanoseconds Register -------- */ 3015 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 3016 #if COMPONENT_TYPEDEF_STYLE == 'N' 3017 typedef union { 3018 struct { 3019 uint32_t RUD:30; /**< bit: 0..29 Register Update */ 3020 uint32_t :2; /**< bit: 30..31 Reserved */ 3021 } bit; /**< Structure used for bit access */ 3022 uint32_t reg; /**< Type used for register access */ 3023 } GMAC_PEFRN_Type; 3024 #endif 3025 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 3026 3027 #define GMAC_PEFRN_OFFSET (0x1FC) /**< (GMAC_PEFRN) PTP Peer Event Frame Received Nanoseconds Register Offset */ 3028 3029 #define GMAC_PEFRN_RUD_Pos 0 /**< (GMAC_PEFRN) Register Update Position */ 3030 #define GMAC_PEFRN_RUD_Msk (_U_(0x3FFFFFFF) << GMAC_PEFRN_RUD_Pos) /**< (GMAC_PEFRN) Register Update Mask */ 3031 #define GMAC_PEFRN_RUD(value) (GMAC_PEFRN_RUD_Msk & ((value) << GMAC_PEFRN_RUD_Pos)) 3032 #define GMAC_PEFRN_MASK _U_(0x3FFFFFFF) /**< \deprecated (GMAC_PEFRN) Register MASK (Use GMAC_PEFRN_Msk instead) */ 3033 #define GMAC_PEFRN_Msk _U_(0x3FFFFFFF) /**< (GMAC_PEFRN) Register Mask */ 3034 3035 3036 /* -------- GMAC_RXLPI : (GMAC Offset: 0x270) (R/ 32) Received LPI Transitions -------- */ 3037 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 3038 #if COMPONENT_TYPEDEF_STYLE == 'N' 3039 typedef union { 3040 struct { 3041 uint32_t COUNT:16; /**< bit: 0..15 Count of RX LPI transitions (cleared on read) */ 3042 uint32_t :16; /**< bit: 16..31 Reserved */ 3043 } bit; /**< Structure used for bit access */ 3044 uint32_t reg; /**< Type used for register access */ 3045 } GMAC_RXLPI_Type; 3046 #endif 3047 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 3048 3049 #define GMAC_RXLPI_OFFSET (0x270) /**< (GMAC_RXLPI) Received LPI Transitions Offset */ 3050 3051 #define GMAC_RXLPI_COUNT_Pos 0 /**< (GMAC_RXLPI) Count of RX LPI transitions (cleared on read) Position */ 3052 #define GMAC_RXLPI_COUNT_Msk (_U_(0xFFFF) << GMAC_RXLPI_COUNT_Pos) /**< (GMAC_RXLPI) Count of RX LPI transitions (cleared on read) Mask */ 3053 #define GMAC_RXLPI_COUNT(value) (GMAC_RXLPI_COUNT_Msk & ((value) << GMAC_RXLPI_COUNT_Pos)) 3054 #define GMAC_RXLPI_MASK _U_(0xFFFF) /**< \deprecated (GMAC_RXLPI) Register MASK (Use GMAC_RXLPI_Msk instead) */ 3055 #define GMAC_RXLPI_Msk _U_(0xFFFF) /**< (GMAC_RXLPI) Register Mask */ 3056 3057 3058 /* -------- GMAC_RXLPITIME : (GMAC Offset: 0x274) (R/ 32) Received LPI Time -------- */ 3059 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 3060 #if COMPONENT_TYPEDEF_STYLE == 'N' 3061 typedef union { 3062 struct { 3063 uint32_t LPITIME:24; /**< bit: 0..23 Time in LPI (cleared on read) */ 3064 uint32_t :8; /**< bit: 24..31 Reserved */ 3065 } bit; /**< Structure used for bit access */ 3066 uint32_t reg; /**< Type used for register access */ 3067 } GMAC_RXLPITIME_Type; 3068 #endif 3069 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 3070 3071 #define GMAC_RXLPITIME_OFFSET (0x274) /**< (GMAC_RXLPITIME) Received LPI Time Offset */ 3072 3073 #define GMAC_RXLPITIME_LPITIME_Pos 0 /**< (GMAC_RXLPITIME) Time in LPI (cleared on read) Position */ 3074 #define GMAC_RXLPITIME_LPITIME_Msk (_U_(0xFFFFFF) << GMAC_RXLPITIME_LPITIME_Pos) /**< (GMAC_RXLPITIME) Time in LPI (cleared on read) Mask */ 3075 #define GMAC_RXLPITIME_LPITIME(value) (GMAC_RXLPITIME_LPITIME_Msk & ((value) << GMAC_RXLPITIME_LPITIME_Pos)) 3076 #define GMAC_RXLPITIME_MASK _U_(0xFFFFFF) /**< \deprecated (GMAC_RXLPITIME) Register MASK (Use GMAC_RXLPITIME_Msk instead) */ 3077 #define GMAC_RXLPITIME_Msk _U_(0xFFFFFF) /**< (GMAC_RXLPITIME) Register Mask */ 3078 3079 3080 /* -------- GMAC_TXLPI : (GMAC Offset: 0x278) (R/ 32) Transmit LPI Transitions -------- */ 3081 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 3082 #if COMPONENT_TYPEDEF_STYLE == 'N' 3083 typedef union { 3084 struct { 3085 uint32_t COUNT:16; /**< bit: 0..15 Count of LPI transitions (cleared on read) */ 3086 uint32_t :16; /**< bit: 16..31 Reserved */ 3087 } bit; /**< Structure used for bit access */ 3088 uint32_t reg; /**< Type used for register access */ 3089 } GMAC_TXLPI_Type; 3090 #endif 3091 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 3092 3093 #define GMAC_TXLPI_OFFSET (0x278) /**< (GMAC_TXLPI) Transmit LPI Transitions Offset */ 3094 3095 #define GMAC_TXLPI_COUNT_Pos 0 /**< (GMAC_TXLPI) Count of LPI transitions (cleared on read) Position */ 3096 #define GMAC_TXLPI_COUNT_Msk (_U_(0xFFFF) << GMAC_TXLPI_COUNT_Pos) /**< (GMAC_TXLPI) Count of LPI transitions (cleared on read) Mask */ 3097 #define GMAC_TXLPI_COUNT(value) (GMAC_TXLPI_COUNT_Msk & ((value) << GMAC_TXLPI_COUNT_Pos)) 3098 #define GMAC_TXLPI_MASK _U_(0xFFFF) /**< \deprecated (GMAC_TXLPI) Register MASK (Use GMAC_TXLPI_Msk instead) */ 3099 #define GMAC_TXLPI_Msk _U_(0xFFFF) /**< (GMAC_TXLPI) Register Mask */ 3100 3101 3102 /* -------- GMAC_TXLPITIME : (GMAC Offset: 0x27c) (R/ 32) Transmit LPI Time -------- */ 3103 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 3104 #if COMPONENT_TYPEDEF_STYLE == 'N' 3105 typedef union { 3106 struct { 3107 uint32_t LPITIME:24; /**< bit: 0..23 Time in LPI (cleared on read) */ 3108 uint32_t :8; /**< bit: 24..31 Reserved */ 3109 } bit; /**< Structure used for bit access */ 3110 uint32_t reg; /**< Type used for register access */ 3111 } GMAC_TXLPITIME_Type; 3112 #endif 3113 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 3114 3115 #define GMAC_TXLPITIME_OFFSET (0x27C) /**< (GMAC_TXLPITIME) Transmit LPI Time Offset */ 3116 3117 #define GMAC_TXLPITIME_LPITIME_Pos 0 /**< (GMAC_TXLPITIME) Time in LPI (cleared on read) Position */ 3118 #define GMAC_TXLPITIME_LPITIME_Msk (_U_(0xFFFFFF) << GMAC_TXLPITIME_LPITIME_Pos) /**< (GMAC_TXLPITIME) Time in LPI (cleared on read) Mask */ 3119 #define GMAC_TXLPITIME_LPITIME(value) (GMAC_TXLPITIME_LPITIME_Msk & ((value) << GMAC_TXLPITIME_LPITIME_Pos)) 3120 #define GMAC_TXLPITIME_MASK _U_(0xFFFFFF) /**< \deprecated (GMAC_TXLPITIME) Register MASK (Use GMAC_TXLPITIME_Msk instead) */ 3121 #define GMAC_TXLPITIME_Msk _U_(0xFFFFFF) /**< (GMAC_TXLPITIME) Register Mask */ 3122 3123 3124 /* -------- GMAC_ISRPQ : (GMAC Offset: 0x400) (R/ 32) Interrupt Status Register Priority Queue (1..5) -------- */ 3125 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 3126 #if COMPONENT_TYPEDEF_STYLE == 'N' 3127 typedef union { 3128 struct { 3129 uint32_t :1; /**< bit: 0 Reserved */ 3130 uint32_t RCOMP:1; /**< bit: 1 Receive Complete */ 3131 uint32_t RXUBR:1; /**< bit: 2 RX Used Bit Read */ 3132 uint32_t :2; /**< bit: 3..4 Reserved */ 3133 uint32_t RLEX:1; /**< bit: 5 Retry Limit Exceeded or Late Collision */ 3134 uint32_t TFC:1; /**< bit: 6 Transmit Frame Corruption Due to AHB Error */ 3135 uint32_t TCOMP:1; /**< bit: 7 Transmit Complete */ 3136 uint32_t :2; /**< bit: 8..9 Reserved */ 3137 uint32_t ROVR:1; /**< bit: 10 Receive Overrun */ 3138 uint32_t HRESP:1; /**< bit: 11 HRESP Not OK */ 3139 uint32_t :20; /**< bit: 12..31 Reserved */ 3140 } bit; /**< Structure used for bit access */ 3141 uint32_t reg; /**< Type used for register access */ 3142 } GMAC_ISRPQ_Type; 3143 #endif 3144 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 3145 3146 #define GMAC_ISRPQ_OFFSET (0x400) /**< (GMAC_ISRPQ) Interrupt Status Register Priority Queue (1..5) Offset */ 3147 3148 #define GMAC_ISRPQ_RCOMP_Pos 1 /**< (GMAC_ISRPQ) Receive Complete Position */ 3149 #define GMAC_ISRPQ_RCOMP_Msk (_U_(0x1) << GMAC_ISRPQ_RCOMP_Pos) /**< (GMAC_ISRPQ) Receive Complete Mask */ 3150 #define GMAC_ISRPQ_RCOMP GMAC_ISRPQ_RCOMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISRPQ_RCOMP_Msk instead */ 3151 #define GMAC_ISRPQ_RXUBR_Pos 2 /**< (GMAC_ISRPQ) RX Used Bit Read Position */ 3152 #define GMAC_ISRPQ_RXUBR_Msk (_U_(0x1) << GMAC_ISRPQ_RXUBR_Pos) /**< (GMAC_ISRPQ) RX Used Bit Read Mask */ 3153 #define GMAC_ISRPQ_RXUBR GMAC_ISRPQ_RXUBR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISRPQ_RXUBR_Msk instead */ 3154 #define GMAC_ISRPQ_RLEX_Pos 5 /**< (GMAC_ISRPQ) Retry Limit Exceeded or Late Collision Position */ 3155 #define GMAC_ISRPQ_RLEX_Msk (_U_(0x1) << GMAC_ISRPQ_RLEX_Pos) /**< (GMAC_ISRPQ) Retry Limit Exceeded or Late Collision Mask */ 3156 #define GMAC_ISRPQ_RLEX GMAC_ISRPQ_RLEX_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISRPQ_RLEX_Msk instead */ 3157 #define GMAC_ISRPQ_TFC_Pos 6 /**< (GMAC_ISRPQ) Transmit Frame Corruption Due to AHB Error Position */ 3158 #define GMAC_ISRPQ_TFC_Msk (_U_(0x1) << GMAC_ISRPQ_TFC_Pos) /**< (GMAC_ISRPQ) Transmit Frame Corruption Due to AHB Error Mask */ 3159 #define GMAC_ISRPQ_TFC GMAC_ISRPQ_TFC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISRPQ_TFC_Msk instead */ 3160 #define GMAC_ISRPQ_TCOMP_Pos 7 /**< (GMAC_ISRPQ) Transmit Complete Position */ 3161 #define GMAC_ISRPQ_TCOMP_Msk (_U_(0x1) << GMAC_ISRPQ_TCOMP_Pos) /**< (GMAC_ISRPQ) Transmit Complete Mask */ 3162 #define GMAC_ISRPQ_TCOMP GMAC_ISRPQ_TCOMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISRPQ_TCOMP_Msk instead */ 3163 #define GMAC_ISRPQ_ROVR_Pos 10 /**< (GMAC_ISRPQ) Receive Overrun Position */ 3164 #define GMAC_ISRPQ_ROVR_Msk (_U_(0x1) << GMAC_ISRPQ_ROVR_Pos) /**< (GMAC_ISRPQ) Receive Overrun Mask */ 3165 #define GMAC_ISRPQ_ROVR GMAC_ISRPQ_ROVR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISRPQ_ROVR_Msk instead */ 3166 #define GMAC_ISRPQ_HRESP_Pos 11 /**< (GMAC_ISRPQ) HRESP Not OK Position */ 3167 #define GMAC_ISRPQ_HRESP_Msk (_U_(0x1) << GMAC_ISRPQ_HRESP_Pos) /**< (GMAC_ISRPQ) HRESP Not OK Mask */ 3168 #define GMAC_ISRPQ_HRESP GMAC_ISRPQ_HRESP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISRPQ_HRESP_Msk instead */ 3169 #define GMAC_ISRPQ_MASK _U_(0xCE6) /**< \deprecated (GMAC_ISRPQ) Register MASK (Use GMAC_ISRPQ_Msk instead) */ 3170 #define GMAC_ISRPQ_Msk _U_(0xCE6) /**< (GMAC_ISRPQ) Register Mask */ 3171 3172 3173 /* -------- GMAC_TBQBAPQ : (GMAC Offset: 0x440) (R/W 32) Transmit Buffer Queue Base Address Register Priority Queue (1..5) -------- */ 3174 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 3175 #if COMPONENT_TYPEDEF_STYLE == 'N' 3176 typedef union { 3177 struct { 3178 uint32_t :2; /**< bit: 0..1 Reserved */ 3179 uint32_t TXBQBA:30; /**< bit: 2..31 Transmit Buffer Queue Base Address */ 3180 } bit; /**< Structure used for bit access */ 3181 uint32_t reg; /**< Type used for register access */ 3182 } GMAC_TBQBAPQ_Type; 3183 #endif 3184 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 3185 3186 #define GMAC_TBQBAPQ_OFFSET (0x440) /**< (GMAC_TBQBAPQ) Transmit Buffer Queue Base Address Register Priority Queue (1..5) Offset */ 3187 3188 #define GMAC_TBQBAPQ_TXBQBA_Pos 2 /**< (GMAC_TBQBAPQ) Transmit Buffer Queue Base Address Position */ 3189 #define GMAC_TBQBAPQ_TXBQBA_Msk (_U_(0x3FFFFFFF) << GMAC_TBQBAPQ_TXBQBA_Pos) /**< (GMAC_TBQBAPQ) Transmit Buffer Queue Base Address Mask */ 3190 #define GMAC_TBQBAPQ_TXBQBA(value) (GMAC_TBQBAPQ_TXBQBA_Msk & ((value) << GMAC_TBQBAPQ_TXBQBA_Pos)) 3191 #define GMAC_TBQBAPQ_MASK _U_(0xFFFFFFFC) /**< \deprecated (GMAC_TBQBAPQ) Register MASK (Use GMAC_TBQBAPQ_Msk instead) */ 3192 #define GMAC_TBQBAPQ_Msk _U_(0xFFFFFFFC) /**< (GMAC_TBQBAPQ) Register Mask */ 3193 3194 3195 /* -------- GMAC_RBQBAPQ : (GMAC Offset: 0x480) (R/W 32) Receive Buffer Queue Base Address Register Priority Queue (1..5) -------- */ 3196 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 3197 #if COMPONENT_TYPEDEF_STYLE == 'N' 3198 typedef union { 3199 struct { 3200 uint32_t :2; /**< bit: 0..1 Reserved */ 3201 uint32_t RXBQBA:30; /**< bit: 2..31 Receive Buffer Queue Base Address */ 3202 } bit; /**< Structure used for bit access */ 3203 uint32_t reg; /**< Type used for register access */ 3204 } GMAC_RBQBAPQ_Type; 3205 #endif 3206 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 3207 3208 #define GMAC_RBQBAPQ_OFFSET (0x480) /**< (GMAC_RBQBAPQ) Receive Buffer Queue Base Address Register Priority Queue (1..5) Offset */ 3209 3210 #define GMAC_RBQBAPQ_RXBQBA_Pos 2 /**< (GMAC_RBQBAPQ) Receive Buffer Queue Base Address Position */ 3211 #define GMAC_RBQBAPQ_RXBQBA_Msk (_U_(0x3FFFFFFF) << GMAC_RBQBAPQ_RXBQBA_Pos) /**< (GMAC_RBQBAPQ) Receive Buffer Queue Base Address Mask */ 3212 #define GMAC_RBQBAPQ_RXBQBA(value) (GMAC_RBQBAPQ_RXBQBA_Msk & ((value) << GMAC_RBQBAPQ_RXBQBA_Pos)) 3213 #define GMAC_RBQBAPQ_MASK _U_(0xFFFFFFFC) /**< \deprecated (GMAC_RBQBAPQ) Register MASK (Use GMAC_RBQBAPQ_Msk instead) */ 3214 #define GMAC_RBQBAPQ_Msk _U_(0xFFFFFFFC) /**< (GMAC_RBQBAPQ) Register Mask */ 3215 3216 3217 /* -------- GMAC_RBSRPQ : (GMAC Offset: 0x4a0) (R/W 32) Receive Buffer Size Register Priority Queue (1..5) -------- */ 3218 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 3219 #if COMPONENT_TYPEDEF_STYLE == 'N' 3220 typedef union { 3221 struct { 3222 uint32_t RBS:16; /**< bit: 0..15 Receive Buffer Size */ 3223 uint32_t :16; /**< bit: 16..31 Reserved */ 3224 } bit; /**< Structure used for bit access */ 3225 uint32_t reg; /**< Type used for register access */ 3226 } GMAC_RBSRPQ_Type; 3227 #endif 3228 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 3229 3230 #define GMAC_RBSRPQ_OFFSET (0x4A0) /**< (GMAC_RBSRPQ) Receive Buffer Size Register Priority Queue (1..5) Offset */ 3231 3232 #define GMAC_RBSRPQ_RBS_Pos 0 /**< (GMAC_RBSRPQ) Receive Buffer Size Position */ 3233 #define GMAC_RBSRPQ_RBS_Msk (_U_(0xFFFF) << GMAC_RBSRPQ_RBS_Pos) /**< (GMAC_RBSRPQ) Receive Buffer Size Mask */ 3234 #define GMAC_RBSRPQ_RBS(value) (GMAC_RBSRPQ_RBS_Msk & ((value) << GMAC_RBSRPQ_RBS_Pos)) 3235 #define GMAC_RBSRPQ_MASK _U_(0xFFFF) /**< \deprecated (GMAC_RBSRPQ) Register MASK (Use GMAC_RBSRPQ_Msk instead) */ 3236 #define GMAC_RBSRPQ_Msk _U_(0xFFFF) /**< (GMAC_RBSRPQ) Register Mask */ 3237 3238 3239 /* -------- GMAC_CBSCR : (GMAC Offset: 0x4bc) (R/W 32) Credit-Based Shaping Control Register -------- */ 3240 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 3241 #if COMPONENT_TYPEDEF_STYLE == 'N' 3242 typedef union { 3243 struct { 3244 uint32_t QBE:1; /**< bit: 0 Queue B CBS Enable */ 3245 uint32_t QAE:1; /**< bit: 1 Queue A CBS Enable */ 3246 uint32_t :30; /**< bit: 2..31 Reserved */ 3247 } bit; /**< Structure used for bit access */ 3248 uint32_t reg; /**< Type used for register access */ 3249 } GMAC_CBSCR_Type; 3250 #endif 3251 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 3252 3253 #define GMAC_CBSCR_OFFSET (0x4BC) /**< (GMAC_CBSCR) Credit-Based Shaping Control Register Offset */ 3254 3255 #define GMAC_CBSCR_QBE_Pos 0 /**< (GMAC_CBSCR) Queue B CBS Enable Position */ 3256 #define GMAC_CBSCR_QBE_Msk (_U_(0x1) << GMAC_CBSCR_QBE_Pos) /**< (GMAC_CBSCR) Queue B CBS Enable Mask */ 3257 #define GMAC_CBSCR_QBE GMAC_CBSCR_QBE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_CBSCR_QBE_Msk instead */ 3258 #define GMAC_CBSCR_QAE_Pos 1 /**< (GMAC_CBSCR) Queue A CBS Enable Position */ 3259 #define GMAC_CBSCR_QAE_Msk (_U_(0x1) << GMAC_CBSCR_QAE_Pos) /**< (GMAC_CBSCR) Queue A CBS Enable Mask */ 3260 #define GMAC_CBSCR_QAE GMAC_CBSCR_QAE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_CBSCR_QAE_Msk instead */ 3261 #define GMAC_CBSCR_MASK _U_(0x03) /**< \deprecated (GMAC_CBSCR) Register MASK (Use GMAC_CBSCR_Msk instead) */ 3262 #define GMAC_CBSCR_Msk _U_(0x03) /**< (GMAC_CBSCR) Register Mask */ 3263 3264 3265 /* -------- GMAC_CBSISQA : (GMAC Offset: 0x4c0) (R/W 32) Credit-Based Shaping IdleSlope Register for Queue A -------- */ 3266 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 3267 #if COMPONENT_TYPEDEF_STYLE == 'N' 3268 typedef union { 3269 struct { 3270 uint32_t IS:32; /**< bit: 0..31 IdleSlope */ 3271 } bit; /**< Structure used for bit access */ 3272 uint32_t reg; /**< Type used for register access */ 3273 } GMAC_CBSISQA_Type; 3274 #endif 3275 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 3276 3277 #define GMAC_CBSISQA_OFFSET (0x4C0) /**< (GMAC_CBSISQA) Credit-Based Shaping IdleSlope Register for Queue A Offset */ 3278 3279 #define GMAC_CBSISQA_IS_Pos 0 /**< (GMAC_CBSISQA) IdleSlope Position */ 3280 #define GMAC_CBSISQA_IS_Msk (_U_(0xFFFFFFFF) << GMAC_CBSISQA_IS_Pos) /**< (GMAC_CBSISQA) IdleSlope Mask */ 3281 #define GMAC_CBSISQA_IS(value) (GMAC_CBSISQA_IS_Msk & ((value) << GMAC_CBSISQA_IS_Pos)) 3282 #define GMAC_CBSISQA_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_CBSISQA) Register MASK (Use GMAC_CBSISQA_Msk instead) */ 3283 #define GMAC_CBSISQA_Msk _U_(0xFFFFFFFF) /**< (GMAC_CBSISQA) Register Mask */ 3284 3285 3286 /* -------- GMAC_CBSISQB : (GMAC Offset: 0x4c4) (R/W 32) Credit-Based Shaping IdleSlope Register for Queue B -------- */ 3287 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 3288 #if COMPONENT_TYPEDEF_STYLE == 'N' 3289 typedef union { 3290 struct { 3291 uint32_t IS:32; /**< bit: 0..31 IdleSlope */ 3292 } bit; /**< Structure used for bit access */ 3293 uint32_t reg; /**< Type used for register access */ 3294 } GMAC_CBSISQB_Type; 3295 #endif 3296 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 3297 3298 #define GMAC_CBSISQB_OFFSET (0x4C4) /**< (GMAC_CBSISQB) Credit-Based Shaping IdleSlope Register for Queue B Offset */ 3299 3300 #define GMAC_CBSISQB_IS_Pos 0 /**< (GMAC_CBSISQB) IdleSlope Position */ 3301 #define GMAC_CBSISQB_IS_Msk (_U_(0xFFFFFFFF) << GMAC_CBSISQB_IS_Pos) /**< (GMAC_CBSISQB) IdleSlope Mask */ 3302 #define GMAC_CBSISQB_IS(value) (GMAC_CBSISQB_IS_Msk & ((value) << GMAC_CBSISQB_IS_Pos)) 3303 #define GMAC_CBSISQB_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_CBSISQB) Register MASK (Use GMAC_CBSISQB_Msk instead) */ 3304 #define GMAC_CBSISQB_Msk _U_(0xFFFFFFFF) /**< (GMAC_CBSISQB) Register Mask */ 3305 3306 3307 /* -------- GMAC_ST1RPQ : (GMAC Offset: 0x500) (R/W 32) Screening Type 1 Register Priority Queue -------- */ 3308 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 3309 #if COMPONENT_TYPEDEF_STYLE == 'N' 3310 typedef union { 3311 struct { 3312 uint32_t QNB:3; /**< bit: 0..2 Queue Number (0-5) */ 3313 uint32_t :1; /**< bit: 3 Reserved */ 3314 uint32_t DSTCM:8; /**< bit: 4..11 Differentiated Services or Traffic Class Match */ 3315 uint32_t UDPM:16; /**< bit: 12..27 UDP Port Match */ 3316 uint32_t DSTCE:1; /**< bit: 28 Differentiated Services or Traffic Class Match Enable */ 3317 uint32_t UDPE:1; /**< bit: 29 UDP Port Match Enable */ 3318 uint32_t :2; /**< bit: 30..31 Reserved */ 3319 } bit; /**< Structure used for bit access */ 3320 uint32_t reg; /**< Type used for register access */ 3321 } GMAC_ST1RPQ_Type; 3322 #endif 3323 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 3324 3325 #define GMAC_ST1RPQ_OFFSET (0x500) /**< (GMAC_ST1RPQ) Screening Type 1 Register Priority Queue Offset */ 3326 3327 #define GMAC_ST1RPQ_QNB_Pos 0 /**< (GMAC_ST1RPQ) Queue Number (0-5) Position */ 3328 #define GMAC_ST1RPQ_QNB_Msk (_U_(0x7) << GMAC_ST1RPQ_QNB_Pos) /**< (GMAC_ST1RPQ) Queue Number (0-5) Mask */ 3329 #define GMAC_ST1RPQ_QNB(value) (GMAC_ST1RPQ_QNB_Msk & ((value) << GMAC_ST1RPQ_QNB_Pos)) 3330 #define GMAC_ST1RPQ_DSTCM_Pos 4 /**< (GMAC_ST1RPQ) Differentiated Services or Traffic Class Match Position */ 3331 #define GMAC_ST1RPQ_DSTCM_Msk (_U_(0xFF) << GMAC_ST1RPQ_DSTCM_Pos) /**< (GMAC_ST1RPQ) Differentiated Services or Traffic Class Match Mask */ 3332 #define GMAC_ST1RPQ_DSTCM(value) (GMAC_ST1RPQ_DSTCM_Msk & ((value) << GMAC_ST1RPQ_DSTCM_Pos)) 3333 #define GMAC_ST1RPQ_UDPM_Pos 12 /**< (GMAC_ST1RPQ) UDP Port Match Position */ 3334 #define GMAC_ST1RPQ_UDPM_Msk (_U_(0xFFFF) << GMAC_ST1RPQ_UDPM_Pos) /**< (GMAC_ST1RPQ) UDP Port Match Mask */ 3335 #define GMAC_ST1RPQ_UDPM(value) (GMAC_ST1RPQ_UDPM_Msk & ((value) << GMAC_ST1RPQ_UDPM_Pos)) 3336 #define GMAC_ST1RPQ_DSTCE_Pos 28 /**< (GMAC_ST1RPQ) Differentiated Services or Traffic Class Match Enable Position */ 3337 #define GMAC_ST1RPQ_DSTCE_Msk (_U_(0x1) << GMAC_ST1RPQ_DSTCE_Pos) /**< (GMAC_ST1RPQ) Differentiated Services or Traffic Class Match Enable Mask */ 3338 #define GMAC_ST1RPQ_DSTCE GMAC_ST1RPQ_DSTCE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ST1RPQ_DSTCE_Msk instead */ 3339 #define GMAC_ST1RPQ_UDPE_Pos 29 /**< (GMAC_ST1RPQ) UDP Port Match Enable Position */ 3340 #define GMAC_ST1RPQ_UDPE_Msk (_U_(0x1) << GMAC_ST1RPQ_UDPE_Pos) /**< (GMAC_ST1RPQ) UDP Port Match Enable Mask */ 3341 #define GMAC_ST1RPQ_UDPE GMAC_ST1RPQ_UDPE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ST1RPQ_UDPE_Msk instead */ 3342 #define GMAC_ST1RPQ_MASK _U_(0x3FFFFFF7) /**< \deprecated (GMAC_ST1RPQ) Register MASK (Use GMAC_ST1RPQ_Msk instead) */ 3343 #define GMAC_ST1RPQ_Msk _U_(0x3FFFFFF7) /**< (GMAC_ST1RPQ) Register Mask */ 3344 3345 3346 /* -------- GMAC_ST2RPQ : (GMAC Offset: 0x540) (R/W 32) Screening Type 2 Register Priority Queue -------- */ 3347 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 3348 #if COMPONENT_TYPEDEF_STYLE == 'N' 3349 typedef union { 3350 struct { 3351 uint32_t QNB:3; /**< bit: 0..2 Queue Number (0-5) */ 3352 uint32_t :1; /**< bit: 3 Reserved */ 3353 uint32_t VLANP:3; /**< bit: 4..6 VLAN Priority */ 3354 uint32_t :1; /**< bit: 7 Reserved */ 3355 uint32_t VLANE:1; /**< bit: 8 VLAN Enable */ 3356 uint32_t I2ETH:3; /**< bit: 9..11 Index of Screening Type 2 EtherType register x */ 3357 uint32_t ETHE:1; /**< bit: 12 EtherType Enable */ 3358 uint32_t COMPA:5; /**< bit: 13..17 Index of Screening Type 2 Compare Word 0/Word 1 register x */ 3359 uint32_t COMPAE:1; /**< bit: 18 Compare A Enable */ 3360 uint32_t COMPB:5; /**< bit: 19..23 Index of Screening Type 2 Compare Word 0/Word 1 register x */ 3361 uint32_t COMPBE:1; /**< bit: 24 Compare B Enable */ 3362 uint32_t COMPC:5; /**< bit: 25..29 Index of Screening Type 2 Compare Word 0/Word 1 register x */ 3363 uint32_t COMPCE:1; /**< bit: 30 Compare C Enable */ 3364 uint32_t :1; /**< bit: 31 Reserved */ 3365 } bit; /**< Structure used for bit access */ 3366 uint32_t reg; /**< Type used for register access */ 3367 } GMAC_ST2RPQ_Type; 3368 #endif 3369 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 3370 3371 #define GMAC_ST2RPQ_OFFSET (0x540) /**< (GMAC_ST2RPQ) Screening Type 2 Register Priority Queue Offset */ 3372 3373 #define GMAC_ST2RPQ_QNB_Pos 0 /**< (GMAC_ST2RPQ) Queue Number (0-5) Position */ 3374 #define GMAC_ST2RPQ_QNB_Msk (_U_(0x7) << GMAC_ST2RPQ_QNB_Pos) /**< (GMAC_ST2RPQ) Queue Number (0-5) Mask */ 3375 #define GMAC_ST2RPQ_QNB(value) (GMAC_ST2RPQ_QNB_Msk & ((value) << GMAC_ST2RPQ_QNB_Pos)) 3376 #define GMAC_ST2RPQ_VLANP_Pos 4 /**< (GMAC_ST2RPQ) VLAN Priority Position */ 3377 #define GMAC_ST2RPQ_VLANP_Msk (_U_(0x7) << GMAC_ST2RPQ_VLANP_Pos) /**< (GMAC_ST2RPQ) VLAN Priority Mask */ 3378 #define GMAC_ST2RPQ_VLANP(value) (GMAC_ST2RPQ_VLANP_Msk & ((value) << GMAC_ST2RPQ_VLANP_Pos)) 3379 #define GMAC_ST2RPQ_VLANE_Pos 8 /**< (GMAC_ST2RPQ) VLAN Enable Position */ 3380 #define GMAC_ST2RPQ_VLANE_Msk (_U_(0x1) << GMAC_ST2RPQ_VLANE_Pos) /**< (GMAC_ST2RPQ) VLAN Enable Mask */ 3381 #define GMAC_ST2RPQ_VLANE GMAC_ST2RPQ_VLANE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ST2RPQ_VLANE_Msk instead */ 3382 #define GMAC_ST2RPQ_I2ETH_Pos 9 /**< (GMAC_ST2RPQ) Index of Screening Type 2 EtherType register x Position */ 3383 #define GMAC_ST2RPQ_I2ETH_Msk (_U_(0x7) << GMAC_ST2RPQ_I2ETH_Pos) /**< (GMAC_ST2RPQ) Index of Screening Type 2 EtherType register x Mask */ 3384 #define GMAC_ST2RPQ_I2ETH(value) (GMAC_ST2RPQ_I2ETH_Msk & ((value) << GMAC_ST2RPQ_I2ETH_Pos)) 3385 #define GMAC_ST2RPQ_ETHE_Pos 12 /**< (GMAC_ST2RPQ) EtherType Enable Position */ 3386 #define GMAC_ST2RPQ_ETHE_Msk (_U_(0x1) << GMAC_ST2RPQ_ETHE_Pos) /**< (GMAC_ST2RPQ) EtherType Enable Mask */ 3387 #define GMAC_ST2RPQ_ETHE GMAC_ST2RPQ_ETHE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ST2RPQ_ETHE_Msk instead */ 3388 #define GMAC_ST2RPQ_COMPA_Pos 13 /**< (GMAC_ST2RPQ) Index of Screening Type 2 Compare Word 0/Word 1 register x Position */ 3389 #define GMAC_ST2RPQ_COMPA_Msk (_U_(0x1F) << GMAC_ST2RPQ_COMPA_Pos) /**< (GMAC_ST2RPQ) Index of Screening Type 2 Compare Word 0/Word 1 register x Mask */ 3390 #define GMAC_ST2RPQ_COMPA(value) (GMAC_ST2RPQ_COMPA_Msk & ((value) << GMAC_ST2RPQ_COMPA_Pos)) 3391 #define GMAC_ST2RPQ_COMPAE_Pos 18 /**< (GMAC_ST2RPQ) Compare A Enable Position */ 3392 #define GMAC_ST2RPQ_COMPAE_Msk (_U_(0x1) << GMAC_ST2RPQ_COMPAE_Pos) /**< (GMAC_ST2RPQ) Compare A Enable Mask */ 3393 #define GMAC_ST2RPQ_COMPAE GMAC_ST2RPQ_COMPAE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ST2RPQ_COMPAE_Msk instead */ 3394 #define GMAC_ST2RPQ_COMPB_Pos 19 /**< (GMAC_ST2RPQ) Index of Screening Type 2 Compare Word 0/Word 1 register x Position */ 3395 #define GMAC_ST2RPQ_COMPB_Msk (_U_(0x1F) << GMAC_ST2RPQ_COMPB_Pos) /**< (GMAC_ST2RPQ) Index of Screening Type 2 Compare Word 0/Word 1 register x Mask */ 3396 #define GMAC_ST2RPQ_COMPB(value) (GMAC_ST2RPQ_COMPB_Msk & ((value) << GMAC_ST2RPQ_COMPB_Pos)) 3397 #define GMAC_ST2RPQ_COMPBE_Pos 24 /**< (GMAC_ST2RPQ) Compare B Enable Position */ 3398 #define GMAC_ST2RPQ_COMPBE_Msk (_U_(0x1) << GMAC_ST2RPQ_COMPBE_Pos) /**< (GMAC_ST2RPQ) Compare B Enable Mask */ 3399 #define GMAC_ST2RPQ_COMPBE GMAC_ST2RPQ_COMPBE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ST2RPQ_COMPBE_Msk instead */ 3400 #define GMAC_ST2RPQ_COMPC_Pos 25 /**< (GMAC_ST2RPQ) Index of Screening Type 2 Compare Word 0/Word 1 register x Position */ 3401 #define GMAC_ST2RPQ_COMPC_Msk (_U_(0x1F) << GMAC_ST2RPQ_COMPC_Pos) /**< (GMAC_ST2RPQ) Index of Screening Type 2 Compare Word 0/Word 1 register x Mask */ 3402 #define GMAC_ST2RPQ_COMPC(value) (GMAC_ST2RPQ_COMPC_Msk & ((value) << GMAC_ST2RPQ_COMPC_Pos)) 3403 #define GMAC_ST2RPQ_COMPCE_Pos 30 /**< (GMAC_ST2RPQ) Compare C Enable Position */ 3404 #define GMAC_ST2RPQ_COMPCE_Msk (_U_(0x1) << GMAC_ST2RPQ_COMPCE_Pos) /**< (GMAC_ST2RPQ) Compare C Enable Mask */ 3405 #define GMAC_ST2RPQ_COMPCE GMAC_ST2RPQ_COMPCE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ST2RPQ_COMPCE_Msk instead */ 3406 #define GMAC_ST2RPQ_MASK _U_(0x7FFFFF77) /**< \deprecated (GMAC_ST2RPQ) Register MASK (Use GMAC_ST2RPQ_Msk instead) */ 3407 #define GMAC_ST2RPQ_Msk _U_(0x7FFFFF77) /**< (GMAC_ST2RPQ) Register Mask */ 3408 3409 3410 /* -------- GMAC_IERPQ : (GMAC Offset: 0x600) (/W 32) Interrupt Enable Register Priority Queue (1..5) -------- */ 3411 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 3412 #if COMPONENT_TYPEDEF_STYLE == 'N' 3413 typedef union { 3414 struct { 3415 uint32_t :1; /**< bit: 0 Reserved */ 3416 uint32_t RCOMP:1; /**< bit: 1 Receive Complete */ 3417 uint32_t RXUBR:1; /**< bit: 2 RX Used Bit Read */ 3418 uint32_t :2; /**< bit: 3..4 Reserved */ 3419 uint32_t RLEX:1; /**< bit: 5 Retry Limit Exceeded or Late Collision */ 3420 uint32_t TFC:1; /**< bit: 6 Transmit Frame Corruption Due to AHB Error */ 3421 uint32_t TCOMP:1; /**< bit: 7 Transmit Complete */ 3422 uint32_t :2; /**< bit: 8..9 Reserved */ 3423 uint32_t ROVR:1; /**< bit: 10 Receive Overrun */ 3424 uint32_t HRESP:1; /**< bit: 11 HRESP Not OK */ 3425 uint32_t :20; /**< bit: 12..31 Reserved */ 3426 } bit; /**< Structure used for bit access */ 3427 uint32_t reg; /**< Type used for register access */ 3428 } GMAC_IERPQ_Type; 3429 #endif 3430 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 3431 3432 #define GMAC_IERPQ_OFFSET (0x600) /**< (GMAC_IERPQ) Interrupt Enable Register Priority Queue (1..5) Offset */ 3433 3434 #define GMAC_IERPQ_RCOMP_Pos 1 /**< (GMAC_IERPQ) Receive Complete Position */ 3435 #define GMAC_IERPQ_RCOMP_Msk (_U_(0x1) << GMAC_IERPQ_RCOMP_Pos) /**< (GMAC_IERPQ) Receive Complete Mask */ 3436 #define GMAC_IERPQ_RCOMP GMAC_IERPQ_RCOMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IERPQ_RCOMP_Msk instead */ 3437 #define GMAC_IERPQ_RXUBR_Pos 2 /**< (GMAC_IERPQ) RX Used Bit Read Position */ 3438 #define GMAC_IERPQ_RXUBR_Msk (_U_(0x1) << GMAC_IERPQ_RXUBR_Pos) /**< (GMAC_IERPQ) RX Used Bit Read Mask */ 3439 #define GMAC_IERPQ_RXUBR GMAC_IERPQ_RXUBR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IERPQ_RXUBR_Msk instead */ 3440 #define GMAC_IERPQ_RLEX_Pos 5 /**< (GMAC_IERPQ) Retry Limit Exceeded or Late Collision Position */ 3441 #define GMAC_IERPQ_RLEX_Msk (_U_(0x1) << GMAC_IERPQ_RLEX_Pos) /**< (GMAC_IERPQ) Retry Limit Exceeded or Late Collision Mask */ 3442 #define GMAC_IERPQ_RLEX GMAC_IERPQ_RLEX_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IERPQ_RLEX_Msk instead */ 3443 #define GMAC_IERPQ_TFC_Pos 6 /**< (GMAC_IERPQ) Transmit Frame Corruption Due to AHB Error Position */ 3444 #define GMAC_IERPQ_TFC_Msk (_U_(0x1) << GMAC_IERPQ_TFC_Pos) /**< (GMAC_IERPQ) Transmit Frame Corruption Due to AHB Error Mask */ 3445 #define GMAC_IERPQ_TFC GMAC_IERPQ_TFC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IERPQ_TFC_Msk instead */ 3446 #define GMAC_IERPQ_TCOMP_Pos 7 /**< (GMAC_IERPQ) Transmit Complete Position */ 3447 #define GMAC_IERPQ_TCOMP_Msk (_U_(0x1) << GMAC_IERPQ_TCOMP_Pos) /**< (GMAC_IERPQ) Transmit Complete Mask */ 3448 #define GMAC_IERPQ_TCOMP GMAC_IERPQ_TCOMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IERPQ_TCOMP_Msk instead */ 3449 #define GMAC_IERPQ_ROVR_Pos 10 /**< (GMAC_IERPQ) Receive Overrun Position */ 3450 #define GMAC_IERPQ_ROVR_Msk (_U_(0x1) << GMAC_IERPQ_ROVR_Pos) /**< (GMAC_IERPQ) Receive Overrun Mask */ 3451 #define GMAC_IERPQ_ROVR GMAC_IERPQ_ROVR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IERPQ_ROVR_Msk instead */ 3452 #define GMAC_IERPQ_HRESP_Pos 11 /**< (GMAC_IERPQ) HRESP Not OK Position */ 3453 #define GMAC_IERPQ_HRESP_Msk (_U_(0x1) << GMAC_IERPQ_HRESP_Pos) /**< (GMAC_IERPQ) HRESP Not OK Mask */ 3454 #define GMAC_IERPQ_HRESP GMAC_IERPQ_HRESP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IERPQ_HRESP_Msk instead */ 3455 #define GMAC_IERPQ_MASK _U_(0xCE6) /**< \deprecated (GMAC_IERPQ) Register MASK (Use GMAC_IERPQ_Msk instead) */ 3456 #define GMAC_IERPQ_Msk _U_(0xCE6) /**< (GMAC_IERPQ) Register Mask */ 3457 3458 3459 /* -------- GMAC_IDRPQ : (GMAC Offset: 0x620) (/W 32) Interrupt Disable Register Priority Queue (1..5) -------- */ 3460 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 3461 #if COMPONENT_TYPEDEF_STYLE == 'N' 3462 typedef union { 3463 struct { 3464 uint32_t :1; /**< bit: 0 Reserved */ 3465 uint32_t RCOMP:1; /**< bit: 1 Receive Complete */ 3466 uint32_t RXUBR:1; /**< bit: 2 RX Used Bit Read */ 3467 uint32_t :2; /**< bit: 3..4 Reserved */ 3468 uint32_t RLEX:1; /**< bit: 5 Retry Limit Exceeded or Late Collision */ 3469 uint32_t TFC:1; /**< bit: 6 Transmit Frame Corruption Due to AHB Error */ 3470 uint32_t TCOMP:1; /**< bit: 7 Transmit Complete */ 3471 uint32_t :2; /**< bit: 8..9 Reserved */ 3472 uint32_t ROVR:1; /**< bit: 10 Receive Overrun */ 3473 uint32_t HRESP:1; /**< bit: 11 HRESP Not OK */ 3474 uint32_t :20; /**< bit: 12..31 Reserved */ 3475 } bit; /**< Structure used for bit access */ 3476 uint32_t reg; /**< Type used for register access */ 3477 } GMAC_IDRPQ_Type; 3478 #endif 3479 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 3480 3481 #define GMAC_IDRPQ_OFFSET (0x620) /**< (GMAC_IDRPQ) Interrupt Disable Register Priority Queue (1..5) Offset */ 3482 3483 #define GMAC_IDRPQ_RCOMP_Pos 1 /**< (GMAC_IDRPQ) Receive Complete Position */ 3484 #define GMAC_IDRPQ_RCOMP_Msk (_U_(0x1) << GMAC_IDRPQ_RCOMP_Pos) /**< (GMAC_IDRPQ) Receive Complete Mask */ 3485 #define GMAC_IDRPQ_RCOMP GMAC_IDRPQ_RCOMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDRPQ_RCOMP_Msk instead */ 3486 #define GMAC_IDRPQ_RXUBR_Pos 2 /**< (GMAC_IDRPQ) RX Used Bit Read Position */ 3487 #define GMAC_IDRPQ_RXUBR_Msk (_U_(0x1) << GMAC_IDRPQ_RXUBR_Pos) /**< (GMAC_IDRPQ) RX Used Bit Read Mask */ 3488 #define GMAC_IDRPQ_RXUBR GMAC_IDRPQ_RXUBR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDRPQ_RXUBR_Msk instead */ 3489 #define GMAC_IDRPQ_RLEX_Pos 5 /**< (GMAC_IDRPQ) Retry Limit Exceeded or Late Collision Position */ 3490 #define GMAC_IDRPQ_RLEX_Msk (_U_(0x1) << GMAC_IDRPQ_RLEX_Pos) /**< (GMAC_IDRPQ) Retry Limit Exceeded or Late Collision Mask */ 3491 #define GMAC_IDRPQ_RLEX GMAC_IDRPQ_RLEX_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDRPQ_RLEX_Msk instead */ 3492 #define GMAC_IDRPQ_TFC_Pos 6 /**< (GMAC_IDRPQ) Transmit Frame Corruption Due to AHB Error Position */ 3493 #define GMAC_IDRPQ_TFC_Msk (_U_(0x1) << GMAC_IDRPQ_TFC_Pos) /**< (GMAC_IDRPQ) Transmit Frame Corruption Due to AHB Error Mask */ 3494 #define GMAC_IDRPQ_TFC GMAC_IDRPQ_TFC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDRPQ_TFC_Msk instead */ 3495 #define GMAC_IDRPQ_TCOMP_Pos 7 /**< (GMAC_IDRPQ) Transmit Complete Position */ 3496 #define GMAC_IDRPQ_TCOMP_Msk (_U_(0x1) << GMAC_IDRPQ_TCOMP_Pos) /**< (GMAC_IDRPQ) Transmit Complete Mask */ 3497 #define GMAC_IDRPQ_TCOMP GMAC_IDRPQ_TCOMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDRPQ_TCOMP_Msk instead */ 3498 #define GMAC_IDRPQ_ROVR_Pos 10 /**< (GMAC_IDRPQ) Receive Overrun Position */ 3499 #define GMAC_IDRPQ_ROVR_Msk (_U_(0x1) << GMAC_IDRPQ_ROVR_Pos) /**< (GMAC_IDRPQ) Receive Overrun Mask */ 3500 #define GMAC_IDRPQ_ROVR GMAC_IDRPQ_ROVR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDRPQ_ROVR_Msk instead */ 3501 #define GMAC_IDRPQ_HRESP_Pos 11 /**< (GMAC_IDRPQ) HRESP Not OK Position */ 3502 #define GMAC_IDRPQ_HRESP_Msk (_U_(0x1) << GMAC_IDRPQ_HRESP_Pos) /**< (GMAC_IDRPQ) HRESP Not OK Mask */ 3503 #define GMAC_IDRPQ_HRESP GMAC_IDRPQ_HRESP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDRPQ_HRESP_Msk instead */ 3504 #define GMAC_IDRPQ_MASK _U_(0xCE6) /**< \deprecated (GMAC_IDRPQ) Register MASK (Use GMAC_IDRPQ_Msk instead) */ 3505 #define GMAC_IDRPQ_Msk _U_(0xCE6) /**< (GMAC_IDRPQ) Register Mask */ 3506 3507 3508 /* -------- GMAC_IMRPQ : (GMAC Offset: 0x640) (R/W 32) Interrupt Mask Register Priority Queue (1..5) -------- */ 3509 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 3510 #if COMPONENT_TYPEDEF_STYLE == 'N' 3511 typedef union { 3512 struct { 3513 uint32_t :1; /**< bit: 0 Reserved */ 3514 uint32_t RCOMP:1; /**< bit: 1 Receive Complete */ 3515 uint32_t RXUBR:1; /**< bit: 2 RX Used Bit Read */ 3516 uint32_t :2; /**< bit: 3..4 Reserved */ 3517 uint32_t RLEX:1; /**< bit: 5 Retry Limit Exceeded or Late Collision */ 3518 uint32_t AHB:1; /**< bit: 6 AHB Error */ 3519 uint32_t TCOMP:1; /**< bit: 7 Transmit Complete */ 3520 uint32_t :2; /**< bit: 8..9 Reserved */ 3521 uint32_t ROVR:1; /**< bit: 10 Receive Overrun */ 3522 uint32_t HRESP:1; /**< bit: 11 HRESP Not OK */ 3523 uint32_t :20; /**< bit: 12..31 Reserved */ 3524 } bit; /**< Structure used for bit access */ 3525 uint32_t reg; /**< Type used for register access */ 3526 } GMAC_IMRPQ_Type; 3527 #endif 3528 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 3529 3530 #define GMAC_IMRPQ_OFFSET (0x640) /**< (GMAC_IMRPQ) Interrupt Mask Register Priority Queue (1..5) Offset */ 3531 3532 #define GMAC_IMRPQ_RCOMP_Pos 1 /**< (GMAC_IMRPQ) Receive Complete Position */ 3533 #define GMAC_IMRPQ_RCOMP_Msk (_U_(0x1) << GMAC_IMRPQ_RCOMP_Pos) /**< (GMAC_IMRPQ) Receive Complete Mask */ 3534 #define GMAC_IMRPQ_RCOMP GMAC_IMRPQ_RCOMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMRPQ_RCOMP_Msk instead */ 3535 #define GMAC_IMRPQ_RXUBR_Pos 2 /**< (GMAC_IMRPQ) RX Used Bit Read Position */ 3536 #define GMAC_IMRPQ_RXUBR_Msk (_U_(0x1) << GMAC_IMRPQ_RXUBR_Pos) /**< (GMAC_IMRPQ) RX Used Bit Read Mask */ 3537 #define GMAC_IMRPQ_RXUBR GMAC_IMRPQ_RXUBR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMRPQ_RXUBR_Msk instead */ 3538 #define GMAC_IMRPQ_RLEX_Pos 5 /**< (GMAC_IMRPQ) Retry Limit Exceeded or Late Collision Position */ 3539 #define GMAC_IMRPQ_RLEX_Msk (_U_(0x1) << GMAC_IMRPQ_RLEX_Pos) /**< (GMAC_IMRPQ) Retry Limit Exceeded or Late Collision Mask */ 3540 #define GMAC_IMRPQ_RLEX GMAC_IMRPQ_RLEX_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMRPQ_RLEX_Msk instead */ 3541 #define GMAC_IMRPQ_AHB_Pos 6 /**< (GMAC_IMRPQ) AHB Error Position */ 3542 #define GMAC_IMRPQ_AHB_Msk (_U_(0x1) << GMAC_IMRPQ_AHB_Pos) /**< (GMAC_IMRPQ) AHB Error Mask */ 3543 #define GMAC_IMRPQ_AHB GMAC_IMRPQ_AHB_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMRPQ_AHB_Msk instead */ 3544 #define GMAC_IMRPQ_TCOMP_Pos 7 /**< (GMAC_IMRPQ) Transmit Complete Position */ 3545 #define GMAC_IMRPQ_TCOMP_Msk (_U_(0x1) << GMAC_IMRPQ_TCOMP_Pos) /**< (GMAC_IMRPQ) Transmit Complete Mask */ 3546 #define GMAC_IMRPQ_TCOMP GMAC_IMRPQ_TCOMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMRPQ_TCOMP_Msk instead */ 3547 #define GMAC_IMRPQ_ROVR_Pos 10 /**< (GMAC_IMRPQ) Receive Overrun Position */ 3548 #define GMAC_IMRPQ_ROVR_Msk (_U_(0x1) << GMAC_IMRPQ_ROVR_Pos) /**< (GMAC_IMRPQ) Receive Overrun Mask */ 3549 #define GMAC_IMRPQ_ROVR GMAC_IMRPQ_ROVR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMRPQ_ROVR_Msk instead */ 3550 #define GMAC_IMRPQ_HRESP_Pos 11 /**< (GMAC_IMRPQ) HRESP Not OK Position */ 3551 #define GMAC_IMRPQ_HRESP_Msk (_U_(0x1) << GMAC_IMRPQ_HRESP_Pos) /**< (GMAC_IMRPQ) HRESP Not OK Mask */ 3552 #define GMAC_IMRPQ_HRESP GMAC_IMRPQ_HRESP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMRPQ_HRESP_Msk instead */ 3553 #define GMAC_IMRPQ_MASK _U_(0xCE6) /**< \deprecated (GMAC_IMRPQ) Register MASK (Use GMAC_IMRPQ_Msk instead) */ 3554 #define GMAC_IMRPQ_Msk _U_(0xCE6) /**< (GMAC_IMRPQ) Register Mask */ 3555 3556 3557 /* -------- GMAC_ST2ER : (GMAC Offset: 0x6e0) (R/W 32) Screening Type 2 Ethertype Register -------- */ 3558 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 3559 #if COMPONENT_TYPEDEF_STYLE == 'N' 3560 typedef union { 3561 struct { 3562 uint32_t COMPVAL:16; /**< bit: 0..15 Ethertype Compare Value */ 3563 uint32_t :16; /**< bit: 16..31 Reserved */ 3564 } bit; /**< Structure used for bit access */ 3565 uint32_t reg; /**< Type used for register access */ 3566 } GMAC_ST2ER_Type; 3567 #endif 3568 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 3569 3570 #define GMAC_ST2ER_OFFSET (0x6E0) /**< (GMAC_ST2ER) Screening Type 2 Ethertype Register Offset */ 3571 3572 #define GMAC_ST2ER_COMPVAL_Pos 0 /**< (GMAC_ST2ER) Ethertype Compare Value Position */ 3573 #define GMAC_ST2ER_COMPVAL_Msk (_U_(0xFFFF) << GMAC_ST2ER_COMPVAL_Pos) /**< (GMAC_ST2ER) Ethertype Compare Value Mask */ 3574 #define GMAC_ST2ER_COMPVAL(value) (GMAC_ST2ER_COMPVAL_Msk & ((value) << GMAC_ST2ER_COMPVAL_Pos)) 3575 #define GMAC_ST2ER_MASK _U_(0xFFFF) /**< \deprecated (GMAC_ST2ER) Register MASK (Use GMAC_ST2ER_Msk instead) */ 3576 #define GMAC_ST2ER_Msk _U_(0xFFFF) /**< (GMAC_ST2ER) Register Mask */ 3577 3578 3579 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 3580 #if COMPONENT_TYPEDEF_STYLE == 'R' 3581 /** \brief GMAC_SA hardware registers */ 3582 typedef struct { 3583 __IO uint32_t GMAC_SAB; /**< (GMAC_SA Offset: 0x00) Specific Address 1 Bottom Register */ 3584 __IO uint32_t GMAC_SAT; /**< (GMAC_SA Offset: 0x04) Specific Address 1 Top Register */ 3585 } GmacSa; 3586 3587 /** \brief GMAC_ST2CW hardware registers */ 3588 typedef struct { 3589 __IO uint32_t GMAC_ST2CW0; /**< (GMAC_ST2CW Offset: 0x00) Screening Type 2 Compare Word 0 Register */ 3590 __IO uint32_t GMAC_ST2CW1; /**< (GMAC_ST2CW Offset: 0x04) Screening Type 2 Compare Word 1 Register */ 3591 } GmacSt2cw; 3592 3593 #define GMACSA_NUMBER 4 3594 #define GMACST2CW_NUMBER 24 3595 /** \brief GMAC hardware registers */ 3596 typedef struct { 3597 __IO uint32_t GMAC_NCR; /**< (GMAC Offset: 0x00) Network Control Register */ 3598 __IO uint32_t GMAC_NCFGR; /**< (GMAC Offset: 0x04) Network Configuration Register */ 3599 __I uint32_t GMAC_NSR; /**< (GMAC Offset: 0x08) Network Status Register */ 3600 __IO uint32_t GMAC_UR; /**< (GMAC Offset: 0x0C) User Register */ 3601 __IO uint32_t GMAC_DCFGR; /**< (GMAC Offset: 0x10) DMA Configuration Register */ 3602 __IO uint32_t GMAC_TSR; /**< (GMAC Offset: 0x14) Transmit Status Register */ 3603 __IO uint32_t GMAC_RBQB; /**< (GMAC Offset: 0x18) Receive Buffer Queue Base Address Register */ 3604 __IO uint32_t GMAC_TBQB; /**< (GMAC Offset: 0x1C) Transmit Buffer Queue Base Address Register */ 3605 __IO uint32_t GMAC_RSR; /**< (GMAC Offset: 0x20) Receive Status Register */ 3606 __I uint32_t GMAC_ISR; /**< (GMAC Offset: 0x24) Interrupt Status Register */ 3607 __O uint32_t GMAC_IER; /**< (GMAC Offset: 0x28) Interrupt Enable Register */ 3608 __O uint32_t GMAC_IDR; /**< (GMAC Offset: 0x2C) Interrupt Disable Register */ 3609 __IO uint32_t GMAC_IMR; /**< (GMAC Offset: 0x30) Interrupt Mask Register */ 3610 __IO uint32_t GMAC_MAN; /**< (GMAC Offset: 0x34) PHY Maintenance Register */ 3611 __I uint32_t GMAC_RPQ; /**< (GMAC Offset: 0x38) Received Pause Quantum Register */ 3612 __IO uint32_t GMAC_TPQ; /**< (GMAC Offset: 0x3C) Transmit Pause Quantum Register */ 3613 __IO uint32_t GMAC_TPSF; /**< (GMAC Offset: 0x40) TX Partial Store and Forward Register */ 3614 __IO uint32_t GMAC_RPSF; /**< (GMAC Offset: 0x44) RX Partial Store and Forward Register */ 3615 __IO uint32_t GMAC_RJFML; /**< (GMAC Offset: 0x48) RX Jumbo Frame Max Length Register */ 3616 __I uint8_t Reserved1[52]; 3617 __IO uint32_t GMAC_HRB; /**< (GMAC Offset: 0x80) Hash Register Bottom */ 3618 __IO uint32_t GMAC_HRT; /**< (GMAC Offset: 0x84) Hash Register Top */ 3619 GmacSa GMAC_SA[GMACSA_NUMBER]; /**< Offset: 0x88 Specific Address 1 Bottom Register */ 3620 __IO uint32_t GMAC_TIDM1; /**< (GMAC Offset: 0xA8) Type ID Match 1 Register */ 3621 __IO uint32_t GMAC_TIDM2; /**< (GMAC Offset: 0xAC) Type ID Match 2 Register */ 3622 __IO uint32_t GMAC_TIDM3; /**< (GMAC Offset: 0xB0) Type ID Match 3 Register */ 3623 __IO uint32_t GMAC_TIDM4; /**< (GMAC Offset: 0xB4) Type ID Match 4 Register */ 3624 __IO uint32_t GMAC_WOL; /**< (GMAC Offset: 0xB8) Wake on LAN Register */ 3625 __IO uint32_t GMAC_IPGS; /**< (GMAC Offset: 0xBC) IPG Stretch Register */ 3626 __IO uint32_t GMAC_SVLAN; /**< (GMAC Offset: 0xC0) Stacked VLAN Register */ 3627 __IO uint32_t GMAC_TPFCP; /**< (GMAC Offset: 0xC4) Transmit PFC Pause Register */ 3628 __IO uint32_t GMAC_SAMB1; /**< (GMAC Offset: 0xC8) Specific Address 1 Mask Bottom Register */ 3629 __IO uint32_t GMAC_SAMT1; /**< (GMAC Offset: 0xCC) Specific Address 1 Mask Top Register */ 3630 __I uint8_t Reserved2[12]; 3631 __IO uint32_t GMAC_NSC; /**< (GMAC Offset: 0xDC) 1588 Timer Nanosecond Comparison Register */ 3632 __IO uint32_t GMAC_SCL; /**< (GMAC Offset: 0xE0) 1588 Timer Second Comparison Low Register */ 3633 __IO uint32_t GMAC_SCH; /**< (GMAC Offset: 0xE4) 1588 Timer Second Comparison High Register */ 3634 __I uint32_t GMAC_EFTSH; /**< (GMAC Offset: 0xE8) PTP Event Frame Transmitted Seconds High Register */ 3635 __I uint32_t GMAC_EFRSH; /**< (GMAC Offset: 0xEC) PTP Event Frame Received Seconds High Register */ 3636 __I uint32_t GMAC_PEFTSH; /**< (GMAC Offset: 0xF0) PTP Peer Event Frame Transmitted Seconds High Register */ 3637 __I uint32_t GMAC_PEFRSH; /**< (GMAC Offset: 0xF4) PTP Peer Event Frame Received Seconds High Register */ 3638 __I uint8_t Reserved3[8]; 3639 __I uint32_t GMAC_OTLO; /**< (GMAC Offset: 0x100) Octets Transmitted Low Register */ 3640 __I uint32_t GMAC_OTHI; /**< (GMAC Offset: 0x104) Octets Transmitted High Register */ 3641 __I uint32_t GMAC_FT; /**< (GMAC Offset: 0x108) Frames Transmitted Register */ 3642 __I uint32_t GMAC_BCFT; /**< (GMAC Offset: 0x10C) Broadcast Frames Transmitted Register */ 3643 __I uint32_t GMAC_MFT; /**< (GMAC Offset: 0x110) Multicast Frames Transmitted Register */ 3644 __I uint32_t GMAC_PFT; /**< (GMAC Offset: 0x114) Pause Frames Transmitted Register */ 3645 __I uint32_t GMAC_BFT64; /**< (GMAC Offset: 0x118) 64 Byte Frames Transmitted Register */ 3646 __I uint32_t GMAC_TBFT127; /**< (GMAC Offset: 0x11C) 65 to 127 Byte Frames Transmitted Register */ 3647 __I uint32_t GMAC_TBFT255; /**< (GMAC Offset: 0x120) 128 to 255 Byte Frames Transmitted Register */ 3648 __I uint32_t GMAC_TBFT511; /**< (GMAC Offset: 0x124) 256 to 511 Byte Frames Transmitted Register */ 3649 __I uint32_t GMAC_TBFT1023; /**< (GMAC Offset: 0x128) 512 to 1023 Byte Frames Transmitted Register */ 3650 __I uint32_t GMAC_TBFT1518; /**< (GMAC Offset: 0x12C) 1024 to 1518 Byte Frames Transmitted Register */ 3651 __I uint32_t GMAC_GTBFT1518; /**< (GMAC Offset: 0x130) Greater Than 1518 Byte Frames Transmitted Register */ 3652 __I uint32_t GMAC_TUR; /**< (GMAC Offset: 0x134) Transmit Underruns Register */ 3653 __I uint32_t GMAC_SCF; /**< (GMAC Offset: 0x138) Single Collision Frames Register */ 3654 __I uint32_t GMAC_MCF; /**< (GMAC Offset: 0x13C) Multiple Collision Frames Register */ 3655 __I uint32_t GMAC_EC; /**< (GMAC Offset: 0x140) Excessive Collisions Register */ 3656 __I uint32_t GMAC_LC; /**< (GMAC Offset: 0x144) Late Collisions Register */ 3657 __I uint32_t GMAC_DTF; /**< (GMAC Offset: 0x148) Deferred Transmission Frames Register */ 3658 __I uint32_t GMAC_CSE; /**< (GMAC Offset: 0x14C) Carrier Sense Errors Register */ 3659 __I uint32_t GMAC_ORLO; /**< (GMAC Offset: 0x150) Octets Received Low Received Register */ 3660 __I uint32_t GMAC_ORHI; /**< (GMAC Offset: 0x154) Octets Received High Received Register */ 3661 __I uint32_t GMAC_FR; /**< (GMAC Offset: 0x158) Frames Received Register */ 3662 __I uint32_t GMAC_BCFR; /**< (GMAC Offset: 0x15C) Broadcast Frames Received Register */ 3663 __I uint32_t GMAC_MFR; /**< (GMAC Offset: 0x160) Multicast Frames Received Register */ 3664 __I uint32_t GMAC_PFR; /**< (GMAC Offset: 0x164) Pause Frames Received Register */ 3665 __I uint32_t GMAC_BFR64; /**< (GMAC Offset: 0x168) 64 Byte Frames Received Register */ 3666 __I uint32_t GMAC_TBFR127; /**< (GMAC Offset: 0x16C) 65 to 127 Byte Frames Received Register */ 3667 __I uint32_t GMAC_TBFR255; /**< (GMAC Offset: 0x170) 128 to 255 Byte Frames Received Register */ 3668 __I uint32_t GMAC_TBFR511; /**< (GMAC Offset: 0x174) 256 to 511 Byte Frames Received Register */ 3669 __I uint32_t GMAC_TBFR1023; /**< (GMAC Offset: 0x178) 512 to 1023 Byte Frames Received Register */ 3670 __I uint32_t GMAC_TBFR1518; /**< (GMAC Offset: 0x17C) 1024 to 1518 Byte Frames Received Register */ 3671 __I uint32_t GMAC_TMXBFR; /**< (GMAC Offset: 0x180) 1519 to Maximum Byte Frames Received Register */ 3672 __I uint32_t GMAC_UFR; /**< (GMAC Offset: 0x184) Undersize Frames Received Register */ 3673 __I uint32_t GMAC_OFR; /**< (GMAC Offset: 0x188) Oversize Frames Received Register */ 3674 __I uint32_t GMAC_JR; /**< (GMAC Offset: 0x18C) Jabbers Received Register */ 3675 __I uint32_t GMAC_FCSE; /**< (GMAC Offset: 0x190) Frame Check Sequence Errors Register */ 3676 __I uint32_t GMAC_LFFE; /**< (GMAC Offset: 0x194) Length Field Frame Errors Register */ 3677 __I uint32_t GMAC_RSE; /**< (GMAC Offset: 0x198) Receive Symbol Errors Register */ 3678 __I uint32_t GMAC_AE; /**< (GMAC Offset: 0x19C) Alignment Errors Register */ 3679 __I uint32_t GMAC_RRE; /**< (GMAC Offset: 0x1A0) Receive Resource Errors Register */ 3680 __I uint32_t GMAC_ROE; /**< (GMAC Offset: 0x1A4) Receive Overrun Register */ 3681 __I uint32_t GMAC_IHCE; /**< (GMAC Offset: 0x1A8) IP Header Checksum Errors Register */ 3682 __I uint32_t GMAC_TCE; /**< (GMAC Offset: 0x1AC) TCP Checksum Errors Register */ 3683 __I uint32_t GMAC_UCE; /**< (GMAC Offset: 0x1B0) UDP Checksum Errors Register */ 3684 __I uint8_t Reserved4[8]; 3685 __IO uint32_t GMAC_TISUBN; /**< (GMAC Offset: 0x1BC) 1588 Timer Increment Sub-nanoseconds Register */ 3686 __IO uint32_t GMAC_TSH; /**< (GMAC Offset: 0x1C0) 1588 Timer Seconds High Register */ 3687 __I uint8_t Reserved5[12]; 3688 __IO uint32_t GMAC_TSL; /**< (GMAC Offset: 0x1D0) 1588 Timer Seconds Low Register */ 3689 __IO uint32_t GMAC_TN; /**< (GMAC Offset: 0x1D4) 1588 Timer Nanoseconds Register */ 3690 __O uint32_t GMAC_TA; /**< (GMAC Offset: 0x1D8) 1588 Timer Adjust Register */ 3691 __IO uint32_t GMAC_TI; /**< (GMAC Offset: 0x1DC) 1588 Timer Increment Register */ 3692 __I uint32_t GMAC_EFTSL; /**< (GMAC Offset: 0x1E0) PTP Event Frame Transmitted Seconds Low Register */ 3693 __I uint32_t GMAC_EFTN; /**< (GMAC Offset: 0x1E4) PTP Event Frame Transmitted Nanoseconds Register */ 3694 __I uint32_t GMAC_EFRSL; /**< (GMAC Offset: 0x1E8) PTP Event Frame Received Seconds Low Register */ 3695 __I uint32_t GMAC_EFRN; /**< (GMAC Offset: 0x1EC) PTP Event Frame Received Nanoseconds Register */ 3696 __I uint32_t GMAC_PEFTSL; /**< (GMAC Offset: 0x1F0) PTP Peer Event Frame Transmitted Seconds Low Register */ 3697 __I uint32_t GMAC_PEFTN; /**< (GMAC Offset: 0x1F4) PTP Peer Event Frame Transmitted Nanoseconds Register */ 3698 __I uint32_t GMAC_PEFRSL; /**< (GMAC Offset: 0x1F8) PTP Peer Event Frame Received Seconds Low Register */ 3699 __I uint32_t GMAC_PEFRN; /**< (GMAC Offset: 0x1FC) PTP Peer Event Frame Received Nanoseconds Register */ 3700 __I uint8_t Reserved6[112]; 3701 __I uint32_t GMAC_RXLPI; /**< (GMAC Offset: 0x270) Received LPI Transitions */ 3702 __I uint32_t GMAC_RXLPITIME; /**< (GMAC Offset: 0x274) Received LPI Time */ 3703 __I uint32_t GMAC_TXLPI; /**< (GMAC Offset: 0x278) Transmit LPI Transitions */ 3704 __I uint32_t GMAC_TXLPITIME; /**< (GMAC Offset: 0x27C) Transmit LPI Time */ 3705 __I uint8_t Reserved7[384]; 3706 __I uint32_t GMAC_ISRPQ[5]; /**< (GMAC Offset: 0x400) Interrupt Status Register Priority Queue (1..5) */ 3707 __I uint8_t Reserved8[44]; 3708 __IO uint32_t GMAC_TBQBAPQ[5]; /**< (GMAC Offset: 0x440) Transmit Buffer Queue Base Address Register Priority Queue (1..5) */ 3709 __I uint8_t Reserved9[44]; 3710 __IO uint32_t GMAC_RBQBAPQ[5]; /**< (GMAC Offset: 0x480) Receive Buffer Queue Base Address Register Priority Queue (1..5) */ 3711 __I uint8_t Reserved10[12]; 3712 __IO uint32_t GMAC_RBSRPQ[5]; /**< (GMAC Offset: 0x4A0) Receive Buffer Size Register Priority Queue (1..5) */ 3713 __I uint8_t Reserved11[8]; 3714 __IO uint32_t GMAC_CBSCR; /**< (GMAC Offset: 0x4BC) Credit-Based Shaping Control Register */ 3715 __IO uint32_t GMAC_CBSISQA; /**< (GMAC Offset: 0x4C0) Credit-Based Shaping IdleSlope Register for Queue A */ 3716 __IO uint32_t GMAC_CBSISQB; /**< (GMAC Offset: 0x4C4) Credit-Based Shaping IdleSlope Register for Queue B */ 3717 __I uint8_t Reserved12[56]; 3718 __IO uint32_t GMAC_ST1RPQ[4]; /**< (GMAC Offset: 0x500) Screening Type 1 Register Priority Queue */ 3719 __I uint8_t Reserved13[48]; 3720 __IO uint32_t GMAC_ST2RPQ[8]; /**< (GMAC Offset: 0x540) Screening Type 2 Register Priority Queue */ 3721 __I uint8_t Reserved14[160]; 3722 __O uint32_t GMAC_IERPQ[5]; /**< (GMAC Offset: 0x600) Interrupt Enable Register Priority Queue (1..5) */ 3723 __I uint8_t Reserved15[12]; 3724 __O uint32_t GMAC_IDRPQ[5]; /**< (GMAC Offset: 0x620) Interrupt Disable Register Priority Queue (1..5) */ 3725 __I uint8_t Reserved16[12]; 3726 __IO uint32_t GMAC_IMRPQ[5]; /**< (GMAC Offset: 0x640) Interrupt Mask Register Priority Queue (1..5) */ 3727 __I uint8_t Reserved17[140]; 3728 __IO uint32_t GMAC_ST2ER[4]; /**< (GMAC Offset: 0x6E0) Screening Type 2 Ethertype Register */ 3729 __I uint8_t Reserved18[16]; 3730 GmacSt2cw GmacSt2cw[GMACST2CW_NUMBER]; /**< Offset: 0x700 Screening Type 2 Compare Word 0 Register */ 3731 } Gmac; 3732 3733 #elif COMPONENT_TYPEDEF_STYLE == 'N' 3734 /** \brief GMAC_SA hardware registers */ 3735 typedef struct { 3736 __IO GMAC_SAB_Type GMAC_SAB; /**< Offset: 0x00 (R/W 32) Specific Address 1 Bottom Register */ 3737 __IO GMAC_SAT_Type GMAC_SAT; /**< Offset: 0x04 (R/W 32) Specific Address 1 Top Register */ 3738 } GmacSa; 3739 3740 /** \brief GMAC_ST2CW hardware registers */ 3741 typedef struct { 3742 __IO GMAC_ST2CW0_Type GMAC_ST2CW0; /**< Offset: 0x00 (R/W 32) Screening Type 2 Compare Word 0 Register */ 3743 __IO GMAC_ST2CW1_Type GMAC_ST2CW1; /**< Offset: 0x04 (R/W 32) Screening Type 2 Compare Word 1 Register */ 3744 } GmacSt2cw; 3745 3746 /** \brief GMAC hardware registers */ 3747 typedef struct { 3748 __IO GMAC_NCR_Type GMAC_NCR; /**< Offset: 0x00 (R/W 32) Network Control Register */ 3749 __IO GMAC_NCFGR_Type GMAC_NCFGR; /**< Offset: 0x04 (R/W 32) Network Configuration Register */ 3750 __I GMAC_NSR_Type GMAC_NSR; /**< Offset: 0x08 (R/ 32) Network Status Register */ 3751 __IO GMAC_UR_Type GMAC_UR; /**< Offset: 0x0C (R/W 32) User Register */ 3752 __IO GMAC_DCFGR_Type GMAC_DCFGR; /**< Offset: 0x10 (R/W 32) DMA Configuration Register */ 3753 __IO GMAC_TSR_Type GMAC_TSR; /**< Offset: 0x14 (R/W 32) Transmit Status Register */ 3754 __IO GMAC_RBQB_Type GMAC_RBQB; /**< Offset: 0x18 (R/W 32) Receive Buffer Queue Base Address Register */ 3755 __IO GMAC_TBQB_Type GMAC_TBQB; /**< Offset: 0x1C (R/W 32) Transmit Buffer Queue Base Address Register */ 3756 __IO GMAC_RSR_Type GMAC_RSR; /**< Offset: 0x20 (R/W 32) Receive Status Register */ 3757 __I GMAC_ISR_Type GMAC_ISR; /**< Offset: 0x24 (R/ 32) Interrupt Status Register */ 3758 __O GMAC_IER_Type GMAC_IER; /**< Offset: 0x28 ( /W 32) Interrupt Enable Register */ 3759 __O GMAC_IDR_Type GMAC_IDR; /**< Offset: 0x2C ( /W 32) Interrupt Disable Register */ 3760 __IO GMAC_IMR_Type GMAC_IMR; /**< Offset: 0x30 (R/W 32) Interrupt Mask Register */ 3761 __IO GMAC_MAN_Type GMAC_MAN; /**< Offset: 0x34 (R/W 32) PHY Maintenance Register */ 3762 __I GMAC_RPQ_Type GMAC_RPQ; /**< Offset: 0x38 (R/ 32) Received Pause Quantum Register */ 3763 __IO GMAC_TPQ_Type GMAC_TPQ; /**< Offset: 0x3C (R/W 32) Transmit Pause Quantum Register */ 3764 __IO GMAC_TPSF_Type GMAC_TPSF; /**< Offset: 0x40 (R/W 32) TX Partial Store and Forward Register */ 3765 __IO GMAC_RPSF_Type GMAC_RPSF; /**< Offset: 0x44 (R/W 32) RX Partial Store and Forward Register */ 3766 __IO GMAC_RJFML_Type GMAC_RJFML; /**< Offset: 0x48 (R/W 32) RX Jumbo Frame Max Length Register */ 3767 __I uint8_t Reserved1[52]; 3768 __IO GMAC_HRB_Type GMAC_HRB; /**< Offset: 0x80 (R/W 32) Hash Register Bottom */ 3769 __IO GMAC_HRT_Type GMAC_HRT; /**< Offset: 0x84 (R/W 32) Hash Register Top */ 3770 GmacSa GMAC_SA[4]; /**< Offset: 0x88 Specific Address 1 Bottom Register */ 3771 __IO GMAC_TIDM1_Type GMAC_TIDM1; /**< Offset: 0xA8 (R/W 32) Type ID Match 1 Register */ 3772 __IO GMAC_TIDM2_Type GMAC_TIDM2; /**< Offset: 0xAC (R/W 32) Type ID Match 2 Register */ 3773 __IO GMAC_TIDM3_Type GMAC_TIDM3; /**< Offset: 0xB0 (R/W 32) Type ID Match 3 Register */ 3774 __IO GMAC_TIDM4_Type GMAC_TIDM4; /**< Offset: 0xB4 (R/W 32) Type ID Match 4 Register */ 3775 __IO GMAC_WOL_Type GMAC_WOL; /**< Offset: 0xB8 (R/W 32) Wake on LAN Register */ 3776 __IO GMAC_IPGS_Type GMAC_IPGS; /**< Offset: 0xBC (R/W 32) IPG Stretch Register */ 3777 __IO GMAC_SVLAN_Type GMAC_SVLAN; /**< Offset: 0xC0 (R/W 32) Stacked VLAN Register */ 3778 __IO GMAC_TPFCP_Type GMAC_TPFCP; /**< Offset: 0xC4 (R/W 32) Transmit PFC Pause Register */ 3779 __IO GMAC_SAMB1_Type GMAC_SAMB1; /**< Offset: 0xC8 (R/W 32) Specific Address 1 Mask Bottom Register */ 3780 __IO GMAC_SAMT1_Type GMAC_SAMT1; /**< Offset: 0xCC (R/W 32) Specific Address 1 Mask Top Register */ 3781 __I uint8_t Reserved2[12]; 3782 __IO GMAC_NSC_Type GMAC_NSC; /**< Offset: 0xDC (R/W 32) 1588 Timer Nanosecond Comparison Register */ 3783 __IO GMAC_SCL_Type GMAC_SCL; /**< Offset: 0xE0 (R/W 32) 1588 Timer Second Comparison Low Register */ 3784 __IO GMAC_SCH_Type GMAC_SCH; /**< Offset: 0xE4 (R/W 32) 1588 Timer Second Comparison High Register */ 3785 __I GMAC_EFTSH_Type GMAC_EFTSH; /**< Offset: 0xE8 (R/ 32) PTP Event Frame Transmitted Seconds High Register */ 3786 __I GMAC_EFRSH_Type GMAC_EFRSH; /**< Offset: 0xEC (R/ 32) PTP Event Frame Received Seconds High Register */ 3787 __I GMAC_PEFTSH_Type GMAC_PEFTSH; /**< Offset: 0xF0 (R/ 32) PTP Peer Event Frame Transmitted Seconds High Register */ 3788 __I GMAC_PEFRSH_Type GMAC_PEFRSH; /**< Offset: 0xF4 (R/ 32) PTP Peer Event Frame Received Seconds High Register */ 3789 __I uint8_t Reserved3[8]; 3790 __I GMAC_OTLO_Type GMAC_OTLO; /**< Offset: 0x100 (R/ 32) Octets Transmitted Low Register */ 3791 __I GMAC_OTHI_Type GMAC_OTHI; /**< Offset: 0x104 (R/ 32) Octets Transmitted High Register */ 3792 __I GMAC_FT_Type GMAC_FT; /**< Offset: 0x108 (R/ 32) Frames Transmitted Register */ 3793 __I GMAC_BCFT_Type GMAC_BCFT; /**< Offset: 0x10C (R/ 32) Broadcast Frames Transmitted Register */ 3794 __I GMAC_MFT_Type GMAC_MFT; /**< Offset: 0x110 (R/ 32) Multicast Frames Transmitted Register */ 3795 __I GMAC_PFT_Type GMAC_PFT; /**< Offset: 0x114 (R/ 32) Pause Frames Transmitted Register */ 3796 __I GMAC_BFT64_Type GMAC_BFT64; /**< Offset: 0x118 (R/ 32) 64 Byte Frames Transmitted Register */ 3797 __I GMAC_TBFT127_Type GMAC_TBFT127; /**< Offset: 0x11C (R/ 32) 65 to 127 Byte Frames Transmitted Register */ 3798 __I GMAC_TBFT255_Type GMAC_TBFT255; /**< Offset: 0x120 (R/ 32) 128 to 255 Byte Frames Transmitted Register */ 3799 __I GMAC_TBFT511_Type GMAC_TBFT511; /**< Offset: 0x124 (R/ 32) 256 to 511 Byte Frames Transmitted Register */ 3800 __I GMAC_TBFT1023_Type GMAC_TBFT1023; /**< Offset: 0x128 (R/ 32) 512 to 1023 Byte Frames Transmitted Register */ 3801 __I GMAC_TBFT1518_Type GMAC_TBFT1518; /**< Offset: 0x12C (R/ 32) 1024 to 1518 Byte Frames Transmitted Register */ 3802 __I GMAC_GTBFT1518_Type GMAC_GTBFT1518; /**< Offset: 0x130 (R/ 32) Greater Than 1518 Byte Frames Transmitted Register */ 3803 __I GMAC_TUR_Type GMAC_TUR; /**< Offset: 0x134 (R/ 32) Transmit Underruns Register */ 3804 __I GMAC_SCF_Type GMAC_SCF; /**< Offset: 0x138 (R/ 32) Single Collision Frames Register */ 3805 __I GMAC_MCF_Type GMAC_MCF; /**< Offset: 0x13C (R/ 32) Multiple Collision Frames Register */ 3806 __I GMAC_EC_Type GMAC_EC; /**< Offset: 0x140 (R/ 32) Excessive Collisions Register */ 3807 __I GMAC_LC_Type GMAC_LC; /**< Offset: 0x144 (R/ 32) Late Collisions Register */ 3808 __I GMAC_DTF_Type GMAC_DTF; /**< Offset: 0x148 (R/ 32) Deferred Transmission Frames Register */ 3809 __I GMAC_CSE_Type GMAC_CSE; /**< Offset: 0x14C (R/ 32) Carrier Sense Errors Register */ 3810 __I GMAC_ORLO_Type GMAC_ORLO; /**< Offset: 0x150 (R/ 32) Octets Received Low Received Register */ 3811 __I GMAC_ORHI_Type GMAC_ORHI; /**< Offset: 0x154 (R/ 32) Octets Received High Received Register */ 3812 __I GMAC_FR_Type GMAC_FR; /**< Offset: 0x158 (R/ 32) Frames Received Register */ 3813 __I GMAC_BCFR_Type GMAC_BCFR; /**< Offset: 0x15C (R/ 32) Broadcast Frames Received Register */ 3814 __I GMAC_MFR_Type GMAC_MFR; /**< Offset: 0x160 (R/ 32) Multicast Frames Received Register */ 3815 __I GMAC_PFR_Type GMAC_PFR; /**< Offset: 0x164 (R/ 32) Pause Frames Received Register */ 3816 __I GMAC_BFR64_Type GMAC_BFR64; /**< Offset: 0x168 (R/ 32) 64 Byte Frames Received Register */ 3817 __I GMAC_TBFR127_Type GMAC_TBFR127; /**< Offset: 0x16C (R/ 32) 65 to 127 Byte Frames Received Register */ 3818 __I GMAC_TBFR255_Type GMAC_TBFR255; /**< Offset: 0x170 (R/ 32) 128 to 255 Byte Frames Received Register */ 3819 __I GMAC_TBFR511_Type GMAC_TBFR511; /**< Offset: 0x174 (R/ 32) 256 to 511 Byte Frames Received Register */ 3820 __I GMAC_TBFR1023_Type GMAC_TBFR1023; /**< Offset: 0x178 (R/ 32) 512 to 1023 Byte Frames Received Register */ 3821 __I GMAC_TBFR1518_Type GMAC_TBFR1518; /**< Offset: 0x17C (R/ 32) 1024 to 1518 Byte Frames Received Register */ 3822 __I GMAC_TMXBFR_Type GMAC_TMXBFR; /**< Offset: 0x180 (R/ 32) 1519 to Maximum Byte Frames Received Register */ 3823 __I GMAC_UFR_Type GMAC_UFR; /**< Offset: 0x184 (R/ 32) Undersize Frames Received Register */ 3824 __I GMAC_OFR_Type GMAC_OFR; /**< Offset: 0x188 (R/ 32) Oversize Frames Received Register */ 3825 __I GMAC_JR_Type GMAC_JR; /**< Offset: 0x18C (R/ 32) Jabbers Received Register */ 3826 __I GMAC_FCSE_Type GMAC_FCSE; /**< Offset: 0x190 (R/ 32) Frame Check Sequence Errors Register */ 3827 __I GMAC_LFFE_Type GMAC_LFFE; /**< Offset: 0x194 (R/ 32) Length Field Frame Errors Register */ 3828 __I GMAC_RSE_Type GMAC_RSE; /**< Offset: 0x198 (R/ 32) Receive Symbol Errors Register */ 3829 __I GMAC_AE_Type GMAC_AE; /**< Offset: 0x19C (R/ 32) Alignment Errors Register */ 3830 __I GMAC_RRE_Type GMAC_RRE; /**< Offset: 0x1A0 (R/ 32) Receive Resource Errors Register */ 3831 __I GMAC_ROE_Type GMAC_ROE; /**< Offset: 0x1A4 (R/ 32) Receive Overrun Register */ 3832 __I GMAC_IHCE_Type GMAC_IHCE; /**< Offset: 0x1A8 (R/ 32) IP Header Checksum Errors Register */ 3833 __I GMAC_TCE_Type GMAC_TCE; /**< Offset: 0x1AC (R/ 32) TCP Checksum Errors Register */ 3834 __I GMAC_UCE_Type GMAC_UCE; /**< Offset: 0x1B0 (R/ 32) UDP Checksum Errors Register */ 3835 __I uint8_t Reserved4[8]; 3836 __IO GMAC_TISUBN_Type GMAC_TISUBN; /**< Offset: 0x1BC (R/W 32) 1588 Timer Increment Sub-nanoseconds Register */ 3837 __IO GMAC_TSH_Type GMAC_TSH; /**< Offset: 0x1C0 (R/W 32) 1588 Timer Seconds High Register */ 3838 __I uint8_t Reserved5[12]; 3839 __IO GMAC_TSL_Type GMAC_TSL; /**< Offset: 0x1D0 (R/W 32) 1588 Timer Seconds Low Register */ 3840 __IO GMAC_TN_Type GMAC_TN; /**< Offset: 0x1D4 (R/W 32) 1588 Timer Nanoseconds Register */ 3841 __O GMAC_TA_Type GMAC_TA; /**< Offset: 0x1D8 ( /W 32) 1588 Timer Adjust Register */ 3842 __IO GMAC_TI_Type GMAC_TI; /**< Offset: 0x1DC (R/W 32) 1588 Timer Increment Register */ 3843 __I GMAC_EFTSL_Type GMAC_EFTSL; /**< Offset: 0x1E0 (R/ 32) PTP Event Frame Transmitted Seconds Low Register */ 3844 __I GMAC_EFTN_Type GMAC_EFTN; /**< Offset: 0x1E4 (R/ 32) PTP Event Frame Transmitted Nanoseconds Register */ 3845 __I GMAC_EFRSL_Type GMAC_EFRSL; /**< Offset: 0x1E8 (R/ 32) PTP Event Frame Received Seconds Low Register */ 3846 __I GMAC_EFRN_Type GMAC_EFRN; /**< Offset: 0x1EC (R/ 32) PTP Event Frame Received Nanoseconds Register */ 3847 __I GMAC_PEFTSL_Type GMAC_PEFTSL; /**< Offset: 0x1F0 (R/ 32) PTP Peer Event Frame Transmitted Seconds Low Register */ 3848 __I GMAC_PEFTN_Type GMAC_PEFTN; /**< Offset: 0x1F4 (R/ 32) PTP Peer Event Frame Transmitted Nanoseconds Register */ 3849 __I GMAC_PEFRSL_Type GMAC_PEFRSL; /**< Offset: 0x1F8 (R/ 32) PTP Peer Event Frame Received Seconds Low Register */ 3850 __I GMAC_PEFRN_Type GMAC_PEFRN; /**< Offset: 0x1FC (R/ 32) PTP Peer Event Frame Received Nanoseconds Register */ 3851 __I uint8_t Reserved6[112]; 3852 __I GMAC_RXLPI_Type GMAC_RXLPI; /**< Offset: 0x270 (R/ 32) Received LPI Transitions */ 3853 __I GMAC_RXLPITIME_Type GMAC_RXLPITIME; /**< Offset: 0x274 (R/ 32) Received LPI Time */ 3854 __I GMAC_TXLPI_Type GMAC_TXLPI; /**< Offset: 0x278 (R/ 32) Transmit LPI Transitions */ 3855 __I GMAC_TXLPITIME_Type GMAC_TXLPITIME; /**< Offset: 0x27C (R/ 32) Transmit LPI Time */ 3856 __I uint8_t Reserved7[384]; 3857 __I GMAC_ISRPQ_Type GMAC_ISRPQ[5]; /**< Offset: 0x400 (R/ 32) Interrupt Status Register Priority Queue (1..5) */ 3858 __I uint8_t Reserved8[44]; 3859 __IO GMAC_TBQBAPQ_Type GMAC_TBQBAPQ[5]; /**< Offset: 0x440 (R/W 32) Transmit Buffer Queue Base Address Register Priority Queue (1..5) */ 3860 __I uint8_t Reserved9[44]; 3861 __IO GMAC_RBQBAPQ_Type GMAC_RBQBAPQ[5]; /**< Offset: 0x480 (R/W 32) Receive Buffer Queue Base Address Register Priority Queue (1..5) */ 3862 __I uint8_t Reserved10[12]; 3863 __IO GMAC_RBSRPQ_Type GMAC_RBSRPQ[5]; /**< Offset: 0x4A0 (R/W 32) Receive Buffer Size Register Priority Queue (1..5) */ 3864 __I uint8_t Reserved11[8]; 3865 __IO GMAC_CBSCR_Type GMAC_CBSCR; /**< Offset: 0x4BC (R/W 32) Credit-Based Shaping Control Register */ 3866 __IO GMAC_CBSISQA_Type GMAC_CBSISQA; /**< Offset: 0x4C0 (R/W 32) Credit-Based Shaping IdleSlope Register for Queue A */ 3867 __IO GMAC_CBSISQB_Type GMAC_CBSISQB; /**< Offset: 0x4C4 (R/W 32) Credit-Based Shaping IdleSlope Register for Queue B */ 3868 __I uint8_t Reserved12[56]; 3869 __IO GMAC_ST1RPQ_Type GMAC_ST1RPQ[4]; /**< Offset: 0x500 (R/W 32) Screening Type 1 Register Priority Queue */ 3870 __I uint8_t Reserved13[48]; 3871 __IO GMAC_ST2RPQ_Type GMAC_ST2RPQ[8]; /**< Offset: 0x540 (R/W 32) Screening Type 2 Register Priority Queue */ 3872 __I uint8_t Reserved14[160]; 3873 __O GMAC_IERPQ_Type GMAC_IERPQ[5]; /**< Offset: 0x600 ( /W 32) Interrupt Enable Register Priority Queue (1..5) */ 3874 __I uint8_t Reserved15[12]; 3875 __O GMAC_IDRPQ_Type GMAC_IDRPQ[5]; /**< Offset: 0x620 ( /W 32) Interrupt Disable Register Priority Queue (1..5) */ 3876 __I uint8_t Reserved16[12]; 3877 __IO GMAC_IMRPQ_Type GMAC_IMRPQ[5]; /**< Offset: 0x640 (R/W 32) Interrupt Mask Register Priority Queue (1..5) */ 3878 __I uint8_t Reserved17[140]; 3879 __IO GMAC_ST2ER_Type GMAC_ST2ER[4]; /**< Offset: 0x6E0 (R/W 32) Screening Type 2 Ethertype Register */ 3880 __I uint8_t Reserved18[16]; 3881 GmacSt2cw GmacSt2cw[24]; /**< Offset: 0x700 Screening Type 2 Compare Word 0 Register */ 3882 } Gmac; 3883 3884 #else /* COMPONENT_TYPEDEF_STYLE */ 3885 #error Unknown component typedef style 3886 #endif /* COMPONENT_TYPEDEF_STYLE */ 3887 3888 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 3889 /** @} end of Gigabit Ethernet MAC */ 3890 3891 #endif /* _SAMV71_GMAC_COMPONENT_H_ */ 3892
